module NOT(A, Y); input A; output Y = ~A; endmodule module NAND(A, B, Y); input A, B; output Y = ~(A & B); endmodule module NOR(A, B, Y); input A, B; output Y = ~(A | B); endmodule module DFF(C, D, Q); input C, D; output reg Q; always @(posedge C) Q <= D; endmodule ynth/issue1211/tb_delay_ul.vhdl?h=master' type='application/atom+xml'/>
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