module NOT(A, Y); input A; output Y = ~A; endmodule module NAND(A, B, Y); input A, B; output Y = ~(A & B); endmodule module NOR(A, B, Y); input A, B; output Y = ~(A | B); endmodule module DFF(C, D, Q); input C, D; output reg Q; always @(posedge C) Q <= D; endmodule ='application/atom+xml'/>
aboutsummaryrefslogtreecommitdiffstats
path: root/tests/verilog/bug2037.ys
blob: 4b629ba9241d1c6c0385351cd204181fc288c0d5 (plain) 
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58