module \$add (A, B, Y); parameter A_SIGNED = 0; parameter B_SIGNED = 0; parameter A_WIDTH = 1; parameter B_WIDTH = 1; parameter Y_WIDTH = 1; input [A_WIDTH-1:0] A; input [B_WIDTH-1:0] B; output [Y_WIDTH-1:0] Y; generate if ((A_WIDTH == 32) && (B_WIDTH == 32)) begin wire [16:0] S1 = A[15:0] + B[15:0]; wire [15:0] S2 = A[31:16] + B[31:16] + S1[16]; assign Y = {S2[15:0], S1[15:0]}; end else wire _TECHMAP_FAIL_ = 1; endgenerate endmodule ChibiOS Git repository'/>
aboutsummaryrefslogtreecommitdiffstats
path: root/os/kernel/include/chheap.h
blob: 0db1cbc1d09db3e6bfb5cf68492b0292edb0fd92 (plain) 
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93