module test(input D, C, R, output reg Q); always @(posedge C, posedge R) if (R) Q <= 0; else Q <= D; endmodule m feed' href='http://git.panaceas.org/cgit.cgi/openwrt/upstream/atom/package/libs/libbsd/Makefile?h=lede-17.01' type='application/atom+xml'/>
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