module test(input [3:0] A, B, output [3:0] Y, Z); assign Y = A + B, Z = B + A; endmodule ss'/>
aboutsummaryrefslogtreecommitdiffstats
path: root/testhal/STM32/STM32F3xx/EXT/readme.txt
blob: e38ba66a6d1f995c2ac0ad4f6abaf36d5d55e5dc (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30