module example(input clk, a, b, c, output reg [1:0] y); always @(posedge clk) if (c) y <= c ? a + b : 2'd0; endmodule ed' href='http://openwrt.panaceas.org/cgit/xen/xen/atom/tools/vnet/vnet-module/skb_context.c?h=3.0.4-branched' type='application/atom+xml'/>
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