module demo1(input clk, input addtwo, output iseven); reg [3:0] cnt; wire [3:0] next_cnt; inc inc_inst (addtwo, iseven, cnt, next_cnt); always @(posedge clk) cnt = (iseven ? cnt == 10 : cnt == 11) ? 0 : next_cnt; `ifdef FORMAL assert property (cnt != 15); initial assume (!cnt[2]); `endif endmodule module inc(input addtwo, output iseven, input [3:0] a, output [3:0] y); assign iseven = !a[0]; assign y = a + (addtwo ? 2 : 1); endmodule it.panaceas.org/git/avr/qmk/firmware' title='avr/qmk/firmware Git repository'/>
aboutsummaryrefslogtreecommitdiffstats
path: root/keyboards/gskt00/rules.mk
blob: f0bbcad813e196a0dfb96ec5caff600d5dfc3bfd (plain) 
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28