#!/usr/bin/python3 from pyosys import libyosys as ys import matplotlib.pyplot as plt import numpy as np design = ys.Design() ys.run_pass("read_verilog ../../tests/simple/fiedler-cooley.v", design); ys.run_pass("prep", design) ys.run_pass("opt -full", design) cell_stats = {} for module in design.selected_whole_modules_warn(): for cell in module.selected_cells(): if cell.type.str() in cell_stats: cell_stats[cell.type.str()] += 1 else: cell_stats[cell.type.str()] = 1 plt.bar(range(len(cell_stats)), height = list(cell_stats.values()),align='center') plt.xticks(range(len(cell_stats)), list(cell_stats.keys())) plt.show() gi/'>index : iCE40/ghdl
[no description]
aboutsummaryrefslogtreecommitdiffstats
path: root/src/grt/grt-ghw.ads
blob: a605138e7c95f1e4e83b91ffccefd229736b86b7 (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83