module example ( input clk, input EN, output LED1, output LED2, output LED3, output LED4, output LED5 ); localparam BITS = 5; localparam LOG2DELAY = 22; reg [BITS+LOG2DELAY-1:0] counter = 0; reg [BITS-1:0] outcnt; always @(posedge clk) begin counter <= counter + EN; outcnt <= counter >> LOG2DELAY; end assign {LED1, LED2, LED3, LED4, LED5} = outcnt ^ (outcnt >> 1); endmodule rg/iCE40/yosys' title='iCE40/yosys Git repository'/>
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