From fb2bf934dc6d2c969906b350c9a1b09a972bfdd7 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Fri, 3 Jan 2014 00:22:17 +0100
Subject: Added correct handling of $memwr priority

---
 tests/simple/memory.v | 17 +++++++++++++++++
 1 file changed, 17 insertions(+)

(limited to 'tests')

diff --git a/tests/simple/memory.v b/tests/simple/memory.v
index aea014a28..eaeee01dd 100644
--- a/tests/simple/memory.v
+++ b/tests/simple/memory.v
@@ -1,4 +1,21 @@
 
+module test00(clk, setA, setB, y);
+
+input clk, setA, setB;
+output y;
+reg mem [1:0];
+
+always @(posedge clk) begin
+	if (setA) mem[0] <= 0;  // this is line 9
+	if (setB) mem[0] <= 1;  // this is line 10
+end
+
+assign y = mem[0];
+
+endmodule
+
+// ----------------------------------------------------------
+
 module test01(clk, wr_en, wr_addr, wr_value, rd_addr, rd_value);
 
 input clk, wr_en;
-- 
cgit v1.2.3