From b515fd2d25851c90c9a0b08414c5ea5edeb916a0 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Tue, 30 Apr 2019 11:25:15 +0200
Subject: Add peepopt_muldiv, fixes #930

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 tests/simple/peepopt.v | 9 +++++++++
 1 file changed, 9 insertions(+)
 create mode 100644 tests/simple/peepopt.v

(limited to 'tests')

diff --git a/tests/simple/peepopt.v b/tests/simple/peepopt.v
new file mode 100644
index 000000000..b27b9fe57
--- /dev/null
+++ b/tests/simple/peepopt.v
@@ -0,0 +1,9 @@
+module peepopt_shiftmul_0 #(parameter N=3, parameter W=3) (input [N*W-1:0] i, input [$clog2(N)-1:0] s, output [W-1:0] o);
+assign o = i[s*W+:W];
+endmodule
+
+module peepopt_muldiv_0(input [1:0] i, output [1:0] o);
+wire [3:0] t;
+assign t = i * 3;
+assign o = t / 3;
+endmodule
-- 
cgit v1.2.3


From e5cb9435a064461b56d55dc6ba1241ba1f179119 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Wed, 1 May 2019 09:32:07 +0200
Subject: Add additional test cases for for-loops

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 tests/simple/forloops.v | 25 +++++++++++++++++++++++++
 1 file changed, 25 insertions(+)
 create mode 100644 tests/simple/forloops.v

(limited to 'tests')

diff --git a/tests/simple/forloops.v b/tests/simple/forloops.v
new file mode 100644
index 000000000..8665222d8
--- /dev/null
+++ b/tests/simple/forloops.v
@@ -0,0 +1,25 @@
+module forloops01 (input clk, a, b, output reg [3:0] p, q, x, y);
+	integer k;
+	always @(posedge clk) begin
+		for (k=0; k<2; k=k+1)
+			p[2*k +: 2] = {a, b} ^ {2{k}};
+		x <= k + {a, b};
+	end
+	always @* begin
+		for (k=0; k<4; k=k+1)
+			q[k] = {~a, ~b, a, b} >> k[1:0];
+		y = k - {a, b};
+	end
+endmodule
+
+module forloops02 (input clk, a, b, output reg [3:0] q, x, output [3:0] y);
+	integer k;
+	always @* begin
+		for (k=0; k<4; k=k+1)
+			q[k] = {~a, ~b, a, b} >> k[1:0];
+	end
+	always @* begin
+		x = k + {a, b};
+	end
+	assign y = k - {a, b};
+endmodule
-- 
cgit v1.2.3


From 6bbe2fdbf32e6335cdbecc21547e54992c3a606d Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Wed, 1 May 2019 10:01:54 +0200
Subject: Add splitcmplxassign test case and silence splitcmplxassign warning

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 tests/simple/mem2reg.v | 22 ++++++++++++++++++++++
 1 file changed, 22 insertions(+)

(limited to 'tests')

diff --git a/tests/simple/mem2reg.v b/tests/simple/mem2reg.v
index 9839fd4a8..100426785 100644
--- a/tests/simple/mem2reg.v
+++ b/tests/simple/mem2reg.v
@@ -92,3 +92,25 @@ module mem2reg_test5(input ctrl, output out);
 	assign out = bar[foo[0]];
 endmodule
 
+// ------------------------------------------------------
+
+module mem2reg_test6 (din, dout);
+        input   wire    [3:0] din;
+        output  reg     [3:0] dout;
+
+        reg [1:0] din_array  [1:0];
+        reg [1:0] dout_array [1:0];
+
+        always @* begin
+		din_array[0] = din[0 +: 2];
+		din_array[1] = din[2 +: 2];
+
+		dout_array[0] = din_array[0];
+		dout_array[1] = din_array[1];
+
+		{dout_array[0][1], dout_array[0][0]} = dout_array[0][0] + dout_array[1][0];
+
+		dout[0 +: 2] = dout_array[0];
+		dout[2 +: 2] = dout_array[1];
+        end
+endmodule
-- 
cgit v1.2.3


From 38f5424f92389d6f4fdf020b214023b2b6efa71a Mon Sep 17 00:00:00 2001
From: Jim Lawson <ucbjrl@berkeley.edu>
Date: Wed, 1 May 2019 13:16:01 -0700
Subject: Fix #938 - Crash occurs in case when use write_firrtl command Add
 missing memory initialization. Sanity-check memory parameters. Add Cell
 pointer to memory object (for error reporting).

---
 tests/memories/firrtl_938.v | 22 ++++++++++++++++++++++
 tests/simple/xfirrtl        |  1 +
 2 files changed, 23 insertions(+)
 create mode 100644 tests/memories/firrtl_938.v

(limited to 'tests')

diff --git a/tests/memories/firrtl_938.v b/tests/memories/firrtl_938.v
new file mode 100644
index 000000000..af5efcd25
--- /dev/null
+++ b/tests/memories/firrtl_938.v
@@ -0,0 +1,22 @@
+module top
+(
+	input [7:0] data_a,
+	input [6:1] addr_a,
+	input we_a, clk,
+	output reg [7:0] q_a
+);
+	// Declare the RAM variable
+	reg [7:0] ram[63:0];
+
+	// Port A
+	always @ (posedge clk)
+	begin
+		if (we_a)
+		begin
+			ram[addr_a] <= data_a;
+			q_a <= data_a;
+		end
+			q_a <= ram[addr_a];
+	end
+
+endmodule
diff --git a/tests/simple/xfirrtl b/tests/simple/xfirrtl
index 50d693513..ba61a4476 100644
--- a/tests/simple/xfirrtl
+++ b/tests/simple/xfirrtl
@@ -16,6 +16,7 @@ operators.v	$pow
 partsel.v	drops modules
 process.v	drops modules
 realexpr.v	drops modules
+retime.v	Initial value (11110101) for (retime_test.ff) not supported
 scopes.v	original verilog issues ( -x where x isn't declared signed)
 sincos.v	$adff
 specify.v	no code (empty module generates error
-- 
cgit v1.2.3


From 98ffe5fb007c0e0d348f961a4e99d8b2f241eac1 Mon Sep 17 00:00:00 2001
From: Jakob Wenzel <wenzel@rs.tu-darmstadt.de>
Date: Thu, 25 Apr 2019 15:12:24 +0200
Subject: fail svinterfaces testcases on yosys error exit

---
 tests/svinterfaces/runone.sh | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

(limited to 'tests')

diff --git a/tests/svinterfaces/runone.sh b/tests/svinterfaces/runone.sh
index 0adecc797..71c2d4976 100755
--- a/tests/svinterfaces/runone.sh
+++ b/tests/svinterfaces/runone.sh
@@ -11,13 +11,13 @@ echo "" > $STDERRFILE
 
 echo -n "Test: ${TESTNAME} -> "
 
+set -e
+
 $PWD/../../yosys -p "read_verilog -sv ${TESTNAME}.sv ; hierarchy -check -top TopModule ; synth ; write_verilog ${TESTNAME}_syn.v" >> $STDOUTFILE >> $STDERRFILE
 $PWD/../../yosys -p "read_verilog -sv ${TESTNAME}_ref.v ; hierarchy -check -top TopModule ; synth ; write_verilog ${TESTNAME}_ref_syn.v" >> $STDOUTFILE >> $STDERRFILE
 
 rm -f a.out reference_result.txt dut_result.txt
 
-set -e
-
 iverilog -g2012 ${TESTNAME}_syn.v
 iverilog -g2012 ${TESTNAME}_ref_syn.v
 
-- 
cgit v1.2.3


From ac10e7d96da4965751fd60a8dd42a8998c011c39 Mon Sep 17 00:00:00 2001
From: Udi Finkelstein <github@udifink.com>
Date: Fri, 3 May 2019 03:10:43 +0300
Subject: Initial implementation of elaboration system tasks (IEEE1800-2017
 section 20.11) This PR allows us to use $info/$warning/$error/$fatal **at
 elaboration time** within a generate block. This is very useful to stop a
 synthesis of a parametrized block when an illegal combination of parameters
 is chosen.

---
 tests/various/elab_sys_tasks.sv | 30 ++++++++++++++++++++++++++++++
 tests/various/elab_sys_tasks.ys |  1 +
 2 files changed, 31 insertions(+)
 create mode 100644 tests/various/elab_sys_tasks.sv
 create mode 100644 tests/various/elab_sys_tasks.ys

(limited to 'tests')

diff --git a/tests/various/elab_sys_tasks.sv b/tests/various/elab_sys_tasks.sv
new file mode 100644
index 000000000..774d85b32
--- /dev/null
+++ b/tests/various/elab_sys_tasks.sv
@@ -0,0 +1,30 @@
+module test;
+localparam X=1;
+genvar i;
+generate
+if (X == 1)
+  $info("X is 1");
+if (X == 1)
+  $warning("X is 1");
+else
+  $error("X is not 1");
+case (X)
+  1: $info("X is 1 in a case statement");
+endcase
+//case (X-1)
+//  1: $warn("X is 2");
+//  default: $warn("X might be anything in a case statement");
+//endcase
+for (i = 0; i < 3; i = i + 1)
+begin
+  case(i)
+    0: $info;
+    1: $warning;
+    default: $info("default case statemnent");
+  endcase
+end
+
+$info("This is a standalone $info(). Next $info has no parameters");
+$info;
+endgenerate
+endmodule
diff --git a/tests/various/elab_sys_tasks.ys b/tests/various/elab_sys_tasks.ys
new file mode 100644
index 000000000..45bee3a60
--- /dev/null
+++ b/tests/various/elab_sys_tasks.ys
@@ -0,0 +1 @@
+read_verilog -sv elab_sys_tasks.sv
-- 
cgit v1.2.3


From d2aa123226f39fb6d076b9a0add2ad4f0e596166 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Fri, 3 May 2019 14:40:51 +0200
Subject: Fix typo in tests/svinterfaces/runone.sh

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 tests/svinterfaces/runone.sh | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

(limited to 'tests')

diff --git a/tests/svinterfaces/runone.sh b/tests/svinterfaces/runone.sh
index 71c2d4976..54cf5f2ec 100755
--- a/tests/svinterfaces/runone.sh
+++ b/tests/svinterfaces/runone.sh
@@ -13,8 +13,8 @@ echo -n "Test: ${TESTNAME} -> "
 
 set -e
 
-$PWD/../../yosys -p "read_verilog -sv ${TESTNAME}.sv ; hierarchy -check -top TopModule ; synth ; write_verilog ${TESTNAME}_syn.v" >> $STDOUTFILE >> $STDERRFILE
-$PWD/../../yosys -p "read_verilog -sv ${TESTNAME}_ref.v ; hierarchy -check -top TopModule ; synth ; write_verilog ${TESTNAME}_ref_syn.v" >> $STDOUTFILE >> $STDERRFILE
+$PWD/../../yosys -p "read_verilog -sv ${TESTNAME}.sv ; hierarchy -check -top TopModule ; synth ; write_verilog ${TESTNAME}_syn.v" >> $STDOUTFILE 2>> $STDERRFILE
+$PWD/../../yosys -p "read_verilog -sv ${TESTNAME}_ref.v ; hierarchy -check -top TopModule ; synth ; write_verilog ${TESTNAME}_ref_syn.v" >> $STDOUTFILE 2>> $STDERRFILE
 
 rm -f a.out reference_result.txt dut_result.txt
 
-- 
cgit v1.2.3


From 1e5f072c0556158924387dedbb78b4cc61bfcf7a Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 3 May 2019 14:03:51 -0700
Subject: iverilog with simcells.v as well

---
 tests/tools/autotest.sh | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

(limited to 'tests')

diff --git a/tests/tools/autotest.sh b/tests/tools/autotest.sh
index bb9c3bfb5..920474a84 100755
--- a/tests/tools/autotest.sh
+++ b/tests/tools/autotest.sh
@@ -147,7 +147,8 @@ do
 		fi
 		if $genvcd; then sed -i 's,// \$dump,$dump,g' ${bn}_tb.v; fi
 		compile_and_run ${bn}_tb_ref ${bn}_out_ref ${bn}_tb.v ${bn}_ref.v $libs \
-					"$toolsdir"/../../techlibs/common/simlib.v
+					"$toolsdir"/../../techlibs/common/simlib.v \
+					"$toolsdir"/../../techlibs/common/simcells.v
 		if $genvcd; then mv testbench.vcd ${bn}_ref.vcd; fi
 
 		test_count=0
-- 
cgit v1.2.3


From 09841c2ac1f36d06faada27093a2cf0cdfb6cb42 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 3 May 2019 15:35:26 -0700
Subject: Add quick-and-dirty specify tests

---
 tests/various/specify.v  | 28 ++++++++++++++++++++++++++++
 tests/various/specify.ys | 25 +++++++++++++++++++++++++
 2 files changed, 53 insertions(+)
 create mode 100644 tests/various/specify.v
 create mode 100644 tests/various/specify.ys

(limited to 'tests')

diff --git a/tests/various/specify.v b/tests/various/specify.v
new file mode 100644
index 000000000..aea0d0fc5
--- /dev/null
+++ b/tests/various/specify.v
@@ -0,0 +1,28 @@
+module test (
+	input EN, CLK,
+	input [3:0] D,
+	output reg [3:0] Q
+);
+	always @(posedge CLK)
+		if (EN) Q <= D;
+
+	specify
+		if (EN) (CLK *> (Q : D)) = (1, 2:3:4);
+		$setup(D, posedge CLK &&& EN, 5);
+		$hold(posedge CLK, D &&& EN, 6);
+	endspecify
+endmodule
+
+module test2 (
+    input A, B,
+	output Q
+);
+    xor (Q, A, B);
+	specify
+		//specparam T_rise = 1;
+        //specparam T_fall = 2;
+        `define T_rise 1
+        `define T_fall 2
+        (A => Q) = (`T_rise,`T_fall);
+	endspecify
+endmodule
diff --git a/tests/various/specify.ys b/tests/various/specify.ys
new file mode 100644
index 000000000..c4e901705
--- /dev/null
+++ b/tests/various/specify.ys
@@ -0,0 +1,25 @@
+read_verilog -specify specify.v
+prep
+cd test
+select t:$specify2 -assert-count 0
+select t:$specify3 -assert-count 1
+select t:$specrule -assert-count 2
+cd test2
+select t:$specify2 -assert-count 1
+select t:$specify3 -assert-count 0
+select t:$specrule -assert-count 0
+write_verilog specify.out
+design -stash gold
+
+read_verilog -specify specify.out
+cd test
+select t:$specify2 -assert-count 0
+select t:$specify3 -assert-count 1
+select t:$specrule -assert-count 2
+cd test2
+select t:$specify2 -assert-count 1
+select t:$specify3 -assert-count 0
+select t:$specrule -assert-count 0
+design -stash gate
+
+# TODO: How to check $specify and $specrule-s are equivalent?
-- 
cgit v1.2.3


From bfb8b3018bbe2017ab35fbdc21813f69c56514bb Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 3 May 2019 15:42:02 -0700
Subject: Fix spacing

---
 tests/various/specify.v | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

(limited to 'tests')

diff --git a/tests/various/specify.v b/tests/various/specify.v
index aea0d0fc5..68d3e33fc 100644
--- a/tests/various/specify.v
+++ b/tests/various/specify.v
@@ -14,15 +14,15 @@ module test (
 endmodule
 
 module test2 (
-    input A, B,
+	input A, B,
 	output Q
 );
-    xor (Q, A, B);
+	xor (Q, A, B);
 	specify
 		//specparam T_rise = 1;
-        //specparam T_fall = 2;
-        `define T_rise 1
-        `define T_fall 2
-        (A => Q) = (`T_rise,`T_fall);
+		//specparam T_fall = 2;
+		`define T_rise 1
+		`define T_fall 2
+		(A => Q) = (`T_rise,`T_fall);
 	endspecify
 endmodule
-- 
cgit v1.2.3


From 554c58715aa4f8f5ed9fb4293946ac420d3f67a2 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 3 May 2019 15:54:25 -0700
Subject: More testing

---
 tests/various/specify.v  | 2 ++
 tests/various/specify.ys | 5 +++--
 2 files changed, 5 insertions(+), 2 deletions(-)

(limited to 'tests')

diff --git a/tests/various/specify.v b/tests/various/specify.v
index 68d3e33fc..afc421da8 100644
--- a/tests/various/specify.v
+++ b/tests/various/specify.v
@@ -24,5 +24,7 @@ module test2 (
 		`define T_rise 1
 		`define T_fall 2
 		(A => Q) = (`T_rise,`T_fall);
+		//(B => Q) = (`T_rise+`T_fall)/2.0;
+		(B => Q) = 1.5;
 	endspecify
 endmodule
diff --git a/tests/various/specify.ys b/tests/various/specify.ys
index c4e901705..87d98e0a0 100644
--- a/tests/various/specify.ys
+++ b/tests/various/specify.ys
@@ -5,7 +5,7 @@ select t:$specify2 -assert-count 0
 select t:$specify3 -assert-count 1
 select t:$specrule -assert-count 2
 cd test2
-select t:$specify2 -assert-count 1
+select t:$specify2 -assert-count 2
 select t:$specify3 -assert-count 0
 select t:$specrule -assert-count 0
 write_verilog specify.out
@@ -17,9 +17,10 @@ select t:$specify2 -assert-count 0
 select t:$specify3 -assert-count 1
 select t:$specrule -assert-count 2
 cd test2
-select t:$specify2 -assert-count 1
+select t:$specify2 -assert-count 2
 select t:$specify3 -assert-count 0
 select t:$specrule -assert-count 0
 design -stash gate
 
 # TODO: How to check $specify and $specrule-s are equivalent?
+#       Otherwise, need more select statements to check parameter values are as expected?
-- 
cgit v1.2.3


From 8c6e94d57c430fc516dbcfbde312dbd7c860477b Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Mon, 6 May 2019 12:26:15 +0200
Subject: Improve tests/various/specify.ys

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 tests/various/specify.ys | 34 ++++++++++++++++++++++++++++++++--
 1 file changed, 32 insertions(+), 2 deletions(-)

(limited to 'tests')

diff --git a/tests/various/specify.ys b/tests/various/specify.ys
index 87d98e0a0..a5ca07219 100644
--- a/tests/various/specify.ys
+++ b/tests/various/specify.ys
@@ -8,10 +8,12 @@ cd test2
 select t:$specify2 -assert-count 2
 select t:$specify3 -assert-count 0
 select t:$specrule -assert-count 0
+cd
 write_verilog specify.out
 design -stash gold
 
 read_verilog -specify specify.out
+prep
 cd test
 select t:$specify2 -assert-count 0
 select t:$specify3 -assert-count 1
@@ -20,7 +22,35 @@ cd test2
 select t:$specify2 -assert-count 2
 select t:$specify3 -assert-count 0
 select t:$specrule -assert-count 0
+cd
 design -stash gate
 
-# TODO: How to check $specify and $specrule-s are equivalent?
-#       Otherwise, need more select statements to check parameter values are as expected?
+design -copy-from gold -as gold test
+design -copy-from gate -as gate test
+rename -hide
+rename -enumerate -pattern A_% t:$specify3
+rename -enumerate -pattern B_% t:$specrule r:TYPE=$setup %i
+rename -enumerate -pattern C_% t:$specrule r:TYPE=$hold %i
+select n:A_* -assert-count 2
+select n:B_* -assert-count 2
+select n:C_* -assert-count 2
+equiv_make gold gate equiv
+hierarchy -top equiv
+equiv_struct
+equiv_induct -seq 5
+equiv_status -assert
+design -reset
+
+design -copy-from gold -as gold test2
+design -copy-from gate -as gate test2
+rename -hide
+rename -enumerate -pattern A_% t:$specify2 r:T_RISE_TYP=1 %i
+rename -enumerate -pattern B_% t:$specify2 n:A_* %d
+select n:A_* -assert-count 2
+select n:B_* -assert-count 2
+equiv_make gold gate equiv
+hierarchy -top equiv
+equiv_struct
+equiv_induct -seq 5
+equiv_status -assert
+design -reset
-- 
cgit v1.2.3


From d97c644bc140655853854a09400383afc4b084d5 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Mon, 6 May 2019 16:03:15 +0200
Subject: Add tests/various/chparam.sh

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 tests/various/chparam.sh | 52 ++++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 52 insertions(+)
 create mode 100644 tests/various/chparam.sh

(limited to 'tests')

diff --git a/tests/various/chparam.sh b/tests/various/chparam.sh
new file mode 100644
index 000000000..9bb8d81db
--- /dev/null
+++ b/tests/various/chparam.sh
@@ -0,0 +1,52 @@
+#!/bin/bash
+
+trap 'echo "ERROR in chparam.sh" >&2; exit 1' ERR
+
+cat > chparam1.sv << "EOT"
+module top #(
+        parameter [31:0] X = 0
+) (
+        input [31:0] din,
+        output [31:0] dout
+);
+        assign dout = X-din;
+endmodule
+
+module top_props #(
+        parameter [31:0] X = 0
+) (
+        input [31:0] dout
+);
+        always @* assert (dout != X);
+endmodule
+
+bind top top_props #(.X(123456789)) props (.*);
+EOT
+
+cat > chparam2.sv << "EOT"
+module top #(
+	parameter [31:0] X = 0
+) (
+	input [31:0] din,
+	output [31:0] dout
+);
+	assign dout = X-din;
+	always @* assert (dout != 123456789);
+endmodule
+EOT
+
+if ../../yosys -q -p 'verific -sv chparam1.sv'; then
+	../../yosys -q -p 'verific -sv chparam1.sv; hierarchy -chparam X 123123123 -top top; prep -flatten' \
+			-p 'sat -verify -prove-asserts -show-ports -set din[0] 1' \
+			-p 'sat -falsify -prove-asserts -show-ports -set din[0] 0'
+
+	../../yosys -q -p 'verific -sv chparam2.sv; hierarchy -chparam X 123123123 -top top; prep -flatten' \
+			-p 'sat -verify -prove-asserts -show-ports -set din[0] 1' \
+			-p 'sat -falsify -prove-asserts -show-ports -set din[0] 0'
+fi
+../../yosys -q -p 'read_verilog -sv chparam2.sv; hierarchy -chparam X 123123123 -top top; prep -flatten' \
+		-p 'sat -verify -prove-asserts -show-ports -set din[0] 1' \
+		-p 'sat -falsify -prove-asserts -show-ports -set din[0] 0'
+
+rm chparam1.sv
+rm chparam2.sv
-- 
cgit v1.2.3


From b7ec698d4063f0e0ae021050782004c523302b0c Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Tue, 7 May 2019 19:58:04 +0200
Subject: Add test case from #997

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 tests/simple/dff_init.v | 12 ++++++++++++
 1 file changed, 12 insertions(+)

(limited to 'tests')

diff --git a/tests/simple/dff_init.v b/tests/simple/dff_init.v
index be947042e..375ea5c4d 100644
--- a/tests/simple/dff_init.v
+++ b/tests/simple/dff_init.v
@@ -40,3 +40,15 @@ module dff1a_test(n1, n1_inv, clk);
       n1 <= n1_inv;
   assign n1_inv = ~n1;
 endmodule
+
+module dff_test_997 (y, clk, wire4);
+// https://github.com/YosysHQ/yosys/issues/997
+   output wire [1:0] y;
+   input             clk;
+   input signed      wire4;
+   reg [1:0]  reg10 = 0;
+   always @(posedge clk) begin
+      reg10 <= wire4;
+   end
+   assign y = reg10;
+endmodule
-- 
cgit v1.2.3


From 1f52332b8d4621d6c5ab1447e82b6e2e53600e52 Mon Sep 17 00:00:00 2001
From: Maciej Kurc <mkurc@antmicro.com>
Date: Thu, 16 May 2019 12:53:43 +0200
Subject: Added tests for Verilog frontent for attributes on parameters and
 localparams

Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
---
 tests/simple/localparam_attr.v | 11 +++++++++++
 tests/simple/param_attr.v      | 11 +++++++++++
 2 files changed, 22 insertions(+)
 create mode 100644 tests/simple/localparam_attr.v
 create mode 100644 tests/simple/param_attr.v

(limited to 'tests')

diff --git a/tests/simple/localparam_attr.v b/tests/simple/localparam_attr.v
new file mode 100644
index 000000000..2ef76c71c
--- /dev/null
+++ b/tests/simple/localparam_attr.v
@@ -0,0 +1,11 @@
+module uut_localparam_attr (I, O);
+
+(* LOCALPARAM_ATTRIBUTE = "attribute_content" *)
+localparam WIDTH = 1;
+
+input  wire [WIDTH-1:0] I;
+output wire [WIDTH-1:0] O;
+
+assign O = I;
+
+endmodule
diff --git a/tests/simple/param_attr.v b/tests/simple/param_attr.v
new file mode 100644
index 000000000..34d63a34e
--- /dev/null
+++ b/tests/simple/param_attr.v
@@ -0,0 +1,11 @@
+module uut_param_attr (I, O);
+
+(* PARAMETER_ATTRIBUTE = "attribute_content" *)
+parameter WIDTH = 1;
+
+input  wire [WIDTH-1:0] I;
+output wire [WIDTH-1:0] O;
+
+assign O = I;
+
+endmodule
-- 
cgit v1.2.3


From c2caf85f7cbcbea4240b56a134e4c3e74189c62d Mon Sep 17 00:00:00 2001
From: Stefan Biereigel <stefan.biereigel@cern.ch>
Date: Thu, 23 May 2019 13:42:42 +0200
Subject: add simple test case for wand/wor

---
 tests/various/wandwor.v | 35 +++++++++++++++++++++++++++++++++++
 1 file changed, 35 insertions(+)
 create mode 100644 tests/various/wandwor.v

(limited to 'tests')

diff --git a/tests/various/wandwor.v b/tests/various/wandwor.v
new file mode 100644
index 000000000..824f89683
--- /dev/null
+++ b/tests/various/wandwor.v
@@ -0,0 +1,35 @@
+module a(Q);
+    output wire Q;
+
+    assign Q = 0;
+endmodule
+
+module b(D);
+    input wire D;
+endmodule
+
+module c;
+    wor D;
+    assign D = 1;
+    assign D = 0;
+    assign D = 1;
+    assign D = 0;
+
+
+    wand E;
+    wire E_wire = E;
+    
+    genvar i;
+    for (i = 0; i < 3; i = i + 1)
+    begin :genloop
+        a a_inst (
+            .Q(E)
+        );
+        
+        b b_inst (
+            .D(E_wire)
+        );
+    end
+
+endmodule
+
-- 
cgit v1.2.3


From 47f9ea142fcca94577519ede3de44b7c8b4f4379 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 23 May 2019 11:26:38 -0700
Subject: Add opt_rmdff tests

---
 tests/various/opt_rmdff.v  | 30 ++++++++++++++++++++++++++++++
 tests/various/opt_rmdff.ys | 25 +++++++++++++++++++++++++
 2 files changed, 55 insertions(+)
 create mode 100644 tests/various/opt_rmdff.v
 create mode 100644 tests/various/opt_rmdff.ys

(limited to 'tests')

diff --git a/tests/various/opt_rmdff.v b/tests/various/opt_rmdff.v
new file mode 100644
index 000000000..224b8d418
--- /dev/null
+++ b/tests/various/opt_rmdff.v
@@ -0,0 +1,30 @@
+module opt_rmdff_test (input C, input D, input E, output reg [16:0] Q);
+\$dffe #(.WIDTH(1), .CLK_POLARITY(1), .EN_POLARITY(1)) remove0 (.CLK(C), .D(D), .EN(1'b0), .Q(Q[0]));
+initial Q[1] = 1'b1;
+\$dffe #(.WIDTH(1), .CLK_POLARITY(1), .EN_POLARITY(1)) remove1 (.CLK(C), .D(D), .EN(1'b0), .Q(Q[1]));
+\$dffe #(.WIDTH(1), .CLK_POLARITY(1), .EN_POLARITY(1)) remove2 (.CLK(C), .D(D), .EN(1'bx), .Q(Q[2]));
+\$dffe #(.WIDTH(1), .CLK_POLARITY(1), .EN_POLARITY(1)) keep2 (.CLK(C), .D(D), .EN(1'b1), .Q(Q[2]));
+initial Q[3] = 1'b0;
+\$dffe #(.WIDTH(1), .CLK_POLARITY(0), .EN_POLARITY(1)) keep3 (.CLK(C), .D(D), .EN(1'b1), .Q(Q[3]));
+\$dffe #(.WIDTH(1), .CLK_POLARITY(1), .EN_POLARITY(0)) remove4 (.CLK(C), .D(D), .EN(1'b1), .Q(Q[4]));
+\$dffe #(.WIDTH(1), .CLK_POLARITY(1), .EN_POLARITY(0)) remove5 (.CLK(C), .D(D), .EN(1'bx), .Q(Q[5]));
+initial Q[6] = 1'b0;
+\$dffe #(.WIDTH(1), .CLK_POLARITY(0), .EN_POLARITY(0)) keep6 (.CLK(C), .D(D), .EN(E), .Q(Q[6]));
+
+\$_DFFE_PP_ remove7 (.C(C), .D(D), .E(1'b0), .Q(Q[7]));
+initial Q[8] = 1'b1;
+\$_DFFE_PP_ remove8 (.C(C), .D(D), .E(1'b0), .Q(Q[8]));
+\$_DFFE_PP_ remove9 (.C(C), .D(D), .E(1'bx), .Q(Q[9]));
+\$_DFFE_PP_ keep10 (.C(C), .D(D), .E(1'b1), .Q(Q[10]));
+initial Q[11] = 1'b0;
+\$_DFFE_PP_ keep11 (.C(C), .D(D), .E(1'b1), .Q(Q[11]));
+
+\$_DFFE_NN_ remove12 (.C(C), .D(D), .E(1'b1), .Q(Q[12]));
+initial Q[13] = 1'b1;
+\$_DFFE_NN_ remove13 (.C(C), .D(D), .E(1'b1), .Q(Q[13]));
+\$_DFFE_NN_ remove14 (.C(C), .D(D), .E(1'bx), .Q(Q[14]));
+\$_DFFE_NN_ keep15 (.C(C), .D(D), .E(1'b0), .Q(Q[15]));
+initial Q[16] = 1'b0;
+\$_DFFE_NN_ keep16 (.C(C), .D(D), .E(1'b0), .Q(Q[16]));
+
+endmodule
diff --git a/tests/various/opt_rmdff.ys b/tests/various/opt_rmdff.ys
new file mode 100644
index 000000000..fffffb4b5
--- /dev/null
+++ b/tests/various/opt_rmdff.ys
@@ -0,0 +1,25 @@
+read_verilog -icells opt_rmdff.v
+prep
+design -stash gold
+read_verilog -icells opt_rmdff.v
+opt_rmdff
+
+select -assert-count 0 c:remove*
+select -assert-min 7 c:keep*
+
+prep
+design -stash gate
+
+design -import gold -as gold
+design -import gate -as gate
+
+equiv_make gold gate equiv
+hierarchy -top equiv
+equiv_simple -undef
+equiv_status -assert
+
+design -load gold
+stat
+
+design -load gate
+stat
-- 
cgit v1.2.3


From f0c6b73b72b4ddc2b60865bcbd8934eba1bb6f52 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 24 May 2019 17:44:57 -0700
Subject: Fix duplicate driver

---
 tests/various/opt_rmdff.v | 30 +++++++++++++++---------------
 1 file changed, 15 insertions(+), 15 deletions(-)

(limited to 'tests')

diff --git a/tests/various/opt_rmdff.v b/tests/various/opt_rmdff.v
index 224b8d418..7a165c231 100644
--- a/tests/various/opt_rmdff.v
+++ b/tests/various/opt_rmdff.v
@@ -3,28 +3,28 @@ module opt_rmdff_test (input C, input D, input E, output reg [16:0] Q);
 initial Q[1] = 1'b1;
 \$dffe #(.WIDTH(1), .CLK_POLARITY(1), .EN_POLARITY(1)) remove1 (.CLK(C), .D(D), .EN(1'b0), .Q(Q[1]));
 \$dffe #(.WIDTH(1), .CLK_POLARITY(1), .EN_POLARITY(1)) remove2 (.CLK(C), .D(D), .EN(1'bx), .Q(Q[2]));
-\$dffe #(.WIDTH(1), .CLK_POLARITY(1), .EN_POLARITY(1)) keep2 (.CLK(C), .D(D), .EN(1'b1), .Q(Q[2]));
+\$dffe #(.WIDTH(1), .CLK_POLARITY(1), .EN_POLARITY(1)) keep3 (.CLK(C), .D(D), .EN(1'b1), .Q(Q[3]));
 initial Q[3] = 1'b0;
-\$dffe #(.WIDTH(1), .CLK_POLARITY(0), .EN_POLARITY(1)) keep3 (.CLK(C), .D(D), .EN(1'b1), .Q(Q[3]));
-\$dffe #(.WIDTH(1), .CLK_POLARITY(1), .EN_POLARITY(0)) remove4 (.CLK(C), .D(D), .EN(1'b1), .Q(Q[4]));
-\$dffe #(.WIDTH(1), .CLK_POLARITY(1), .EN_POLARITY(0)) remove5 (.CLK(C), .D(D), .EN(1'bx), .Q(Q[5]));
+\$dffe #(.WIDTH(1), .CLK_POLARITY(0), .EN_POLARITY(1)) keep4 (.CLK(C), .D(D), .EN(1'b1), .Q(Q[4]));
+\$dffe #(.WIDTH(1), .CLK_POLARITY(1), .EN_POLARITY(0)) remove5 (.CLK(C), .D(D), .EN(1'b1), .Q(Q[5]));
+\$dffe #(.WIDTH(1), .CLK_POLARITY(1), .EN_POLARITY(0)) remove6 (.CLK(C), .D(D), .EN(1'bx), .Q(Q[6]));
 initial Q[6] = 1'b0;
-\$dffe #(.WIDTH(1), .CLK_POLARITY(0), .EN_POLARITY(0)) keep6 (.CLK(C), .D(D), .EN(E), .Q(Q[6]));
+\$dffe #(.WIDTH(1), .CLK_POLARITY(0), .EN_POLARITY(0)) keep7 (.CLK(C), .D(D), .EN(E), .Q(Q[7]));
 
-\$_DFFE_PP_ remove7 (.C(C), .D(D), .E(1'b0), .Q(Q[7]));
-initial Q[8] = 1'b1;
 \$_DFFE_PP_ remove8 (.C(C), .D(D), .E(1'b0), .Q(Q[8]));
-\$_DFFE_PP_ remove9 (.C(C), .D(D), .E(1'bx), .Q(Q[9]));
-\$_DFFE_PP_ keep10 (.C(C), .D(D), .E(1'b1), .Q(Q[10]));
-initial Q[11] = 1'b0;
+initial Q[8] = 1'b1;
+\$_DFFE_PP_ remove9 (.C(C), .D(D), .E(1'b0), .Q(Q[9]));
+\$_DFFE_PP_ remove10 (.C(C), .D(D), .E(1'bx), .Q(Q[10]));
 \$_DFFE_PP_ keep11 (.C(C), .D(D), .E(1'b1), .Q(Q[11]));
+initial Q[12] = 1'b0;
+\$_DFFE_PP_ keep12 (.C(C), .D(D), .E(1'b1), .Q(Q[12]));
 
-\$_DFFE_NN_ remove12 (.C(C), .D(D), .E(1'b1), .Q(Q[12]));
-initial Q[13] = 1'b1;
 \$_DFFE_NN_ remove13 (.C(C), .D(D), .E(1'b1), .Q(Q[13]));
-\$_DFFE_NN_ remove14 (.C(C), .D(D), .E(1'bx), .Q(Q[14]));
-\$_DFFE_NN_ keep15 (.C(C), .D(D), .E(1'b0), .Q(Q[15]));
-initial Q[16] = 1'b0;
+initial Q[14] = 1'b1;
+\$_DFFE_NN_ remove14 (.C(C), .D(D), .E(1'b1), .Q(Q[14]));
+\$_DFFE_NN_ remove15 (.C(C), .D(D), .E(1'bx), .Q(Q[15]));
 \$_DFFE_NN_ keep16 (.C(C), .D(D), .E(1'b0), .Q(Q[16]));
+initial Q[17] = 1'b0;
+\$_DFFE_NN_ keep17 (.C(C), .D(D), .E(1'b0), .Q(Q[17]));
 
 endmodule
-- 
cgit v1.2.3


From 4bd9465ed3eb3ba2c0f45830b3337eaace4ec562 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 24 May 2019 18:32:02 -0700
Subject: Call proc

---
 tests/various/opt_rmdff.ys | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'tests')

diff --git a/tests/various/opt_rmdff.ys b/tests/various/opt_rmdff.ys
index fffffb4b5..89cd3f0c8 100644
--- a/tests/various/opt_rmdff.ys
+++ b/tests/various/opt_rmdff.ys
@@ -2,12 +2,12 @@ read_verilog -icells opt_rmdff.v
 prep
 design -stash gold
 read_verilog -icells opt_rmdff.v
+proc
 opt_rmdff
 
 select -assert-count 0 c:remove*
 select -assert-min 7 c:keep*
 
-prep
 design -stash gate
 
 design -import gold -as gold
-- 
cgit v1.2.3


From d15da4bc11c48d2eccb7fdc3543bf8176a281e1b Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 24 May 2019 18:33:18 -0700
Subject: Add more tests

---
 tests/various/opt_rmdff.v  | 60 ++++++++++++++++++++++++++++++----------------
 tests/various/opt_rmdff.ys |  1 +
 2 files changed, 41 insertions(+), 20 deletions(-)

(limited to 'tests')

diff --git a/tests/various/opt_rmdff.v b/tests/various/opt_rmdff.v
index 7a165c231..5d7d602c4 100644
--- a/tests/various/opt_rmdff.v
+++ b/tests/various/opt_rmdff.v
@@ -1,30 +1,50 @@
-module opt_rmdff_test (input C, input D, input E, output reg [16:0] Q);
-\$dffe #(.WIDTH(1), .CLK_POLARITY(1), .EN_POLARITY(1)) remove0 (.CLK(C), .D(D), .EN(1'b0), .Q(Q[0]));
+module opt_rmdff_test (input C, input D, input E, output reg [29:0] Q);
+//\$dffe #(.WIDTH(1), .CLK_POLARITY(1), .EN_POLARITY(1)) remove0 (.CLK(C), .D(D), .EN(1'b0), .Q(Q[0])); // EN is never active
 initial Q[1] = 1'b1;
-\$dffe #(.WIDTH(1), .CLK_POLARITY(1), .EN_POLARITY(1)) remove1 (.CLK(C), .D(D), .EN(1'b0), .Q(Q[1]));
-\$dffe #(.WIDTH(1), .CLK_POLARITY(1), .EN_POLARITY(1)) remove2 (.CLK(C), .D(D), .EN(1'bx), .Q(Q[2]));
-\$dffe #(.WIDTH(1), .CLK_POLARITY(1), .EN_POLARITY(1)) keep3 (.CLK(C), .D(D), .EN(1'b1), .Q(Q[3]));
+\$dffe #(.WIDTH(1), .CLK_POLARITY(1), .EN_POLARITY(1)) remove1 (.CLK(C), .D(D), .EN(1'b0), .Q(Q[1])); // EN is never active
+\$dffe #(.WIDTH(1), .CLK_POLARITY(1), .EN_POLARITY(1)) remove2 (.CLK(C), .D(D), .EN(1'bx), .Q(Q[2])); // EN is don't care
+\$dffe #(.WIDTH(1), .CLK_POLARITY(1), .EN_POLARITY(1)) keep3 (.CLK(C), .D(D), .EN(1'b1), .Q(Q[3])); // EN is always active
 initial Q[3] = 1'b0;
-\$dffe #(.WIDTH(1), .CLK_POLARITY(0), .EN_POLARITY(1)) keep4 (.CLK(C), .D(D), .EN(1'b1), .Q(Q[4]));
-\$dffe #(.WIDTH(1), .CLK_POLARITY(1), .EN_POLARITY(0)) remove5 (.CLK(C), .D(D), .EN(1'b1), .Q(Q[5]));
-\$dffe #(.WIDTH(1), .CLK_POLARITY(1), .EN_POLARITY(0)) remove6 (.CLK(C), .D(D), .EN(1'bx), .Q(Q[6]));
+\$dffe #(.WIDTH(1), .CLK_POLARITY(0), .EN_POLARITY(1)) keep4 (.CLK(C), .D(D), .EN(1'b1), .Q(Q[4])); // EN is always active
+\$dffe #(.WIDTH(1), .CLK_POLARITY(1), .EN_POLARITY(0)) remove5 (.CLK(C), .D(D), .EN(1'b1), .Q(Q[5])); // EN is never active
+\$dffe #(.WIDTH(1), .CLK_POLARITY(1), .EN_POLARITY(0)) remove6 (.CLK(C), .D(D), .EN(1'bx), .Q(Q[6])); // EN is don't care
 initial Q[6] = 1'b0;
-\$dffe #(.WIDTH(1), .CLK_POLARITY(0), .EN_POLARITY(0)) keep7 (.CLK(C), .D(D), .EN(E), .Q(Q[7]));
+\$dffe #(.WIDTH(1), .CLK_POLARITY(0), .EN_POLARITY(0)) keep7 (.CLK(C), .D(D), .EN(E), .Q(Q[7])); // EN is non constant
 
-\$_DFFE_PP_ remove8 (.C(C), .D(D), .E(1'b0), .Q(Q[8]));
-initial Q[8] = 1'b1;
-\$_DFFE_PP_ remove9 (.C(C), .D(D), .E(1'b0), .Q(Q[9]));
-\$_DFFE_PP_ remove10 (.C(C), .D(D), .E(1'bx), .Q(Q[10]));
-\$_DFFE_PP_ keep11 (.C(C), .D(D), .E(1'b1), .Q(Q[11]));
+\$_DFFE_PP_ remove8 (.C(C), .D(D), .E(1'b0), .Q(Q[8])); // EN is never active
+initial Q[9] = 1'b1;
+\$_DFFE_PP_ remove9 (.C(C), .D(D), .E(1'b0), .Q(Q[9])); // EN is never active
+\$_DFFE_PP_ remove10 (.C(C), .D(D), .E(1'bx), .Q(Q[10])); // EN is don't care
+\$_DFFE_PP_ keep11 (.C(C), .D(D), .E(1'b1), .Q(Q[11])); // EN is always active
 initial Q[12] = 1'b0;
-\$_DFFE_PP_ keep12 (.C(C), .D(D), .E(1'b1), .Q(Q[12]));
+\$_DFFE_PP_ keep12 (.C(C), .D(D), .E(1'b1), .Q(Q[12])); // EN is always active
 
-\$_DFFE_NN_ remove13 (.C(C), .D(D), .E(1'b1), .Q(Q[13]));
+\$_DFFE_NN_ remove13 (.C(C), .D(D), .E(1'b1), .Q(Q[13])); // EN is never active
 initial Q[14] = 1'b1;
-\$_DFFE_NN_ remove14 (.C(C), .D(D), .E(1'b1), .Q(Q[14]));
-\$_DFFE_NN_ remove15 (.C(C), .D(D), .E(1'bx), .Q(Q[15]));
-\$_DFFE_NN_ keep16 (.C(C), .D(D), .E(1'b0), .Q(Q[16]));
+\$_DFFE_NN_ remove14 (.C(C), .D(D), .E(1'b1), .Q(Q[14])); // EN is never active
+\$_DFFE_NN_ remove15 (.C(C), .D(D), .E(1'bx), .Q(Q[15])); // EN is don't care
+\$_DFFE_NN_ keep16 (.C(C), .D(D), .E(1'b0), .Q(Q[16])); // EN is always active
 initial Q[17] = 1'b0;
-\$_DFFE_NN_ keep17 (.C(C), .D(D), .E(1'b0), .Q(Q[17]));
+\$_DFFE_NN_ keep17 (.C(C), .D(D), .E(1'b0), .Q(Q[17])); // EN is always active
+
+\$dffe #(.WIDTH(1), .CLK_POLARITY(1), .EN_POLARITY(1)) remove18 (.CLK(1'b0), .D(D), .EN(EN), .Q(Q[18])); // CLK is constant
+initial Q[19] = 1'b1;
+\$dffe #(.WIDTH(1), .CLK_POLARITY(1), .EN_POLARITY(1)) remove19 (.CLK(1'b1), .D(D), .EN(EN), .Q(Q[19])); // CLK is constant
+\$dffe #(.WIDTH(1), .CLK_POLARITY(1), .EN_POLARITY(1)) remove20 (.CLK(C), .D(1'bx), .EN(EN), .Q(Q[20])); // D is undriven, Q has no initial value
+initial Q[21] = 1'b0;
+\$dffe #(.WIDTH(1), .CLK_POLARITY(1), .EN_POLARITY(1)) keep21 (.CLK(C), .D(1'bx), .EN(EN), .Q(Q[21])); // D is undriven, Q has initial value
+//\$dffe #(.WIDTH(1), .CLK_POLARITY(0), .EN_POLARITY(1)) remove22 (.CLK(C), .D(1'b0), .EN(1'b1), .Q(Q[22])); // D is constant, no initial Q value, EN is always active
+//                                                                                                           // (TODO, Q starts with 1'bx and becomes 1'b0)
+initial Q[23] = 1'b0;
+\$dffe #(.WIDTH(1), .CLK_POLARITY(1), .EN_POLARITY(1)) noenable23 (.CLK(C), .D(1'b0), .EN(1'b1), .Q(Q[23])); // D is constant, initial Q value same as D, EN is always active
+initial Q[24] = 1'b1;
+\$dffe #(.WIDTH(1), .CLK_POLARITY(1), .EN_POLARITY(0)) keep24 (.CLK(C), .D(1'b0), .EN(1'b0), .Q(Q[24])); // D is constant, initial Q value NOT same as D, EN is always active
+initial Q[25] = 1'b1;
+\$dffe #(.WIDTH(1), .CLK_POLARITY(1), .EN_POLARITY(0)) remove25 (.CLK(C), .D(1'b0), .EN(1'b1), .Q(Q[25])); // D is constant, EN is never active
+\$dffe #(.WIDTH(1), .CLK_POLARITY(1), .EN_POLARITY(1)) remove26 (.CLK(C), .D(Q[26]), .EN(1'b1), .Q(Q[26])); // D is Q, EN is always active
+\$dffe #(.WIDTH(1), .CLK_POLARITY(1), .EN_POLARITY(0)) remove27 (.CLK(C), .D(Q[27]), .EN(1'b1), .Q(Q[27])); // D is Q, EN is never active, but no initial value
+\$dffe #(.WIDTH(1), .CLK_POLARITY(1), .EN_POLARITY(0)) remove28 (.CLK(C), .D(Q[28]), .EN(EN), .Q(Q[28])); // EN is nonconst, but no initial value
+initial Q[29] = 1'b1;
+\$dffe #(.WIDTH(1), .CLK_POLARITY(1), .EN_POLARITY(1)) keep29 (.CLK(C), .D(Q[29]), .EN(1'b1), .Q(Q[29])); // EN is always active, but with initial value
 
 endmodule
diff --git a/tests/various/opt_rmdff.ys b/tests/various/opt_rmdff.ys
index 89cd3f0c8..081f81782 100644
--- a/tests/various/opt_rmdff.ys
+++ b/tests/various/opt_rmdff.ys
@@ -7,6 +7,7 @@ opt_rmdff
 
 select -assert-count 0 c:remove*
 select -assert-min 7 c:keep*
+select -assert-count 0  t:$dffe 7:$_DFFE_* %u c:noenable* %i
 
 design -stash gate
 
-- 
cgit v1.2.3


From e1cb1bb94815a60f81e8d5026b92864e7e4afe11 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 24 May 2019 18:34:27 -0700
Subject: Fix typos

---
 tests/various/opt_rmdff.v | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

(limited to 'tests')

diff --git a/tests/various/opt_rmdff.v b/tests/various/opt_rmdff.v
index 5d7d602c4..207eccc8e 100644
--- a/tests/various/opt_rmdff.v
+++ b/tests/various/opt_rmdff.v
@@ -1,5 +1,5 @@
 module opt_rmdff_test (input C, input D, input E, output reg [29:0] Q);
-//\$dffe #(.WIDTH(1), .CLK_POLARITY(1), .EN_POLARITY(1)) remove0 (.CLK(C), .D(D), .EN(1'b0), .Q(Q[0])); // EN is never active
+\$dffe #(.WIDTH(1), .CLK_POLARITY(1), .EN_POLARITY(1)) remove0 (.CLK(C), .D(D), .EN(1'b0), .Q(Q[0])); // EN is never active
 initial Q[1] = 1'b1;
 \$dffe #(.WIDTH(1), .CLK_POLARITY(1), .EN_POLARITY(1)) remove1 (.CLK(C), .D(D), .EN(1'b0), .Q(Q[1])); // EN is never active
 \$dffe #(.WIDTH(1), .CLK_POLARITY(1), .EN_POLARITY(1)) remove2 (.CLK(C), .D(D), .EN(1'bx), .Q(Q[2])); // EN is don't care
@@ -27,12 +27,12 @@ initial Q[14] = 1'b1;
 initial Q[17] = 1'b0;
 \$_DFFE_NN_ keep17 (.C(C), .D(D), .E(1'b0), .Q(Q[17])); // EN is always active
 
-\$dffe #(.WIDTH(1), .CLK_POLARITY(1), .EN_POLARITY(1)) remove18 (.CLK(1'b0), .D(D), .EN(EN), .Q(Q[18])); // CLK is constant
+\$dffe #(.WIDTH(1), .CLK_POLARITY(1), .EN_POLARITY(1)) remove18 (.CLK(1'b0), .D(D), .EN(E), .Q(Q[18])); // CLK is constant
 initial Q[19] = 1'b1;
-\$dffe #(.WIDTH(1), .CLK_POLARITY(1), .EN_POLARITY(1)) remove19 (.CLK(1'b1), .D(D), .EN(EN), .Q(Q[19])); // CLK is constant
-\$dffe #(.WIDTH(1), .CLK_POLARITY(1), .EN_POLARITY(1)) remove20 (.CLK(C), .D(1'bx), .EN(EN), .Q(Q[20])); // D is undriven, Q has no initial value
+\$dffe #(.WIDTH(1), .CLK_POLARITY(1), .EN_POLARITY(1)) remove19 (.CLK(1'b1), .D(D), .EN(E), .Q(Q[19])); // CLK is constant
+\$dffe #(.WIDTH(1), .CLK_POLARITY(1), .EN_POLARITY(1)) remove20 (.CLK(C), .D(1'bx), .EN(E), .Q(Q[20])); // D is undriven, Q has no initial value
 initial Q[21] = 1'b0;
-\$dffe #(.WIDTH(1), .CLK_POLARITY(1), .EN_POLARITY(1)) keep21 (.CLK(C), .D(1'bx), .EN(EN), .Q(Q[21])); // D is undriven, Q has initial value
+\$dffe #(.WIDTH(1), .CLK_POLARITY(1), .EN_POLARITY(1)) keep21 (.CLK(C), .D(1'bx), .EN(E), .Q(Q[21])); // D is undriven, Q has initial value
 //\$dffe #(.WIDTH(1), .CLK_POLARITY(0), .EN_POLARITY(1)) remove22 (.CLK(C), .D(1'b0), .EN(1'b1), .Q(Q[22])); // D is constant, no initial Q value, EN is always active
 //                                                                                                           // (TODO, Q starts with 1'bx and becomes 1'b0)
 initial Q[23] = 1'b0;
@@ -43,7 +43,7 @@ initial Q[25] = 1'b1;
 \$dffe #(.WIDTH(1), .CLK_POLARITY(1), .EN_POLARITY(0)) remove25 (.CLK(C), .D(1'b0), .EN(1'b1), .Q(Q[25])); // D is constant, EN is never active
 \$dffe #(.WIDTH(1), .CLK_POLARITY(1), .EN_POLARITY(1)) remove26 (.CLK(C), .D(Q[26]), .EN(1'b1), .Q(Q[26])); // D is Q, EN is always active
 \$dffe #(.WIDTH(1), .CLK_POLARITY(1), .EN_POLARITY(0)) remove27 (.CLK(C), .D(Q[27]), .EN(1'b1), .Q(Q[27])); // D is Q, EN is never active, but no initial value
-\$dffe #(.WIDTH(1), .CLK_POLARITY(1), .EN_POLARITY(0)) remove28 (.CLK(C), .D(Q[28]), .EN(EN), .Q(Q[28])); // EN is nonconst, but no initial value
+\$dffe #(.WIDTH(1), .CLK_POLARITY(1), .EN_POLARITY(0)) remove28 (.CLK(C), .D(Q[28]), .EN(E), .Q(Q[28])); // EN is nonconst, but no initial value
 initial Q[29] = 1'b1;
 \$dffe #(.WIDTH(1), .CLK_POLARITY(1), .EN_POLARITY(1)) keep29 (.CLK(C), .D(Q[29]), .EN(1'b1), .Q(Q[29])); // EN is always active, but with initial value
 
-- 
cgit v1.2.3


From f3e86e06e698491b110ac66b88bc3c0ce3cda174 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 24 May 2019 18:43:26 -0700
Subject: Fix init

---
 tests/various/opt_rmdff.v | 54 +++++++++++++++++++++++------------------------
 1 file changed, 27 insertions(+), 27 deletions(-)

(limited to 'tests')

diff --git a/tests/various/opt_rmdff.v b/tests/various/opt_rmdff.v
index 207eccc8e..b1c06703c 100644
--- a/tests/various/opt_rmdff.v
+++ b/tests/various/opt_rmdff.v
@@ -1,50 +1,50 @@
-module opt_rmdff_test (input C, input D, input E, output reg [29:0] Q);
+module opt_rmdff_test (input C, input D, input E, output [29:0] Q);
 \$dffe #(.WIDTH(1), .CLK_POLARITY(1), .EN_POLARITY(1)) remove0 (.CLK(C), .D(D), .EN(1'b0), .Q(Q[0])); // EN is never active
-initial Q[1] = 1'b1;
-\$dffe #(.WIDTH(1), .CLK_POLARITY(1), .EN_POLARITY(1)) remove1 (.CLK(C), .D(D), .EN(1'b0), .Q(Q[1])); // EN is never active
+(* init = "1'b1" *) wire Q1; assign Q[1] = Q1;
+\$dffe #(.WIDTH(1), .CLK_POLARITY(1), .EN_POLARITY(1)) remove1 (.CLK(C), .D(D), .EN(1'b0), .Q(Q1)); // EN is never active
 \$dffe #(.WIDTH(1), .CLK_POLARITY(1), .EN_POLARITY(1)) remove2 (.CLK(C), .D(D), .EN(1'bx), .Q(Q[2])); // EN is don't care
 \$dffe #(.WIDTH(1), .CLK_POLARITY(1), .EN_POLARITY(1)) keep3 (.CLK(C), .D(D), .EN(1'b1), .Q(Q[3])); // EN is always active
-initial Q[3] = 1'b0;
-\$dffe #(.WIDTH(1), .CLK_POLARITY(0), .EN_POLARITY(1)) keep4 (.CLK(C), .D(D), .EN(1'b1), .Q(Q[4])); // EN is always active
+(* init = "1'b0" *) wire Q4; assign Q[4] = Q4;
+\$dffe #(.WIDTH(1), .CLK_POLARITY(0), .EN_POLARITY(1)) keep4 (.CLK(C), .D(D), .EN(1'b1), .Q(Q4)); // EN is always active
 \$dffe #(.WIDTH(1), .CLK_POLARITY(1), .EN_POLARITY(0)) remove5 (.CLK(C), .D(D), .EN(1'b1), .Q(Q[5])); // EN is never active
 \$dffe #(.WIDTH(1), .CLK_POLARITY(1), .EN_POLARITY(0)) remove6 (.CLK(C), .D(D), .EN(1'bx), .Q(Q[6])); // EN is don't care
-initial Q[6] = 1'b0;
-\$dffe #(.WIDTH(1), .CLK_POLARITY(0), .EN_POLARITY(0)) keep7 (.CLK(C), .D(D), .EN(E), .Q(Q[7])); // EN is non constant
+(* init = "1'b0" *) wire Q7; assign Q[7] = Q7;
+\$dffe #(.WIDTH(1), .CLK_POLARITY(0), .EN_POLARITY(0)) keep7 (.CLK(C), .D(D), .EN(E), .Q(Q7)); // EN is non constant
 
 \$_DFFE_PP_ remove8 (.C(C), .D(D), .E(1'b0), .Q(Q[8])); // EN is never active
-initial Q[9] = 1'b1;
-\$_DFFE_PP_ remove9 (.C(C), .D(D), .E(1'b0), .Q(Q[9])); // EN is never active
+(* init = "1'b1" *) wire Q9; assign Q[9] = Q9;
+\$_DFFE_PP_ remove9 (.C(C), .D(D), .E(1'b0), .Q(Q9)); // EN is never active
 \$_DFFE_PP_ remove10 (.C(C), .D(D), .E(1'bx), .Q(Q[10])); // EN is don't care
 \$_DFFE_PP_ keep11 (.C(C), .D(D), .E(1'b1), .Q(Q[11])); // EN is always active
-initial Q[12] = 1'b0;
-\$_DFFE_PP_ keep12 (.C(C), .D(D), .E(1'b1), .Q(Q[12])); // EN is always active
+(* init = "1'b0" *) wire Q12; assign Q[12] = Q12;
+\$_DFFE_PP_ keep12 (.C(C), .D(D), .E(1'b1), .Q(Q12)); // EN is always active
 
 \$_DFFE_NN_ remove13 (.C(C), .D(D), .E(1'b1), .Q(Q[13])); // EN is never active
-initial Q[14] = 1'b1;
-\$_DFFE_NN_ remove14 (.C(C), .D(D), .E(1'b1), .Q(Q[14])); // EN is never active
+(* init = "1'b1" *) wire Q14; assign Q[14] = Q14;
+\$_DFFE_NN_ remove14 (.C(C), .D(D), .E(1'b1), .Q(Q14)); // EN is never active
 \$_DFFE_NN_ remove15 (.C(C), .D(D), .E(1'bx), .Q(Q[15])); // EN is don't care
 \$_DFFE_NN_ keep16 (.C(C), .D(D), .E(1'b0), .Q(Q[16])); // EN is always active
-initial Q[17] = 1'b0;
-\$_DFFE_NN_ keep17 (.C(C), .D(D), .E(1'b0), .Q(Q[17])); // EN is always active
+(* init = "1'b0" *) wire Q17; assign Q[17] = Q17;
+\$_DFFE_NN_ keep17 (.C(C), .D(D), .E(1'b0), .Q(Q17)); // EN is always active
 
 \$dffe #(.WIDTH(1), .CLK_POLARITY(1), .EN_POLARITY(1)) remove18 (.CLK(1'b0), .D(D), .EN(E), .Q(Q[18])); // CLK is constant
-initial Q[19] = 1'b1;
-\$dffe #(.WIDTH(1), .CLK_POLARITY(1), .EN_POLARITY(1)) remove19 (.CLK(1'b1), .D(D), .EN(E), .Q(Q[19])); // CLK is constant
+(* init = "1'b1" *) wire Q19; assign Q[19] = Q19;
+\$dffe #(.WIDTH(1), .CLK_POLARITY(1), .EN_POLARITY(1)) remove19 (.CLK(1'b1), .D(D), .EN(E), .Q(Q19)); // CLK is constant
 \$dffe #(.WIDTH(1), .CLK_POLARITY(1), .EN_POLARITY(1)) remove20 (.CLK(C), .D(1'bx), .EN(E), .Q(Q[20])); // D is undriven, Q has no initial value
-initial Q[21] = 1'b0;
-\$dffe #(.WIDTH(1), .CLK_POLARITY(1), .EN_POLARITY(1)) keep21 (.CLK(C), .D(1'bx), .EN(E), .Q(Q[21])); // D is undriven, Q has initial value
+(* init = "1'b0" *) wire Q21; assign Q[21] = Q21;
+\$dffe #(.WIDTH(1), .CLK_POLARITY(1), .EN_POLARITY(1)) keep21 (.CLK(C), .D(1'bx), .EN(E), .Q(Q21)); // D is undriven, Q has initial value
 //\$dffe #(.WIDTH(1), .CLK_POLARITY(0), .EN_POLARITY(1)) remove22 (.CLK(C), .D(1'b0), .EN(1'b1), .Q(Q[22])); // D is constant, no initial Q value, EN is always active
 //                                                                                                           // (TODO, Q starts with 1'bx and becomes 1'b0)
-initial Q[23] = 1'b0;
-\$dffe #(.WIDTH(1), .CLK_POLARITY(1), .EN_POLARITY(1)) noenable23 (.CLK(C), .D(1'b0), .EN(1'b1), .Q(Q[23])); // D is constant, initial Q value same as D, EN is always active
-initial Q[24] = 1'b1;
-\$dffe #(.WIDTH(1), .CLK_POLARITY(1), .EN_POLARITY(0)) keep24 (.CLK(C), .D(1'b0), .EN(1'b0), .Q(Q[24])); // D is constant, initial Q value NOT same as D, EN is always active
-initial Q[25] = 1'b1;
-\$dffe #(.WIDTH(1), .CLK_POLARITY(1), .EN_POLARITY(0)) remove25 (.CLK(C), .D(1'b0), .EN(1'b1), .Q(Q[25])); // D is constant, EN is never active
+(* init = "1'b0" *) wire Q23; assign Q[23] = Q23;
+\$dffe #(.WIDTH(1), .CLK_POLARITY(1), .EN_POLARITY(1)) noenable23 (.CLK(C), .D(1'b0), .EN(1'b1), .Q(Q23)); // D is constant, initial Q value same as D, EN is always active
+(* init = "1'b1" *) wire Q24; assign Q[24] = Q24;
+\$dffe #(.WIDTH(1), .CLK_POLARITY(1), .EN_POLARITY(0)) keep24 (.CLK(C), .D(1'b0), .EN(1'b0), .Q(Q24)); // D is constant, initial Q value NOT same as D, EN is always active
+(* init = "1'b1" *) wire Q25; assign Q[25] = Q25;
+\$dffe #(.WIDTH(1), .CLK_POLARITY(1), .EN_POLARITY(0)) remove25 (.CLK(C), .D(1'b0), .EN(1'b1), .Q(Q25)); // D is constant, EN is never active
 \$dffe #(.WIDTH(1), .CLK_POLARITY(1), .EN_POLARITY(1)) remove26 (.CLK(C), .D(Q[26]), .EN(1'b1), .Q(Q[26])); // D is Q, EN is always active
 \$dffe #(.WIDTH(1), .CLK_POLARITY(1), .EN_POLARITY(0)) remove27 (.CLK(C), .D(Q[27]), .EN(1'b1), .Q(Q[27])); // D is Q, EN is never active, but no initial value
 \$dffe #(.WIDTH(1), .CLK_POLARITY(1), .EN_POLARITY(0)) remove28 (.CLK(C), .D(Q[28]), .EN(E), .Q(Q[28])); // EN is nonconst, but no initial value
-initial Q[29] = 1'b1;
-\$dffe #(.WIDTH(1), .CLK_POLARITY(1), .EN_POLARITY(1)) keep29 (.CLK(C), .D(Q[29]), .EN(1'b1), .Q(Q[29])); // EN is always active, but with initial value
+(* init = "1'b1" *) wire Q29; assign Q[29] = Q29;
+\$dffe #(.WIDTH(1), .CLK_POLARITY(1), .EN_POLARITY(1)) keep29 (.CLK(C), .D(Q[29]), .EN(1'b1), .Q(Q29)); // EN is always active, but with initial value
 
 endmodule
-- 
cgit v1.2.3


From c5fe04acfde6e0f8c4c8f3d77a917a5918e8b839 Mon Sep 17 00:00:00 2001
From: Stefan Biereigel <stefan@biereigel.de>
Date: Mon, 27 May 2019 18:10:39 +0200
Subject: remove port direction workaround from test case

---
 tests/various/wandwor.v | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

(limited to 'tests')

diff --git a/tests/various/wandwor.v b/tests/various/wandwor.v
index 824f89683..d1dca6269 100644
--- a/tests/various/wandwor.v
+++ b/tests/various/wandwor.v
@@ -17,7 +17,6 @@ module c;
 
 
     wand E;
-    wire E_wire = E;
     
     genvar i;
     for (i = 0; i < 3; i = i + 1)
@@ -27,7 +26,7 @@ module c;
         );
         
         b b_inst (
-            .D(E_wire)
+            .D(E)
         );
     end
 
-- 
cgit v1.2.3


From f68b658b4b88b9a71377d19d7d693f07eccf433e Mon Sep 17 00:00:00 2001
From: Stefan Biereigel <stefan@biereigel.de>
Date: Mon, 27 May 2019 18:45:54 +0200
Subject: reformat wand/wor test

---
 tests/various/wandwor.v | 43 +++++++++++++++++++++----------------------
 1 file changed, 21 insertions(+), 22 deletions(-)

(limited to 'tests')

diff --git a/tests/various/wandwor.v b/tests/various/wandwor.v
index d1dca6269..fc072daa3 100644
--- a/tests/various/wandwor.v
+++ b/tests/various/wandwor.v
@@ -1,34 +1,33 @@
 module a(Q);
-    output wire Q;
-
-    assign Q = 0;
+	output wire Q = 0;
 endmodule
 
 module b(D);
-    input wire D;
+	input wire D;
 endmodule
 
 module c;
-    wor D;
-    assign D = 1;
-    assign D = 0;
-    assign D = 1;
-    assign D = 0;
+	// net definitions
+	wor D;
+	wand E;
+
+	// assignments to wired logic nets
+	assign D = 1;
+	assign D = 0;
+	assign D = 1;
+	assign D = 0;
 
+	// assignments of wired logic nets to wires
+	wire F = E;
 
-    wand E;
-    
-    genvar i;
-    for (i = 0; i < 3; i = i + 1)
-    begin :genloop
-        a a_inst (
-            .Q(E)
-        );
-        
-        b b_inst (
-            .D(E)
-        );
-    end
+	genvar i;
+	for (i = 0; i < 3; i = i + 1)
+	begin : genloop
+		// connection of module outputs
+		a a_inst (.Q(E));
 
+		// connection of module inputs
+		b b_inst (.D(E));
+	end
 endmodule
 
-- 
cgit v1.2.3


From e3ebac44df5bcbd976c7f88f2192d69a337ac3bf Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Tue, 28 May 2019 16:42:50 +0200
Subject: Add actual wandwor test that is part of "make test"

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 tests/simple/wandwor.v  | 36 ++++++++++++++++++++++++++++++++++++
 tests/various/wandwor.v | 33 ---------------------------------
 2 files changed, 36 insertions(+), 33 deletions(-)
 create mode 100644 tests/simple/wandwor.v
 delete mode 100644 tests/various/wandwor.v

(limited to 'tests')

diff --git a/tests/simple/wandwor.v b/tests/simple/wandwor.v
new file mode 100644
index 000000000..34404aa26
--- /dev/null
+++ b/tests/simple/wandwor.v
@@ -0,0 +1,36 @@
+module wandwor_test0 (A, B, C, D, X, Y, Z);
+	input A, B, C, D;
+	output wor X;
+	output wand Y;
+	output Z;
+
+	assign X = A, X = B, Y = C, Y = D;
+	foo foo_0 (C, D, X);
+	foo foo_1 (A, B, Y);
+	foo foo_2 (X, Y, Z);
+endmodule
+
+module wandwor_test1 (A, B, C, D, X, Y, Z);
+	input [3:0] A, B, C, D;
+	output wor [3:0] X;
+	output wand [3:0] Y;
+	output Z;
+
+	bar bar_inst (
+		.I0({A, B}),
+		.I1({B, A}),
+		.O({X, Y})
+	);
+
+	assign X = C, X = D;
+	assign Y = C, Y = D;
+	assign Z = ^{X,Y};
+endmodule
+
+module foo(input I0, I1, output O);
+	assign O = I0 ^ I1;
+endmodule
+
+module bar(input [7:0] I0, I1, output [7:0] O);
+	assign O = I0 + I1;
+endmodule
diff --git a/tests/various/wandwor.v b/tests/various/wandwor.v
deleted file mode 100644
index fc072daa3..000000000
--- a/tests/various/wandwor.v
+++ /dev/null
@@ -1,33 +0,0 @@
-module a(Q);
-	output wire Q = 0;
-endmodule
-
-module b(D);
-	input wire D;
-endmodule
-
-module c;
-	// net definitions
-	wor D;
-	wand E;
-
-	// assignments to wired logic nets
-	assign D = 1;
-	assign D = 0;
-	assign D = 1;
-	assign D = 0;
-
-	// assignments of wired logic nets to wires
-	wire F = E;
-
-	genvar i;
-	for (i = 0; i < 3; i = i + 1)
-	begin : genloop
-		// connection of module outputs
-		a a_inst (.Q(E));
-
-		// connection of module inputs
-		b b_inst (.D(E));
-	end
-endmodule
-
-- 
cgit v1.2.3


From cb285e4b87112779efe84a7b6c5ae4a76a69ae01 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Tue, 28 May 2019 15:33:47 +0200
Subject: Do not use shiftmul peepopt pattern when mul result is truncated,
 fixes #1047

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 tests/simple/peepopt.v | 4 ++++
 1 file changed, 4 insertions(+)

(limited to 'tests')

diff --git a/tests/simple/peepopt.v b/tests/simple/peepopt.v
index b27b9fe57..1bf427897 100644
--- a/tests/simple/peepopt.v
+++ b/tests/simple/peepopt.v
@@ -2,6 +2,10 @@ module peepopt_shiftmul_0 #(parameter N=3, parameter W=3) (input [N*W-1:0] i, in
 assign o = i[s*W+:W];
 endmodule
 
+module peepopt_shiftmul_1 (output y, input [2:0] w);
+assign y = 1'b1 >> (w * (3'b110));
+endmodule
+
 module peepopt_muldiv_0(input [1:0] i, output [1:0] o);
 wire [3:0] t;
 assign t = i * 3;
-- 
cgit v1.2.3


From 5739cf52650ccb3627868d9c9d7e02888efad12b Mon Sep 17 00:00:00 2001
From: Maciej Kurc <mkurc@antmicro.com>
Date: Mon, 3 Jun 2019 09:12:51 +0200
Subject: Added tests for attributes

Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
---
 tests/simple/attrib01_module.v             | 21 ++++++++++++++++++++
 tests/simple/attrib02_port_decl.v          | 25 +++++++++++++++++++++++
 tests/simple/attrib03_parameter.v          | 28 ++++++++++++++++++++++++++
 tests/simple/attrib04_net_var.v            | 32 ++++++++++++++++++++++++++++++
 tests/simple/attrib05_port_conn.v.DISABLED | 21 ++++++++++++++++++++
 tests/simple/attrib06_operator_suffix.v    | 23 +++++++++++++++++++++
 tests/simple/attrib07_func_call.v.DISABLED | 21 ++++++++++++++++++++
 tests/simple/attrib08_mod_inst.v           | 22 ++++++++++++++++++++
 tests/simple/attrib09_case.v               | 26 ++++++++++++++++++++++++
 9 files changed, 219 insertions(+)
 create mode 100644 tests/simple/attrib01_module.v
 create mode 100644 tests/simple/attrib02_port_decl.v
 create mode 100644 tests/simple/attrib03_parameter.v
 create mode 100644 tests/simple/attrib04_net_var.v
 create mode 100644 tests/simple/attrib05_port_conn.v.DISABLED
 create mode 100644 tests/simple/attrib06_operator_suffix.v
 create mode 100644 tests/simple/attrib07_func_call.v.DISABLED
 create mode 100644 tests/simple/attrib08_mod_inst.v
 create mode 100644 tests/simple/attrib09_case.v

(limited to 'tests')

diff --git a/tests/simple/attrib01_module.v b/tests/simple/attrib01_module.v
new file mode 100644
index 000000000..adef34f5b
--- /dev/null
+++ b/tests/simple/attrib01_module.v
@@ -0,0 +1,21 @@
+module bar(clk, rst, inp, out);
+  input  wire clk;
+  input  wire rst;
+  input  wire inp;
+  output reg  out;
+
+  always @(posedge clk)
+    if (rst) out <= 1'd0;
+    else     out <= ~inp;
+
+endmodule
+
+module foo(clk, rst, inp, out);
+  input  wire clk;
+  input  wire rst;
+  input  wire inp;
+  output wire out;
+
+  bar bar_instance (clk, rst, inp, out);
+endmodule
+
diff --git a/tests/simple/attrib02_port_decl.v b/tests/simple/attrib02_port_decl.v
new file mode 100644
index 000000000..3505e7265
--- /dev/null
+++ b/tests/simple/attrib02_port_decl.v
@@ -0,0 +1,25 @@
+module bar(clk, rst, inp, out);
+  (* this_is_clock = 1 *)
+  input  wire clk;
+  (* this_is_reset = 1 *)
+  input  wire rst;
+  input  wire inp;
+  (* an_output_register = 1*)
+  output reg  out;
+
+  always @(posedge clk)
+    if (rst) out <= 1'd0;
+    else     out <= ~inp;
+
+endmodule
+
+module foo(clk, rst, inp, out);
+  (* this_is_the_master_clock *)
+  input  wire clk;
+  input  wire rst;
+  input  wire inp;
+  output wire out;
+
+  bar bar_instance (clk, rst, inp, out);
+endmodule
+
diff --git a/tests/simple/attrib03_parameter.v b/tests/simple/attrib03_parameter.v
new file mode 100644
index 000000000..562d225cd
--- /dev/null
+++ b/tests/simple/attrib03_parameter.v
@@ -0,0 +1,28 @@
+module bar(clk, rst, inp, out);
+
+  (* bus_width *)
+  parameter WIDTH = 2;
+
+  (* an_attribute_on_localparam = 55 *)
+  localparam INCREMENT = 5;
+
+  input  wire clk;
+  input  wire rst;
+  input  wire [WIDTH-1:0] inp;
+  output reg  [WIDTH-1:0] out;
+
+  always @(posedge clk)
+    if (rst) out <= 0;
+    else     out <= inp + INCREMENT;
+
+endmodule
+
+module foo(clk, rst, inp, out);
+  input  wire clk;
+  input  wire rst;
+  input  wire [7:0] inp;
+  output wire [7:0] out;
+
+  bar # (.WIDTH(8)) bar_instance (clk, rst, inp, out);
+endmodule
+
diff --git a/tests/simple/attrib04_net_var.v b/tests/simple/attrib04_net_var.v
new file mode 100644
index 000000000..8b5523406
--- /dev/null
+++ b/tests/simple/attrib04_net_var.v
@@ -0,0 +1,32 @@
+module bar(clk, rst, inp, out);
+  input  wire clk;
+  input  wire rst;
+  input  wire inp;
+  output reg  out;
+
+  (* this_is_a_prescaler *)
+  reg [7:0] counter;
+
+  (* temp_wire *)
+  wire out_val;
+
+  always @(posedge clk)
+    counter <= counter + 1;
+
+  assign out_val = inp ^ counter[4];
+
+  always @(posedge clk)
+    if (rst) out <= 1'd0;
+    else     out <= out_val;
+
+endmodule
+
+module foo(clk, rst, inp, out);
+  input  wire clk;
+  input  wire rst;
+  input  wire inp;
+  output wire out;
+
+  bar bar_instance (clk, rst, inp, out);
+endmodule
+
diff --git a/tests/simple/attrib05_port_conn.v.DISABLED b/tests/simple/attrib05_port_conn.v.DISABLED
new file mode 100644
index 000000000..e20e66319
--- /dev/null
+++ b/tests/simple/attrib05_port_conn.v.DISABLED
@@ -0,0 +1,21 @@
+module bar(clk, rst, inp, out);
+  input  wire clk;
+  input  wire rst;
+  input  wire inp;
+  output reg  out;
+
+  always @(posedge clk)
+    if (rst) out <= 1'd0;
+    else     out <= ~inp;
+
+endmodule
+
+module foo(clk, rst, inp, out);
+  input  wire clk;
+  input  wire rst;
+  input  wire inp;
+  output wire out;
+
+  bar bar_instance ( (* clock_connected *) clk, rst, (* this_is_the_input *) inp, out);
+endmodule
+
diff --git a/tests/simple/attrib06_operator_suffix.v b/tests/simple/attrib06_operator_suffix.v
new file mode 100644
index 000000000..e21173c58
--- /dev/null
+++ b/tests/simple/attrib06_operator_suffix.v
@@ -0,0 +1,23 @@
+module bar(clk, rst, inp_a, inp_b, out);
+  input  wire clk;
+  input  wire rst;
+  input  wire [7:0] inp_a;
+  input  wire [7:0] inp_b;
+  output reg  [7:0] out;
+
+  always @(posedge clk)
+    if (rst) out <= 0;
+    else     out <= inp_a + (* ripple_adder *) inp_b;
+
+endmodule
+
+module foo(clk, rst, inp_a, inp_b, out);
+  input  wire clk;
+  input  wire rst;
+  input  wire [7:0] inp_a;
+  input  wire [7:0] inp_b;
+  output wire [7:0] out;
+
+  bar bar_instance (clk, rst, inp_a, inp_b, out);
+endmodule
+
diff --git a/tests/simple/attrib07_func_call.v.DISABLED b/tests/simple/attrib07_func_call.v.DISABLED
new file mode 100644
index 000000000..f55ef2316
--- /dev/null
+++ b/tests/simple/attrib07_func_call.v.DISABLED
@@ -0,0 +1,21 @@
+function [7:0] do_add;
+  input [7:0] inp_a;
+  input [7:0] inp_b;
+
+  do_add = inp_a + inp_b;
+
+endfunction
+
+module foo(clk, rst, inp_a, inp_b, out);
+  input  wire clk;
+  input  wire rst;
+  input  wire [7:0] inp_a;
+  input  wire [7:0] inp_b;
+  output wire [7:0] out;
+
+  always @(posedge clk)
+    if (rst) out <= 0;
+    else     out <= do_add (* combinational_adder *) (inp_a, inp_b);
+
+endmodule
+
diff --git a/tests/simple/attrib08_mod_inst.v b/tests/simple/attrib08_mod_inst.v
new file mode 100644
index 000000000..c5a32234e
--- /dev/null
+++ b/tests/simple/attrib08_mod_inst.v
@@ -0,0 +1,22 @@
+module bar(clk, rst, inp, out);
+  input  wire clk;
+  input  wire rst;
+  input  wire inp;
+  output reg  out;
+
+  always @(posedge clk)
+    if (rst) out <= 1'd0;
+    else     out <= ~inp;
+
+endmodule
+
+module foo(clk, rst, inp, out);
+  input  wire clk;
+  input  wire rst;
+  input  wire inp;
+  output wire out;
+
+  (* my_module_instance = 99 *)
+  bar bar_instance (clk, rst, inp, out);
+endmodule
+
diff --git a/tests/simple/attrib09_case.v b/tests/simple/attrib09_case.v
new file mode 100644
index 000000000..8551bf9d0
--- /dev/null
+++ b/tests/simple/attrib09_case.v
@@ -0,0 +1,26 @@
+module bar(clk, rst, inp, out);
+  input  wire clk;
+  input  wire rst;
+  input  wire [1:0] inp;
+  output reg  [1:0] out;
+
+  always @(inp)
+    (* full_case, parallel_case *)
+    case(inp)
+      2'd0: out <= 2'd3;
+      2'd1: out <= 2'd2;
+      2'd2: out <= 2'd1;
+      2'd3: out <= 2'd0;
+    endcase
+
+endmodule
+
+module foo(clk, rst, inp, out);
+  input  wire clk;
+  input  wire rst;
+  input  wire [1:0] inp;
+  output wire [1:0] out;
+
+  bar bar_instance (clk, rst, inp, out);
+endmodule
+
-- 
cgit v1.2.3


From b79bd5b3ca086718e308c75cbece0b07bbe48733 Mon Sep 17 00:00:00 2001
From: Maciej Kurc <mkurc@antmicro.com>
Date: Tue, 4 Jun 2019 10:42:42 +0200
Subject: Moved tests that fail with Icarus Verilog to /tests/various. Those
 tests are just for parsing Verilog.

Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
---
 tests/various/attrib05_port_conn.v  | 21 +++++++++++++++++++++
 tests/various/attrib05_port_conn.ys |  2 ++
 tests/various/attrib07_func_call.v  | 21 +++++++++++++++++++++
 tests/various/attrib07_func_call.ys |  2 ++
 4 files changed, 46 insertions(+)
 create mode 100644 tests/various/attrib05_port_conn.v
 create mode 100644 tests/various/attrib05_port_conn.ys
 create mode 100644 tests/various/attrib07_func_call.v
 create mode 100644 tests/various/attrib07_func_call.ys

(limited to 'tests')

diff --git a/tests/various/attrib05_port_conn.v b/tests/various/attrib05_port_conn.v
new file mode 100644
index 000000000..e20e66319
--- /dev/null
+++ b/tests/various/attrib05_port_conn.v
@@ -0,0 +1,21 @@
+module bar(clk, rst, inp, out);
+  input  wire clk;
+  input  wire rst;
+  input  wire inp;
+  output reg  out;
+
+  always @(posedge clk)
+    if (rst) out <= 1'd0;
+    else     out <= ~inp;
+
+endmodule
+
+module foo(clk, rst, inp, out);
+  input  wire clk;
+  input  wire rst;
+  input  wire inp;
+  output wire out;
+
+  bar bar_instance ( (* clock_connected *) clk, rst, (* this_is_the_input *) inp, out);
+endmodule
+
diff --git a/tests/various/attrib05_port_conn.ys b/tests/various/attrib05_port_conn.ys
new file mode 100644
index 000000000..27a016733
--- /dev/null
+++ b/tests/various/attrib05_port_conn.ys
@@ -0,0 +1,2 @@
+# Read and parse Verilog file
+read_verilog attrib05_port_conn.v
diff --git a/tests/various/attrib07_func_call.v b/tests/various/attrib07_func_call.v
new file mode 100644
index 000000000..f55ef2316
--- /dev/null
+++ b/tests/various/attrib07_func_call.v
@@ -0,0 +1,21 @@
+function [7:0] do_add;
+  input [7:0] inp_a;
+  input [7:0] inp_b;
+
+  do_add = inp_a + inp_b;
+
+endfunction
+
+module foo(clk, rst, inp_a, inp_b, out);
+  input  wire clk;
+  input  wire rst;
+  input  wire [7:0] inp_a;
+  input  wire [7:0] inp_b;
+  output wire [7:0] out;
+
+  always @(posedge clk)
+    if (rst) out <= 0;
+    else     out <= do_add (* combinational_adder *) (inp_a, inp_b);
+
+endmodule
+
diff --git a/tests/various/attrib07_func_call.ys b/tests/various/attrib07_func_call.ys
new file mode 100644
index 000000000..774827651
--- /dev/null
+++ b/tests/various/attrib07_func_call.ys
@@ -0,0 +1,2 @@
+# Read and parse Verilog file
+read_verilog attrib07_func_call.v
-- 
cgit v1.2.3


From 88f59770932720cfc1e987c98e53faedd7388ed8 Mon Sep 17 00:00:00 2001
From: tux3 <barrdetwix@gmail.com>
Date: Wed, 5 Jun 2019 00:47:54 +0200
Subject: SystemVerilog support for implicit named port connections

This is the `foo foo(.port1, .port2);` SystemVerilog syntax
introduced in IEEE1800-2005.
---
 tests/simple/run-test.sh        |  3 ++-
 tests/tools/autotest.sh         | 15 +++++++++++++--
 tests/various/implicit_ports.sv | 19 +++++++++++++++++++
 tests/various/implicit_ports.ys |  8 ++++++++
 4 files changed, 42 insertions(+), 3 deletions(-)
 create mode 100644 tests/various/implicit_ports.sv
 create mode 100644 tests/various/implicit_ports.ys

(limited to 'tests')

diff --git a/tests/simple/run-test.sh b/tests/simple/run-test.sh
index aaa1cf940..967ac49f2 100755
--- a/tests/simple/run-test.sh
+++ b/tests/simple/run-test.sh
@@ -17,4 +17,5 @@ if ! which iverilog > /dev/null ; then
   exit 1
 fi
 
-exec ${MAKE:-make} -f ../tools/autotest.mk $seed *.v
+shopt -s nullglob
+exec ${MAKE:-make} -f ../tools/autotest.mk $seed *.{sv,v}
diff --git a/tests/tools/autotest.sh b/tests/tools/autotest.sh
index 920474a84..0a511f29c 100755
--- a/tests/tools/autotest.sh
+++ b/tests/tools/autotest.sh
@@ -89,6 +89,13 @@ done
 
 compile_and_run() {
 	exe="$1"; output="$2"; shift 2
+	ext=${1##*.}
+	if [ "$ext" == "sv" ]; then
+		language_gen="-g2012"
+	else
+		language_gen="-g2005"
+	fi
+
 	if $use_modelsim; then
 		altver=$( ls -v /opt/altera/ | grep '^[0-9]' | tail -n1; )
 		/opt/altera/$altver/modelsim_ase/bin/vlib work
@@ -99,7 +106,7 @@ compile_and_run() {
 		/opt/Xilinx/Vivado/$xilver/bin/xvlog $xinclude_opts -d outfile=\"$output\" "$@"
 		/opt/Xilinx/Vivado/$xilver/bin/xelab -R work.testbench
 	else
-		iverilog $include_opts -Doutfile=\"$output\" -s testbench -o "$exe" "$@"
+		iverilog $language_gen $include_opts -Doutfile=\"$output\" -s testbench -o "$exe" "$@"
 		vvp -n "$exe"
 	fi
 }
@@ -110,7 +117,7 @@ for fn
 do
 	bn=${fn%.*}
 	ext=${fn##*.}
-	if [[ "$ext" != "v" ]] && [[ "$ext" != "aag" ]] && [[ "$ext" != "aig" ]]; then
+	if [[ "$ext" != "v" ]] && [[ "$ext" != "sv" ]] && [[ "$ext" != "aag" ]] && [[ "$ext" != "aig" ]]; then
 		echo "Invalid argument: $fn" >&2
 		exit 1
 	fi
@@ -123,6 +130,10 @@ do
 		echo -n "Test: $bn "
 	fi
 
+	if [ "$ext" == sv ]; then
+		frontend="$frontend -sv"
+	fi
+
 	rm -f ${bn}.{err,log,skip}
 	mkdir -p ${bn}.out
 	rm -rf ${bn}.out/*
diff --git a/tests/various/implicit_ports.sv b/tests/various/implicit_ports.sv
new file mode 100644
index 000000000..6a766bd51
--- /dev/null
+++ b/tests/various/implicit_ports.sv
@@ -0,0 +1,19 @@
+// Test implicit port connections
+module alu (input [2:0] a, input [2:0] b, input cin, output cout, output [2:0] result);
+	assign cout = cin;
+	assign result = a + b;
+endmodule
+
+module named_ports(output [2:0] alu_result, output cout);
+	wire [2:0] a = 3'b010, b = 3'b100;
+	wire cin = 1;
+
+	alu alu (
+		.a(a),
+		.b, // Implicit connection is equivalent to .b(b)
+		.cin(), // Explicitely unconnected
+		.cout(cout),
+		.result(alu_result)
+	);
+endmodule
+
diff --git a/tests/various/implicit_ports.ys b/tests/various/implicit_ports.ys
new file mode 100644
index 000000000..7b4764921
--- /dev/null
+++ b/tests/various/implicit_ports.ys
@@ -0,0 +1,8 @@
+read_verilog -sv implicit_ports.sv
+proc; opt
+
+flatten
+select -module named_ports
+
+sat -verify -prove alu_result 6
+sat -verify -set-all-undef cout
-- 
cgit v1.2.3


From a0b57f2a6ffae3b5770e38bf5a9af0df50db8522 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Fri, 7 Jun 2019 11:46:16 +0200
Subject: Cleanup tux3-implicit_named_connection

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 tests/simple/implicit_ports.sv  | 16 ++++++++++++++++
 tests/various/implicit_ports.sv | 19 -------------------
 tests/various/implicit_ports.ys |  8 --------
 3 files changed, 16 insertions(+), 27 deletions(-)
 create mode 100644 tests/simple/implicit_ports.sv
 delete mode 100644 tests/various/implicit_ports.sv
 delete mode 100644 tests/various/implicit_ports.ys

(limited to 'tests')

diff --git a/tests/simple/implicit_ports.sv b/tests/simple/implicit_ports.sv
new file mode 100644
index 000000000..8b0a6f386
--- /dev/null
+++ b/tests/simple/implicit_ports.sv
@@ -0,0 +1,16 @@
+// Test implicit port connections
+module alu (input [2:0] a, input [2:0] b, input cin, output cout, output [2:0] result);
+	assign cout = cin;
+	assign result = a + b;
+endmodule
+
+module named_ports(input [2:0] a, b, output [2:0] alu_result, output cout);
+	wire cin = 1;
+	alu alu (
+		.a(a),
+		.b, // Implicit connection is equivalent to .b(b)
+		.cin(), // Explicitely unconnected
+		.cout(cout),
+		.result(alu_result)
+	);
+endmodule
diff --git a/tests/various/implicit_ports.sv b/tests/various/implicit_ports.sv
deleted file mode 100644
index 6a766bd51..000000000
--- a/tests/various/implicit_ports.sv
+++ /dev/null
@@ -1,19 +0,0 @@
-// Test implicit port connections
-module alu (input [2:0] a, input [2:0] b, input cin, output cout, output [2:0] result);
-	assign cout = cin;
-	assign result = a + b;
-endmodule
-
-module named_ports(output [2:0] alu_result, output cout);
-	wire [2:0] a = 3'b010, b = 3'b100;
-	wire cin = 1;
-
-	alu alu (
-		.a(a),
-		.b, // Implicit connection is equivalent to .b(b)
-		.cin(), // Explicitely unconnected
-		.cout(cout),
-		.result(alu_result)
-	);
-endmodule
-
diff --git a/tests/various/implicit_ports.ys b/tests/various/implicit_ports.ys
deleted file mode 100644
index 7b4764921..000000000
--- a/tests/various/implicit_ports.ys
+++ /dev/null
@@ -1,8 +0,0 @@
-read_verilog -sv implicit_ports.sv
-proc; opt
-
-flatten
-select -module named_ports
-
-sat -verify -prove alu_result 6
-sat -verify -set-all-undef cout
-- 
cgit v1.2.3


From f01a61f093528e5111e5dac8aedbf8c7c468be1c Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Fri, 7 Jun 2019 13:12:25 +0200
Subject: Rename implicit_ports.sv test to implicit_ports.v

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 tests/simple/implicit_ports.sv | 16 ----------------
 tests/simple/implicit_ports.v  | 16 ++++++++++++++++
 2 files changed, 16 insertions(+), 16 deletions(-)
 delete mode 100644 tests/simple/implicit_ports.sv
 create mode 100644 tests/simple/implicit_ports.v

(limited to 'tests')

diff --git a/tests/simple/implicit_ports.sv b/tests/simple/implicit_ports.sv
deleted file mode 100644
index 8b0a6f386..000000000
--- a/tests/simple/implicit_ports.sv
+++ /dev/null
@@ -1,16 +0,0 @@
-// Test implicit port connections
-module alu (input [2:0] a, input [2:0] b, input cin, output cout, output [2:0] result);
-	assign cout = cin;
-	assign result = a + b;
-endmodule
-
-module named_ports(input [2:0] a, b, output [2:0] alu_result, output cout);
-	wire cin = 1;
-	alu alu (
-		.a(a),
-		.b, // Implicit connection is equivalent to .b(b)
-		.cin(), // Explicitely unconnected
-		.cout(cout),
-		.result(alu_result)
-	);
-endmodule
diff --git a/tests/simple/implicit_ports.v b/tests/simple/implicit_ports.v
new file mode 100644
index 000000000..8b0a6f386
--- /dev/null
+++ b/tests/simple/implicit_ports.v
@@ -0,0 +1,16 @@
+// Test implicit port connections
+module alu (input [2:0] a, input [2:0] b, input cin, output cout, output [2:0] result);
+	assign cout = cin;
+	assign result = a + b;
+endmodule
+
+module named_ports(input [2:0] a, b, output [2:0] alu_result, output cout);
+	wire cin = 1;
+	alu alu (
+		.a(a),
+		.b, // Implicit connection is equivalent to .b(b)
+		.cin(), // Explicitely unconnected
+		.cout(cout),
+		.result(alu_result)
+	);
+endmodule
-- 
cgit v1.2.3


From 1b113a05742377f5b18d52bc5bf50b1991e88c19 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 7 Jun 2019 11:05:25 -0700
Subject: Add symbols to AIGER test inputs for ABC

---
 tests/aiger/and.aag      | 5 -----
 tests/aiger/and.aig      | 3 ---
 tests/aiger/and_.aag     | 8 ++++++++
 tests/aiger/and_.aig     | 5 +++++
 tests/aiger/buffer.aag   | 2 ++
 tests/aiger/buffer.aig   | 2 ++
 tests/aiger/cnt1.aag     | 1 +
 tests/aiger/cnt1.aig     | 1 +
 tests/aiger/cnt1e.aag    | 1 +
 tests/aiger/cnt1e.aig    | 3 ++-
 tests/aiger/false.aag    | 1 +
 tests/aiger/false.aig    | 1 +
 tests/aiger/inverter.aag | 2 ++
 tests/aiger/inverter.aig | 2 ++
 tests/aiger/notcnt1e.aag | 1 +
 tests/aiger/notcnt1e.aig | 3 ++-
 tests/aiger/or.aag       | 5 -----
 tests/aiger/or.aig       | 3 ---
 tests/aiger/or_.aag      | 8 ++++++++
 tests/aiger/or_.aig      | 5 +++++
 tests/aiger/toggle.aag   | 2 ++
 tests/aiger/toggle.aig   | 2 ++
 tests/aiger/true.aag     | 1 +
 tests/aiger/true.aig     | 1 +
 24 files changed, 50 insertions(+), 18 deletions(-)
 delete mode 100644 tests/aiger/and.aag
 delete mode 100644 tests/aiger/and.aig
 create mode 100644 tests/aiger/and_.aag
 create mode 100644 tests/aiger/and_.aig
 delete mode 100644 tests/aiger/or.aag
 delete mode 100644 tests/aiger/or.aig
 create mode 100644 tests/aiger/or_.aag
 create mode 100644 tests/aiger/or_.aig

(limited to 'tests')

diff --git a/tests/aiger/and.aag b/tests/aiger/and.aag
deleted file mode 100644
index d1ef2c5a5..000000000
--- a/tests/aiger/and.aag
+++ /dev/null
@@ -1,5 +0,0 @@
-aag 3 2 0 1 1
-2
-4
-6
-6 2 4
diff --git a/tests/aiger/and.aig b/tests/aiger/and.aig
deleted file mode 100644
index da0fa0719..000000000
--- a/tests/aiger/and.aig
+++ /dev/null
@@ -1,3 +0,0 @@
-aig 3 2 0 1 1
-6
-
\ No newline at end of file
diff --git a/tests/aiger/and_.aag b/tests/aiger/and_.aag
new file mode 100644
index 000000000..cadd505f0
--- /dev/null
+++ b/tests/aiger/and_.aag
@@ -0,0 +1,8 @@
+aag 3 2 0 1 1
+2
+4
+6
+6 2 4
+i0 pi0
+i1 pi1
+o0 po0
diff --git a/tests/aiger/and_.aig b/tests/aiger/and_.aig
new file mode 100644
index 000000000..13c7a0c17
--- /dev/null
+++ b/tests/aiger/and_.aig
@@ -0,0 +1,5 @@
+aig 3 2 0 1 1
+6
+i0 pi0
+i1 pi1
+o0 po0
diff --git a/tests/aiger/buffer.aag b/tests/aiger/buffer.aag
index 94a6fb1ed..211106ed6 100644
--- a/tests/aiger/buffer.aag
+++ b/tests/aiger/buffer.aag
@@ -1,3 +1,5 @@
 aag 1 1 0 1 0
 2
 2
+i0 pi0
+o0 po0
diff --git a/tests/aiger/buffer.aig b/tests/aiger/buffer.aig
index 0c715fdeb..01df6f1cf 100644
--- a/tests/aiger/buffer.aig
+++ b/tests/aiger/buffer.aig
@@ -1,2 +1,4 @@
 aig 1 1 0 1 0
 2
+i0 pi0
+o0 po0
diff --git a/tests/aiger/cnt1.aag b/tests/aiger/cnt1.aag
index ce4f28fcb..75598862c 100644
--- a/tests/aiger/cnt1.aag
+++ b/tests/aiger/cnt1.aag
@@ -1,3 +1,4 @@
 aag 1 0 1 0 0 1
 2 3
 2
+b0 po0
diff --git a/tests/aiger/cnt1.aig b/tests/aiger/cnt1.aig
index 8d0ba13b1..6fcf62522 100644
--- a/tests/aiger/cnt1.aig
+++ b/tests/aiger/cnt1.aig
@@ -1,3 +1,4 @@
 aig 1 0 1 0 0 1
 3
 2
+b0 po0
diff --git a/tests/aiger/cnt1e.aag b/tests/aiger/cnt1e.aag
index 6db3f0ffd..35cd5a482 100644
--- a/tests/aiger/cnt1e.aag
+++ b/tests/aiger/cnt1e.aag
@@ -6,3 +6,4 @@ aag 5 1 1 0 3 1
 8 4 2
 10 9 7
 b0 AIGER_NEVER
+i0 po0
diff --git a/tests/aiger/cnt1e.aig b/tests/aiger/cnt1e.aig
index d8d159f11..7284dd42a 100644
--- a/tests/aiger/cnt1e.aig
+++ b/tests/aiger/cnt1e.aig
@@ -1,4 +1,5 @@
 aig 5 1 1 0 3 1
 10
 4
-

b0 AIGER_NEVER
+

i0 po0
+b0 AIGER_NEVER
diff --git a/tests/aiger/false.aag b/tests/aiger/false.aag
index 421e64a91..bab4a06a6 100644
--- a/tests/aiger/false.aag
+++ b/tests/aiger/false.aag
@@ -1,2 +1,3 @@
 aag 0 0 0 1 0
 0
+o0 po0
diff --git a/tests/aiger/false.aig b/tests/aiger/false.aig
index ad7d039fa..4dc442d7b 100644
--- a/tests/aiger/false.aig
+++ b/tests/aiger/false.aig
@@ -1,2 +1,3 @@
 aig 0 0 0 1 0
 0
+o0 po0
diff --git a/tests/aiger/inverter.aag b/tests/aiger/inverter.aag
index ff7c28542..428bad9e4 100644
--- a/tests/aiger/inverter.aag
+++ b/tests/aiger/inverter.aag
@@ -1,3 +1,5 @@
 aag 1 1 0 1 0
 2
 3
+i0 pi0
+o0 po0
diff --git a/tests/aiger/inverter.aig b/tests/aiger/inverter.aig
index 525d82392..5bec90ae3 100644
--- a/tests/aiger/inverter.aig
+++ b/tests/aiger/inverter.aig
@@ -1,2 +1,4 @@
 aig 1 1 0 1 0
 3
+i0 pi0
+o0 po0
diff --git a/tests/aiger/notcnt1e.aag b/tests/aiger/notcnt1e.aag
index 141c864f7..2ed645d84 100644
--- a/tests/aiger/notcnt1e.aag
+++ b/tests/aiger/notcnt1e.aag
@@ -6,3 +6,4 @@ aag 5 1 1 0 3 1
 8 4 2
 10 9 7
 b0 AIGER_NEVER
+i0 pi0
diff --git a/tests/aiger/notcnt1e.aig b/tests/aiger/notcnt1e.aig
index 7c85a7290..fd7e94508 100644
--- a/tests/aiger/notcnt1e.aig
+++ b/tests/aiger/notcnt1e.aig
@@ -1,4 +1,5 @@
 aig 5 1 1 0 3 1
 10
 5
-

b0 AIGER_NEVER
+

i0 pi0
+b0 AIGER_NEVER
diff --git a/tests/aiger/or.aag b/tests/aiger/or.aag
deleted file mode 100644
index f780e339f..000000000
--- a/tests/aiger/or.aag
+++ /dev/null
@@ -1,5 +0,0 @@
-aag 3 2 0 1 1
-2
-4
-7
-6 3 5
diff --git a/tests/aiger/or.aig b/tests/aiger/or.aig
deleted file mode 100644
index 75c9e4480..000000000
--- a/tests/aiger/or.aig
+++ /dev/null
@@ -1,3 +0,0 @@
-aig 3 2 0 1 1
-7
-

\ No newline at end of file
diff --git a/tests/aiger/or_.aag b/tests/aiger/or_.aag
new file mode 100644
index 000000000..0f619dba3
--- /dev/null
+++ b/tests/aiger/or_.aag
@@ -0,0 +1,8 @@
+aag 3 2 0 1 1
+2
+4
+7
+6 3 5
+i0 pi0
+i1 pi1
+o0 po0
diff --git a/tests/aiger/or_.aig b/tests/aiger/or_.aig
new file mode 100644
index 000000000..051687512
--- /dev/null
+++ b/tests/aiger/or_.aig
@@ -0,0 +1,5 @@
+aig 3 2 0 1 1
+7
+
i0 pi0
+i1 pi1
+o0 po0
diff --git a/tests/aiger/toggle.aag b/tests/aiger/toggle.aag
index 09651012d..b1a1582d7 100644
--- a/tests/aiger/toggle.aag
+++ b/tests/aiger/toggle.aag
@@ -2,3 +2,5 @@ aag 1 0 1 2 0
 2 3
 2
 3
+o0 po0
+o1 po1
diff --git a/tests/aiger/toggle.aig b/tests/aiger/toggle.aig
index b69e21aaf..68b41763f 100644
--- a/tests/aiger/toggle.aig
+++ b/tests/aiger/toggle.aig
@@ -2,3 +2,5 @@ aig 1 0 1 2 0
 3
 2
 3
+o0 po0
+o1 po1
diff --git a/tests/aiger/true.aag b/tests/aiger/true.aag
index 366893648..66a9eab46 100644
--- a/tests/aiger/true.aag
+++ b/tests/aiger/true.aag
@@ -1,2 +1,3 @@
 aag 0 0 0 1 0
 1
+o0 po0
diff --git a/tests/aiger/true.aig b/tests/aiger/true.aig
index 10086f389..f9bad6000 100644
--- a/tests/aiger/true.aig
+++ b/tests/aiger/true.aig
@@ -1,2 +1,3 @@
 aig 0 0 0 1 0
 1
+o0 po0
-- 
cgit v1.2.3


From ebe29b66593414d0317879359d1f1d1f61a9ecc4 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 7 Jun 2019 11:05:36 -0700
Subject: Use ABC to convert AIGER to Verilog, then sat against Yosys

---
 tests/aiger/run-test.sh | 36 +++++++++++++++---------------------
 1 file changed, 15 insertions(+), 21 deletions(-)

(limited to 'tests')

diff --git a/tests/aiger/run-test.sh b/tests/aiger/run-test.sh
index e0a34f023..70300d305 100755
--- a/tests/aiger/run-test.sh
+++ b/tests/aiger/run-test.sh
@@ -1,24 +1,18 @@
 #!/bin/bash
 
-OPTIND=1
-seed=""    # default to no seed specified
-while getopts "S:" opt
-do
-    case "$opt" in
-	S) arg="${OPTARG#"${OPTARG%%[![:space:]]*}"}" # remove leading space
-	   seed="SEED=$arg" ;;
-    esac
+set -e
+for aig in *.aig; do
+    ../../yosys-abc -c "read -c $aig; write ${aig%.*}_ref.v"
+    ../../yosys -p "
+read_verilog ${aig%.*}_ref.v
+prep
+design -stash gold
+read_aiger -clk_name clock $aig
+prep
+design -stash gate
+design -import gold -as gold
+design -import gate -as gate
+miter -equiv -flatten -make_assert -make_outputs gold gate miter
+sat -verify -prove-asserts -show-ports -seq 16 miter
+"
 done
-shift "$((OPTIND-1))"
-
-# check for Icarus Verilog
-if ! which iverilog > /dev/null ; then
-  echo "$0: Error: Icarus Verilog 'iverilog' not found."
-  exit 1
-fi
-
-echo "===== AAG ======"
-${MAKE:-make} -f ../tools/autotest.mk $seed *.aag EXTRA_FLAGS="-f aiger"
-
-echo "===== AIG ======"
-exec ${MAKE:-make} -f ../tools/autotest.mk $seed *.aig EXTRA_FLAGS="-f aiger"
-- 
cgit v1.2.3


From abc40924ed5dc4aba91c7f1e83ca90f54e9eb455 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 7 Jun 2019 11:06:57 -0700
Subject: Use ABC to convert from AIGER to Verilog

---
 tests/tools/autotest.sh | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

(limited to 'tests')

diff --git a/tests/tools/autotest.sh b/tests/tools/autotest.sh
index 0a511f29c..23964a751 100755
--- a/tests/tools/autotest.sh
+++ b/tests/tools/autotest.sh
@@ -146,9 +146,10 @@ do
 		rm -f ${bn}_ref.fir
 		if [[ "$ext" == "v" ]]; then
 			egrep -v '^\s*`timescale' ../$fn > ${bn}_ref.${ext}
+		elif [[ "$ext" == "aig" ]] || [[ "$ext" == "aag" ]]; then
+			"$toolsdir"/../../yosys-abc -c "read_aiger ../${fn}; write ${bn}_ref.v"
 		else
-			"$toolsdir"/../../yosys -f "$frontend $include_opts" -b "verilog" -o ${bn}_ref.v ../${fn}
-			frontend="verilog -noblackbox"
+			cp ../${fn} ${bn}_ref.${ext}
 		fi
 
 		if [ ! -f ../${bn}_tb.v ]; then
-- 
cgit v1.2.3


From 65924fd12f48b4ec5a4d51efeea977992d033ecf Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 7 Jun 2019 11:28:05 -0700
Subject: Test *.aag too, by using *.aig as reference

---
 tests/aiger/run-test.sh | 19 +++++++++++++++++++
 1 file changed, 19 insertions(+)

(limited to 'tests')

diff --git a/tests/aiger/run-test.sh b/tests/aiger/run-test.sh
index 70300d305..e56d0fa80 100755
--- a/tests/aiger/run-test.sh
+++ b/tests/aiger/run-test.sh
@@ -1,6 +1,25 @@
 #!/bin/bash
 
 set -e
+
+for aag in *.aag; do
+    # Since ABC cannot read *.aag, read the *.aig instead
+    # (which would have been created by the reference aig2aig utility)
+    ../../yosys-abc -c "read -c ${aag%.*}.aig; write ${aag%.*}_ref.v"
+    ../../yosys -p "
+read_verilog ${aag%.*}_ref.v
+prep
+design -stash gold
+read_aiger -clk_name clock $aag
+prep
+design -stash gate
+design -import gold -as gold
+design -import gate -as gate
+miter -equiv -flatten -make_assert -make_outputs gold gate miter
+sat -verify -prove-asserts -show-ports -seq 16 miter
+"
+done
+
 for aig in *.aig; do
     ../../yosys-abc -c "read -c $aig; write ${aig%.*}_ref.v"
     ../../yosys -p "
-- 
cgit v1.2.3


From a91ea6612a73568782c80bd12ce2875353e2b5c5 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Mon, 10 Jun 2019 10:27:55 -0700
Subject: Add some more comments

---
 tests/aiger/run-test.sh | 7 ++++++-
 1 file changed, 6 insertions(+), 1 deletion(-)

(limited to 'tests')

diff --git a/tests/aiger/run-test.sh b/tests/aiger/run-test.sh
index e56d0fa80..f52eb4ac1 100755
--- a/tests/aiger/run-test.sh
+++ b/tests/aiger/run-test.sh
@@ -2,9 +2,14 @@
 
 set -e
 
+# NB: *.aag and *.aig must contain a symbol table naming the primary
+#     inputs and outputs, otherwise ABC and Yosys will name them
+#     arbitrarily (and inconsistently with each other).
+
 for aag in *.aag; do
     # Since ABC cannot read *.aag, read the *.aig instead
-    # (which would have been created by the reference aig2aig utility)
+    # (which would have been created by the reference aig2aig utility,
+    #  available from http://fmv.jku.at/aiger/)
     ../../yosys-abc -c "read -c ${aag%.*}.aig; write ${aag%.*}_ref.v"
     ../../yosys -p "
 read_verilog ${aag%.*}_ref.v
-- 
cgit v1.2.3