From e39c422734219bb0601827cb7c1d081f7ac7817b Mon Sep 17 00:00:00 2001
From: Jannis Harder <me@jix.one>
Date: Tue, 31 May 2022 17:47:07 +0200
Subject: chformal: Test -coverprecond and reuse the src attribute

---
 tests/various/chformal_coverprecond.ys | 25 +++++++++++++++++++++++++
 1 file changed, 25 insertions(+)
 create mode 100644 tests/various/chformal_coverprecond.ys

(limited to 'tests')

diff --git a/tests/various/chformal_coverprecond.ys b/tests/various/chformal_coverprecond.ys
new file mode 100644
index 000000000..59e302a72
--- /dev/null
+++ b/tests/various/chformal_coverprecond.ys
@@ -0,0 +1,25 @@
+read_verilog -formal <<EOT
+module top(input a, b, c, d);
+
+    always @* begin
+        if (a) assert (b == c);
+        if (!a) assert (b != c);
+        if (b) assume (c);
+        if (c) cover (d);
+    end
+
+endmodule
+EOT
+
+prep -top top
+
+select -assert-count 1 t:$cover
+
+chformal -cover -coverprecond
+select -assert-count 2 t:$cover
+
+chformal -assert -coverprecond
+select -assert-count 4 t:$cover
+
+chformal -assume -coverprecond
+select -assert-count 5 t:$cover
-- 
cgit v1.2.3


From 5dfad5101d92edb484da2e5306cde58b8d958e7d Mon Sep 17 00:00:00 2001
From: George Rennie <georgerennie@gmail.com>
Date: Sat, 18 Jun 2022 18:28:12 +0100
Subject: chformal: Rename -coverprecond to -coverenable

---
 tests/various/chformal_coverenable.ys  | 25 +++++++++++++++++++++++++
 tests/various/chformal_coverprecond.ys | 25 -------------------------
 2 files changed, 25 insertions(+), 25 deletions(-)
 create mode 100644 tests/various/chformal_coverenable.ys
 delete mode 100644 tests/various/chformal_coverprecond.ys

(limited to 'tests')

diff --git a/tests/various/chformal_coverenable.ys b/tests/various/chformal_coverenable.ys
new file mode 100644
index 000000000..52b3ee6bf
--- /dev/null
+++ b/tests/various/chformal_coverenable.ys
@@ -0,0 +1,25 @@
+read_verilog -formal <<EOT
+module top(input a, b, c, d);
+
+    always @* begin
+        if (a) assert (b == c);
+        if (!a) assert (b != c);
+        if (b) assume (c);
+        if (c) cover (d);
+    end
+
+endmodule
+EOT
+
+prep -top top
+
+select -assert-count 1 t:$cover
+
+chformal -cover -coverenable
+select -assert-count 2 t:$cover
+
+chformal -assert -coverenable
+select -assert-count 4 t:$cover
+
+chformal -assume -coverenable
+select -assert-count 5 t:$cover
diff --git a/tests/various/chformal_coverprecond.ys b/tests/various/chformal_coverprecond.ys
deleted file mode 100644
index 59e302a72..000000000
--- a/tests/various/chformal_coverprecond.ys
+++ /dev/null
@@ -1,25 +0,0 @@
-read_verilog -formal <<EOT
-module top(input a, b, c, d);
-
-    always @* begin
-        if (a) assert (b == c);
-        if (!a) assert (b != c);
-        if (b) assume (c);
-        if (c) cover (d);
-    end
-
-endmodule
-EOT
-
-prep -top top
-
-select -assert-count 1 t:$cover
-
-chformal -cover -coverprecond
-select -assert-count 2 t:$cover
-
-chformal -assert -coverprecond
-select -assert-count 4 t:$cover
-
-chformal -assume -coverprecond
-select -assert-count 5 t:$cover
-- 
cgit v1.2.3