From e91368a5f423b0e4188c13512816e0ecaf09a0d9 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Marcin=20Ko=C5=9Bcielnicki?= <mwk@0x04.net>
Date: Wed, 18 Mar 2020 20:58:36 +0100
Subject: fsm_extract: Initialize celltypes with full design.

Fixes #1781.
---
 tests/various/bug1781.ys | 33 +++++++++++++++++++++++++++++++++
 1 file changed, 33 insertions(+)
 create mode 100644 tests/various/bug1781.ys

(limited to 'tests')

diff --git a/tests/various/bug1781.ys b/tests/various/bug1781.ys
new file mode 100644
index 000000000..60dcc0830
--- /dev/null
+++ b/tests/various/bug1781.ys
@@ -0,0 +1,33 @@
+read_verilog <<EOT
+
+module top(input clk, input rst);
+
+reg [1:0] state;
+
+always @(posedge clk, posedge rst) begin
+	if (rst)
+		state <= 0;
+	else
+		case (state)
+			2'b00: state <= 2'b01;
+			2'b01: state <= 2'b10;
+			2'b10: state <= 2'b00;
+		endcase
+end
+
+sub sub_i(.i(state == 0));
+
+endmodule
+
+
+(* blackbox, keep *)
+module sub(input i);
+endmodule
+
+EOT
+
+proc
+fsm
+
+# Make sure there is a driver
+select -assert-any t:sub %ci %a w:* %i %ci c:* %i
-- 
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