From ef1a1402bcecd5cf3edc41b9842ab5500e52a95e Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddieh@ece.ubc.ca>
Date: Tue, 19 Feb 2019 15:25:03 -0800
Subject: Add a quick abc9 test

---
 tests/techmap/abc9/abc9.v          |  6 ++++++
 tests/techmap/abc9/abc9_runtest.sh |  5 +++++
 tests/techmap/abc9/run-test.sh     | 10 ++++++++++
 tests/techmap/run-test.sh          |  8 ++++++++
 4 files changed, 29 insertions(+)
 create mode 100644 tests/techmap/abc9/abc9.v
 create mode 100644 tests/techmap/abc9/abc9_runtest.sh
 create mode 100755 tests/techmap/abc9/run-test.sh

(limited to 'tests')

diff --git a/tests/techmap/abc9/abc9.v b/tests/techmap/abc9/abc9.v
new file mode 100644
index 000000000..2d9aea366
--- /dev/null
+++ b/tests/techmap/abc9/abc9.v
@@ -0,0 +1,6 @@
+module top(input [1:0] a, output [1:0] b, output c, output d, output e);
+assign b = a;
+assign c = ^a;
+assign d = ~c;
+assign e = d;
+endmodule
diff --git a/tests/techmap/abc9/abc9_runtest.sh b/tests/techmap/abc9/abc9_runtest.sh
new file mode 100644
index 000000000..2deaad719
--- /dev/null
+++ b/tests/techmap/abc9/abc9_runtest.sh
@@ -0,0 +1,5 @@
+#!/bin/bash
+
+set -ev
+
+../../../yosys -p 'abc9 -lut 4; check; select -assert-count 2 t:$lut; select -assert-none c:* t:$lut %n %i' abc9.v
diff --git a/tests/techmap/abc9/run-test.sh b/tests/techmap/abc9/run-test.sh
new file mode 100755
index 000000000..e2fc11e52
--- /dev/null
+++ b/tests/techmap/abc9/run-test.sh
@@ -0,0 +1,10 @@
+#!/bin/bash
+set -e
+for x in *_runtest.sh; do
+	echo "Running $x.."
+	if ! bash $x &> ${x%.sh}.log; then
+		tail ${x%.sh}.log
+		echo ERROR
+		exit 1
+	fi
+done
diff --git a/tests/techmap/run-test.sh b/tests/techmap/run-test.sh
index e2fc11e52..129451e08 100755
--- a/tests/techmap/run-test.sh
+++ b/tests/techmap/run-test.sh
@@ -8,3 +8,11 @@ for x in *_runtest.sh; do
 		exit 1
 	fi
 done
+
+for d in */; do
+    if [ -x $d/run-test.sh ]; then
+        cd $d
+        bash run-test.sh
+        cd ..
+    fi
+done
-- 
cgit v1.2.3


From 945bbcc2989c6b6cad2ef3b9aae253f23d6a2697 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddieh@ece.ubc.ca>
Date: Wed, 20 Feb 2019 15:31:35 -0800
Subject: Add tests/simple_abc9

---
 tests/simple_abc9/run-test.sh | 23 +++++++++++++++++++++++
 1 file changed, 23 insertions(+)
 create mode 100755 tests/simple_abc9/run-test.sh

(limited to 'tests')

diff --git a/tests/simple_abc9/run-test.sh b/tests/simple_abc9/run-test.sh
new file mode 100755
index 000000000..5c51e44f9
--- /dev/null
+++ b/tests/simple_abc9/run-test.sh
@@ -0,0 +1,23 @@
+#!/bin/bash
+
+OPTIND=1
+seed=""    # default to no seed specified
+while getopts "S:" opt
+do
+    case "$opt" in
+	S) arg="${OPTARG#"${OPTARG%%[![:space:]]*}"}" # remove leading space
+	   seed="SEED=$arg" ;;
+    esac
+done
+shift "$((OPTIND-1))"
+
+# check for Icarus Verilog
+if ! which iverilog > /dev/null ; then
+  echo "$0: Error: Icarus Verilog 'iverilog' not found."
+  exit 1
+fi
+
+cp ../simple/*.v .
+rm dff_different_styles.v # FIXME: dffsr1 fails because opt_rmdff does something fishy (#816)
+rm partsel.v # FIXME: Contains 1'hx, thus write_xaiger fails
+exec ${MAKE:-make} -f ../tools/autotest.mk $seed *.v EXTRA_FLAGS="-p \"synth -abc9 -lut 4\""
-- 
cgit v1.2.3


From 43d5471570bd208ec87e2994f53a835c1e8ef3b9 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddieh@ece.ubc.ca>
Date: Wed, 20 Feb 2019 15:34:59 -0800
Subject: Move tests/techmap/abc9 to simple_abc9

---
 tests/simple_abc9/abc9.v           |  6 ++++++
 tests/techmap/abc9/abc9.v          |  6 ------
 tests/techmap/abc9/abc9_runtest.sh |  5 -----
 tests/techmap/abc9/run-test.sh     | 10 ----------
 tests/techmap/run-test.sh          |  8 --------
 5 files changed, 6 insertions(+), 29 deletions(-)
 create mode 100644 tests/simple_abc9/abc9.v
 delete mode 100644 tests/techmap/abc9/abc9.v
 delete mode 100644 tests/techmap/abc9/abc9_runtest.sh
 delete mode 100755 tests/techmap/abc9/run-test.sh

(limited to 'tests')

diff --git a/tests/simple_abc9/abc9.v b/tests/simple_abc9/abc9.v
new file mode 100644
index 000000000..2d9aea366
--- /dev/null
+++ b/tests/simple_abc9/abc9.v
@@ -0,0 +1,6 @@
+module top(input [1:0] a, output [1:0] b, output c, output d, output e);
+assign b = a;
+assign c = ^a;
+assign d = ~c;
+assign e = d;
+endmodule
diff --git a/tests/techmap/abc9/abc9.v b/tests/techmap/abc9/abc9.v
deleted file mode 100644
index 2d9aea366..000000000
--- a/tests/techmap/abc9/abc9.v
+++ /dev/null
@@ -1,6 +0,0 @@
-module top(input [1:0] a, output [1:0] b, output c, output d, output e);
-assign b = a;
-assign c = ^a;
-assign d = ~c;
-assign e = d;
-endmodule
diff --git a/tests/techmap/abc9/abc9_runtest.sh b/tests/techmap/abc9/abc9_runtest.sh
deleted file mode 100644
index 2deaad719..000000000
--- a/tests/techmap/abc9/abc9_runtest.sh
+++ /dev/null
@@ -1,5 +0,0 @@
-#!/bin/bash
-
-set -ev
-
-../../../yosys -p 'abc9 -lut 4; check; select -assert-count 2 t:$lut; select -assert-none c:* t:$lut %n %i' abc9.v
diff --git a/tests/techmap/abc9/run-test.sh b/tests/techmap/abc9/run-test.sh
deleted file mode 100755
index e2fc11e52..000000000
--- a/tests/techmap/abc9/run-test.sh
+++ /dev/null
@@ -1,10 +0,0 @@
-#!/bin/bash
-set -e
-for x in *_runtest.sh; do
-	echo "Running $x.."
-	if ! bash $x &> ${x%.sh}.log; then
-		tail ${x%.sh}.log
-		echo ERROR
-		exit 1
-	fi
-done
diff --git a/tests/techmap/run-test.sh b/tests/techmap/run-test.sh
index 129451e08..e2fc11e52 100755
--- a/tests/techmap/run-test.sh
+++ b/tests/techmap/run-test.sh
@@ -8,11 +8,3 @@ for x in *_runtest.sh; do
 		exit 1
 	fi
 done
-
-for d in */; do
-    if [ -x $d/run-test.sh ]; then
-        cd $d
-        bash run-test.sh
-        cd ..
-    fi
-done
-- 
cgit v1.2.3


From 869343b040d60ffa9bfdda81660c2ecd88848e79 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddieh@ece.ubc.ca>
Date: Wed, 20 Feb 2019 16:19:01 -0800
Subject: simple_abc9 tests to now preserve memories

---
 tests/simple_abc9/run-test.sh | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'tests')

diff --git a/tests/simple_abc9/run-test.sh b/tests/simple_abc9/run-test.sh
index 5c51e44f9..1baf31244 100755
--- a/tests/simple_abc9/run-test.sh
+++ b/tests/simple_abc9/run-test.sh
@@ -20,4 +20,4 @@ fi
 cp ../simple/*.v .
 rm dff_different_styles.v # FIXME: dffsr1 fails because opt_rmdff does something fishy (#816)
 rm partsel.v # FIXME: Contains 1'hx, thus write_xaiger fails
-exec ${MAKE:-make} -f ../tools/autotest.mk $seed *.v EXTRA_FLAGS="-p \"synth -abc9 -lut 4\""
+exec ${MAKE:-make} -f ../tools/autotest.mk $seed *.v EXTRA_FLAGS="-p \"hierarchy; synth -run coarse; techmap; opt -full; abc9 -lut 4\""
-- 
cgit v1.2.3


From c6fd057eda5dba371ff9c1142019b801bee81111 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddieh@ece.ubc.ca>
Date: Thu, 21 Feb 2019 10:37:45 -0800
Subject: Add abc9.v testcase to simple_abc9

---
 tests/simple_abc9/abc9.v | 50 ++++++++++++++++++++++++++++++++++++++++++++----
 1 file changed, 46 insertions(+), 4 deletions(-)

(limited to 'tests')

diff --git a/tests/simple_abc9/abc9.v b/tests/simple_abc9/abc9.v
index 2d9aea366..d387b99eb 100644
--- a/tests/simple_abc9/abc9.v
+++ b/tests/simple_abc9/abc9.v
@@ -1,6 +1,48 @@
-module top(input [1:0] a, output [1:0] b, output c, output d, output e);
+module abc9_test001(input a, output o);
+assign o = a;
+endmodule
+
+module abc9_test002(input [1:0] a, output o);
+assign o = a[1];
+endmodule
+
+module abc9_test003(input [1:0] a, output [1:0] o);
+assign o = a;
+endmodule
+
+module abc9_test004(input [1:0] a, output o);
+assign o = ^a;
+endmodule
+
+module abc9_test005(input [1:0] a, output o, output p);
+assign o = ^a;
+assign p = ~o;
+endmodule
+
+module abc9_test006(input [1:0] a, output [2:0] o);
+assign o[0] = ^a;
+assign o[1] = ~o[0];
+assign o[2] = o[1];
+endmodule
+
+module abc9_test007(input a, output o);
+wire b, c;
+assign c = ~a;
+assign b = c;
+abc9_test007_sub s(b, o);
+endmodule
+
+module abc9_test007_sub(input a, output b);
 assign b = a;
-assign c = ^a;
-assign d = ~c;
-assign e = d;
+endmodule
+
+module abc9_test008(input a, output o);
+wire b, c;
+assign b = ~a;
+assign c = b;
+abc9_test008_sub s(b, o);
+endmodule
+
+module abc9_test008_sub(input a, output b);
+assign b = ~a;
 endmodule
-- 
cgit v1.2.3


From 107da3becff01cdedf6572ece3af9a74463a3e93 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddieh@ece.ubc.ca>
Date: Thu, 21 Feb 2019 11:16:25 -0800
Subject: Working simple_abc9 tests

---
 tests/simple_abc9/run-test.sh | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

(limited to 'tests')

diff --git a/tests/simple_abc9/run-test.sh b/tests/simple_abc9/run-test.sh
index 1baf31244..bf48d007d 100755
--- a/tests/simple_abc9/run-test.sh
+++ b/tests/simple_abc9/run-test.sh
@@ -18,6 +18,6 @@ if ! which iverilog > /dev/null ; then
 fi
 
 cp ../simple/*.v .
-rm dff_different_styles.v # FIXME: dffsr1 fails because opt_rmdff does something fishy (#816)
 rm partsel.v # FIXME: Contains 1'hx, thus write_xaiger fails
-exec ${MAKE:-make} -f ../tools/autotest.mk $seed *.v EXTRA_FLAGS="-p \"hierarchy; synth -run coarse; techmap; opt -full; abc9 -lut 4\""
+DOLLAR='?'
+exec ${MAKE:-make} -f ../tools/autotest.mk $seed *.v EXTRA_FLAGS="-p 'hierarchy; synth -run coarse; techmap; opt -full; abc9 -lut 4; stat; check -assert; select -assert-none t:${DOLLAR}_NOT_ t:${DOLLAR}_AND_'"
-- 
cgit v1.2.3


From 5994382a20a0b7e890d22d032eecb39b61e0b3ce Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddieh@ece.ubc.ca>
Date: Thu, 21 Feb 2019 11:16:57 -0800
Subject: tests/simple to also do LUT synth

---
 tests/tools/autotest.sh | 1 +
 1 file changed, 1 insertion(+)

(limited to 'tests')

diff --git a/tests/tools/autotest.sh b/tests/tools/autotest.sh
index 65fd4cb1f..34007b689 100755
--- a/tests/tools/autotest.sh
+++ b/tests/tools/autotest.sh
@@ -180,6 +180,7 @@ do
 		else
 			test_passes -f "$frontend $include_opts" -p "hierarchy; proc; opt; memory; opt; fsm; opt -full -fine" ${bn}_ref.v
 			test_passes -f "$frontend $include_opts" -p "hierarchy; synth -run coarse; techmap; opt; abc -dff" ${bn}_ref.v
+			test_passes -f "$frontend $include_opts" -p "hierarchy; synth -run coarse; techmap; opt; abc -lut 4" ${bn}_ref.v
 			if [ -n "$firrtl2verilog" ]; then
 			    if test -z "$xfirrtl" || ! grep "$fn" "$xfirrtl" ; then
 				"$toolsdir"/../../yosys -b "firrtl" -o ${bn}_ref.fir -f "$frontend $include_opts" -p "prep -nordff; proc; opt; memory; opt; fsm; opt -full -fine; pmuxtree" ${bn}_ref.v
-- 
cgit v1.2.3


From ca870688c33f7a71eea78709d85a069957966ba6 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddieh@ece.ubc.ca>
Date: Thu, 21 Feb 2019 13:15:45 -0800
Subject: Revert "tests/simple to also do LUT synth"

This reverts commit 5994382a20a0b7e890d22d032eecb39b61e0b3ce.
---
 tests/tools/autotest.sh | 1 -
 1 file changed, 1 deletion(-)

(limited to 'tests')

diff --git a/tests/tools/autotest.sh b/tests/tools/autotest.sh
index 2b8e60200..13c25432f 100755
--- a/tests/tools/autotest.sh
+++ b/tests/tools/autotest.sh
@@ -178,7 +178,6 @@ do
 		else
 			test_passes -f "$frontend $include_opts" -p "hierarchy; proc; opt; memory; opt; fsm; opt -full -fine" ${bn}_ref.v
 			test_passes -f "$frontend $include_opts" -p "hierarchy; synth -run coarse; techmap; opt; abc -dff" ${bn}_ref.v
-			test_passes -f "$frontend $include_opts" -p "hierarchy; synth -run coarse; techmap; opt; abc -lut 4" ${bn}_ref.v
 			if [ -n "$firrtl2verilog" ]; then
 			    if test -z "$xfirrtl" || ! grep "$fn" "$xfirrtl" ; then
 				"$toolsdir"/../../yosys -b "firrtl" -o ${bn}_ref.fir -f "$frontend $include_opts" -p "prep -nordff; proc; opt; memory; opt; fsm; opt -full -fine; pmuxtree" ${bn}_ref.v
-- 
cgit v1.2.3


From 65c8ccf7b57a69f1e1629a3b3df7505073b0474c Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddieh@ece.ubc.ca>
Date: Mon, 25 Feb 2019 15:06:23 -0800
Subject: Add broken testcases

---
 tests/simple_abc9/abc9.v | 46 ++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 46 insertions(+)

(limited to 'tests')

diff --git a/tests/simple_abc9/abc9.v b/tests/simple_abc9/abc9.v
index d387b99eb..ad0e86d24 100644
--- a/tests/simple_abc9/abc9.v
+++ b/tests/simple_abc9/abc9.v
@@ -46,3 +46,49 @@ endmodule
 module abc9_test008_sub(input a, output b);
 assign b = ~a;
 endmodule
+
+// TODO
+//module abc9_test009(inout io, input oe);
+//reg latch;
+//always @(io or oe)
+//    if (!oe)
+//        latch <= io;
+//assign io = oe ? ~latch : 1'bz;
+//endmodule
+
+// TODO
+//module abc9_test010(inout [7:0] io, input oe);
+//reg [7:0] latch;
+//always @(io or oe)
+//    if (!oe)
+//        latch <= io;
+//assign io = oe ? ~latch : 1'bz;
+//endmodule
+
+// TODO
+//module abc9_test011(inout [7:0] io, input oe);
+//reg [7:0] latch;
+//always @(io or oe)
+//    if (!oe)
+//        latch[3:0] <= io;
+//    else
+//        latch[7:4] <= io;
+//assign io[3:0] = oe ? ~latch[3:0] : 4'bz;
+//assign io[7:4] = !oe ? {latch[4], latch[7:3]} : 4'bz;
+//endmodule
+
+// TODO
+//module abc9_test012(inout [7:0] io, input oe);
+//abc9_test012_sub sub(io, oe);
+//endmodule
+//
+//module abc9_test012_sub(inout [7:0] io, input oe);
+//reg [7:0] latch;
+//always @(io or oe)
+//    if (!oe)
+//        latch[3:0] <= io;
+//    else
+//        latch[7:4] <= io;
+//assign io[3:0] = oe ? ~latch[3:0] : 4'bz;
+//assign io[7:4] = !oe ? {latch[4], latch[7:3]} : 4'bz;
+//endmodule
-- 
cgit v1.2.3


From 66b5f5166b358ae7efebd278ad32cd05f3eb72be Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddieh@ece.ubc.ca>
Date: Tue, 26 Feb 2019 11:39:17 -0800
Subject: Enable two inout tests

---
 tests/simple_abc9/abc9.v | 30 ++++++++++++++----------------
 1 file changed, 14 insertions(+), 16 deletions(-)

(limited to 'tests')

diff --git a/tests/simple_abc9/abc9.v b/tests/simple_abc9/abc9.v
index ad0e86d24..8a809e480 100644
--- a/tests/simple_abc9/abc9.v
+++ b/tests/simple_abc9/abc9.v
@@ -47,23 +47,21 @@ module abc9_test008_sub(input a, output b);
 assign b = ~a;
 endmodule
 
-// TODO
-//module abc9_test009(inout io, input oe);
-//reg latch;
-//always @(io or oe)
-//    if (!oe)
-//        latch <= io;
-//assign io = oe ? ~latch : 1'bz;
-//endmodule
+module abc9_test009(inout io, input oe);
+reg latch;
+always @(io or oe)
+    if (!oe)
+        latch <= io;
+assign io = oe ? ~latch : 1'bz;
+endmodule
 
-// TODO
-//module abc9_test010(inout [7:0] io, input oe);
-//reg [7:0] latch;
-//always @(io or oe)
-//    if (!oe)
-//        latch <= io;
-//assign io = oe ? ~latch : 1'bz;
-//endmodule
+module abc9_test010(inout [7:0] io, input oe);
+reg [7:0] latch;
+always @(io or oe)
+    if (!oe)
+        latch <= io;
+assign io = oe ? ~latch : 8'bz;
+endmodule
 
 // TODO
 //module abc9_test011(inout [7:0] io, input oe);
-- 
cgit v1.2.3


From dfb23a79dd0e2ffbe4f058eadb552d8194540eef Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddieh@ece.ubc.ca>
Date: Tue, 26 Feb 2019 12:18:48 -0800
Subject: Uncomment out more tests

---
 tests/simple_abc9/abc9.v | 64 +++++++++++++++++++++++++++++-------------------
 1 file changed, 39 insertions(+), 25 deletions(-)

(limited to 'tests')

diff --git a/tests/simple_abc9/abc9.v b/tests/simple_abc9/abc9.v
index 8a809e480..eca340693 100644
--- a/tests/simple_abc9/abc9.v
+++ b/tests/simple_abc9/abc9.v
@@ -63,30 +63,44 @@ always @(io or oe)
 assign io = oe ? ~latch : 8'bz;
 endmodule
 
-// TODO
-//module abc9_test011(inout [7:0] io, input oe);
-//reg [7:0] latch;
-//always @(io or oe)
-//    if (!oe)
-//        latch[3:0] <= io;
-//    else
-//        latch[7:4] <= io;
-//assign io[3:0] = oe ? ~latch[3:0] : 4'bz;
-//assign io[7:4] = !oe ? {latch[4], latch[7:3]} : 4'bz;
-//endmodule
-
-// TODO
-//module abc9_test012(inout [7:0] io, input oe);
-//abc9_test012_sub sub(io, oe);
-//endmodule
-//
-//module abc9_test012_sub(inout [7:0] io, input oe);
-//reg [7:0] latch;
+module abc9_test011(inout io, input oe);
+reg latch;
+always @(io or oe)
+    if (!oe)
+        latch <= io;
+//assign io = oe ? ~latch : 8'bz;
+endmodule
+
+module abc9_test012(inout io, input oe);
+reg latch;
 //always @(io or oe)
 //    if (!oe)
-//        latch[3:0] <= io;
-//    else
-//        latch[7:4] <= io;
-//assign io[3:0] = oe ? ~latch[3:0] : 4'bz;
-//assign io[7:4] = !oe ? {latch[4], latch[7:3]} : 4'bz;
-//endmodule
+//        latch <= io;
+assign io = oe ? ~latch : 8'bz;
+endmodule
+
+module abc9_test013(inout [3:0] io, input oe);
+reg [3:0] latch;
+always @(io or oe)
+    if (!oe)
+        latch[3:0] <= io[3:0];
+    else
+        latch[7:4] <= io;
+assign io[3:0] = oe ? ~latch[3:0] : 4'bz;
+assign io[7:4] = !oe ? {latch[4], latch[7:3]} : 4'bz;
+endmodule
+
+module abc9_test014(inout [7:0] io, input oe);
+abc9_test012_sub sub(io, oe);
+endmodule
+
+module abc9_test012_sub(inout [7:0] io, input oe);
+reg [7:0] latch;
+always @(io or oe)
+    if (!oe)
+        latch[3:0] <= io;
+    else
+        latch[7:4] <= io;
+assign io[3:0] = oe ? ~latch[3:0] : 4'bz;
+assign io[7:4] = !oe ? {latch[4], latch[7:3]} : 4'bz;
+endmodule
-- 
cgit v1.2.3


From 0c8a839f13bf7bc8368625ab55960dd3f219b0d8 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Tue, 16 Apr 2019 13:10:35 -0700
Subject: Re-enable partsel.v test

---
 tests/simple_abc9/run-test.sh | 1 -
 1 file changed, 1 deletion(-)

(limited to 'tests')

diff --git a/tests/simple_abc9/run-test.sh b/tests/simple_abc9/run-test.sh
index bf48d007d..af003d52e 100755
--- a/tests/simple_abc9/run-test.sh
+++ b/tests/simple_abc9/run-test.sh
@@ -18,6 +18,5 @@ if ! which iverilog > /dev/null ; then
 fi
 
 cp ../simple/*.v .
-rm partsel.v # FIXME: Contains 1'hx, thus write_xaiger fails
 DOLLAR='?'
 exec ${MAKE:-make} -f ../tools/autotest.mk $seed *.v EXTRA_FLAGS="-p 'hierarchy; synth -run coarse; techmap; opt -full; abc9 -lut 4; stat; check -assert; select -assert-none t:${DOLLAR}_NOT_ t:${DOLLAR}_AND_'"
-- 
cgit v1.2.3


From 59c993e4372df1624b538bd12aee96381c874f6f Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 19 Apr 2019 15:47:53 -0700
Subject: Select to find union of both sets on stack

---
 tests/simple_abc9/run-test.sh | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'tests')

diff --git a/tests/simple_abc9/run-test.sh b/tests/simple_abc9/run-test.sh
index af003d52e..97f284378 100755
--- a/tests/simple_abc9/run-test.sh
+++ b/tests/simple_abc9/run-test.sh
@@ -19,4 +19,4 @@ fi
 
 cp ../simple/*.v .
 DOLLAR='?'
-exec ${MAKE:-make} -f ../tools/autotest.mk $seed *.v EXTRA_FLAGS="-p 'hierarchy; synth -run coarse; techmap; opt -full; abc9 -lut 4; stat; check -assert; select -assert-none t:${DOLLAR}_NOT_ t:${DOLLAR}_AND_'"
+exec ${MAKE:-make} -f ../tools/autotest.mk $seed *.v EXTRA_FLAGS="-p 'hierarchy; synth -run coarse; techmap; opt -full; abc9 -lut 4; stat; check -assert; select -assert-none t:${DOLLAR}_NOT_ t:${DOLLAR}_AND_ %%'"
-- 
cgit v1.2.3


From bfd71e09906096c72039beebb1b3b6a79dd6b36c Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Tue, 23 Apr 2019 16:11:14 -0700
Subject: Fix abc9 with (* keep *) wires

---
 tests/simple_abc9/abc9.v | 38 ++++++++++++++++++++++++++++++++++++++
 1 file changed, 38 insertions(+)

(limited to 'tests')

diff --git a/tests/simple_abc9/abc9.v b/tests/simple_abc9/abc9.v
index eca340693..f37d975ff 100644
--- a/tests/simple_abc9/abc9.v
+++ b/tests/simple_abc9/abc9.v
@@ -104,3 +104,41 @@ always @(io or oe)
 assign io[3:0] = oe ? ~latch[3:0] : 4'bz;
 assign io[7:4] = !oe ? {latch[4], latch[7:3]} : 4'bz;
 endmodule
+
+module abc9_test015(input a, output b, input c);
+assign b = ~a;
+(* keep *) wire d;
+assign d = ~c;
+endmodule
+
+module abc9_test016(input a, output b);
+assign b = ~a;
+(* keep *) reg c;
+always @* c <= ~a;
+endmodule
+
+module abc9_test017(input a, output b);
+assign b = ~a;
+(* keep *) reg c;
+always @* c = b;
+endmodule
+
+module abc9_test018(input a, output b, output c);
+assign b = ~a;
+(* keep *) wire [1:0] d;
+assign c = &d;
+endmodule
+
+module abc9_test019(input a, output b);
+assign b = ~a;
+(* keep *) reg [1:0] c;
+reg d;
+always @* d <= &c;
+endmodule
+
+module abc9_test020(input a, output b);
+assign b = ~a;
+(* keep *) reg [1:0] c;
+(* keep *) reg d;
+always @* d <= &c;
+endmodule
-- 
cgit v1.2.3


From eec314e2621d3d055d7810f4b7e573a99e0239b2 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 24 Apr 2019 21:06:53 -0700
Subject: Remove topo sort no-loop assertion, with test

---
 tests/simple_abc9/abc.box     |  2 ++
 tests/simple_abc9/abc9.v      | 73 +++++++++++++++++++++++++++++++++++++++++++
 tests/simple_abc9/run-test.sh |  2 +-
 3 files changed, 76 insertions(+), 1 deletion(-)
 create mode 100644 tests/simple_abc9/abc.box

(limited to 'tests')

diff --git a/tests/simple_abc9/abc.box b/tests/simple_abc9/abc.box
new file mode 100644
index 000000000..a8801d807
--- /dev/null
+++ b/tests/simple_abc9/abc.box
@@ -0,0 +1,2 @@
+MUXF8 1 0 3 1
+1 1 1
diff --git a/tests/simple_abc9/abc9.v b/tests/simple_abc9/abc9.v
index f37d975ff..fb5b759fb 100644
--- a/tests/simple_abc9/abc9.v
+++ b/tests/simple_abc9/abc9.v
@@ -142,3 +142,76 @@ assign b = ~a;
 (* keep *) reg d;
 always @* d <= &c;
 endmodule
+
+module abc9_test021(clk, rst, s_eth_hdr_valid, s_eth_hdr_ready, s_eth_dest_mac, s_eth_src_mac, s_eth_type, s_eth_payload_axis_tdata, s_eth_payload_axis_tkeep, s_eth_payload_axis_tvalid, s_eth_payload_axis_tready, s_eth_payload_axis_tlast, s_eth_payload_axis_tid, s_eth_payload_axis_tdest, s_eth_payload_axis_tuser, m_eth_hdr_valid, m_eth_hdr_ready, m_eth_dest_mac, m_eth_src_mac, m_eth_type, m_eth_payload_axis_tdata, m_eth_payload_axis_tkeep, m_eth_payload_axis_tvalid, m_eth_payload_axis_tready, m_eth_payload_axis_tlast, m_eth_payload_axis_tid, m_eth_payload_axis_tdest, m_eth_payload_axis_tuser);
+  input clk;
+  output [47:0] m_eth_dest_mac;
+  input m_eth_hdr_ready;
+  output m_eth_hdr_valid;
+  output [7:0] m_eth_payload_axis_tdata;
+  output [7:0] m_eth_payload_axis_tdest;
+  output [7:0] m_eth_payload_axis_tid;
+  output m_eth_payload_axis_tkeep;
+  output m_eth_payload_axis_tlast;
+  input m_eth_payload_axis_tready;
+  output m_eth_payload_axis_tuser;
+  output m_eth_payload_axis_tvalid;
+  output [47:0] m_eth_src_mac;
+  output [15:0] m_eth_type;
+  input rst;
+  input [191:0] s_eth_dest_mac;
+  output [3:0] s_eth_hdr_ready;
+  input [3:0] s_eth_hdr_valid;
+  input [31:0] s_eth_payload_axis_tdata;
+  input [31:0] s_eth_payload_axis_tdest;
+  input [31:0] s_eth_payload_axis_tid;
+  input [3:0] s_eth_payload_axis_tkeep;
+  input [3:0] s_eth_payload_axis_tlast;
+  output [3:0] s_eth_payload_axis_tready;
+  input [3:0] s_eth_payload_axis_tuser;
+  input [3:0] s_eth_payload_axis_tvalid;
+  input [191:0] s_eth_src_mac;
+  input [63:0] s_eth_type;
+  (* keep *)
+  wire [0:0] grant, request;
+  wire a;
+  not u0 (
+    a,
+    grant[0]
+  );
+  and u1  (
+    request[0],
+    s_eth_hdr_valid[0],
+    a
+  );
+  (* keep *)
+  MUXF8 u2  (
+    .I0(1'bx),
+    .I1(1'bx),
+    .O(o),
+    .S(1'bx)
+  );
+  arbiter  arb_inst (
+    .acknowledge(acknowledge),
+    .clk(clk),
+    .grant(grant),
+    .grant_encoded(grant_encoded),
+    .grant_valid(grant_valid),
+    .request(request),
+    .rst(rst)
+  );
+endmodule
+
+module arbiter (clk, rst, request, acknowledge, grant, grant_valid, grant_encoded);
+  input [3:0] acknowledge;
+  input clk;
+  output [3:0] grant;
+  output [1:0] grant_encoded;
+  output grant_valid;
+  input [3:0] request;
+  input rst;
+endmodule
+
+(* abc_box_id=1 *)
+module MUXF8(input I0, I1, S, output O);
+endmodule
diff --git a/tests/simple_abc9/run-test.sh b/tests/simple_abc9/run-test.sh
index 97f284378..4935d41ad 100755
--- a/tests/simple_abc9/run-test.sh
+++ b/tests/simple_abc9/run-test.sh
@@ -19,4 +19,4 @@ fi
 
 cp ../simple/*.v .
 DOLLAR='?'
-exec ${MAKE:-make} -f ../tools/autotest.mk $seed *.v EXTRA_FLAGS="-p 'hierarchy; synth -run coarse; techmap; opt -full; abc9 -lut 4; stat; check -assert; select -assert-none t:${DOLLAR}_NOT_ t:${DOLLAR}_AND_ %%'"
+exec ${MAKE:-make} -f ../tools/autotest.mk $seed *.v EXTRA_FLAGS="-p 'hierarchy; synth -run coarse; opt -full; techmap; abc9 -lut 4 -box ../abc.box; stat; check -assert; select -assert-none t:${DOLLAR}_NOT_ t:${DOLLAR}_AND_ %%'"
-- 
cgit v1.2.3


From 0eb7150a5706e81ff36a6a57d8c0c6a2fda05e07 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 25 Apr 2019 18:08:05 -0700
Subject: Add test

---
 tests/various/split_shiftx.v  | 118 ++++++++++++++++++++++++++++++++++++++++++
 tests/various/split_shiftx.ys |  21 ++++++++
 2 files changed, 139 insertions(+)
 create mode 100644 tests/various/split_shiftx.v
 create mode 100644 tests/various/split_shiftx.ys

(limited to 'tests')

diff --git a/tests/various/split_shiftx.v b/tests/various/split_shiftx.v
new file mode 100644
index 000000000..dfcea3880
--- /dev/null
+++ b/tests/various/split_shiftx.v
@@ -0,0 +1,118 @@
+module split_shiftx_test01(i, s, o);
+  wire [3:0] _0_;
+  input [8:0] i;
+  output [2:0] o;
+  input [1:0] s;
+  \$macc  #(
+    .A_WIDTH(32'd4),
+    .B_WIDTH(32'd0),
+    .CONFIG(10'h282),
+    .CONFIG_WIDTH(32'd10),
+    .Y_WIDTH(32'd4)
+  ) _1_ (
+    .A({ 2'h3, s }),
+    .B(),
+    .Y(_0_)
+  );
+  \$shiftx  #(
+    .A_SIGNED(32'd0),
+    .A_WIDTH(32'd9),
+    .B_SIGNED(32'd1),
+    .B_WIDTH(32'd5),
+    .Y_WIDTH(32'd3)
+  ) _2_ (
+    .A(i),
+    .B({ 1'h0, _0_ }),
+    .Y(o)
+  );
+endmodule
+
+// Sign bit is 1
+module split_shiftx_test02(i, s, o);
+  wire [3:0] _0_;
+  input [8:0] i;
+  output [2:0] o;
+  input [1:0] s;
+  \$macc  #(
+    .A_WIDTH(32'd4),
+    .B_WIDTH(32'd0),
+    .CONFIG(10'h282),
+    .CONFIG_WIDTH(32'd10),
+    .Y_WIDTH(32'd4)
+  ) _1_ (
+    .A({ 2'h3, s }),
+    .B(),
+    .Y(_0_)
+  );
+  \$shiftx  #(
+    .A_SIGNED(32'd0),
+    .A_WIDTH(32'd9),
+    .B_SIGNED(32'd1),
+    .B_WIDTH(32'd5),
+    .Y_WIDTH(32'd3)
+  ) _2_ (
+    .A(i),
+    .B({ 1'h1, _0_ }),
+    .Y(o)
+  );
+endmodule
+
+// Non constant $macc
+module split_shiftx_test03(i, s, o);
+  wire [3:0] _0_;
+  input [8:0] i;
+  output [2:0] o;
+  input [1:0] s;
+  \$macc  #(
+    .A_WIDTH(32'd4),
+    .B_WIDTH(32'd0),
+    .CONFIG(10'h282),
+    .CONFIG_WIDTH(32'd10),
+    .Y_WIDTH(32'd4)
+  ) _1_ (
+    .A({ s, s }),
+    .B(),
+    .Y(_0_)
+  );
+  \$shiftx  #(
+    .A_SIGNED(32'd0),
+    .A_WIDTH(32'd9),
+    .B_SIGNED(32'd1),
+    .B_WIDTH(32'd5),
+    .Y_WIDTH(32'd3)
+  ) _2_ (
+    .A(i),
+    .B({ 1'h0, _0_ }),
+    .Y(o)
+  );
+endmodule
+
+// Wrong constant $macc
+module split_shiftx_test04(i, s, o);
+  wire [3:0] _0_;
+  input [8:0] i;
+  output [2:0] o;
+  input [1:0] s;
+  \$macc  #(
+    .A_WIDTH(32'd4),
+    .B_WIDTH(32'd0),
+    .CONFIG(10'h282),
+    .CONFIG_WIDTH(32'd10),
+    .Y_WIDTH(32'd4)
+  ) _1_ (
+    .A({ 2'h2, s }),
+    .B(),
+    .Y(_0_)
+  );
+  \$shiftx  #(
+    .A_SIGNED(32'd0),
+    .A_WIDTH(32'd9),
+    .B_SIGNED(32'd1),
+    .B_WIDTH(32'd5),
+    .Y_WIDTH(32'd3)
+  ) _2_ (
+    .A(i),
+    .B({ 1'h0, _0_ }),
+    .Y(o)
+  );
+endmodule
diff --git a/tests/various/split_shiftx.ys b/tests/various/split_shiftx.ys
new file mode 100644
index 000000000..810348aa3
--- /dev/null
+++ b/tests/various/split_shiftx.ys
@@ -0,0 +1,21 @@
+read_verilog -icells split_shiftx.v
+split_shiftx
+
+cd split_shiftx_test01
+select -assert-count 3 t:$shiftx
+select -assert-count 0 t: t:$shiftx %n %i
+
+cd split_shiftx_test02
+select -assert-count 1 t:$shiftx
+select -assert-count 1 t:$macc
+select -assert-count 0 t: t:$shiftx t:$macc %u %n %i
+
+cd split_shiftx_test03
+select -assert-count 1 t:$shiftx
+select -assert-count 1 t:$macc
+select -assert-count 0 t: t:$shiftx t:$macc %u %n %i
+
+cd split_shiftx_test04
+select -assert-count 1 t:$shiftx
+select -assert-count 1 t:$macc
+select -assert-count 0 t: t:$shiftx t:$macc %u %n %i
-- 
cgit v1.2.3


From 0f1ba949243aa7ccc7c6b42738a60a09be7a209e Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 26 Apr 2019 19:45:47 -0700
Subject: Remove split_shiftx tests

---
 tests/various/split_shiftx.v  | 118 ------------------------------------------
 tests/various/split_shiftx.ys |  21 --------
 2 files changed, 139 deletions(-)
 delete mode 100644 tests/various/split_shiftx.v
 delete mode 100644 tests/various/split_shiftx.ys

(limited to 'tests')

diff --git a/tests/various/split_shiftx.v b/tests/various/split_shiftx.v
deleted file mode 100644
index dfcea3880..000000000
--- a/tests/various/split_shiftx.v
+++ /dev/null
@@ -1,118 +0,0 @@
-module split_shiftx_test01(i, s, o);
-  wire [3:0] _0_;
-  input [8:0] i;
-  output [2:0] o;
-  input [1:0] s;
-  \$macc  #(
-    .A_WIDTH(32'd4),
-    .B_WIDTH(32'd0),
-    .CONFIG(10'h282),
-    .CONFIG_WIDTH(32'd10),
-    .Y_WIDTH(32'd4)
-  ) _1_ (
-    .A({ 2'h3, s }),
-    .B(),
-    .Y(_0_)
-  );
-  \$shiftx  #(
-    .A_SIGNED(32'd0),
-    .A_WIDTH(32'd9),
-    .B_SIGNED(32'd1),
-    .B_WIDTH(32'd5),
-    .Y_WIDTH(32'd3)
-  ) _2_ (
-    .A(i),
-    .B({ 1'h0, _0_ }),
-    .Y(o)
-  );
-endmodule
-
-// Sign bit is 1
-module split_shiftx_test02(i, s, o);
-  wire [3:0] _0_;
-  input [8:0] i;
-  output [2:0] o;
-  input [1:0] s;
-  \$macc  #(
-    .A_WIDTH(32'd4),
-    .B_WIDTH(32'd0),
-    .CONFIG(10'h282),
-    .CONFIG_WIDTH(32'd10),
-    .Y_WIDTH(32'd4)
-  ) _1_ (
-    .A({ 2'h3, s }),
-    .B(),
-    .Y(_0_)
-  );
-  \$shiftx  #(
-    .A_SIGNED(32'd0),
-    .A_WIDTH(32'd9),
-    .B_SIGNED(32'd1),
-    .B_WIDTH(32'd5),
-    .Y_WIDTH(32'd3)
-  ) _2_ (
-    .A(i),
-    .B({ 1'h1, _0_ }),
-    .Y(o)
-  );
-endmodule
-
-// Non constant $macc
-module split_shiftx_test03(i, s, o);
-  wire [3:0] _0_;
-  input [8:0] i;
-  output [2:0] o;
-  input [1:0] s;
-  \$macc  #(
-    .A_WIDTH(32'd4),
-    .B_WIDTH(32'd0),
-    .CONFIG(10'h282),
-    .CONFIG_WIDTH(32'd10),
-    .Y_WIDTH(32'd4)
-  ) _1_ (
-    .A({ s, s }),
-    .B(),
-    .Y(_0_)
-  );
-  \$shiftx  #(
-    .A_SIGNED(32'd0),
-    .A_WIDTH(32'd9),
-    .B_SIGNED(32'd1),
-    .B_WIDTH(32'd5),
-    .Y_WIDTH(32'd3)
-  ) _2_ (
-    .A(i),
-    .B({ 1'h0, _0_ }),
-    .Y(o)
-  );
-endmodule
-
-// Wrong constant $macc
-module split_shiftx_test04(i, s, o);
-  wire [3:0] _0_;
-  input [8:0] i;
-  output [2:0] o;
-  input [1:0] s;
-  \$macc  #(
-    .A_WIDTH(32'd4),
-    .B_WIDTH(32'd0),
-    .CONFIG(10'h282),
-    .CONFIG_WIDTH(32'd10),
-    .Y_WIDTH(32'd4)
-  ) _1_ (
-    .A({ 2'h2, s }),
-    .B(),
-    .Y(_0_)
-  );
-  \$shiftx  #(
-    .A_SIGNED(32'd0),
-    .A_WIDTH(32'd9),
-    .B_SIGNED(32'd1),
-    .B_WIDTH(32'd5),
-    .Y_WIDTH(32'd3)
-  ) _2_ (
-    .A(i),
-    .B({ 1'h0, _0_ }),
-    .Y(o)
-  );
-endmodule
diff --git a/tests/various/split_shiftx.ys b/tests/various/split_shiftx.ys
deleted file mode 100644
index 810348aa3..000000000
--- a/tests/various/split_shiftx.ys
+++ /dev/null
@@ -1,21 +0,0 @@
-read_verilog -icells split_shiftx.v
-split_shiftx
-
-cd split_shiftx_test01
-select -assert-count 3 t:$shiftx
-select -assert-count 0 t: t:$shiftx %n %i
-
-cd split_shiftx_test02
-select -assert-count 1 t:$shiftx
-select -assert-count 1 t:$macc
-select -assert-count 0 t: t:$shiftx t:$macc %u %n %i
-
-cd split_shiftx_test03
-select -assert-count 1 t:$shiftx
-select -assert-count 1 t:$macc
-select -assert-count 0 t: t:$shiftx t:$macc %u %n %i
-
-cd split_shiftx_test04
-select -assert-count 1 t:$shiftx
-select -assert-count 1 t:$macc
-select -assert-count 0 t: t:$shiftx t:$macc %u %n %i
-- 
cgit v1.2.3


From 5f39c262c278f90f6bbb55d5969b970230876ef5 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Tue, 28 May 2019 09:38:58 -0700
Subject: From master

---
 tests/tools/autotest.sh | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'tests')

diff --git a/tests/tools/autotest.sh b/tests/tools/autotest.sh
index 1825990a9..920474a84 100755
--- a/tests/tools/autotest.sh
+++ b/tests/tools/autotest.sh
@@ -132,13 +132,13 @@ do
 		fn=$(basename $fn)
 		bn=$(basename $bn)
 
+		rm -f ${bn}_ref.fir
 		if [[ "$ext" == "v" ]]; then
 			egrep -v '^\s*`timescale' ../$fn > ${bn}_ref.${ext}
 		else
 			"$toolsdir"/../../yosys -f "$frontend $include_opts" -b "verilog" -o ${bn}_ref.v ../${fn}
 			frontend="verilog -noblackbox"
 		fi
-		rm -f ${bn}_ref.fir
 
 		if [ ! -f ../${bn}_tb.v ]; then
 			"$toolsdir"/../../yosys -f "$frontend $include_opts" -b "test_autotb $autotb_opts" -o ${bn}_tb.v ${bn}_ref.v
-- 
cgit v1.2.3


From 92197326b8fa406e94c952cfcb778611642a3e00 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Tue, 28 May 2019 12:43:07 -0700
Subject: Add abc9_test022

---
 tests/simple_abc9/abc9.v | 22 ++++++++++++++++++++++
 1 file changed, 22 insertions(+)

(limited to 'tests')

diff --git a/tests/simple_abc9/abc9.v b/tests/simple_abc9/abc9.v
index fb5b759fb..e666d1a6a 100644
--- a/tests/simple_abc9/abc9.v
+++ b/tests/simple_abc9/abc9.v
@@ -143,6 +143,7 @@ assign b = ~a;
 always @* d <= &c;
 endmodule
 
+// Citation: https://github.com/alexforencich/verilog-ethernet
 module abc9_test021(clk, rst, s_eth_hdr_valid, s_eth_hdr_ready, s_eth_dest_mac, s_eth_src_mac, s_eth_type, s_eth_payload_axis_tdata, s_eth_payload_axis_tkeep, s_eth_payload_axis_tvalid, s_eth_payload_axis_tready, s_eth_payload_axis_tlast, s_eth_payload_axis_tid, s_eth_payload_axis_tdest, s_eth_payload_axis_tuser, m_eth_hdr_valid, m_eth_hdr_ready, m_eth_dest_mac, m_eth_src_mac, m_eth_type, m_eth_payload_axis_tdata, m_eth_payload_axis_tkeep, m_eth_payload_axis_tvalid, m_eth_payload_axis_tready, m_eth_payload_axis_tlast, m_eth_payload_axis_tid, m_eth_payload_axis_tdest, m_eth_payload_axis_tuser);
   input clk;
   output [47:0] m_eth_dest_mac;
@@ -215,3 +216,24 @@ endmodule
 (* abc_box_id=1 *)
 module MUXF8(input I0, I1, S, output O);
 endmodule
+
+// Citation: https://github.com/alexforencich/verilog-ethernet
+// TODO: yosys -p "synth_xilinx -abc9 -top abc9_test022" abc9.v -q
+// returns before b4321a31
+//   Warning: Wire abc9_test022.\m_eth_payload_axis_tkeep [7] is used but has no
+//   driver.
+//   Warning: Wire abc9_test022.\m_eth_payload_axis_tkeep [3] is used but has no
+//   driver.
+module abc9_test022
+(
+    input  wire        clk,
+    input  wire        i,
+    output wire [7:0]  m_eth_payload_axis_tkeep
+);
+
+reg [7:0]  m_eth_payload_axis_tkeep_reg = 8'd0;
+assign m_eth_payload_axis_tkeep = m_eth_payload_axis_tkeep_reg;
+always @(posedge clk)
+    m_eth_payload_axis_tkeep_reg <= i ? 8'hff : 8'h0f;
+
+endmodule
-- 
cgit v1.2.3


From aa2380c17a7c97d4c3835cd6d78310cf4961c4f8 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 29 May 2019 15:24:38 -0700
Subject: Add abc_test024

---
 tests/simple_abc9/abc9.v | 25 +++++++++++++++++++------
 1 file changed, 19 insertions(+), 6 deletions(-)

(limited to 'tests')

diff --git a/tests/simple_abc9/abc9.v b/tests/simple_abc9/abc9.v
index e666d1a6a..7af2ace01 100644
--- a/tests/simple_abc9/abc9.v
+++ b/tests/simple_abc9/abc9.v
@@ -230,10 +230,23 @@ module abc9_test022
     input  wire        i,
     output wire [7:0]  m_eth_payload_axis_tkeep
 );
-
-reg [7:0]  m_eth_payload_axis_tkeep_reg = 8'd0;
-assign m_eth_payload_axis_tkeep = m_eth_payload_axis_tkeep_reg;
-always @(posedge clk)
-    m_eth_payload_axis_tkeep_reg <= i ? 8'hff : 8'h0f;
-
+    reg [7:0]  m_eth_payload_axis_tkeep_reg = 8'd0;
+    assign m_eth_payload_axis_tkeep = m_eth_payload_axis_tkeep_reg;
+    always @(posedge clk)
+        m_eth_payload_axis_tkeep_reg <= i ? 8'hff : 8'h0f;
+endmodule
+
+// Citation: https://github.com/riscv/riscv-bitmanip
+// TODO: yosys -p "synth_xilinx -abc9 -top abc9_test024" abc9.v -q
+// returns before 14233843
+//   Warning: Wire abc9_test024.\dout [1] is used but has no driver.
+module abc9_test024 #(
+	parameter integer N = 2,
+	parameter integer M = 2
+) (
+	input [7:0] din,
+	output [M-1:0] dout
+);
+	wire [2*M-1:0] mask = {M{1'b1}};
+	assign dout = (mask << din[N-1:0]) >> M;
 endmodule
-- 
cgit v1.2.3


From 25befbf5425458cf8cc5ee89635ad7e5f42d5778 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 29 May 2019 15:26:33 -0700
Subject: Rename to #23

---
 tests/simple_abc9/abc9.v | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

(limited to 'tests')

diff --git a/tests/simple_abc9/abc9.v b/tests/simple_abc9/abc9.v
index 7af2ace01..2752ff8cc 100644
--- a/tests/simple_abc9/abc9.v
+++ b/tests/simple_abc9/abc9.v
@@ -237,10 +237,10 @@ module abc9_test022
 endmodule
 
 // Citation: https://github.com/riscv/riscv-bitmanip
-// TODO: yosys -p "synth_xilinx -abc9 -top abc9_test024" abc9.v -q
+// TODO: yosys -p "synth_xilinx -abc9 -top abc9_test023" abc9.v -q
 // returns before 14233843
-//   Warning: Wire abc9_test024.\dout [1] is used but has no driver.
-module abc9_test024 #(
+//   Warning: Wire abc9_test023.\dout [1] is used but has no driver.
+module abc9_test023 #(
 	parameter integer N = 2,
 	parameter integer M = 2
 ) (
-- 
cgit v1.2.3


From 86efe9a616b70ffa64bb344d83aa42956e5fd470 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 12 Jun 2019 09:01:15 -0700
Subject: Revert "Merge remote-tracking branch 'origin/eddie/muxpack' into
 xc7mux"

This reverts commit 2223ca91b0cc559bb876e8e97372a8f77da1603e, reversing
changes made to eaee250a6e63e58dfef63fa30c4120db78223e24.
---
 tests/various/muxpack.v  | 26 --------------------------
 tests/various/muxpack.ys | 15 ---------------
 2 files changed, 41 deletions(-)

(limited to 'tests')

diff --git a/tests/various/muxpack.v b/tests/various/muxpack.v
index f1bd5ea8e..7c189fff8 100644
--- a/tests/various/muxpack.v
+++ b/tests/various/muxpack.v
@@ -110,29 +110,3 @@ always @* begin
     endcase
 end
 endmodule
-
-module mux_if_bal_8_2 #(parameter N=8, parameter W=2) (input [N*W-1:0] i, input [$clog2(N)-1:0] s, output reg [W-1:0] o);
-always @*
-    if (s[0] == 1'b0)
-     if (s[1] == 1'b0)
-      if (s[2] == 1'b0)
-       o <= i[0*W+:W];
-      else
-       o <= i[1*W+:W];
-     else
-      if (s[2] == 1'b0)
-       o <= i[2*W+:W];
-      else
-       o <= i[3*W+:W];
-    else
-     if (s[1] == 1'b0)
-      if (s[2] == 1'b0)
-       o <= i[4*W+:W];
-      else
-       o <= i[5*W+:W];
-     else
-      if (s[2] == 1'b0)
-       o <= i[6*W+:W];
-      else
-       o <= i[7*W+:W];
-endmodule
diff --git a/tests/various/muxpack.ys b/tests/various/muxpack.ys
index 9ea743b9f..0c5b82818 100644
--- a/tests/various/muxpack.ys
+++ b/tests/various/muxpack.ys
@@ -133,18 +133,3 @@ design -import gold -as gold
 design -import gate -as gate
 miter -equiv -flatten -make_assert -make_outputs gold gate miter
 sat -verify -prove-asserts -show-ports miter
-
-design -load read
-hierarchy -top mux_if_bal_8_2
-prep
-design -save gold
-muxpack
-opt
-stat
-select -assert-count 7 t:$mux
-select -assert-count 0 t:$pmux
-design -stash gate
-design -import gold -as gold
-design -import gate -as gate
-miter -equiv -flatten -make_assert -make_outputs gold gate miter
-sat -verify -prove-asserts -show-ports miter
-- 
cgit v1.2.3


From 2cbcd6224c0293a3abdf00f51c515fc556d9d3e1 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 12 Jun 2019 09:05:02 -0700
Subject: Revert "Merge remote-tracking branch 'origin/eddie/shregmap_improve'
 into xc7mux"

This reverts commit a138381ac3f2c820d187f08531ffd823d6cbcfd5, reversing
changes made to b77c5da76919f7f99f171a0a2775896fbc8debc2.
---
 tests/various/shregmap.v  | 22 ----------------------
 tests/various/shregmap.ys | 31 -------------------------------
 2 files changed, 53 deletions(-)
 delete mode 100644 tests/various/shregmap.v
 delete mode 100644 tests/various/shregmap.ys

(limited to 'tests')

diff --git a/tests/various/shregmap.v b/tests/various/shregmap.v
deleted file mode 100644
index 56e05c2c0..000000000
--- a/tests/various/shregmap.v
+++ /dev/null
@@ -1,22 +0,0 @@
-module shregmap_test(input i, clk, output [1:0] q);
-reg head = 1'b0;
-reg [3:0] shift1 = 4'b0000;
-reg [3:0] shift2 = 4'b0000;
-
-always @(posedge clk) begin
-    head <= i;
-    shift1 <= {shift1[2:0], head};
-    shift2 <= {shift2[2:0], head};
-end
-
-assign q = {shift2[3], shift1[3]};
-endmodule
-
-module $__SHREG_DFF_P_(input C, D, output Q);
-parameter DEPTH = 1;
-parameter [DEPTH-1:0] INIT = {DEPTH{1'b0}};
-reg [DEPTH-1:0] r = INIT;
-always @(posedge C) 
-    r <= { r[DEPTH-2:0], D };
-assign Q = r[DEPTH-1];
-endmodule
diff --git a/tests/various/shregmap.ys b/tests/various/shregmap.ys
deleted file mode 100644
index ca7f47015..000000000
--- a/tests/various/shregmap.ys
+++ /dev/null
@@ -1,31 +0,0 @@
-read_verilog shregmap.v
-design -copy-to model $__SHREG_DFF_P_
-hierarchy -top shregmap_test
-prep
-design -save gold
-
-techmap
-shregmap -init
-
-opt
-
-stat
-# show -width
-select -assert-count 1 t:$_DFF_P_
-select -assert-count 2 t:$__SHREG_DFF_P_
-
-design -stash gate
-
-design -import gold -as gold
-design -import gate -as gate
-design -copy-from model -as $__SHREG_DFF_P_ \$__SHREG_DFF_P_
-prep
-
-miter -equiv -flatten -make_assert -make_outputs gold gate miter
-sat -verify -prove-asserts -show-ports -seq 5 miter
-
-design -load gold
-stat
-
-design -load gate
-stat
-- 
cgit v1.2.3


From 2e7b3eee400a4d845398be8e15ca023672f05270 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 12 Jun 2019 15:43:43 -0700
Subject: Add a couple more tests

---
 tests/simple_abc9/abc9.v | 12 ++++++++++++
 1 file changed, 12 insertions(+)

(limited to 'tests')

diff --git a/tests/simple_abc9/abc9.v b/tests/simple_abc9/abc9.v
index 2752ff8cc..0b83c34a3 100644
--- a/tests/simple_abc9/abc9.v
+++ b/tests/simple_abc9/abc9.v
@@ -250,3 +250,15 @@ module abc9_test023 #(
 	wire [2*M-1:0] mask = {M{1'b1}};
 	assign dout = (mask << din[N-1:0]) >> M;
 endmodule
+
+module abc9_test024(input [3:0] i, output [3:0] o);
+abc9_test024_sub a(i[1:0], o[1:0]);
+endmodule
+
+module abc9_test024_sub(input [1:0] i, output [1:0] o);
+assign o = i;
+endmodule
+
+module abc9_test025(input [3:0] i, output [3:0] o);
+abc9_test024_sub a(i[2:1], o[2:1]);
+endmodule
-- 
cgit v1.2.3


From 9f275c1437cb48c28b717f0996edab9da9e73aa0 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 12 Jun 2019 16:33:05 -0700
Subject: Revert "Merge remote-tracking branch 'origin/eddie/muxpack' into
 xc7mux"

This reverts commit 2223ca91b0cc559bb876e8e97372a8f77da1603e, reversing
changes made to eaee250a6e63e58dfef63fa30c4120db78223e24.
---
 tests/various/muxpack.v  | 112 ---------------------------------------
 tests/various/muxpack.ys | 135 -----------------------------------------------
 2 files changed, 247 deletions(-)
 delete mode 100644 tests/various/muxpack.v
 delete mode 100644 tests/various/muxpack.ys

(limited to 'tests')

diff --git a/tests/various/muxpack.v b/tests/various/muxpack.v
deleted file mode 100644
index 7c189fff8..000000000
--- a/tests/various/muxpack.v
+++ /dev/null
@@ -1,112 +0,0 @@
-module mux_if_unbal_4_1 #(parameter N=4, parameter W=1) (input [N*W-1:0] i, input [$clog2(N)-1:0] s, output reg [W-1:0] o);
-always @*
-    if (s == 0) o <= i[0*W+:W];
-    else if (s == 1) o <= i[1*W+:W];
-    else if (s == 2) o <= i[2*W+:W];
-    else if (s == 3) o <= i[3*W+:W];
-    else o <= {W{1'bx}};
-endmodule
-
-module mux_if_unbal_5_3 #(parameter N=5, parameter W=3) (input [N*W-1:0] i, input [$clog2(N)-1:0] s, output reg [W-1:0] o);
-always @* begin
-    o <= {W{1'bx}};
-    if (s == 0) o <= i[0*W+:W];
-    if (s == 1) o <= i[1*W+:W];
-    if (s == 2) o <= i[2*W+:W];
-    if (s == 3) o <= i[3*W+:W];
-    if (s == 4) o <= i[4*W+:W];
-end
-endmodule
-
-module mux_if_unbal_5_3_invert #(parameter N=5, parameter W=3) (input [N*W-1:0] i, input [$clog2(N)-1:0] s, output reg [W-1:0] o);
-always @*
-    if (s != 0) 
-	   	if (s != 1) 
-			if (s != 2)
-				if (s != 3)
-					if (s != 4) o <= i[4*W+:W];
-					else o <= i[0*W+:W];
-				else o <= i[3*W+:W];
-			else o <= i[2*W+:W];
-		else o <= i[1*W+:W];
-    else o <= {W{1'bx}};
-endmodule
-
-module mux_if_unbal_5_3_width_mismatch #(parameter N=5, parameter W=3) (input [N*W-1:0] i, input [$clog2(N)-1:0] s, output reg [W-1:0] o);
-always @* begin
-    o <= {W{1'bx}};
-    if (s == 0) o <= i[0*W+:W];
-    if (s == 1) o <= i[1*W+:W];
-    if (s == 2) o[W-2:0] <= i[2*W+:W-1];
-    if (s == 3) o <= i[3*W+:W];
-    if (s == 4) o <= i[4*W+:W];
-end
-endmodule
-
-module mux_if_unbal_4_1_missing #(parameter N=5, parameter W=3) (input [N*W-1:0] i, input [$clog2(N)-1:0] s, output reg [W-1:0] o);
-always @* begin
-    if (s == 0) o <= i[0*W+:W];
-//    else if (s == 1) o <= i[1*W+:W];
-//    else if (s == 2) o <= i[2*W+:W];
-    else if (s == 3) o <= i[3*W+:W];
-    else o <= {W{1'bx}};
-end
-endmodule
-
-module mux_if_unbal_5_3_order #(parameter N=5, parameter W=3) (input [N*W-1:0] i, input [$clog2(N)-1:0] s, output reg [W-1:0] o);
-always @* begin
-    o <= {W{1'bx}};
-    if (s == 3) o <= i[3*W+:W];
-    if (s == 2) o <= i[2*W+:W];
-    if (s == 1) o <= i[1*W+:W];
-    if (s == 4) o <= i[4*W+:W];
-    if (s == 0) o <= i[0*W+:W];
-end
-endmodule
-
-module mux_if_unbal_4_1_nonexcl #(parameter N=4, parameter W=1) (input [N*W-1:0] i, input [$clog2(N)-1:0] s, output reg [W-1:0] o);
-always @*
-    if (s == 0) o <= i[0*W+:W];
-    else if (s == 1) o <= i[1*W+:W];
-    else if (s == 2) o <= i[2*W+:W];
-    else if (s == 3) o <= i[3*W+:W];
-	else if (s == 0) o <= {W{1'b0}};
-    else o <= {W{1'bx}};
-endmodule
-
-module mux_if_unbal_5_3_nonexcl #(parameter N=5, parameter W=3) (input [N*W-1:0] i, input [$clog2(N)-1:0] s, output reg [W-1:0] o);
-always @* begin
-    o <= {W{1'bx}};
-    if (s == 0) o <= i[0*W+:W];
-    if (s == 1) o <= i[1*W+:W];
-    if (s == 2) o <= i[2*W+:W];
-    if (s == 3) o <= i[3*W+:W];
-    if (s == 4) o <= i[4*W+:W];
-	if (s == 0) o <= i[2*W+:W];
-end
-endmodule
-
-module mux_case_unbal_8_7#(parameter N=8, parameter W=7) (input [N*W-1:0] i, input [$clog2(N)-1:0] s, output reg [W-1:0] o);
-always @* begin
-    o <= {W{1'bx}};
-    case (s)
-    0: o <= i[0*W+:W];
-    default:
-        case (s)
-        1: o <= i[1*W+:W];
-        2: o <= i[2*W+:W];
-        default:
-            case (s)
-            3: o <= i[3*W+:W];
-            4: o <= i[4*W+:W];
-            5: o <= i[5*W+:W];
-            default:
-                case (s)
-                    6: o <= i[6*W+:W];
-                    default: o <= i[7*W+:W];
-                endcase
-            endcase
-        endcase
-    endcase
-end
-endmodule
diff --git a/tests/various/muxpack.ys b/tests/various/muxpack.ys
deleted file mode 100644
index 0c5b82818..000000000
--- a/tests/various/muxpack.ys
+++ /dev/null
@@ -1,135 +0,0 @@
-read_verilog muxpack.v
-design -save read
-hierarchy -top mux_if_unbal_4_1
-prep
-design -save gold
-muxpack
-opt
-stat
-select -assert-count 0 t:$mux
-select -assert-count 1 t:$pmux
-design -stash gate
-design -import gold -as gold
-design -import gate -as gate
-miter -equiv -flatten -make_assert -make_outputs gold gate miter
-sat -verify -prove-asserts -show-ports miter
-
-design -load read
-hierarchy -top mux_if_unbal_5_3
-prep
-design -save gold
-muxpack
-opt
-stat
-select -assert-count 0 t:$mux
-select -assert-count 1 t:$pmux
-design -stash gate
-design -import gold -as gold
-design -import gate -as gate
-miter -equiv -flatten -make_assert -make_outputs gold gate miter
-sat -verify -prove-asserts -show-ports miter
-
-design -load read
-hierarchy -top mux_if_unbal_5_3_invert
-prep
-design -save gold
-muxpack
-opt
-stat
-select -assert-count 0 t:$mux
-select -assert-count 1 t:$pmux
-design -stash gate
-design -import gold -as gold
-design -import gate -as gate
-miter -equiv -flatten -make_assert -make_outputs gold gate miter
-sat -verify -prove-asserts -show-ports miter
-
-design -load read
-hierarchy -top mux_if_unbal_5_3_width_mismatch
-prep
-design -save gold
-muxpack
-opt
-stat
-select -assert-count 0 t:$mux
-select -assert-count 2 t:$pmux
-design -stash gate
-design -import gold -as gold
-design -import gate -as gate
-miter -equiv -flatten -make_assert -make_outputs gold gate miter
-sat -verify -prove-asserts -show-ports miter
-
-design -load read
-hierarchy -top mux_if_unbal_4_1_missing
-prep
-design -save gold
-muxpack
-opt
-stat
-select -assert-count 0 t:$mux
-select -assert-count 1 t:$pmux
-design -stash gate
-design -import gold -as gold
-design -import gate -as gate
-miter -equiv -flatten -make_assert -make_outputs gold gate miter
-sat -verify -prove-asserts -show-ports miter
-
-design -load read
-hierarchy -top mux_if_unbal_5_3_order
-prep
-design -save gold
-muxpack
-opt
-stat
-select -assert-count 0 t:$mux
-select -assert-count 1 t:$pmux
-design -stash gate
-design -import gold -as gold
-design -import gate -as gate
-miter -equiv -flatten -make_assert -make_outputs gold gate miter
-sat -verify -prove-asserts -show-ports miter
-
-design -load read
-hierarchy -top mux_if_unbal_4_1_nonexcl
-prep
-design -save gold
-muxpack
-opt
-stat
-select -assert-count 0 t:$mux
-select -assert-count 1 t:$pmux
-design -stash gate
-design -import gold -as gold
-design -import gate -as gate
-miter -equiv -flatten -make_assert -make_outputs gold gate miter
-sat -verify -prove-asserts -show-ports miter
-
-design -load read
-hierarchy -top mux_if_unbal_5_3_nonexcl
-prep
-design -save gold
-muxpack
-opt
-stat
-select -assert-count 0 t:$mux
-select -assert-count 1 t:$pmux
-design -stash gate
-design -import gold -as gold
-design -import gate -as gate
-miter -equiv -flatten -make_assert -make_outputs gold gate miter
-sat -verify -prove-asserts -show-ports miter
-
-design -load read
-hierarchy -top mux_case_unbal_8_7
-prep
-design -save gold
-muxpack
-opt
-stat
-select -assert-count 0 t:$mux
-select -assert-count 1 t:$pmux
-design -stash gate
-design -import gold -as gold
-design -import gate -as gate
-miter -equiv -flatten -make_assert -make_outputs gold gate miter
-sat -verify -prove-asserts -show-ports miter
-- 
cgit v1.2.3


From 014606affe3f1753ac16d2afd684967d72d83746 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 20 Jun 2019 17:29:45 -0700
Subject: Fix issue with part of PI being 1'bx

---
 tests/simple_abc9/abc9.v | 5 +++++
 1 file changed, 5 insertions(+)

(limited to 'tests')

diff --git a/tests/simple_abc9/abc9.v b/tests/simple_abc9/abc9.v
index 0b83c34a3..64b625efe 100644
--- a/tests/simple_abc9/abc9.v
+++ b/tests/simple_abc9/abc9.v
@@ -262,3 +262,8 @@ endmodule
 module abc9_test025(input [3:0] i, output [3:0] o);
 abc9_test024_sub a(i[2:1], o[2:1]);
 endmodule
+
+module abc9_test026(output [3:0] o, p);
+assign o = { 1'b1, 1'bx };
+assign p = { 1'b1, 1'bx, 1'b0 };
+endmodule
-- 
cgit v1.2.3


From 9dca024a30e5f6cfb06e1abb584ce1320fb81f16 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Mon, 24 Jun 2019 21:52:53 -0700
Subject: Add tests/various/abc9.{v,ys} with SCC test

---
 tests/various/abc9.v  |  5 +++++
 tests/various/abc9.ys | 14 ++++++++++++++
 2 files changed, 19 insertions(+)
 create mode 100644 tests/various/abc9.v
 create mode 100644 tests/various/abc9.ys

(limited to 'tests')

diff --git a/tests/various/abc9.v b/tests/various/abc9.v
new file mode 100644
index 000000000..8271cd249
--- /dev/null
+++ b/tests/various/abc9.v
@@ -0,0 +1,5 @@
+module abc9_test027(output reg o);
+initial o = 1'b0;
+always @*
+    o <= ~o;
+endmodule
diff --git a/tests/various/abc9.ys b/tests/various/abc9.ys
new file mode 100644
index 000000000..922f7005d
--- /dev/null
+++ b/tests/various/abc9.ys
@@ -0,0 +1,14 @@
+read_verilog abc9.v
+proc
+design -save gold
+
+abc9 -lut 4
+check
+design -stash gate
+
+design -import gold -as gold
+design -import gate -as gate
+
+miter -equiv -flatten -make_assert -make_outputs gold gate miter
+sat -verify -prove-asserts -show-ports miter
+
-- 
cgit v1.2.3


From 6c256b8cda66e2ba128d5fa3ba344fe4717711f8 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 27 Jun 2019 11:20:15 -0700
Subject: Merge origin/master

---
 tests/various/muxcover.ys | 320 ++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 320 insertions(+)

(limited to 'tests')

diff --git a/tests/various/muxcover.ys b/tests/various/muxcover.ys
index 8ef619b46..67e9625e6 100644
--- a/tests/various/muxcover.ys
+++ b/tests/various/muxcover.ys
@@ -188,3 +188,323 @@ design -import gate -as gate
 miter -equiv -flatten -make_assert -make_outputs gold gate miter
 sat -verify -prove-asserts -show-ports miter
 
+## MUX2 in MUX4 :: https://github.com/YosysHQ/yosys/issues/1132
+
+design -reset
+read_verilog -formal <<EOT
+module mux2in4(input [1:0] i, input s, output o);
+    assign o = s ? i[1] : i[0];
+endmodule
+EOT
+prep
+design -save gold
+
+techmap
+muxcover -mux4=99 -nodecode
+clean
+opt_expr -mux_bool
+select -assert-count 0 t:$_MUX_
+select -assert-count 1 t:$_MUX4_
+select -assert-count 0 t:$_MUX8_
+select -assert-count 0 t:$_MUX16_
+techmap -map +/simcells.v t:$_MUX4_
+design -stash gate
+
+design -import gold -as gold
+design -import gate -as gate
+
+miter -equiv -flatten -make_assert -make_outputs gold gate miter
+sat -verify -prove-asserts -show-ports miter
+
+## MUX2 in MUX8 :: https://github.com/YosysHQ/yosys/issues/1132
+
+design -reset
+read_verilog -formal <<EOT
+module mux2in8(input [1:0] i, input s, output o);
+    assign o = s ? i[1] : i[0];
+endmodule
+EOT
+prep
+design -save gold
+
+techmap
+muxcover -mux8=99 -nodecode
+clean
+opt_expr -mux_bool
+select -assert-count 0 t:$_MUX_
+select -assert-count 0 t:$_MUX4_
+select -assert-count 1 t:$_MUX8_
+select -assert-count 0 t:$_MUX16_
+techmap -map +/simcells.v t:$_MUX8_
+design -stash gate
+
+design -import gold -as gold
+design -import gate -as gate
+
+miter -equiv -flatten -make_assert -make_outputs gold gate miter
+sat -verify -prove-asserts -show-ports miter
+
+## MUX4 in MUX8 :: https://github.com/YosysHQ/yosys/issues/1132
+
+design -reset
+read_verilog -formal <<EOT
+module mux4in8(input [3:0] i, input [1:0] s, output o);
+    assign o = s[1] ? (s[0] ? i[3] : i[2]) : (s[0] ? i[1] : i[0]);
+endmodule
+EOT
+prep
+design -save gold
+
+techmap
+muxcover -mux8=299 -nodecode
+clean
+opt_expr -mux_bool
+select -assert-count 0 t:$_MUX_
+select -assert-count 0 t:$_MUX4_
+select -assert-count 1 t:$_MUX8_
+select -assert-count 0 t:$_MUX16_
+techmap -map +/simcells.v t:$_MUX8_
+design -stash gate
+
+design -import gold -as gold
+design -import gate -as gate
+
+miter -equiv -flatten -make_assert -make_outputs gold gate miter
+sat -verify -prove-asserts -show-ports miter
+
+## MUX2 in MUX16 :: https://github.com/YosysHQ/yosys/issues/1132
+
+design -reset
+read_verilog -formal <<EOT
+module mux2in16(input [1:0] i, input s, output o);
+    assign o = s ? i[1] : i[0];
+endmodule
+EOT
+prep
+design -save gold
+
+techmap
+muxcover -mux16=99 -nodecode
+clean
+opt_expr -mux_bool
+select -assert-count 0 t:$_MUX_
+select -assert-count 0 t:$_MUX4_
+select -assert-count 0 t:$_MUX8_
+select -assert-count 1 t:$_MUX16_
+techmap -map +/simcells.v t:$_MUX16_
+design -stash gate
+
+design -import gold -as gold
+design -import gate -as gate
+
+miter -equiv -flatten -make_assert -make_outputs gold gate miter
+sat -verify -prove-asserts -show-ports miter
+
+## MUX4 in MUX16 :: https://github.com/YosysHQ/yosys/issues/1132
+
+design -reset
+read_verilog -formal <<EOT
+module mux4in16(input [3:0] i, input [1:0] s, output o);
+    assign o = s[1] ? (s[0] ? i[3] : i[2]) : (s[0] ? i[1] : i[0]);
+endmodule
+EOT
+prep
+design -save gold
+
+techmap
+muxcover -mux16=299 -nodecode
+clean
+opt_expr -mux_bool
+select -assert-count 0 t:$_MUX_
+select -assert-count 0 t:$_MUX4_
+select -assert-count 0 t:$_MUX8_
+select -assert-count 1 t:$_MUX16_
+techmap -map +/simcells.v t:$_MUX16_
+design -stash gate
+
+design -import gold -as gold
+design -import gate -as gate
+
+miter -equiv -flatten -make_assert -make_outputs gold gate miter
+sat -verify -prove-asserts -show-ports miter
+
+## MUX8 in MUX16 :: https://github.com/YosysHQ/yosys/issues/1132
+
+design -reset
+read_verilog -formal <<EOT
+module mux4in16(input [7:0] i, input [2:0] s, output o);
+    assign o = s[2] ? s[1] ? (s[0] ? i[3] : i[2]) : (s[0] ? i[1] : i[0])
+                    : s[1] ? (s[0] ? i[7] : i[6]) : (s[0] ? i[5] : i[4]);
+endmodule
+EOT
+prep
+design -save gold
+
+techmap
+muxcover -mux16=699 -nodecode
+clean
+opt_expr -mux_bool
+select -assert-count 0 t:$_MUX_
+select -assert-count 0 t:$_MUX4_
+select -assert-count 0 t:$_MUX8_
+select -assert-count 1 t:$_MUX16_
+techmap -map +/simcells.v t:$_MUX16_
+design -stash gate
+
+design -import gold -as gold
+design -import gate -as gate
+
+miter -equiv -flatten -make_assert -make_outputs gold gate miter
+sat -verify -prove-asserts -show-ports miter
+
+## mux_if_bal_5_1 :: https://github.com/YosysHQ/yosys/issues/1132
+
+design -reset
+read_verilog -formal <<EOT
+module mux_if_bal_5_1 #(parameter N=5, parameter W=1) (input [N*W-1:0] i, input [$clog2(N)-1:0] s, output reg [W-1:0] o);
+always @* begin
+    o <= {{W{{1'bx}}}};
+    if (s[0] == 1'b0)
+     if (s[1] == 1'b0)
+      if (s[2] == 1'b0)
+       o <= i[0*W+:W];
+      else
+       o <= i[1*W+:W];
+     else
+      if (s[2] == 1'b0)
+       o <= i[2*W+:W];
+      else
+       o <= i[3*W+:W];
+    else
+     if (s[1] == 1'b0)
+      if (s[2] == 1'b0)
+       o <= i[4*W+:W];
+end
+endmodule
+EOT
+prep
+design -save gold
+
+wreduce
+opt -full
+techmap
+muxcover -mux8=350
+clean
+opt_expr -mux_bool
+select -assert-count 0 t:$_MUX_
+select -assert-count 0 t:$_MUX4_
+select -assert-count 1 t:$_MUX8_
+select -assert-count 0 t:$_MUX16_
+techmap -map +/simcells.v t:$_MUX8_
+design -stash gate
+
+design -import gold -as gold
+design -import gate -as gate
+
+miter -equiv -flatten -make_assert -make_outputs -ignore_gold_x gold gate miter
+sat -verify -prove-asserts -show-ports miter
+
+## mux_if_bal_5_1 (nodecode) :: https://github.com/YosysHQ/yosys/issues/1132
+design -load gold
+
+wreduce
+opt -full
+techmap
+muxcover -mux8=350 -nodecode
+clean
+opt_expr -mux_bool
+select -assert-count 0 t:$_MUX_
+select -assert-count 0 t:$_MUX4_
+select -assert-count 1 t:$_MUX8_
+select -assert-count 0 t:$_MUX16_
+techmap -map +/simcells.v t:$_MUX8_
+design -stash gate
+
+design -import gold -as gold
+design -import gate -as gate
+
+miter -equiv -flatten -make_assert -make_outputs -ignore_gold_x gold gate miter
+sat -verify -prove-asserts -show-ports miter
+
+## mux_if_bal_9_1 :: https://github.com/YosysHQ/yosys/issues/1132
+
+design -reset
+read_verilog -formal <<EOT
+module mux_if_bal_9_1 #(parameter N=9, parameter W=1) (input [N*W-1:0] i, input [$clog2(N)-1:0] s, output reg [W-1:0] o);
+always @* begin
+    o <= {{W{{1'bx}}}};
+    if (s[3] == 1'b0)
+     if (s[2] == 1'b0)
+      if (s[1] == 1'b0)
+       if (s[0] == 1'b0)
+        o <= i[0*W+:W];
+       else
+        o <= i[1*W+:W];
+      else
+       if (s[0] == 1'b0)
+        o <= i[2*W+:W];
+       else
+        o <= i[3*W+:W];
+     else
+      if (s[1] == 1'b0)
+       if (s[0] == 1'b0)
+        o <= i[4*W+:W];
+       else
+        o <= i[5*W+:W];
+      else
+       if (s[0] == 1'b0)
+        o <= i[6*W+:W];
+       else
+        o <= i[7*W+:W];
+    else
+     if (s[2] == 1'b0)
+      if (s[1] == 1'b0)
+       if (s[0] == 1'b0)
+        o <= i[8*W+:W];
+end
+endmodule
+EOT
+prep
+design -save gold
+
+wreduce
+opt -full
+techmap
+muxcover -mux16=750
+clean
+opt_expr -mux_bool
+select -assert-count 0 t:$_MUX_
+select -assert-count 0 t:$_MUX4_
+select -assert-count 0 t:$_MUX8_
+select -assert-count 1 t:$_MUX16_
+techmap -map +/simcells.v t:$_MUX16_
+design -stash gate
+
+design -import gold -as gold
+design -import gate -as gate
+
+miter -equiv -flatten -make_assert -make_outputs -ignore_gold_x gold gate miter
+sat -verify -prove-asserts -show-ports miter
+
+## mux_if_bal_9_1 (nodecode) :: https://github.com/YosysHQ/yosys/issues/1132
+
+design -load gold
+
+wreduce
+opt -full
+techmap
+muxcover -mux16=750 -nodecode
+clean
+opt_expr -mux_bool
+select -assert-count 0 t:$_MUX_
+select -assert-count 0 t:$_MUX4_
+select -assert-count 0 t:$_MUX8_
+select -assert-count 1 t:$_MUX16_
+techmap -map +/simcells.v t:$_MUX16_
+design -stash gate
+
+design -import gold -as gold
+design -import gate -as gate
+
+miter -equiv -flatten -make_assert -make_outputs -ignore_gold_x gold gate miter
+sat -verify -prove-asserts -show-ports miter
-- 
cgit v1.2.3