From b515fd2d25851c90c9a0b08414c5ea5edeb916a0 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Tue, 30 Apr 2019 11:25:15 +0200 Subject: Add peepopt_muldiv, fixes #930 Signed-off-by: Clifford Wolf --- tests/simple/peepopt.v | 9 +++++++++ 1 file changed, 9 insertions(+) create mode 100644 tests/simple/peepopt.v (limited to 'tests') diff --git a/tests/simple/peepopt.v b/tests/simple/peepopt.v new file mode 100644 index 000000000..b27b9fe57 --- /dev/null +++ b/tests/simple/peepopt.v @@ -0,0 +1,9 @@ +module peepopt_shiftmul_0 #(parameter N=3, parameter W=3) (input [N*W-1:0] i, input [$clog2(N)-1:0] s, output [W-1:0] o); +assign o = i[s*W+:W]; +endmodule + +module peepopt_muldiv_0(input [1:0] i, output [1:0] o); +wire [3:0] t; +assign t = i * 3; +assign o = t / 3; +endmodule -- cgit v1.2.3 From 6bbe2fdbf32e6335cdbecc21547e54992c3a606d Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Wed, 1 May 2019 10:01:54 +0200 Subject: Add splitcmplxassign test case and silence splitcmplxassign warning Signed-off-by: Clifford Wolf --- tests/simple/mem2reg.v | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) (limited to 'tests') diff --git a/tests/simple/mem2reg.v b/tests/simple/mem2reg.v index 9839fd4a8..100426785 100644 --- a/tests/simple/mem2reg.v +++ b/tests/simple/mem2reg.v @@ -92,3 +92,25 @@ module mem2reg_test5(input ctrl, output out); assign out = bar[foo[0]]; endmodule +// ------------------------------------------------------ + +module mem2reg_test6 (din, dout); + input wire [3:0] din; + output reg [3:0] dout; + + reg [1:0] din_array [1:0]; + reg [1:0] dout_array [1:0]; + + always @* begin + din_array[0] = din[0 +: 2]; + din_array[1] = din[2 +: 2]; + + dout_array[0] = din_array[0]; + dout_array[1] = din_array[1]; + + {dout_array[0][1], dout_array[0][0]} = dout_array[0][0] + dout_array[1][0]; + + dout[0 +: 2] = dout_array[0]; + dout[2 +: 2] = dout_array[1]; + end +endmodule -- cgit v1.2.3 From 38f5424f92389d6f4fdf020b214023b2b6efa71a Mon Sep 17 00:00:00 2001 From: Jim Lawson Date: Wed, 1 May 2019 13:16:01 -0700 Subject: Fix #938 - Crash occurs in case when use write_firrtl command Add missing memory initialization. Sanity-check memory parameters. Add Cell pointer to memory object (for error reporting). --- tests/memories/firrtl_938.v | 22 ++++++++++++++++++++++ tests/simple/xfirrtl | 1 + 2 files changed, 23 insertions(+) create mode 100644 tests/memories/firrtl_938.v (limited to 'tests') diff --git a/tests/memories/firrtl_938.v b/tests/memories/firrtl_938.v new file mode 100644 index 000000000..af5efcd25 --- /dev/null +++ b/tests/memories/firrtl_938.v @@ -0,0 +1,22 @@ +module top +( + input [7:0] data_a, + input [6:1] addr_a, + input we_a, clk, + output reg [7:0] q_a +); + // Declare the RAM variable + reg [7:0] ram[63:0]; + + // Port A + always @ (posedge clk) + begin + if (we_a) + begin + ram[addr_a] <= data_a; + q_a <= data_a; + end + q_a <= ram[addr_a]; + end + +endmodule diff --git a/tests/simple/xfirrtl b/tests/simple/xfirrtl index 50d693513..ba61a4476 100644 --- a/tests/simple/xfirrtl +++ b/tests/simple/xfirrtl @@ -16,6 +16,7 @@ operators.v $pow partsel.v drops modules process.v drops modules realexpr.v drops modules +retime.v Initial value (11110101) for (retime_test.ff) not supported scopes.v original verilog issues ( -x where x isn't declared signed) sincos.v $adff specify.v no code (empty module generates error -- cgit v1.2.3 From 98ffe5fb007c0e0d348f961a4e99d8b2f241eac1 Mon Sep 17 00:00:00 2001 From: Jakob Wenzel Date: Thu, 25 Apr 2019 15:12:24 +0200 Subject: fail svinterfaces testcases on yosys error exit --- tests/svinterfaces/runone.sh | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'tests') diff --git a/tests/svinterfaces/runone.sh b/tests/svinterfaces/runone.sh index 0adecc797..71c2d4976 100755 --- a/tests/svinterfaces/runone.sh +++ b/tests/svinterfaces/runone.sh @@ -11,13 +11,13 @@ echo "" > $STDERRFILE echo -n "Test: ${TESTNAME} -> " +set -e + $PWD/../../yosys -p "read_verilog -sv ${TESTNAME}.sv ; hierarchy -check -top TopModule ; synth ; write_verilog ${TESTNAME}_syn.v" >> $STDOUTFILE >> $STDERRFILE $PWD/../../yosys -p "read_verilog -sv ${TESTNAME}_ref.v ; hierarchy -check -top TopModule ; synth ; write_verilog ${TESTNAME}_ref_syn.v" >> $STDOUTFILE >> $STDERRFILE rm -f a.out reference_result.txt dut_result.txt -set -e - iverilog -g2012 ${TESTNAME}_syn.v iverilog -g2012 ${TESTNAME}_ref_syn.v -- cgit v1.2.3 From d2aa123226f39fb6d076b9a0add2ad4f0e596166 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Fri, 3 May 2019 14:40:51 +0200 Subject: Fix typo in tests/svinterfaces/runone.sh Signed-off-by: Clifford Wolf --- tests/svinterfaces/runone.sh | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'tests') diff --git a/tests/svinterfaces/runone.sh b/tests/svinterfaces/runone.sh index 71c2d4976..54cf5f2ec 100755 --- a/tests/svinterfaces/runone.sh +++ b/tests/svinterfaces/runone.sh @@ -13,8 +13,8 @@ echo -n "Test: ${TESTNAME} -> " set -e -$PWD/../../yosys -p "read_verilog -sv ${TESTNAME}.sv ; hierarchy -check -top TopModule ; synth ; write_verilog ${TESTNAME}_syn.v" >> $STDOUTFILE >> $STDERRFILE -$PWD/../../yosys -p "read_verilog -sv ${TESTNAME}_ref.v ; hierarchy -check -top TopModule ; synth ; write_verilog ${TESTNAME}_ref_syn.v" >> $STDOUTFILE >> $STDERRFILE +$PWD/../../yosys -p "read_verilog -sv ${TESTNAME}.sv ; hierarchy -check -top TopModule ; synth ; write_verilog ${TESTNAME}_syn.v" >> $STDOUTFILE 2>> $STDERRFILE +$PWD/../../yosys -p "read_verilog -sv ${TESTNAME}_ref.v ; hierarchy -check -top TopModule ; synth ; write_verilog ${TESTNAME}_ref_syn.v" >> $STDOUTFILE 2>> $STDERRFILE rm -f a.out reference_result.txt dut_result.txt -- cgit v1.2.3 From 1e5f072c0556158924387dedbb78b4cc61bfcf7a Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 3 May 2019 14:03:51 -0700 Subject: iverilog with simcells.v as well --- tests/tools/autotest.sh | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'tests') diff --git a/tests/tools/autotest.sh b/tests/tools/autotest.sh index bb9c3bfb5..920474a84 100755 --- a/tests/tools/autotest.sh +++ b/tests/tools/autotest.sh @@ -147,7 +147,8 @@ do fi if $genvcd; then sed -i 's,// \$dump,$dump,g' ${bn}_tb.v; fi compile_and_run ${bn}_tb_ref ${bn}_out_ref ${bn}_tb.v ${bn}_ref.v $libs \ - "$toolsdir"/../../techlibs/common/simlib.v + "$toolsdir"/../../techlibs/common/simlib.v \ + "$toolsdir"/../../techlibs/common/simcells.v if $genvcd; then mv testbench.vcd ${bn}_ref.vcd; fi test_count=0 -- cgit v1.2.3