From a7cc4673c3f75f414a82c81a507da5042bba361f Mon Sep 17 00:00:00 2001 From: Claire Wolf Date: Sun, 8 Mar 2020 16:12:12 +0100 Subject: Fix partsel expr bit width handling and add test case Signed-off-by: Claire Wolf --- tests/simple/partsel.v | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'tests') diff --git a/tests/simple/partsel.v b/tests/simple/partsel.v index 7461358ad..83493fcb0 100644 --- a/tests/simple/partsel.v +++ b/tests/simple/partsel.v @@ -60,3 +60,7 @@ always @(posedge clk) begin end endmodule + +module partsel_test003(input [2:0] a, b, input [31:0] din, output [3:0] dout); +assign dout = din[a*b +: 2]; +endmodule -- cgit v1.2.3