From d20c1dac73e344dda73ec2b526ffb764efc9fdd8 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 13 Feb 2020 17:58:43 -0800 Subject: verilog: ignore ranges too without -specify --- tests/various/specify.v | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'tests') diff --git a/tests/various/specify.v b/tests/various/specify.v index 5655ded21..c160d2ec4 100644 --- a/tests/various/specify.v +++ b/tests/various/specify.v @@ -55,3 +55,10 @@ specify $setup(d, posedge clk &&& e, 1:2:3); endspecify endmodule + +module test6(input clk, d, e, output q); +specify + (d[0] *> q[0]) = (3,1); + (posedge clk[0] => (q[0] +: d[0])) = (3,1); +endspecify +endmodule -- cgit v1.2.3