From c43e52d2d7d16c26b1a4a9c20fad83c9f4577910 Mon Sep 17 00:00:00 2001
From: David Shah <dave@ds0.me>
Date: Wed, 11 Sep 2019 13:55:16 +0100
Subject: Add equiv_opt -multiclock

Signed-off-by: David Shah <dave@ds0.me>
---
 tests/various/equiv_opt_multiclock.ys | 12 ++++++++++++
 1 file changed, 12 insertions(+)
 create mode 100644 tests/various/equiv_opt_multiclock.ys

(limited to 'tests')

diff --git a/tests/various/equiv_opt_multiclock.ys b/tests/various/equiv_opt_multiclock.ys
new file mode 100644
index 000000000..81e36d018
--- /dev/null
+++ b/tests/various/equiv_opt_multiclock.ys
@@ -0,0 +1,12 @@
+read_verilog <<EOT
+module top(input clk, pre, d, output reg q);
+	always @(posedge clk, posedge pre)
+		if (pre)
+			q <= 1'b1;
+		else
+			q <= d;
+endmodule
+EOT
+
+prep
+equiv_opt -assert -multiclock -map +/simcells.v synth
-- 
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