From c1ed1c28be9bd9880cc036d13f43294bf257788b Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Marcelina=20Ko=C5=9Bcielnicka?= <mwk@0x04.net>
Date: Wed, 5 Aug 2020 21:01:20 +0200
Subject: peeopt.shiftmul: Add a signedness check.

Fixes #2332.
---
 tests/techmap/bug2332.ys | 11 +++++++++++
 1 file changed, 11 insertions(+)
 create mode 100644 tests/techmap/bug2332.ys

(limited to 'tests')

diff --git a/tests/techmap/bug2332.ys b/tests/techmap/bug2332.ys
new file mode 100644
index 000000000..ed6b35eb2
--- /dev/null
+++ b/tests/techmap/bug2332.ys
@@ -0,0 +1,11 @@
+read_verilog <<EOT
+module top(input [31:0] a, input signed [2:0] x, output [2:0] o);
+
+wire [5:0] t = x * 3;
+assign o = a >> t;
+
+endmodule
+EOT
+
+wreduce
+equiv_opt -assert peepopt
-- 
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