From f9c096eedabdf7cd2cdd770da73bdd17d86559e7 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Mon, 27 Oct 2014 13:21:57 +0100 Subject: Added support for task and function args in parentheses --- tests/simple/task_func.v | 36 +++++++++++++++++++++++++++++++++++- 1 file changed, 35 insertions(+), 1 deletion(-) (limited to 'tests') diff --git a/tests/simple/task_func.v b/tests/simple/task_func.v index 51e31015f..9b8e26e51 100644 --- a/tests/simple/task_func.v +++ b/tests/simple/task_func.v @@ -33,8 +33,42 @@ end endmodule +// ------------------------------------------------------------------- -module task_func_test02( input [7:0] din_a, input [7:0] din_b, output [7:0] dout_a); +module task_func_test02(clk, a, b, c, x, y, z, w); + +input clk; +input [7:0] a, b, c; +output reg [7:0] x, y, z, w; + +function [7:0] sum_shift(input [3:0] s1, s2, s3); +sum_shift = s1 + (s2 << 2) + (s3 << 4); +endfunction + +task reset_w; +w = 0; +endtask + +task add_to(output [7:0] out, input [7:0] in); +out = out + in; +endtask + +always @(posedge clk) begin + x = sum_shift(a, b, c); + y = sum_shift(a[7:4], b[5:2], c[3:0]); + z = sum_shift(a[0], b[5:4], c >> 5) ^ sum_shift(1, 2, 3); + + reset_w; + add_to(w, x); + add_to(w, y); + add_to(w, z); +end + +endmodule + +// ------------------------------------------------------------------- + +module task_func_test03( input [7:0] din_a, input [7:0] din_b, output [7:0] dout_a); assign dout_a = test(din_a,din_b); function [7:0] test; input [7:0] a; -- cgit v1.2.3 From 1e0f6b5ddbfc3a7bc30f2537decf45654e7f1524 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sun, 9 Nov 2014 11:02:20 +0100 Subject: Added "yosys -qq" to also quiet warning messages --- tests/realmath/run-test.sh | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'tests') diff --git a/tests/realmath/run-test.sh b/tests/realmath/run-test.sh index b8e222ad6..0997ccb5d 100755 --- a/tests/realmath/run-test.sh +++ b/tests/realmath/run-test.sh @@ -11,7 +11,7 @@ echo "running tests.." for ((i = 0; i < 100; i++)); do echo -n "[$i]" idx=$( printf "%05d" $i ) - ../../../yosys -q uut_${idx}.ys + ../../../yosys -qq uut_${idx}.ys iverilog -o uut_${idx}_tb uut_${idx}_tb.v uut_${idx}.v uut_${idx}_syn.v ./uut_${idx}_tb | tee uut_${idx}.err if test -s uut_${idx}.err; then -- cgit v1.2.3 From 340e7696670a4a7f46b01f2414945e6c4cefb1ce Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Thu, 1 Jan 2015 17:01:17 +0100 Subject: Bram testbench (incomplete) --- tests/bram/.gitignore | 1 + tests/bram/generate.py | 119 +++++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 120 insertions(+) create mode 100644 tests/bram/.gitignore create mode 100644 tests/bram/generate.py (limited to 'tests') diff --git a/tests/bram/.gitignore b/tests/bram/.gitignore new file mode 100644 index 000000000..9c595a6fb --- /dev/null +++ b/tests/bram/.gitignore @@ -0,0 +1 @@ +temp diff --git a/tests/bram/generate.py b/tests/bram/generate.py new file mode 100644 index 000000000..f33bc8e03 --- /dev/null +++ b/tests/bram/generate.py @@ -0,0 +1,119 @@ +#!/usr/bin/python + +from __future__ import division +from __future__ import print_function + +import sys +import random + +def create_bram(dsc_f, sim_f, k1, k2): + while True: + init = random.randrange(2) + abits = random.randrange(1, 16) + dbits = random.randrange(1, 16) + groups = random.randrange(5) + + if random.randrange(2): + abits = 2 ** random.randrange(1, 4) + if random.randrange(2): + dbits = 2 ** random.randrange(1, 4) + + ports = [ random.randrange(3) for i in range(groups) ] + wrmode = [ random.randrange(2) for i in range(groups) ] + enable = [ random.randrange(4) for i in range(groups) ] + transp = [ random.randrange(4) for i in range(groups) ] + clocks = [ random.randrange(4) for i in range(groups) ] + clkpol = [ random.randrange(4) for i in range(groups) ] + + for p1 in range(groups): + if wrmode[p1] == 0: + enable[p1] = 0 + else: + enable[p1] = 2**enable[p1] + while dbits < enable[p1] or dbits % enable[p1] != 0: + enable[p1] //= 2 + + config_ok = True + if wrmode.count(1) <= ports.count(0): config_ok = False + if wrmode.count(0) <= ports.count(0): config_ok = False + if config_ok: break + + print('bram bram_%03d_%03d' % (k1, k2), file=dsc_f) + print(' init %d' % init, file=dsc_f) + print(' abits %d' % abits, file=dsc_f) + print(' dbits %d' % dbits, file=dsc_f) + print(' groups %d' % groups, file=dsc_f) + print(' ports %s' % " ".join(["%d" % i for i in ports]), file=dsc_f) + print(' wrmode %s' % " ".join(["%d" % i for i in wrmode]), file=dsc_f) + print(' enable %s' % " ".join(["%d" % i for i in enable]), file=dsc_f) + print(' transp %s' % " ".join(["%d" % i for i in transp]), file=dsc_f) + print(' clocks %s' % " ".join(["%d" % i for i in clocks]), file=dsc_f) + print(' clkpol %s' % " ".join(["%d" % i for i in clkpol]), file=dsc_f) + print('endbram', file=dsc_f) + print('match bram_%03d_%03d' % (k1, k2), file=dsc_f) + print('endmatch', file=dsc_f) + + states = set() + v_ports = set() + v_stmts = list() + + v_stmts.append("reg [%d:0] memory [0:%d];" % (dbits-1, 2**abits-1)) + + for p1 in range(groups): + for p2 in range(ports[p1]): + pf = "%c%d" % (chr(ord('A') + p1), p2 + 1) + + if clocks[p1] and not ("CLK%d" % clocks[p1]) in v_ports: + v_ports.add("CLK%d" % clocks[p1]) + v_stmts.append("input CLK%d;" % clocks[p1]) + + v_ports.add("%sADDR" % pf) + v_stmts.append("input [%d:0] %sADDR;" % (abits-1, pf)) + + v_ports.add("%sDATA" % pf) + v_stmts.append("%s [%d:0] %sDATA;" % ("input" if wrmode[p1] else "output reg", dbits-1, pf)) + + if wrmode[p1] and enable[p1]: + v_ports.add("%sEN" % pf) + v_stmts.append("input [%d:0] %sEN;" % (enable[p1]-1, pf)) + + assign_op = "<=" + if clocks[p1] == 0: + v_stmts.append("always @* begin") + assign_op = "=" + elif clkpol[p1] == 0: + v_stmts.append("always @(negedge CLK%d) begin" % clocks[p1]) + elif clkpol[p1] == 1: + v_stmts.append("always @(posedge CLK%d) begin" % clocks[p1]) + else: + if not ('CP', clkpol[p1]) in states: + v_stmts.append("parameter CLKPOL%d = 0;" % clkpol[p1]) + states.add(('CP', clkpol[p1])) + if not ('CPW', clocks[p1], clkpol[p1]) in states: + v_stmts.append("wire CLK%d_CLKPOL%d = CLK%d == CLKPOL%d;" % (clocks[p1], clkpol[p1], clocks[p1], clkpol[p1])) + states.add(('CPW', clocks[p1], clkpol[p1])) + v_stmts.append("always @(posedge CLK%d_CLKPOL%d) begin" % (clocks[p1], clkpol[p1])) + + if wrmode[p1]: + for i in range(enable[p1]): + enrange = "[%d:%d]" % ((i+1)*dbits/enable[p1]-1, i*dbits/enable[p1]) + v_stmts.append(" if (%sEN[%d]) memory[%sADDR]%s %s %sDATA%s;" % (pf, i, pf, enrange, assign_op, pf, enrange)) + else: + v_stmts.append(" %sDATA %s memory[%sADDR];" % (pf, assign_op, pf)) + v_stmts.append("end") + + print('module bram_%03d_%03d(%s);' % (k1, k2, ", ".join(v_ports)), file=sim_f) + for stmt in v_stmts: + print(' %s' % stmt, file=sim_f) + print('endmodule', file=sim_f) + +for k1 in range(10): + dsc_f = file('temp/brams_%03d.txt' % k1, 'w'); + sim_f = file('temp/brams_%03d.v' % k1, 'w'); + + for k2 in range(10): + create_bram(dsc_f, sim_f, k1, k2) + + dsc_f.close() + sim_f.close() + -- cgit v1.2.3 From 24ae156a747d5b933693878e7f2ed4c311e36570 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Thu, 1 Jan 2015 19:42:39 +0100 Subject: Progress in bram testbench --- tests/bram/generate.py | 185 ++++++++++++++++++++++++++++++++++++----------- tests/bram/run-single.sh | 9 +++ tests/bram/run-test.sh | 32 ++++++++ 3 files changed, 184 insertions(+), 42 deletions(-) create mode 100644 tests/bram/run-single.sh create mode 100755 tests/bram/run-test.sh (limited to 'tests') diff --git a/tests/bram/generate.py b/tests/bram/generate.py index f33bc8e03..93255556d 100644 --- a/tests/bram/generate.py +++ b/tests/bram/generate.py @@ -6,11 +6,13 @@ from __future__ import print_function import sys import random -def create_bram(dsc_f, sim_f, k1, k2): +debug_mode = False + +def create_bram(dsc_f, sim_f, ref_f, tb_f, k1, k2): while True: init = random.randrange(2) - abits = random.randrange(1, 16) - dbits = random.randrange(1, 16) + abits = random.randrange(1, 8) + dbits = random.randrange(1, 8) groups = random.randrange(5) if random.randrange(2): @@ -25,6 +27,12 @@ def create_bram(dsc_f, sim_f, k1, k2): clocks = [ random.randrange(4) for i in range(groups) ] clkpol = [ random.randrange(4) for i in range(groups) ] + # XXX + init = 0 + transp = [ 0 for i in range(groups) ] + clocks = [ random.randrange(1, 4) for i in range(groups) ] + clkpol = [ 1 for i in range(groups) ] + for p1 in range(groups): if wrmode[p1] == 0: enable[p1] = 0 @@ -38,82 +46,175 @@ def create_bram(dsc_f, sim_f, k1, k2): if wrmode.count(0) <= ports.count(0): config_ok = False if config_ok: break - print('bram bram_%03d_%03d' % (k1, k2), file=dsc_f) - print(' init %d' % init, file=dsc_f) - print(' abits %d' % abits, file=dsc_f) - print(' dbits %d' % dbits, file=dsc_f) - print(' groups %d' % groups, file=dsc_f) - print(' ports %s' % " ".join(["%d" % i for i in ports]), file=dsc_f) - print(' wrmode %s' % " ".join(["%d" % i for i in wrmode]), file=dsc_f) - print(' enable %s' % " ".join(["%d" % i for i in enable]), file=dsc_f) - print(' transp %s' % " ".join(["%d" % i for i in transp]), file=dsc_f) - print(' clocks %s' % " ".join(["%d" % i for i in clocks]), file=dsc_f) - print(' clkpol %s' % " ".join(["%d" % i for i in clkpol]), file=dsc_f) - print('endbram', file=dsc_f) - print('match bram_%03d_%03d' % (k1, k2), file=dsc_f) - print('endmatch', file=dsc_f) + print("bram bram_%02d_%02d" % (k1, k2), file=dsc_f) + print(" init %d" % init, file=dsc_f) + print(" abits %d" % abits, file=dsc_f) + print(" dbits %d" % dbits, file=dsc_f) + print(" groups %d" % groups, file=dsc_f) + print(" ports %s" % " ".join(["%d" % i for i in ports]), file=dsc_f) + print(" wrmode %s" % " ".join(["%d" % i for i in wrmode]), file=dsc_f) + print(" enable %s" % " ".join(["%d" % i for i in enable]), file=dsc_f) + print(" transp %s" % " ".join(["%d" % i for i in transp]), file=dsc_f) + print(" clocks %s" % " ".join(["%d" % i for i in clocks]), file=dsc_f) + print(" clkpol %s" % " ".join(["%d" % i for i in clkpol]), file=dsc_f) + print("endbram", file=dsc_f) + print("match bram_%02d_%02d" % (k1, k2), file=dsc_f) + print("endmatch", file=dsc_f) states = set() v_ports = set() v_stmts = list() + v_always = dict() + + tb_decls = list() + tb_clocks = list() + tb_addr = list() + tb_din = list() + tb_dout = list() + tb_addrlist = list() + tb_delay = 0 + + for i in range(10): + tb_addrlist.append(random.randrange(1048576)) - v_stmts.append("reg [%d:0] memory [0:%d];" % (dbits-1, 2**abits-1)) + t = random.randrange(1048576) + for i in range(10): + tb_addrlist.append(t ^ (1 << i)) + + v_stmts.append("(* nomem2reg *) reg [%d:0] memory [0:%d];" % (dbits-1, 2**abits-1)) for p1 in range(groups): for p2 in range(ports[p1]): - pf = "%c%d" % (chr(ord('A') + p1), p2 + 1) + pf = "%c%d" % (chr(ord("A") + p1), p2 + 1) if clocks[p1] and not ("CLK%d" % clocks[p1]) in v_ports: v_ports.add("CLK%d" % clocks[p1]) v_stmts.append("input CLK%d;" % clocks[p1]) + tb_decls.append("reg CLK%d;" % clocks[p1]) + tb_clocks.append("CLK%d" % clocks[p1]) v_ports.add("%sADDR" % pf) v_stmts.append("input [%d:0] %sADDR;" % (abits-1, pf)) + tb_decls.append("reg [%d:0] %sADDR;" % (abits-1, pf)) + tb_addr.append("%sADDR" % pf) v_ports.add("%sDATA" % pf) v_stmts.append("%s [%d:0] %sDATA;" % ("input" if wrmode[p1] else "output reg", dbits-1, pf)) + if wrmode[p1]: + tb_decls.append("reg [%d:0] %sDATA;" % (dbits-1, pf)) + tb_din.append("%sDATA" % pf) + else: + tb_decls.append("wire [%d:0] %sDATA;" % (dbits-1, pf)) + tb_decls.append("wire [%d:0] %sDATA_R;" % (dbits-1, pf)) + tb_dout.append("%sDATA" % pf) + if wrmode[p1] and enable[p1]: v_ports.add("%sEN" % pf) v_stmts.append("input [%d:0] %sEN;" % (enable[p1]-1, pf)) + tb_decls.append("reg [%d:0] %sEN;" % (enable[p1]-1, pf)) + tb_din.append("%sEN" % pf) assign_op = "<=" if clocks[p1] == 0: - v_stmts.append("always @* begin") + always_hdr = "always @* begin" assign_op = "=" elif clkpol[p1] == 0: - v_stmts.append("always @(negedge CLK%d) begin" % clocks[p1]) + always_hdr = "always @(negedge CLK%d) begin" % clocks[p1] elif clkpol[p1] == 1: - v_stmts.append("always @(posedge CLK%d) begin" % clocks[p1]) + always_hdr = "always @(posedge CLK%d) begin" % clocks[p1] else: - if not ('CP', clkpol[p1]) in states: + if not ("CP", clkpol[p1]) in states: v_stmts.append("parameter CLKPOL%d = 0;" % clkpol[p1]) - states.add(('CP', clkpol[p1])) - if not ('CPW', clocks[p1], clkpol[p1]) in states: + states.add(("CP", clkpol[p1])) + if not ("CPW", clocks[p1], clkpol[p1]) in states: v_stmts.append("wire CLK%d_CLKPOL%d = CLK%d == CLKPOL%d;" % (clocks[p1], clkpol[p1], clocks[p1], clkpol[p1])) - states.add(('CPW', clocks[p1], clkpol[p1])) - v_stmts.append("always @(posedge CLK%d_CLKPOL%d) begin" % (clocks[p1], clkpol[p1])) + states.add(("CPW", clocks[p1], clkpol[p1])) + always_hdr = "always @(posedge CLK%d_CLKPOL%d) begin" % (clocks[p1], clkpol[p1]) + + if not always_hdr in v_always: + v_always[always_hdr] = list() if wrmode[p1]: + tb_delay += 1 + assign_op += " #%d" % tb_delay for i in range(enable[p1]): enrange = "[%d:%d]" % ((i+1)*dbits/enable[p1]-1, i*dbits/enable[p1]) - v_stmts.append(" if (%sEN[%d]) memory[%sADDR]%s %s %sDATA%s;" % (pf, i, pf, enrange, assign_op, pf, enrange)) + v_always[always_hdr].append("if (%sEN[%d]) memory[%sADDR]%s %s %sDATA%s;" % (pf, i, pf, enrange, assign_op, pf, enrange)) else: - v_stmts.append(" %sDATA %s memory[%sADDR];" % (pf, assign_op, pf)) - v_stmts.append("end") - - print('module bram_%03d_%03d(%s);' % (k1, k2, ", ".join(v_ports)), file=sim_f) - for stmt in v_stmts: - print(' %s' % stmt, file=sim_f) - print('endmodule', file=sim_f) + v_always[always_hdr].append("%sDATA %s memory[%sADDR];" % (pf, assign_op, pf)) -for k1 in range(10): - dsc_f = file('temp/brams_%03d.txt' % k1, 'w'); - sim_f = file('temp/brams_%03d.v' % k1, 'w'); + for a in v_always: + v_stmts.append(a) + for l in v_always[a]: + v_stmts.append(" " + l) + v_stmts.append("end") - for k2 in range(10): - create_bram(dsc_f, sim_f, k1, k2) + print("module bram_%02d_%02d(%s);" % (k1, k2, ", ".join(v_ports)), file=sim_f) + for stmt in v_stmts: + print(" %s" % stmt, file=sim_f) + print("endmodule", file=sim_f) - dsc_f.close() - sim_f.close() + print("module bram_%02d_%02d_ref(%s);" % (k1, k2, ", ".join(v_ports)), file=ref_f) + for stmt in v_stmts: + print(" %s" % stmt, file=ref_f) + print("endmodule", file=ref_f) + + print("module bram_%02d_%02d_tb;" % (k1, k2), file=tb_f) + for stmt in tb_decls: + print(" %s" % stmt, file=tb_f) + print(" bram_%02d_%02d uut (" % (k1, k2), file=tb_f) + print(" " + ",\n ".join([".%s(%s)" % (p, p) for p in (tb_clocks + tb_addr + tb_din + tb_dout)]), file=tb_f) + print(" );", file=tb_f) + print(" bram_%02d_%02d_ref ref (" % (k1, k2), file=tb_f) + print(" " + ",\n ".join([".%s(%s)" % (p, p) for p in (tb_clocks + tb_addr + tb_din)]) + ",", file=tb_f) + print(" " + ",\n ".join([".%s(%s_R)" % (p, p) for p in tb_dout]), file=tb_f) + print(" );", file=tb_f) + + expr_dout = "{%s}" % ", ".join(tb_dout) + expr_dout_ref = "{%s}" % ", ".join(i + "_R" for i in tb_dout) + + print(" wire error = %s !== %s;" % (expr_dout, expr_dout_ref), file=tb_f) + + print(" initial begin", file=tb_f) + + if debug_mode: + print(" $dumpfile(\"temp/bram_%02d_%02d_tb.vcd\");" % (k1, k2), file=tb_f) + print(" $dumpvars(1, bram_%02d_%02d_tb);" % (k1, k2), file=tb_f) + + for p in (tb_clocks + tb_addr + tb_din): + if p[-2:] == "EN": + print(" %s <= ~0;" % p, file=tb_f) + else: + print(" %s <= 0;" % p, file=tb_f) + print(" #%d;" % (1000 + k2), file=tb_f) + + for v in [1, 0, 1, 0]: + for p in tb_clocks: + print(" %s = %d;" % (p, v), file=tb_f) + print(" #1000;", file=tb_f) + + for i in range(100): + for p in tb_din: + print(" %s = %d;" % (p, random.randrange(1048576)), file=tb_f) + for p in tb_addr: + print(" %s = %d;" % (p, random.choice(tb_addrlist)), file=tb_f) + if len(tb_clocks): + c = random.choice(tb_clocks) + print(" %s = !%s;" % (c, c), file=tb_f) + print(" #1;", file=tb_f) + print(" $display(\"bram_%02d_%02d %3d: %%b %%b %%s\", %s, %s, error ? \"ERROR\" : \"OK\");" % + (k1, k2, i, expr_dout, expr_dout_ref), file=tb_f) + + print(" end", file=tb_f) + print("endmodule", file=tb_f) + +for k1 in range(5): + dsc_f = file("temp/brams_%02d.txt" % k1, "w"); + sim_f = file("temp/brams_%02d.v" % k1, "w"); + ref_f = file("temp/brams_%02d_ref.v" % k1, "w"); + tb_f = file("temp/brams_%02d_tb.v" % k1, "w"); + + for k2 in range(1 if debug_mode else 10): + create_bram(dsc_f, sim_f, ref_f, tb_f, k1, k2) diff --git a/tests/bram/run-single.sh b/tests/bram/run-single.sh new file mode 100644 index 000000000..abaae0e2e --- /dev/null +++ b/tests/bram/run-single.sh @@ -0,0 +1,9 @@ +#!/bin/bash +set -e +../../yosys -qq -p "proc; opt; memory -nomap; memory_bram -rules temp/brams_${2}.txt; opt -fast -full" \ + -l temp/synth_${1}_${2}.log -o temp/synth_${1}_${2}.v temp/brams_${1}.v +iverilog -o temp/tb_${1}_${2}.tb temp/brams_${1}_tb.v temp/brams_${1}_ref.v \ + temp/synth_${1}_${2}.v temp/brams_${2}.v ../../techlibs/common/simlib.v +temp/tb_${1}_${2}.tb > temp/tb_${1}_${2}.txt +if grep -H -C1 ERROR temp/tb_${1}_${2}.txt; then exit 1; fi +exit 0 diff --git a/tests/bram/run-test.sh b/tests/bram/run-test.sh new file mode 100755 index 000000000..cc18aff1e --- /dev/null +++ b/tests/bram/run-test.sh @@ -0,0 +1,32 @@ +#!/bin/bash + +# run this test many times: +# time bash -c 'for ((i=0; i<100; i++)); do echo "-- $i --"; bash run-test.sh || exit 1; done' + +set -e +rm -rf temp +mkdir -p temp + +echo "generating tests.." +python generate.py + +{ + echo -n "all:" + for i in $( ls temp/brams_*.txt | sed 's,.*_,,; s,\..*,,;' ); do + for j in $( ls temp/brams_*.txt | sed 's,.*_,,; s,\..*,,;' | grep -v $i ); do + echo -n " temp/job_$i$j.ok" + done; done + echo + for i in $( ls temp/brams_*.txt | sed 's,.*_,,; s,\..*,,;' ); do + for j in $( ls temp/brams_*.txt | sed 's,.*_,,; s,\..*,,;' | grep -v $i ); do + echo "temp/job_$i$j.ok:" + echo " @bash run-single.sh $i $j" + echo " @echo 'Passed test $i vs $j.'" + echo " @touch \$@" + done; done +} > temp/makefile + +echo "running tests.." +${MAKE:-make} -f temp/makefile + +exit 0 -- cgit v1.2.3 From 36c20f2ede51580f7c68b96b9cde9473187a8fc6 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Fri, 2 Jan 2015 00:07:44 +0100 Subject: Progress in memory_bram --- tests/bram/generate.py | 44 +++++++++++++++++++++++++++----------------- tests/bram/run-single.sh | 2 +- tests/bram/run-test.sh | 8 ++++---- 3 files changed, 32 insertions(+), 22 deletions(-) (limited to 'tests') diff --git a/tests/bram/generate.py b/tests/bram/generate.py index 93255556d..37b23a526 100644 --- a/tests/bram/generate.py +++ b/tests/bram/generate.py @@ -13,7 +13,11 @@ def create_bram(dsc_f, sim_f, ref_f, tb_f, k1, k2): init = random.randrange(2) abits = random.randrange(1, 8) dbits = random.randrange(1, 8) - groups = random.randrange(5) + groups = random.randrange(1, 5) + + # XXX + init = 0 + groups = 2 if random.randrange(2): abits = 2 ** random.randrange(1, 4) @@ -28,10 +32,12 @@ def create_bram(dsc_f, sim_f, ref_f, tb_f, k1, k2): clkpol = [ random.randrange(4) for i in range(groups) ] # XXX - init = 0 + ports = [ 1 for i in range(groups) ] + wrmode = [ 1 for i in range(groups) ] transp = [ 0 for i in range(groups) ] - clocks = [ random.randrange(1, 4) for i in range(groups) ] + clocks = [ 1 for i in range(groups) ] clkpol = [ 1 for i in range(groups) ] + wrmode[0] = 0 for p1 in range(groups): if wrmode[p1] == 0: @@ -72,7 +78,6 @@ def create_bram(dsc_f, sim_f, ref_f, tb_f, k1, k2): tb_din = list() tb_dout = list() tb_addrlist = list() - tb_delay = 0 for i in range(10): tb_addrlist.append(random.randrange(1048576)) @@ -133,20 +138,22 @@ def create_bram(dsc_f, sim_f, ref_f, tb_f, k1, k2): always_hdr = "always @(posedge CLK%d_CLKPOL%d) begin" % (clocks[p1], clkpol[p1]) if not always_hdr in v_always: - v_always[always_hdr] = list() + v_always[always_hdr] = [list(), list(), list()] if wrmode[p1]: - tb_delay += 1 - assign_op += " #%d" % tb_delay for i in range(enable[p1]): enrange = "[%d:%d]" % ((i+1)*dbits/enable[p1]-1, i*dbits/enable[p1]) - v_always[always_hdr].append("if (%sEN[%d]) memory[%sADDR]%s %s %sDATA%s;" % (pf, i, pf, enrange, assign_op, pf, enrange)) + v_always[always_hdr][1].append("if (%sEN[%d]) memory[%sADDR]%s = %sDATA%s;" % (pf, i, pf, enrange, pf, enrange)) else: - v_always[always_hdr].append("%sDATA %s memory[%sADDR];" % (pf, assign_op, pf)) + v_always[always_hdr][2 if transp[p1] else 0].append("%sDATA %s memory[%sADDR];" % (pf, assign_op, pf)) for a in v_always: v_stmts.append(a) - for l in v_always[a]: + for l in v_always[a][0]: + v_stmts.append(" " + l) + for l in v_always[a][1]: + v_stmts.append(" " + l) + for l in v_always[a][2]: v_stmts.append(" " + l) v_stmts.append("end") @@ -179,8 +186,8 @@ def create_bram(dsc_f, sim_f, ref_f, tb_f, k1, k2): print(" initial begin", file=tb_f) if debug_mode: - print(" $dumpfile(\"temp/bram_%02d_%02d_tb.vcd\");" % (k1, k2), file=tb_f) - print(" $dumpvars(1, bram_%02d_%02d_tb);" % (k1, k2), file=tb_f) + print(" $dumpfile(`vcd_file);", file=tb_f) + print(" $dumpvars(2, bram_%02d_%02d_tb);" % (k1, k2), file=tb_f) for p in (tb_clocks + tb_addr + tb_din): if p[-2:] == "EN": @@ -195,14 +202,14 @@ def create_bram(dsc_f, sim_f, ref_f, tb_f, k1, k2): print(" #1000;", file=tb_f) for i in range(100): - for p in tb_din: - print(" %s = %d;" % (p, random.randrange(1048576)), file=tb_f) - for p in tb_addr: - print(" %s = %d;" % (p, random.choice(tb_addrlist)), file=tb_f) if len(tb_clocks): c = random.choice(tb_clocks) print(" %s = !%s;" % (c, c), file=tb_f) - print(" #1;", file=tb_f) + for p in tb_din: + print(" %s <= %d;" % (p, random.randrange(1048576)), file=tb_f) + for p in tb_addr: + print(" %s <= %d;" % (p, random.choice(tb_addrlist)), file=tb_f) + print(" #1000;", file=tb_f) print(" $display(\"bram_%02d_%02d %3d: %%b %%b %%s\", %s, %s, error ? \"ERROR\" : \"OK\");" % (k1, k2, i, expr_dout, expr_dout_ref), file=tb_f) @@ -215,6 +222,9 @@ for k1 in range(5): ref_f = file("temp/brams_%02d_ref.v" % k1, "w"); tb_f = file("temp/brams_%02d_tb.v" % k1, "w"); + for f in [sim_f, ref_f, tb_f]: + print("`timescale 1 ns / 1 ns", file=f) + for k2 in range(1 if debug_mode else 10): create_bram(dsc_f, sim_f, ref_f, tb_f, k1, k2) diff --git a/tests/bram/run-single.sh b/tests/bram/run-single.sh index abaae0e2e..254e85187 100644 --- a/tests/bram/run-single.sh +++ b/tests/bram/run-single.sh @@ -2,7 +2,7 @@ set -e ../../yosys -qq -p "proc; opt; memory -nomap; memory_bram -rules temp/brams_${2}.txt; opt -fast -full" \ -l temp/synth_${1}_${2}.log -o temp/synth_${1}_${2}.v temp/brams_${1}.v -iverilog -o temp/tb_${1}_${2}.tb temp/brams_${1}_tb.v temp/brams_${1}_ref.v \ +iverilog -Dvcd_file=\"temp/tb_${1}_${2}.vcd\" -o temp/tb_${1}_${2}.tb temp/brams_${1}_tb.v temp/brams_${1}_ref.v \ temp/synth_${1}_${2}.v temp/brams_${2}.v ../../techlibs/common/simlib.v temp/tb_${1}_${2}.tb > temp/tb_${1}_${2}.txt if grep -H -C1 ERROR temp/tb_${1}_${2}.txt; then exit 1; fi diff --git a/tests/bram/run-test.sh b/tests/bram/run-test.sh index cc18aff1e..68523740b 100755 --- a/tests/bram/run-test.sh +++ b/tests/bram/run-test.sh @@ -14,14 +14,14 @@ python generate.py echo -n "all:" for i in $( ls temp/brams_*.txt | sed 's,.*_,,; s,\..*,,;' ); do for j in $( ls temp/brams_*.txt | sed 's,.*_,,; s,\..*,,;' | grep -v $i ); do - echo -n " temp/job_$i$j.ok" + echo -n " temp/job_${i}_${j}.ok" done; done echo for i in $( ls temp/brams_*.txt | sed 's,.*_,,; s,\..*,,;' ); do for j in $( ls temp/brams_*.txt | sed 's,.*_,,; s,\..*,,;' | grep -v $i ); do - echo "temp/job_$i$j.ok:" - echo " @bash run-single.sh $i $j" - echo " @echo 'Passed test $i vs $j.'" + echo "temp/job_${i}_${j}.ok:" + echo " @bash run-single.sh ${i} ${j}" + echo " @echo 'Passed test ${i}_${j}.'" echo " @touch \$@" done; done } > temp/makefile -- cgit v1.2.3 From bbf89c4dc68475b57709897ab0728e31963a1ddb Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Fri, 2 Jan 2015 13:59:47 +0100 Subject: Progress in memory_bram --- tests/bram/generate.py | 17 ++++++----------- tests/bram/run-single.sh | 5 ++++- tests/bram/run-test.sh | 2 +- 3 files changed, 11 insertions(+), 13 deletions(-) (limited to 'tests') diff --git a/tests/bram/generate.py b/tests/bram/generate.py index 37b23a526..b03d15296 100644 --- a/tests/bram/generate.py +++ b/tests/bram/generate.py @@ -15,10 +15,6 @@ def create_bram(dsc_f, sim_f, ref_f, tb_f, k1, k2): dbits = random.randrange(1, 8) groups = random.randrange(1, 5) - # XXX - init = 0 - groups = 2 - if random.randrange(2): abits = 2 ** random.randrange(1, 4) if random.randrange(2): @@ -32,12 +28,10 @@ def create_bram(dsc_f, sim_f, ref_f, tb_f, k1, k2): clkpol = [ random.randrange(4) for i in range(groups) ] # XXX - ports = [ 1 for i in range(groups) ] - wrmode = [ 1 for i in range(groups) ] + init = 0 transp = [ 0 for i in range(groups) ] clocks = [ 1 for i in range(groups) ] clkpol = [ 1 for i in range(groups) ] - wrmode[0] = 0 for p1 in range(groups): if wrmode[p1] == 0: @@ -187,7 +181,7 @@ def create_bram(dsc_f, sim_f, ref_f, tb_f, k1, k2): if debug_mode: print(" $dumpfile(`vcd_file);", file=tb_f) - print(" $dumpvars(2, bram_%02d_%02d_tb);" % (k1, k2), file=tb_f) + print(" $dumpvars(0, bram_%02d_%02d_tb);" % (k1, k2), file=tb_f) for p in (tb_clocks + tb_addr + tb_din): if p[-2:] == "EN": @@ -205,13 +199,14 @@ def create_bram(dsc_f, sim_f, ref_f, tb_f, k1, k2): if len(tb_clocks): c = random.choice(tb_clocks) print(" %s = !%s;" % (c, c), file=tb_f) + print(" #100;", file=tb_f) + print(" $display(\"bram_%02d_%02d %3d: %%b %%b %%s\", %s, %s, error ? \"ERROR\" : \"OK\");" % + (k1, k2, i, expr_dout, expr_dout_ref), file=tb_f) for p in tb_din: print(" %s <= %d;" % (p, random.randrange(1048576)), file=tb_f) for p in tb_addr: print(" %s <= %d;" % (p, random.choice(tb_addrlist)), file=tb_f) - print(" #1000;", file=tb_f) - print(" $display(\"bram_%02d_%02d %3d: %%b %%b %%s\", %s, %s, error ? \"ERROR\" : \"OK\");" % - (k1, k2, i, expr_dout, expr_dout_ref), file=tb_f) + print(" #900;", file=tb_f) print(" end", file=tb_f) print("endmodule", file=tb_f) diff --git a/tests/bram/run-single.sh b/tests/bram/run-single.sh index 254e85187..8a022e597 100644 --- a/tests/bram/run-single.sh +++ b/tests/bram/run-single.sh @@ -5,5 +5,8 @@ set -e iverilog -Dvcd_file=\"temp/tb_${1}_${2}.vcd\" -o temp/tb_${1}_${2}.tb temp/brams_${1}_tb.v temp/brams_${1}_ref.v \ temp/synth_${1}_${2}.v temp/brams_${2}.v ../../techlibs/common/simlib.v temp/tb_${1}_${2}.tb > temp/tb_${1}_${2}.txt -if grep -H -C1 ERROR temp/tb_${1}_${2}.txt; then exit 1; fi +if grep -q ERROR temp/tb_${1}_${2}.txt; then + grep -HC2 ERROR temp/tb_${1}_${2}.txt | head + exit 1 +fi exit 0 diff --git a/tests/bram/run-test.sh b/tests/bram/run-test.sh index 68523740b..cdf7d61b6 100755 --- a/tests/bram/run-test.sh +++ b/tests/bram/run-test.sh @@ -21,7 +21,7 @@ python generate.py for j in $( ls temp/brams_*.txt | sed 's,.*_,,; s,\..*,,;' | grep -v $i ); do echo "temp/job_${i}_${j}.ok:" echo " @bash run-single.sh ${i} ${j}" - echo " @echo 'Passed test ${i}_${j}.'" + echo " @echo 'Passed memory_bram test ${i}_${j}.'" echo " @touch \$@" done; done } > temp/makefile -- cgit v1.2.3 From 03b3c025400b2e02afcdbb3337d16d82e361d6aa Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Fri, 2 Jan 2015 17:50:15 +0100 Subject: Progress in bram testbench --- tests/bram/generate.py | 39 ++++++++++++++++++++++++++++----------- 1 file changed, 28 insertions(+), 11 deletions(-) (limited to 'tests') diff --git a/tests/bram/generate.py b/tests/bram/generate.py index b03d15296..b2419d7f4 100644 --- a/tests/bram/generate.py +++ b/tests/bram/generate.py @@ -3,34 +3,35 @@ from __future__ import division from __future__ import print_function +import os import sys import random debug_mode = False +seed = os.getpid() def create_bram(dsc_f, sim_f, ref_f, tb_f, k1, k2): while True: init = random.randrange(2) abits = random.randrange(1, 8) dbits = random.randrange(1, 8) - groups = random.randrange(1, 5) + groups = random.randrange(2, 5) if random.randrange(2): abits = 2 ** random.randrange(1, 4) if random.randrange(2): dbits = 2 ** random.randrange(1, 4) - ports = [ random.randrange(3) for i in range(groups) ] - wrmode = [ random.randrange(2) for i in range(groups) ] - enable = [ random.randrange(4) for i in range(groups) ] - transp = [ random.randrange(4) for i in range(groups) ] - clocks = [ random.randrange(4) for i in range(groups) ] - clkpol = [ random.randrange(4) for i in range(groups) ] + ports = [ random.randrange(1, 3) for i in range(groups) ] + wrmode = [ random.randrange(0, 2) for i in range(groups) ] + enable = [ random.randrange(0, 4) for i in range(groups) ] + transp = [ random.randrange(0, 4) for i in range(groups) ] + clocks = [ random.randrange(1, 4) for i in range(groups) ] + clkpol = [ random.randrange(0, 4) for i in range(groups) ] # XXX init = 0 transp = [ 0 for i in range(groups) ] - clocks = [ 1 for i in range(groups) ] clkpol = [ 1 for i in range(groups) ] for p1 in range(groups): @@ -42,8 +43,9 @@ def create_bram(dsc_f, sim_f, ref_f, tb_f, k1, k2): enable[p1] //= 2 config_ok = True - if wrmode.count(1) <= ports.count(0): config_ok = False - if wrmode.count(0) <= ports.count(0): config_ok = False + if sum(ports) > 3: config_ok = False # XXX + if wrmode.count(1) == 0: config_ok = False + if wrmode.count(0) == 0: config_ok = False if config_ok: break print("bram bram_%02d_%02d" % (k1, k2), file=dsc_f) @@ -82,9 +84,12 @@ def create_bram(dsc_f, sim_f, ref_f, tb_f, k1, k2): v_stmts.append("(* nomem2reg *) reg [%d:0] memory [0:%d];" % (dbits-1, 2**abits-1)) + portindex = 0 + for p1 in range(groups): for p2 in range(ports[p1]): pf = "%c%d" % (chr(ord("A") + p1), p2 + 1) + portindex += 1 if clocks[p1] and not ("CLK%d" % clocks[p1]) in v_ports: v_ports.add("CLK%d" % clocks[p1]) @@ -133,6 +138,8 @@ def create_bram(dsc_f, sim_f, ref_f, tb_f, k1, k2): if not always_hdr in v_always: v_always[always_hdr] = [list(), list(), list()] + v_always[always_hdr][1].append("`delay(%d)" % portindex); + v_always[always_hdr][2].append("`delay(%d)" % (sum(ports)-portindex+1)); if wrmode[p1]: for i in range(enable[p1]): @@ -195,7 +202,7 @@ def create_bram(dsc_f, sim_f, ref_f, tb_f, k1, k2): print(" %s = %d;" % (p, v), file=tb_f) print(" #1000;", file=tb_f) - for i in range(100): + for i in range(20 if debug_mode else 100): if len(tb_clocks): c = random.choice(tb_clocks) print(" %s = !%s;" % (c, c), file=tb_f) @@ -211,6 +218,9 @@ def create_bram(dsc_f, sim_f, ref_f, tb_f, k1, k2): print(" end", file=tb_f) print("endmodule", file=tb_f) +print("Rng seed: %d" % seed) +random.seed(seed) + for k1 in range(5): dsc_f = file("temp/brams_%02d.txt" % k1, "w"); sim_f = file("temp/brams_%02d.v" % k1, "w"); @@ -220,6 +230,13 @@ for k1 in range(5): for f in [sim_f, ref_f, tb_f]: print("`timescale 1 ns / 1 ns", file=f) + for f in [sim_f, ref_f]: + print("`ifdef SYNTHESIS", file=f) + print(" `define delay(n)", file=f) + print("`else", file=f) + print(" `define delay(n) #n;", file=f) + print("`endif", file=f) + for k2 in range(1 if debug_mode else 10): create_bram(dsc_f, sim_f, ref_f, tb_f, k1, k2) -- cgit v1.2.3 From 1dca7ae486edd47f786b07dba6a672b45ed9a4a5 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Fri, 2 Jan 2015 18:54:22 +0100 Subject: Fixes and improvements in bram test --- tests/bram/generate.py | 28 ++++++++-------------------- 1 file changed, 8 insertions(+), 20 deletions(-) (limited to 'tests') diff --git a/tests/bram/generate.py b/tests/bram/generate.py index b2419d7f4..514dfb9fb 100644 --- a/tests/bram/generate.py +++ b/tests/bram/generate.py @@ -8,7 +8,7 @@ import sys import random debug_mode = False -seed = os.getpid() +seed = (int(os.times()[4]*100) + os.getpid()) % 900000 + 100000 def create_bram(dsc_f, sim_f, ref_f, tb_f, k1, k2): while True: @@ -43,7 +43,6 @@ def create_bram(dsc_f, sim_f, ref_f, tb_f, k1, k2): enable[p1] //= 2 config_ok = True - if sum(ports) > 3: config_ok = False # XXX if wrmode.count(1) == 0: config_ok = False if wrmode.count(0) == 0: config_ok = False if config_ok: break @@ -66,7 +65,6 @@ def create_bram(dsc_f, sim_f, ref_f, tb_f, k1, k2): states = set() v_ports = set() v_stmts = list() - v_always = dict() tb_decls = list() tb_clocks = list() @@ -136,27 +134,17 @@ def create_bram(dsc_f, sim_f, ref_f, tb_f, k1, k2): states.add(("CPW", clocks[p1], clkpol[p1])) always_hdr = "always @(posedge CLK%d_CLKPOL%d) begin" % (clocks[p1], clkpol[p1]) - if not always_hdr in v_always: - v_always[always_hdr] = [list(), list(), list()] - v_always[always_hdr][1].append("`delay(%d)" % portindex); - v_always[always_hdr][2].append("`delay(%d)" % (sum(ports)-portindex+1)); - + v_stmts.append(always_hdr) if wrmode[p1]: + v_stmts.append(" `delay(%d)" % portindex); for i in range(enable[p1]): enrange = "[%d:%d]" % ((i+1)*dbits/enable[p1]-1, i*dbits/enable[p1]) - v_always[always_hdr][1].append("if (%sEN[%d]) memory[%sADDR]%s = %sDATA%s;" % (pf, i, pf, enrange, pf, enrange)) + v_stmts.append(" if (%sEN[%d]) memory[%sADDR]%s = %sDATA%s;" % (pf, i, pf, enrange, pf, enrange)) else: - v_always[always_hdr][2 if transp[p1] else 0].append("%sDATA %s memory[%sADDR];" % (pf, assign_op, pf)) - - for a in v_always: - v_stmts.append(a) - for l in v_always[a][0]: - v_stmts.append(" " + l) - for l in v_always[a][1]: - v_stmts.append(" " + l) - for l in v_always[a][2]: - v_stmts.append(" " + l) - v_stmts.append("end") + if transp[p1]: + v_stmts.append(" `delay(%d)" % (sum(ports)+1)) + v_stmts.append(" %sDATA %s memory[%sADDR];" % (pf, assign_op, pf)) + v_stmts.append("end") print("module bram_%02d_%02d(%s);" % (k1, k2, ", ".join(v_ports)), file=sim_f) for stmt in v_stmts: -- cgit v1.2.3 From 90f4017703a275c1a32cb347e4b60bd43873bbce Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Fri, 2 Jan 2015 22:45:26 +0100 Subject: Added proper clkpol support to memory_bram --- tests/bram/generate.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'tests') diff --git a/tests/bram/generate.py b/tests/bram/generate.py index 514dfb9fb..0e803218a 100644 --- a/tests/bram/generate.py +++ b/tests/bram/generate.py @@ -32,7 +32,7 @@ def create_bram(dsc_f, sim_f, ref_f, tb_f, k1, k2): # XXX init = 0 transp = [ 0 for i in range(groups) ] - clkpol = [ 1 for i in range(groups) ] + clkpol = [ random.randrange(0, 2) for i in range(groups) ] for p1 in range(groups): if wrmode[p1] == 0: -- cgit v1.2.3 From a7e43ae3d97ef14c8d624d8fdfe938ae9f47ce84 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sat, 3 Jan 2015 10:57:01 +0100 Subject: Progress in memory_bram --- tests/bram/generate.py | 25 ++++++++++++++----------- tests/bram/run-single.sh | 4 ++-- tests/bram/run-test.sh | 2 +- 3 files changed, 17 insertions(+), 14 deletions(-) (limited to 'tests') diff --git a/tests/bram/generate.py b/tests/bram/generate.py index 0e803218a..840bfbd98 100644 --- a/tests/bram/generate.py +++ b/tests/bram/generate.py @@ -32,7 +32,6 @@ def create_bram(dsc_f, sim_f, ref_f, tb_f, k1, k2): # XXX init = 0 transp = [ 0 for i in range(groups) ] - clkpol = [ random.randrange(0, 2) for i in range(groups) ] for p1 in range(groups): if wrmode[p1] == 0: @@ -134,15 +133,25 @@ def create_bram(dsc_f, sim_f, ref_f, tb_f, k1, k2): states.add(("CPW", clocks[p1], clkpol[p1])) always_hdr = "always @(posedge CLK%d_CLKPOL%d) begin" % (clocks[p1], clkpol[p1]) + v_stmts.append("`ifndef SYNTHESIS") + v_stmts.append("event UPDATE_%s;" % pf) + v_stmts.append("`endif") + v_stmts.append(always_hdr) if wrmode[p1]: - v_stmts.append(" `delay(%d)" % portindex); + v_stmts.append(" `ifndef SYNTHESIS"); + v_stmts.append(" #%d;" % portindex); + v_stmts.append(" -> UPDATE_%s;" % pf) + v_stmts.append(" `endif") for i in range(enable[p1]): enrange = "[%d:%d]" % ((i+1)*dbits/enable[p1]-1, i*dbits/enable[p1]) v_stmts.append(" if (%sEN[%d]) memory[%sADDR]%s = %sDATA%s;" % (pf, i, pf, enrange, pf, enrange)) else: + v_stmts.append(" `ifndef SYNTHESIS"); if transp[p1]: - v_stmts.append(" `delay(%d)" % (sum(ports)+1)) + v_stmts.append(" #%d;" % sum(ports)); + v_stmts.append(" -> UPDATE_%s;" % pf) + v_stmts.append(" `endif") v_stmts.append(" %sDATA %s memory[%sADDR];" % (pf, assign_op, pf)) v_stmts.append("end") @@ -177,13 +186,14 @@ def create_bram(dsc_f, sim_f, ref_f, tb_f, k1, k2): if debug_mode: print(" $dumpfile(`vcd_file);", file=tb_f) print(" $dumpvars(0, bram_%02d_%02d_tb);" % (k1, k2), file=tb_f) + print(" #%d;" % (1000 + k2), file=tb_f) for p in (tb_clocks + tb_addr + tb_din): if p[-2:] == "EN": print(" %s <= ~0;" % p, file=tb_f) else: print(" %s <= 0;" % p, file=tb_f) - print(" #%d;" % (1000 + k2), file=tb_f) + print(" #1000;", file=tb_f) for v in [1, 0, 1, 0]: for p in tb_clocks: @@ -218,13 +228,6 @@ for k1 in range(5): for f in [sim_f, ref_f, tb_f]: print("`timescale 1 ns / 1 ns", file=f) - for f in [sim_f, ref_f]: - print("`ifdef SYNTHESIS", file=f) - print(" `define delay(n)", file=f) - print("`else", file=f) - print(" `define delay(n) #n;", file=f) - print("`endif", file=f) - for k2 in range(1 if debug_mode else 10): create_bram(dsc_f, sim_f, ref_f, tb_f, k1, k2) diff --git a/tests/bram/run-single.sh b/tests/bram/run-single.sh index 8a022e597..cb8295d1b 100644 --- a/tests/bram/run-single.sh +++ b/tests/bram/run-single.sh @@ -2,8 +2,8 @@ set -e ../../yosys -qq -p "proc; opt; memory -nomap; memory_bram -rules temp/brams_${2}.txt; opt -fast -full" \ -l temp/synth_${1}_${2}.log -o temp/synth_${1}_${2}.v temp/brams_${1}.v -iverilog -Dvcd_file=\"temp/tb_${1}_${2}.vcd\" -o temp/tb_${1}_${2}.tb temp/brams_${1}_tb.v temp/brams_${1}_ref.v \ - temp/synth_${1}_${2}.v temp/brams_${2}.v ../../techlibs/common/simlib.v +iverilog -Dvcd_file=\"temp/tb_${1}_${2}.vcd\" -DSIMLIB_MEMDELAY=1ns -o temp/tb_${1}_${2}.tb temp/brams_${1}_tb.v \ + temp/brams_${1}_ref.v temp/synth_${1}_${2}.v temp/brams_${2}.v ../../techlibs/common/simlib.v temp/tb_${1}_${2}.tb > temp/tb_${1}_${2}.txt if grep -q ERROR temp/tb_${1}_${2}.txt; then grep -HC2 ERROR temp/tb_${1}_${2}.txt | head diff --git a/tests/bram/run-test.sh b/tests/bram/run-test.sh index cdf7d61b6..d617187ec 100755 --- a/tests/bram/run-test.sh +++ b/tests/bram/run-test.sh @@ -1,7 +1,7 @@ #!/bin/bash # run this test many times: -# time bash -c 'for ((i=0; i<100; i++)); do echo "-- $i --"; bash run-test.sh || exit 1; done' +# MAKE="make -j8" time bash -c 'for ((i=0; i<100; i++)); do echo "-- $i --"; bash run-test.sh || exit 1; done' set -e rm -rf temp -- cgit v1.2.3 From fd2c224c04b0fff83d2255c86533686fe2dc8883 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sat, 3 Jan 2015 12:41:46 +0100 Subject: memory_bram transp support --- tests/bram/generate.py | 108 ++++++++++++++++++++++++++++++------------------- 1 file changed, 66 insertions(+), 42 deletions(-) (limited to 'tests') diff --git a/tests/bram/generate.py b/tests/bram/generate.py index 840bfbd98..7b5816fca 100644 --- a/tests/bram/generate.py +++ b/tests/bram/generate.py @@ -12,7 +12,7 @@ seed = (int(os.times()[4]*100) + os.getpid()) % 900000 + 100000 def create_bram(dsc_f, sim_f, ref_f, tb_f, k1, k2): while True: - init = random.randrange(2) + init = 0 # random.randrange(2) abits = random.randrange(1, 8) dbits = random.randrange(1, 8) groups = random.randrange(2, 5) @@ -22,29 +22,38 @@ def create_bram(dsc_f, sim_f, ref_f, tb_f, k1, k2): if random.randrange(2): dbits = 2 ** random.randrange(1, 4) - ports = [ random.randrange(1, 3) for i in range(groups) ] - wrmode = [ random.randrange(0, 2) for i in range(groups) ] - enable = [ random.randrange(0, 4) for i in range(groups) ] - transp = [ random.randrange(0, 4) for i in range(groups) ] - clocks = [ random.randrange(1, 4) for i in range(groups) ] - clkpol = [ random.randrange(0, 4) for i in range(groups) ] + while True: + wrmode = [ random.randrange(0, 2) for i in range(groups) ] + if wrmode.count(1) == 0: continue + if wrmode.count(0) == 0: continue + break - # XXX - init = 0 - transp = [ 0 for i in range(groups) ] - - for p1 in range(groups): - if wrmode[p1] == 0: - enable[p1] = 0 - else: - enable[p1] = 2**enable[p1] - while dbits < enable[p1] or dbits % enable[p1] != 0: - enable[p1] //= 2 - - config_ok = True - if wrmode.count(1) == 0: config_ok = False - if wrmode.count(0) == 0: config_ok = False - if config_ok: break + if random.randrange(2) or True: + maxpol = 4 + maxtransp = 1 + else: + maxpol = 2 + maxtransp = 2 + + def generate_enable(i): + if wrmode[i]: + v = 2 ** random.randrange(0, 4) + while dbits < v or dbits % v != 0: + v //= 2 + return v + return 0 + + def generate_transp(i): + if wrmode[i] == 0: + return random.randrange(maxtransp) + return 0 + + ports = [ random.randrange(1, 3) for i in range(groups) ] + enable = [ generate_enable(i) for i in range(groups) ] + transp = [ generate_transp(i) for i in range(groups) ] + clocks = [ random.randrange(1, 4) for i in range(groups) ] + clkpol = [ random.randrange(maxpol) for i in range(groups) ] + break print("bram bram_%02d_%02d" % (k1, k2), file=dsc_f) print(" init %d" % init, file=dsc_f) @@ -64,6 +73,7 @@ def create_bram(dsc_f, sim_f, ref_f, tb_f, k1, k2): states = set() v_ports = set() v_stmts = list() + v_always = dict() tb_decls = list() tb_clocks = list() @@ -82,12 +92,17 @@ def create_bram(dsc_f, sim_f, ref_f, tb_f, k1, k2): v_stmts.append("(* nomem2reg *) reg [%d:0] memory [0:%d];" % (dbits-1, 2**abits-1)) portindex = 0 + last_always_hdr = (-1, "") for p1 in range(groups): for p2 in range(ports[p1]): pf = "%c%d" % (chr(ord("A") + p1), p2 + 1) portindex += 1 + v_stmts.append("`ifndef SYNTHESIS") + v_stmts.append(" event UPDATE_%s;" % pf) + v_stmts.append("`endif") + if clocks[p1] and not ("CLK%d" % clocks[p1]) in v_ports: v_ports.add("CLK%d" % clocks[p1]) v_stmts.append("input CLK%d;" % clocks[p1]) @@ -133,27 +148,36 @@ def create_bram(dsc_f, sim_f, ref_f, tb_f, k1, k2): states.add(("CPW", clocks[p1], clkpol[p1])) always_hdr = "always @(posedge CLK%d_CLKPOL%d) begin" % (clocks[p1], clkpol[p1]) - v_stmts.append("`ifndef SYNTHESIS") - v_stmts.append("event UPDATE_%s;" % pf) - v_stmts.append("`endif") + if last_always_hdr[1] != always_hdr: + last_always_hdr = (portindex, always_hdr) + v_always[last_always_hdr] = list() - v_stmts.append(always_hdr) if wrmode[p1]: - v_stmts.append(" `ifndef SYNTHESIS"); - v_stmts.append(" #%d;" % portindex); - v_stmts.append(" -> UPDATE_%s;" % pf) - v_stmts.append(" `endif") for i in range(enable[p1]): enrange = "[%d:%d]" % ((i+1)*dbits/enable[p1]-1, i*dbits/enable[p1]) - v_stmts.append(" if (%sEN[%d]) memory[%sADDR]%s = %sDATA%s;" % (pf, i, pf, enrange, pf, enrange)) + v_always[last_always_hdr].append((portindex, pf, "if (%sEN[%d]) memory[%sADDR]%s = %sDATA%s;" % (pf, i, pf, enrange, pf, enrange))) else: - v_stmts.append(" `ifndef SYNTHESIS"); - if transp[p1]: - v_stmts.append(" #%d;" % sum(ports)); - v_stmts.append(" -> UPDATE_%s;" % pf) + v_always[last_always_hdr].append((sum(ports)+1 if transp[p1] else 0, pf, "%sDATA %s memory[%sADDR];" % (pf, assign_op, pf))) + + for always_hdr in sorted(v_always): + v_stmts.append(always_hdr[1]) + triggered_events = set() + time_cursor = 0 + v_always[always_hdr].sort() + for t, p, s in v_always[always_hdr]: + if time_cursor != t or not p in triggered_events: + v_stmts.append(" `ifndef SYNTHESIS") + stmt = "" + if time_cursor != t: + stmt += " #%d;" % (t-time_cursor) + time_cursor = t + if not p in triggered_events: + stmt += (" -> UPDATE_%s;" % p) + triggered_events.add(p) + v_stmts.append(" %s" % stmt) v_stmts.append(" `endif") - v_stmts.append(" %sDATA %s memory[%sADDR];" % (pf, assign_op, pf)) - v_stmts.append("end") + v_stmts.append(" %s" % s) + v_stmts.append("end") print("module bram_%02d_%02d(%s);" % (k1, k2, ", ".join(v_ports)), file=sim_f) for stmt in v_stmts: @@ -220,10 +244,10 @@ print("Rng seed: %d" % seed) random.seed(seed) for k1 in range(5): - dsc_f = file("temp/brams_%02d.txt" % k1, "w"); - sim_f = file("temp/brams_%02d.v" % k1, "w"); - ref_f = file("temp/brams_%02d_ref.v" % k1, "w"); - tb_f = file("temp/brams_%02d_tb.v" % k1, "w"); + dsc_f = file("temp/brams_%02d.txt" % k1, "w") + sim_f = file("temp/brams_%02d.v" % k1, "w") + ref_f = file("temp/brams_%02d_ref.v" % k1, "w") + tb_f = file("temp/brams_%02d_tb.v" % k1, "w") for f in [sim_f, ref_f, tb_f]: print("`timescale 1 ns / 1 ns", file=f) -- cgit v1.2.3 From a7fe87f8886900b3e9056caf392978e06c5a74ae Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sat, 3 Jan 2015 17:34:05 +0100 Subject: Added memory_bram 'or_next_if_better' feature --- tests/bram/generate.py | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) (limited to 'tests') diff --git a/tests/bram/generate.py b/tests/bram/generate.py index 7b5816fca..03f2555dc 100644 --- a/tests/bram/generate.py +++ b/tests/bram/generate.py @@ -10,7 +10,7 @@ import random debug_mode = False seed = (int(os.times()[4]*100) + os.getpid()) % 900000 + 100000 -def create_bram(dsc_f, sim_f, ref_f, tb_f, k1, k2): +def create_bram(dsc_f, sim_f, ref_f, tb_f, k1, k2, or_next): while True: init = 0 # random.randrange(2) abits = random.randrange(1, 8) @@ -68,6 +68,8 @@ def create_bram(dsc_f, sim_f, ref_f, tb_f, k1, k2): print(" clkpol %s" % " ".join(["%d" % i for i in clkpol]), file=dsc_f) print("endbram", file=dsc_f) print("match bram_%02d_%02d" % (k1, k2), file=dsc_f) + if or_next: + print(" or_next_if_better", file=dsc_f) print("endmatch", file=dsc_f) states = set() @@ -252,6 +254,7 @@ for k1 in range(5): for f in [sim_f, ref_f, tb_f]: print("`timescale 1 ns / 1 ns", file=f) - for k2 in range(1 if debug_mode else 10): - create_bram(dsc_f, sim_f, ref_f, tb_f, k1, k2) + lenk2 = 1 if debug_mode else 10 + for k2 in range(lenk2): + create_bram(dsc_f, sim_f, ref_f, tb_f, k1, k2, random.randrange(2 if k2+1 < lenk2 else 1)) -- cgit v1.2.3 From 45918b8315423cb91400a0127550a1d54220c447 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sat, 3 Jan 2015 17:40:20 +0100 Subject: Added "memory -bram" --- tests/bram/run-single.sh | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'tests') diff --git a/tests/bram/run-single.sh b/tests/bram/run-single.sh index cb8295d1b..19a235c7a 100644 --- a/tests/bram/run-single.sh +++ b/tests/bram/run-single.sh @@ -1,6 +1,6 @@ #!/bin/bash set -e -../../yosys -qq -p "proc; opt; memory -nomap; memory_bram -rules temp/brams_${2}.txt; opt -fast -full" \ +../../yosys -qq -p "proc; opt; memory -nomap -bram temp/brams_${2}.txt; opt -fast -full" \ -l temp/synth_${1}_${2}.log -o temp/synth_${1}_${2}.v temp/brams_${1}.v iverilog -Dvcd_file=\"temp/tb_${1}_${2}.vcd\" -DSIMLIB_MEMDELAY=1ns -o temp/tb_${1}_${2}.tb temp/brams_${1}_tb.v \ temp/brams_${1}_ref.v temp/synth_${1}_${2}.v temp/brams_${2}.v ../../techlibs/common/simlib.v -- cgit v1.2.3 From daae35319be6c8f8905f25826a8f5960cdfeda20 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sun, 4 Jan 2015 13:14:30 +0100 Subject: Added memory_bram "shuffle_enable" feature --- tests/bram/generate.py | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'tests') diff --git a/tests/bram/generate.py b/tests/bram/generate.py index 03f2555dc..4bf3a9541 100644 --- a/tests/bram/generate.py +++ b/tests/bram/generate.py @@ -68,6 +68,10 @@ def create_bram(dsc_f, sim_f, ref_f, tb_f, k1, k2, or_next): print(" clkpol %s" % " ".join(["%d" % i for i in clkpol]), file=dsc_f) print("endbram", file=dsc_f) print("match bram_%02d_%02d" % (k1, k2), file=dsc_f) + if random.randrange(2): + non_zero_enables = [i for i in enable if i] + if len(non_zero_enables): + print(" shuffle_enable %d" % random.choice(non_zero_enables), file=dsc_f) if or_next: print(" or_next_if_better", file=dsc_f) print("endmatch", file=dsc_f) -- cgit v1.2.3 From dfa42e272cd13a08314299817423052488eb58ab Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Tue, 13 Jan 2015 12:59:29 +0100 Subject: Tiny fix in vcdcd.pl --- tests/tools/vcdcd.pl | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'tests') diff --git a/tests/tools/vcdcd.pl b/tests/tools/vcdcd.pl index 2abfb7a21..6f497e99c 100755 --- a/tests/tools/vcdcd.pl +++ b/tests/tools/vcdcd.pl @@ -80,8 +80,8 @@ for my $net (sort keys %gold_signals_hash) { for my $fullname (keys $gate_signals_hash{$net}) { $orig_net_names{$fullname} = 1; } - for my $_ (sort keys %orig_net_names) { - push @signals, $_; + for my $net (sort keys %orig_net_names) { + push @signals, $net; print " $1" if /(\[([0-9]+|[0-9]+:[0-9]+)\])$/; } print "\n"; -- cgit v1.2.3 From f630868bc992d0c26b38a7e48933545b461249f1 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sun, 18 Jan 2015 12:57:36 +0100 Subject: Improvements in opt_muxtree --- tests/simple/muxtree.v | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'tests') diff --git a/tests/simple/muxtree.v b/tests/simple/muxtree.v index c5060eae9..46c78d4cf 100644 --- a/tests/simple/muxtree.v +++ b/tests/simple/muxtree.v @@ -70,3 +70,11 @@ end endmodule + +// test case for muxtree with select on leaves + +module select_leaves(input C, D, output reg Q); + always @(posedge C) + Q <= Q ? Q : D ? 1'b1 : Q; +endmodule + -- cgit v1.2.3 From 694cc01f1de8e0d7db7c5e03cb93796430c6ca5b Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sun, 18 Jan 2015 13:24:01 +0100 Subject: improvements in muxtree/select_leaves test --- tests/simple/muxtree.v | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) (limited to 'tests') diff --git a/tests/simple/muxtree.v b/tests/simple/muxtree.v index 46c78d4cf..1fb1cea5e 100644 --- a/tests/simple/muxtree.v +++ b/tests/simple/muxtree.v @@ -73,8 +73,11 @@ endmodule // test case for muxtree with select on leaves -module select_leaves(input C, D, output reg Q); +module select_leaves(input R, C, D, output reg Q); always @(posedge C) - Q <= Q ? Q : D ? 1'b1 : Q; + if (!R) + Q <= R; + else + Q <= Q ? Q : D ? D : Q; endmodule -- cgit v1.2.3 From 8d295730e568421d3dc5b0779bd90d826e874254 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sun, 18 Jan 2015 19:05:29 +0100 Subject: Refactoring of memory_bram and xilinx brams --- tests/bram/generate.py | 4 ++-- tests/tools/cmp_tbdata.c | 2 ++ 2 files changed, 4 insertions(+), 2 deletions(-) (limited to 'tests') diff --git a/tests/bram/generate.py b/tests/bram/generate.py index 4bf3a9541..2adfdcfb0 100644 --- a/tests/bram/generate.py +++ b/tests/bram/generate.py @@ -69,9 +69,9 @@ def create_bram(dsc_f, sim_f, ref_f, tb_f, k1, k2, or_next): print("endbram", file=dsc_f) print("match bram_%02d_%02d" % (k1, k2), file=dsc_f) if random.randrange(2): - non_zero_enables = [i for i in enable if i] + non_zero_enables = [chr(ord('A') + i) for i in range(len(enable)) if enable[i]] if len(non_zero_enables): - print(" shuffle_enable %d" % random.choice(non_zero_enables), file=dsc_f) + print(" shuffle_enable %c" % random.choice(non_zero_enables), file=dsc_f) if or_next: print(" or_next_if_better", file=dsc_f) print("endmatch", file=dsc_f) diff --git a/tests/tools/cmp_tbdata.c b/tests/tools/cmp_tbdata.c index 86485efd0..b81ae1cab 100644 --- a/tests/tools/cmp_tbdata.c +++ b/tests/tools/cmp_tbdata.c @@ -53,6 +53,8 @@ int main(int argc, char **argv) // here means we don't care about the result. if (buffer1[i] == 'z' || buffer1[i] == 'x') continue; + if (buffer1[i] == 'Z' || buffer1[i] == 'X') + continue; check(buffer1[i] == buffer2[i]); } -- cgit v1.2.3 From e666611534174621e8089c732186e4aa07f0ce68 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Tue, 27 Jan 2015 19:30:06 +0100 Subject: Bugfix in resource sharing test --- tests/share/run-test.sh | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'tests') diff --git a/tests/share/run-test.sh b/tests/share/run-test.sh index 203d6fcd7..6e880677c 100755 --- a/tests/share/run-test.sh +++ b/tests/share/run-test.sh @@ -18,7 +18,7 @@ for i in $( ls temp/*.ys | sed 's,[^0-9],,g; s,^0*\(.\),\1,g;' ); do done echo -failed_share=$( echo $( gawk '/^#job#/ { j=$2; db[j]=0; } /^Removing [24] cells/ { delete db[j]; } END { for (j in db) print(j); }' temp/all_share_log.txt ) ) +failed_share=$( echo $( gawk '/^#job#/ { j=$2; db[j]=0; } /^Removing [246] cells/ { delete db[j]; } END { for (j in db) print(j); }' temp/all_share_log.txt ) ) if [ -n "$failed_share" ]; then echo "Resource sharing failed for the following test cases: $failed_share" false -- cgit v1.2.3 From d58c3eca3a6d4ab00021769fb31ee0279c2fcbab Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Thu, 12 Feb 2015 17:45:44 +0100 Subject: Some test related fixes (incl. removal of three bad test cases) --- tests/asicworld/code_hdl_models_dlatch_reset.v | 30 ------------- tests/asicworld/code_hdl_models_ram_sp_ar_sw.v | 58 ------------------------ tests/asicworld/code_hdl_models_ram_sp_sr_sw.v | 62 -------------------------- tests/tools/autotest.sh | 2 +- 4 files changed, 1 insertion(+), 151 deletions(-) delete mode 100644 tests/asicworld/code_hdl_models_dlatch_reset.v delete mode 100644 tests/asicworld/code_hdl_models_ram_sp_ar_sw.v delete mode 100644 tests/asicworld/code_hdl_models_ram_sp_sr_sw.v (limited to 'tests') diff --git a/tests/asicworld/code_hdl_models_dlatch_reset.v b/tests/asicworld/code_hdl_models_dlatch_reset.v deleted file mode 100644 index 2cfc6fbd8..000000000 --- a/tests/asicworld/code_hdl_models_dlatch_reset.v +++ /dev/null @@ -1,30 +0,0 @@ -//----------------------------------------------------- -// Design Name : dlatch_reset -// File Name : dlatch_reset.v -// Function : DLATCH async reset -// Coder : Deepak Kumar Tala -//----------------------------------------------------- -module dlatch_reset ( -data , // Data Input -en , // LatchInput -reset , // Reset input -q // Q output -); -//-----------Input Ports--------------- -input data, en, reset ; - -//-----------Output Ports--------------- -output q; - -//------------Internal Variables-------- -reg q; - -//-------------Code Starts Here--------- -always @ ( en or reset or data) -if (~reset) begin - q <= 1'b0; -end else if (en) begin - q <= data; -end - -endmodule //End Of Module dlatch_reset diff --git a/tests/asicworld/code_hdl_models_ram_sp_ar_sw.v b/tests/asicworld/code_hdl_models_ram_sp_ar_sw.v deleted file mode 100644 index d3338f749..000000000 --- a/tests/asicworld/code_hdl_models_ram_sp_ar_sw.v +++ /dev/null @@ -1,58 +0,0 @@ -//----------------------------------------------------- -// Design Name : ram_sp_ar_sw -// File Name : ram_sp_ar_sw.v -// Function : Asynchronous read write RAM -// Coder : Deepak Kumar Tala -//----------------------------------------------------- -module ram_sp_ar_sw ( -clk , // Clock Input -address , // Address Input -data , // Data bi-directional -cs , // Chip Select -we , // Write Enable/Read Enable -oe // Output Enable -); - -parameter DATA_WIDTH = 8 ; -parameter ADDR_WIDTH = 8 ; -parameter RAM_DEPTH = 1 << ADDR_WIDTH; - -//--------------Input Ports----------------------- -input clk ; -input [ADDR_WIDTH-1:0] address ; -input cs ; -input we ; -input oe ; - -//--------------Inout Ports----------------------- -inout [DATA_WIDTH-1:0] data ; - -//--------------Internal variables---------------- -reg [DATA_WIDTH-1:0] data_out ; -reg [DATA_WIDTH-1:0] mem [0:RAM_DEPTH-1]; - -//--------------Code Starts Here------------------ - -// Tri-State Buffer control -// output : When we = 0, oe = 1, cs = 1 -assign data = (cs && oe && !we) ? data_out : 8'bz; - -// Memory Write Block -// Write Operation : When we = 1, cs = 1 -always @ (posedge clk) -begin : MEM_WRITE - if ( cs && we ) begin - mem[address] = data; - end -end - -// Memory Read Block -// Read Operation : When we = 0, oe = 1, cs = 1 -always @ (address or cs or we or oe) -begin : MEM_READ - if (cs && !we && oe) begin - data_out = mem[address]; - end -end - -endmodule // End of Module ram_sp_ar_sw diff --git a/tests/asicworld/code_hdl_models_ram_sp_sr_sw.v b/tests/asicworld/code_hdl_models_ram_sp_sr_sw.v deleted file mode 100644 index c7fd9554d..000000000 --- a/tests/asicworld/code_hdl_models_ram_sp_sr_sw.v +++ /dev/null @@ -1,62 +0,0 @@ -//----------------------------------------------------- -// Design Name : ram_sp_sr_sw -// File Name : ram_sp_sr_sw.v -// Function : Synchronous read write RAM -// Coder : Deepak Kumar Tala -//----------------------------------------------------- -module ram_sp_sr_sw ( -clk , // Clock Input -address , // Address Input -data , // Data bi-directional -cs , // Chip Select -we , // Write Enable/Read Enable -oe // Output Enable -); - -parameter DATA_WIDTH = 8 ; -parameter ADDR_WIDTH = 8 ; -parameter RAM_DEPTH = 1 << ADDR_WIDTH; - -//--------------Input Ports----------------------- -input clk ; -input [ADDR_WIDTH-1:0] address ; -input cs ; -input we ; -input oe ; - -//--------------Inout Ports----------------------- -inout [DATA_WIDTH-1:0] data ; - -//--------------Internal variables---------------- -reg [DATA_WIDTH-1:0] data_out ; -reg [DATA_WIDTH-1:0] mem [0:RAM_DEPTH-1]; -reg oe_r; - -//--------------Code Starts Here------------------ - -// Tri-State Buffer control -// output : When we = 0, oe = 1, cs = 1 -assign data = (cs && oe && !we) ? data_out : 8'bz; - -// Memory Write Block -// Write Operation : When we = 1, cs = 1 -always @ (posedge clk) -begin : MEM_WRITE - if ( cs && we ) begin - mem[address] = data; - end -end - -// Memory Read Block -// Read Operation : When we = 0, oe = 1, cs = 1 -always @ (posedge clk) -begin : MEM_READ - if (cs && !we && oe) begin - data_out = mem[address]; - oe_r = 1; - end else begin - oe_r = 0; - end -end - -endmodule // End of Module ram_sp_sr_sw diff --git a/tests/tools/autotest.sh b/tests/tools/autotest.sh index 50f5cb580..6fdc27928 100755 --- a/tests/tools/autotest.sh +++ b/tests/tools/autotest.sh @@ -145,7 +145,7 @@ do elif [ "$frontend" = "verific_gates" ]; then test_passes -p "verific -vlog2k $fn; verific -import -gates -all; opt; memory;;" else - test_passes -f "$frontend" -p "hierarchy; proc; opt; memory; opt; fsm; opt -fine" $fn + test_passes -f "$frontend" -p "hierarchy; proc; opt; memory; opt; fsm; opt -full -fine" $fn test_passes -f "$frontend" -p "hierarchy; synth -run coarse; techmap; opt; abc -dff" $fn fi touch ../${bn}.log -- cgit v1.2.3 From 913c304fe62cb962e32fa0eb024fa4fc3110639c Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sat, 14 Feb 2015 11:26:20 +0100 Subject: Added $meminit test case --- tests/simple/memory.v | 30 ++++++++++++++++++++++++++++++ 1 file changed, 30 insertions(+) (limited to 'tests') diff --git a/tests/simple/memory.v b/tests/simple/memory.v index db06c56d2..f7c37309c 100644 --- a/tests/simple/memory.v +++ b/tests/simple/memory.v @@ -205,3 +205,33 @@ module memtest08(input clk, input [3:0] a, b, c, output reg [3:0] y); end endmodule +// ---------------------------------------------------------- + +module memtest09 ( + input clk, + input [1:0] a_addr, a_din, b_addr, b_din, + input a_wen, b_wen, + output reg [1:0] a_dout, b_dout +); + reg [1:0] memory [0:3]; + + initial begin + memory[0] <= 0; + memory[1] <= 1; + memory[2] <= 2; + memory[3] <= 3; + end + + always @(posedge clk) begin + if (a_wen) + memory[a_addr] <= a_din; + a_dout <= memory[a_addr]; + end + + always @(posedge clk) begin + if (b_wen) + memory[b_addr] <= b_din; + b_dout <= memory[b_addr]; + end +endmodule + -- cgit v1.2.3 From dcf2e242406d563254013ea7db4b29b55be96eff Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sat, 14 Feb 2015 12:55:03 +0100 Subject: Added $meminit support to "memory" command --- tests/simple/memory.v | 23 ++++++++--------------- tests/techmap/mem_simple_4x1_map.v | 5 +++++ 2 files changed, 13 insertions(+), 15 deletions(-) (limited to 'tests') diff --git a/tests/simple/memory.v b/tests/simple/memory.v index f7c37309c..23e93ac91 100644 --- a/tests/simple/memory.v +++ b/tests/simple/memory.v @@ -209,29 +209,22 @@ endmodule module memtest09 ( input clk, - input [1:0] a_addr, a_din, b_addr, b_din, + input [3:0] a_addr, a_din, b_addr, b_din, input a_wen, b_wen, - output reg [1:0] a_dout, b_dout + output reg [3:0] a_dout, b_dout ); - reg [1:0] memory [0:3]; - - initial begin - memory[0] <= 0; - memory[1] <= 1; - memory[2] <= 2; - memory[3] <= 3; - end + reg [3:0] memory [0:35]; always @(posedge clk) begin if (a_wen) - memory[a_addr] <= a_din; - a_dout <= memory[a_addr]; + memory[10 + a_addr] <= a_din; + a_dout <= memory[10 + a_addr]; end always @(posedge clk) begin - if (b_wen) - memory[b_addr] <= b_din; - b_dout <= memory[b_addr]; + if (b_wen && (10 + a_addr != 20 + b_addr)) + memory[20 + b_addr] <= b_din; + b_dout <= memory[20 + b_addr]; end endmodule diff --git a/tests/techmap/mem_simple_4x1_map.v b/tests/techmap/mem_simple_4x1_map.v index 820f89de4..868f5d00c 100644 --- a/tests/techmap/mem_simple_4x1_map.v +++ b/tests/techmap/mem_simple_4x1_map.v @@ -5,6 +5,7 @@ module \$mem (RD_CLK, RD_ADDR, RD_DATA, WR_CLK, WR_EN, WR_ADDR, WR_DATA); parameter OFFSET = 0; parameter ABITS = 8; parameter WIDTH = 8; + parameter signed INIT = 1'bx; parameter RD_PORTS = 1; parameter RD_CLK_ENABLE = 1'b1; @@ -37,6 +38,10 @@ module \$mem (RD_CLK, RD_ADDR, RD_DATA, WR_CLK, WR_EN, WR_ADDR, WR_DATA); initial begin _TECHMAP_FAIL_ <= 0; + // no initialized memories + if (INIT !== 1'bx) + _TECHMAP_FAIL_ <= 1; + // only map cells with only one read and one write port if (RD_PORTS > 1 || WR_PORTS > 1) _TECHMAP_FAIL_ <= 1; -- cgit v1.2.3 From e9368a1d7e13bc691f86f25cd80981110b937cab Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sat, 14 Feb 2015 14:21:15 +0100 Subject: Various fixes for memories with offsets --- tests/simple/memory.v | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'tests') diff --git a/tests/simple/memory.v b/tests/simple/memory.v index 23e93ac91..67f89cd75 100644 --- a/tests/simple/memory.v +++ b/tests/simple/memory.v @@ -213,7 +213,7 @@ module memtest09 ( input a_wen, b_wen, output reg [3:0] a_dout, b_dout ); - reg [3:0] memory [0:35]; + reg [3:0] memory [10:35]; always @(posedge clk) begin if (a_wen) @@ -222,7 +222,7 @@ module memtest09 ( end always @(posedge clk) begin - if (b_wen && (10 + a_addr != 20 + b_addr)) + if (b_wen && (10 + a_addr != 20 + b_addr || !a_wen)) memory[20 + b_addr] <= b_din; b_dout <= memory[20 + b_addr]; end -- cgit v1.2.3 From 604c097f9818a5b29fa06223b88930630fafca5e Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Fri, 20 Mar 2015 09:10:02 +0100 Subject: fix for python 2.6.6 --- tests/fsm/generate.py | 146 +++++++++++++++++++++++---------------------- tests/realmath/generate.py | 99 +++++++++++++++--------------- tests/share/generate.py | 92 ++++++++++++++-------------- 3 files changed, 172 insertions(+), 165 deletions(-) (limited to 'tests') diff --git a/tests/fsm/generate.py b/tests/fsm/generate.py index b5b4626df..fc67543f2 100644 --- a/tests/fsm/generate.py +++ b/tests/fsm/generate.py @@ -34,76 +34,78 @@ def random_expr(variables): raise AssertionError for idx in range(50): - with file('temp/uut_%05d.v' % idx, 'w') as f, redirect_stdout(f): - rst2 = random.choice([False, True]) - if rst2: - print('module uut_%05d(clk, rst1, rst2, rst, a, b, c, x, y, z);' % (idx)) - print(' input clk, rst1, rst2;') - print(' output rst;') - print(' assign rst = rst1 || rst2;') - else: - print('module uut_%05d(clk, rst, a, b, c, x, y, z);' % (idx)) - print(' input clk, rst;') - variables=['a', 'b', 'c', 'x', 'y', 'z'] - print(' input%s [%d:0] a;' % (random.choice(['', ' signed']), random.randint(0, 31))) - print(' input%s [%d:0] b;' % (random.choice(['', ' signed']), random.randint(0, 31))) - print(' input%s [%d:0] c;' % (random.choice(['', ' signed']), random.randint(0, 31))) - print(' output reg%s [%d:0] x;' % (random.choice(['', ' signed']), random.randint(0, 31))) - print(' output reg%s [%d:0] y;' % (random.choice(['', ' signed']), random.randint(0, 31))) - print(' output reg%s [%d:0] z;' % (random.choice(['', ' signed']), random.randint(0, 31))) - state_bits = random.randint(5, 16); - print(' %sreg [%d:0] state;' % (random.choice(['', '(* fsm_encoding = "one-hot" *)', - '(* fsm_encoding = "binary" *)']), state_bits-1)) - states=[] - for i in range(random.randint(2, 10)): - n = random.randint(0, 2**state_bits-1) - if n not in states: - states.append(n) - print(' always @(posedge clk) begin') - print(' if (%s) begin' % ('rst1' if rst2 else 'rst')) - print(' x <= %d;' % random.randint(0, 2**31-1)) - print(' y <= %d;' % random.randint(0, 2**31-1)) - print(' z <= %d;' % random.randint(0, 2**31-1)) - print(' state <= %d;' % random.choice(states)) - print(' end else begin') - print(' case (state)') - for state in states: - print(' %d: begin' % state) - for var in ('x', 'y', 'z'): - print(' %s <= %s;' % (var, random_expr(variables))) - next_states = states[:] - for i in range(random.randint(0, len(states))): - next_state = random.choice(next_states) - next_states.remove(next_state) - print(' if ((%s) %s (%s)) state <= %s;' % (random_expr(variables), - random.choice(['<', '<=', '>=', '>']), random_expr(variables), next_state)) - print(' end') - print(' endcase') - if rst2: - print(' if (rst2) begin') - print(' x <= a;') - print(' y <= b;') - print(' z <= c;') - print(' state <= %d;' % random.choice(states)) - print(' end') - print(' end') - print(' end') - print('endmodule') - with file('temp/uut_%05d.ys' % idx, 'w') as f, redirect_stdout(f): - if test_verific: - print('read_verilog temp/uut_%05d.v' % idx) - print('proc;; rename uut_%05d gold' % idx) - print('verific -vlog2k temp/uut_%05d.v' % idx) - print('verific -import uut_%05d' % idx) - print('rename uut_%05d gate' % idx) - else: - print('read_verilog temp/uut_%05d.v' % idx) - print('proc;;') - print('copy uut_%05d gold' % idx) - print('rename uut_%05d gate' % idx) - print('cd gate') - print('opt; wreduce; share%s; opt; fsm;;' % random.choice(['', ' -aggressive'])) - print('cd ..') - print('miter -equiv -flatten -ignore_gold_x -make_outputs -make_outcmp gold gate miter') - print('sat -verify-no-timeout -timeout 20 -seq 5 -set-at 1 %s_rst 1 -prove trigger 0 -prove-skip 1 -show-inputs -show-outputs miter' % ('gold' if rst2 else 'in')) + with file('temp/uut_%05d.v' % idx, 'w') as f: + with redirect_stdout(f): + rst2 = random.choice([False, True]) + if rst2: + print('module uut_%05d(clk, rst1, rst2, rst, a, b, c, x, y, z);' % (idx)) + print(' input clk, rst1, rst2;') + print(' output rst;') + print(' assign rst = rst1 || rst2;') + else: + print('module uut_%05d(clk, rst, a, b, c, x, y, z);' % (idx)) + print(' input clk, rst;') + variables=['a', 'b', 'c', 'x', 'y', 'z'] + print(' input%s [%d:0] a;' % (random.choice(['', ' signed']), random.randint(0, 31))) + print(' input%s [%d:0] b;' % (random.choice(['', ' signed']), random.randint(0, 31))) + print(' input%s [%d:0] c;' % (random.choice(['', ' signed']), random.randint(0, 31))) + print(' output reg%s [%d:0] x;' % (random.choice(['', ' signed']), random.randint(0, 31))) + print(' output reg%s [%d:0] y;' % (random.choice(['', ' signed']), random.randint(0, 31))) + print(' output reg%s [%d:0] z;' % (random.choice(['', ' signed']), random.randint(0, 31))) + state_bits = random.randint(5, 16); + print(' %sreg [%d:0] state;' % (random.choice(['', '(* fsm_encoding = "one-hot" *)', + '(* fsm_encoding = "binary" *)']), state_bits-1)) + states=[] + for i in range(random.randint(2, 10)): + n = random.randint(0, 2**state_bits-1) + if n not in states: + states.append(n) + print(' always @(posedge clk) begin') + print(' if (%s) begin' % ('rst1' if rst2 else 'rst')) + print(' x <= %d;' % random.randint(0, 2**31-1)) + print(' y <= %d;' % random.randint(0, 2**31-1)) + print(' z <= %d;' % random.randint(0, 2**31-1)) + print(' state <= %d;' % random.choice(states)) + print(' end else begin') + print(' case (state)') + for state in states: + print(' %d: begin' % state) + for var in ('x', 'y', 'z'): + print(' %s <= %s;' % (var, random_expr(variables))) + next_states = states[:] + for i in range(random.randint(0, len(states))): + next_state = random.choice(next_states) + next_states.remove(next_state) + print(' if ((%s) %s (%s)) state <= %s;' % (random_expr(variables), + random.choice(['<', '<=', '>=', '>']), random_expr(variables), next_state)) + print(' end') + print(' endcase') + if rst2: + print(' if (rst2) begin') + print(' x <= a;') + print(' y <= b;') + print(' z <= c;') + print(' state <= %d;' % random.choice(states)) + print(' end') + print(' end') + print(' end') + print('endmodule') + with file('temp/uut_%05d.ys' % idx, 'w') as f: + with redirect_stdout(f): + if test_verific: + print('read_verilog temp/uut_%05d.v' % idx) + print('proc;; rename uut_%05d gold' % idx) + print('verific -vlog2k temp/uut_%05d.v' % idx) + print('verific -import uut_%05d' % idx) + print('rename uut_%05d gate' % idx) + else: + print('read_verilog temp/uut_%05d.v' % idx) + print('proc;;') + print('copy uut_%05d gold' % idx) + print('rename uut_%05d gate' % idx) + print('cd gate') + print('opt; wreduce; share%s; opt; fsm;;' % random.choice(['', ' -aggressive'])) + print('cd ..') + print('miter -equiv -flatten -ignore_gold_x -make_outputs -make_outcmp gold gate miter') + print('sat -verify-no-timeout -timeout 20 -seq 5 -set-at 1 %s_rst 1 -prove trigger 0 -prove-skip 1 -show-inputs -show-outputs miter' % ('gold' if rst2 else 'in')) diff --git a/tests/realmath/generate.py b/tests/realmath/generate.py index 972021dc8..24d13561a 100644 --- a/tests/realmath/generate.py +++ b/tests/realmath/generate.py @@ -40,52 +40,55 @@ def random_expression(depth = 3, maxparam = 0): raise for idx in range(100): - with file('temp/uut_%05d.v' % idx, 'w') as f, redirect_stdout(f): - print('module uut_%05d(output [63:0] %s);\n' % (idx, ', '.join(['y%02d' % i for i in range(100)]))) - for i in range(30): - if idx < 10: - print('localparam p%02d = %s;' % (i, random_expression())) - else: - print('localparam%s p%02d = %s;' % (random.choice(['', ' real', ' integer']), i, random_expression())) - for i in range(30, 60): - if idx < 10: - print('localparam p%02d = %s;' % (i, random_expression(maxparam = 30))) - else: - print('localparam%s p%02d = %s;' % (random.choice(['', ' real', ' integer']), i, random_expression(maxparam = 30))) - for i in range(100): - print('assign y%02d = 65536 * (%s);' % (i, random_expression(maxparam = 60))) - print('endmodule') - with file('temp/uut_%05d.ys' % idx, 'w') as f, redirect_stdout(f): - print('read_verilog uut_%05d.v' % idx) - print('rename uut_%05d uut_%05d_syn' % (idx, idx)) - print('write_verilog uut_%05d_syn.v' % idx) - with file('temp/uut_%05d_tb.v' % idx, 'w') as f, redirect_stdout(f): - print('module uut_%05d_tb;\n' % idx) - print('wire [63:0] %s;' % (', '.join(['r%02d' % i for i in range(100)]))) - print('wire [63:0] %s;' % (', '.join(['s%02d' % i for i in range(100)]))) - print('uut_%05d ref(%s);' % (idx, ', '.join(['r%02d' % i for i in range(100)]))) - print('uut_%05d_syn syn(%s);' % (idx, ', '.join(['s%02d' % i for i in range(100)]))) - print('task compare_ref_syn;') - print(' input [7:0] i;') - print(' input [63:0] r, s;') - print(' reg [64*8-1:0] buffer;') - print(' integer j;') - print(' begin') - print(' if (-1 <= $signed(r-s) && $signed(r-s) <= +1) begin') - print(' // $display("%d: %b %b", i, r, s);') - print(' end else if (r === s) begin ') - print(' // $display("%d: %b %b", i, r, s);') - print(' end else begin ') - print(' for (j = 0; j < 64; j = j+1)') - print(' buffer[j*8 +: 8] = r[j] !== s[j] ? "^" : " ";') - print(' $display("\\n%3d: %b %b", i, r, s);') - print(' $display(" %s %s", buffer, buffer);') - print(' end') - print(' end') - print('endtask') - print('initial begin #1;') - for i in range(100): - print(' compare_ref_syn(%2d, r%02d, s%02d);' % (i, i, i)) - print('end') - print('endmodule') + with file('temp/uut_%05d.v' % idx, 'w') as f: + with redirect_stdout(f): + print('module uut_%05d(output [63:0] %s);\n' % (idx, ', '.join(['y%02d' % i for i in range(100)]))) + for i in range(30): + if idx < 10: + print('localparam p%02d = %s;' % (i, random_expression())) + else: + print('localparam%s p%02d = %s;' % (random.choice(['', ' real', ' integer']), i, random_expression())) + for i in range(30, 60): + if idx < 10: + print('localparam p%02d = %s;' % (i, random_expression(maxparam = 30))) + else: + print('localparam%s p%02d = %s;' % (random.choice(['', ' real', ' integer']), i, random_expression(maxparam = 30))) + for i in range(100): + print('assign y%02d = 65536 * (%s);' % (i, random_expression(maxparam = 60))) + print('endmodule') + with file('temp/uut_%05d.ys' % idx, 'w') as f: + with redirect_stdout(f): + print('read_verilog uut_%05d.v' % idx) + print('rename uut_%05d uut_%05d_syn' % (idx, idx)) + print('write_verilog uut_%05d_syn.v' % idx) + with file('temp/uut_%05d_tb.v' % idx, 'w') as f: + with redirect_stdout(f): + print('module uut_%05d_tb;\n' % idx) + print('wire [63:0] %s;' % (', '.join(['r%02d' % i for i in range(100)]))) + print('wire [63:0] %s;' % (', '.join(['s%02d' % i for i in range(100)]))) + print('uut_%05d ref(%s);' % (idx, ', '.join(['r%02d' % i for i in range(100)]))) + print('uut_%05d_syn syn(%s);' % (idx, ', '.join(['s%02d' % i for i in range(100)]))) + print('task compare_ref_syn;') + print(' input [7:0] i;') + print(' input [63:0] r, s;') + print(' reg [64*8-1:0] buffer;') + print(' integer j;') + print(' begin') + print(' if (-1 <= $signed(r-s) && $signed(r-s) <= +1) begin') + print(' // $display("%d: %b %b", i, r, s);') + print(' end else if (r === s) begin ') + print(' // $display("%d: %b %b", i, r, s);') + print(' end else begin ') + print(' for (j = 0; j < 64; j = j+1)') + print(' buffer[j*8 +: 8] = r[j] !== s[j] ? "^" : " ";') + print(' $display("\\n%3d: %b %b", i, r, s);') + print(' $display(" %s %s", buffer, buffer);') + print(' end') + print(' end') + print('endtask') + print('initial begin #1;') + for i in range(100): + print(' compare_ref_syn(%2d, r%02d, s%02d);' % (i, i, i)) + print('end') + print('endmodule') diff --git a/tests/share/generate.py b/tests/share/generate.py index a06a642d8..bb96fec61 100644 --- a/tests/share/generate.py +++ b/tests/share/generate.py @@ -25,49 +25,51 @@ def maybe_plus_x(expr): return expr for idx in range(100): - with file('temp/uut_%05d.v' % idx, 'w') as f, redirect_stdout(f): - if random.choice(['bin', 'uni']) == 'bin': - print('module uut_%05d(a, b, c, d, x, s, y);' % (idx)) - op = random.choice([ - random.choice(['+', '-', '*', '/', '%']), - random.choice(['<', '<=', '==', '!=', '===', '!==', '>=', '>' ]), - random.choice(['<<', '>>', '<<<', '>>>']), - random.choice(['|', '&', '^', '~^', '||', '&&']), - ]) - print(' input%s [%d:0] a;' % (random.choice(['', ' signed']), random.randint(0, 8))) - print(' input%s [%d:0] b;' % (random.choice(['', ' signed']), random.randint(0, 8))) - print(' input%s [%d:0] c;' % (random.choice(['', ' signed']), random.randint(0, 8))) - print(' input%s [%d:0] d;' % (random.choice(['', ' signed']), random.randint(0, 8))) - print(' input%s [%d:0] x;' % (random.choice(['', ' signed']), random.randint(0, 8))) - print(' input s;') - print(' output [%d:0] y;' % random.randint(0, 8)) - print(' assign y = (s ? %s(%s %s %s) : %s(%s %s %s))%s;' % - (random.choice(['', '$signed', '$unsigned']), maybe_plus_x('a'), op, maybe_plus_x('b'), - random.choice(['', '$signed', '$unsigned']), maybe_plus_x('c'), op, maybe_plus_x('d'), - random_plus_x() if random.randint(0, 4) == 0 else '')) - print('endmodule') - else: - print('module uut_%05d(a, b, x, s, y);' % (idx)) - op = random.choice(['~', '-', '!']) - print(' input%s [%d:0] a;' % (random.choice(['', ' signed']), random.randint(0, 8))) - print(' input%s [%d:0] b;' % (random.choice(['', ' signed']), random.randint(0, 8))) - print(' input%s [%d:0] x;' % (random.choice(['', ' signed']), random.randint(0, 8))) - print(' input s;') - print(' output [%d:0] y;' % random.randint(0, 8)) - print(' assign y = (s ? %s(%s%s) : %s(%s%s))%s;' % - (random.choice(['', '$signed', '$unsigned']), op, maybe_plus_x('a'), - random.choice(['', '$signed', '$unsigned']), op, maybe_plus_x('b'), - random_plus_x() if random.randint(0, 4) == 0 else '')) - print('endmodule') - with file('temp/uut_%05d.ys' % idx, 'w') as f, redirect_stdout(f): - print('read_verilog temp/uut_%05d.v' % idx) - print('proc;;') - print('copy uut_%05d gold' % idx) - print('rename uut_%05d gate' % idx) - print('tee -a temp/all_share_log.txt log') - print('tee -a temp/all_share_log.txt log #job# uut_%05d' % idx) - print('tee -a temp/all_share_log.txt wreduce') - print('tee -a temp/all_share_log.txt share -aggressive gate') - print('miter -equiv -flatten -ignore_gold_x -make_outputs -make_outcmp gold gate miter') - print('sat -set-def-inputs -verify -prove trigger 0 -show-inputs -show-outputs miter') + with file('temp/uut_%05d.v' % idx, 'w') as f: + with redirect_stdout(f): + if random.choice(['bin', 'uni']) == 'bin': + print('module uut_%05d(a, b, c, d, x, s, y);' % (idx)) + op = random.choice([ + random.choice(['+', '-', '*', '/', '%']), + random.choice(['<', '<=', '==', '!=', '===', '!==', '>=', '>' ]), + random.choice(['<<', '>>', '<<<', '>>>']), + random.choice(['|', '&', '^', '~^', '||', '&&']), + ]) + print(' input%s [%d:0] a;' % (random.choice(['', ' signed']), random.randint(0, 8))) + print(' input%s [%d:0] b;' % (random.choice(['', ' signed']), random.randint(0, 8))) + print(' input%s [%d:0] c;' % (random.choice(['', ' signed']), random.randint(0, 8))) + print(' input%s [%d:0] d;' % (random.choice(['', ' signed']), random.randint(0, 8))) + print(' input%s [%d:0] x;' % (random.choice(['', ' signed']), random.randint(0, 8))) + print(' input s;') + print(' output [%d:0] y;' % random.randint(0, 8)) + print(' assign y = (s ? %s(%s %s %s) : %s(%s %s %s))%s;' % + (random.choice(['', '$signed', '$unsigned']), maybe_plus_x('a'), op, maybe_plus_x('b'), + random.choice(['', '$signed', '$unsigned']), maybe_plus_x('c'), op, maybe_plus_x('d'), + random_plus_x() if random.randint(0, 4) == 0 else '')) + print('endmodule') + else: + print('module uut_%05d(a, b, x, s, y);' % (idx)) + op = random.choice(['~', '-', '!']) + print(' input%s [%d:0] a;' % (random.choice(['', ' signed']), random.randint(0, 8))) + print(' input%s [%d:0] b;' % (random.choice(['', ' signed']), random.randint(0, 8))) + print(' input%s [%d:0] x;' % (random.choice(['', ' signed']), random.randint(0, 8))) + print(' input s;') + print(' output [%d:0] y;' % random.randint(0, 8)) + print(' assign y = (s ? %s(%s%s) : %s(%s%s))%s;' % + (random.choice(['', '$signed', '$unsigned']), op, maybe_plus_x('a'), + random.choice(['', '$signed', '$unsigned']), op, maybe_plus_x('b'), + random_plus_x() if random.randint(0, 4) == 0 else '')) + print('endmodule') + with file('temp/uut_%05d.ys' % idx, 'w') as f: + with redirect_stdout(f): + print('read_verilog temp/uut_%05d.v' % idx) + print('proc;;') + print('copy uut_%05d gold' % idx) + print('rename uut_%05d gate' % idx) + print('tee -a temp/all_share_log.txt log') + print('tee -a temp/all_share_log.txt log #job# uut_%05d' % idx) + print('tee -a temp/all_share_log.txt wreduce') + print('tee -a temp/all_share_log.txt share -aggressive gate') + print('miter -equiv -flatten -ignore_gold_x -make_outputs -make_outcmp gold gate miter') + print('sat -set-def-inputs -verify -prove trigger 0 -show-inputs -show-outputs miter') -- cgit v1.2.3