From 3f0bb441f8a3014bf6b3a656b673fc07663bda76 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Mon, 4 Feb 2019 16:46:24 -0800 Subject: Add tests --- tests/aig/and.aag | 5 +++++ tests/aig/buffer.aag | 3 +++ tests/aig/cnt1.aag | 3 +++ tests/aig/cnt1e.aag | 8 ++++++++ tests/aig/empty.aag | 1 + tests/aig/false.aag | 2 ++ tests/aig/halfadder.aag | 14 ++++++++++++++ tests/aig/inverter.aag | 3 +++ tests/aig/notcnt1.aag | 4 ++++ tests/aig/notcnt1e.aag | 8 ++++++++ tests/aig/or.aag | 5 +++++ tests/aig/run-test.sh | 20 ++++++++++++++++++++ tests/aig/toggle-re.aag | 14 ++++++++++++++ tests/aig/toggle.aag | 4 ++++ tests/aig/true.aag | 2 ++ tests/tools/autotest.sh | 21 +++++++++++++-------- 16 files changed, 109 insertions(+), 8 deletions(-) create mode 100644 tests/aig/and.aag create mode 100644 tests/aig/buffer.aag create mode 100644 tests/aig/cnt1.aag create mode 100644 tests/aig/cnt1e.aag create mode 100644 tests/aig/empty.aag create mode 100644 tests/aig/false.aag create mode 100644 tests/aig/halfadder.aag create mode 100644 tests/aig/inverter.aag create mode 100644 tests/aig/notcnt1.aag create mode 100644 tests/aig/notcnt1e.aag create mode 100644 tests/aig/or.aag create mode 100755 tests/aig/run-test.sh create mode 100644 tests/aig/toggle-re.aag create mode 100644 tests/aig/toggle.aag create mode 100644 tests/aig/true.aag (limited to 'tests') diff --git a/tests/aig/and.aag b/tests/aig/and.aag new file mode 100644 index 000000000..d1ef2c5a5 --- /dev/null +++ b/tests/aig/and.aag @@ -0,0 +1,5 @@ +aag 3 2 0 1 1 +2 +4 +6 +6 2 4 diff --git a/tests/aig/buffer.aag b/tests/aig/buffer.aag new file mode 100644 index 000000000..94a6fb1ed --- /dev/null +++ b/tests/aig/buffer.aag @@ -0,0 +1,3 @@ +aag 1 1 0 1 0 +2 +2 diff --git a/tests/aig/cnt1.aag b/tests/aig/cnt1.aag new file mode 100644 index 000000000..ce4f28fcb --- /dev/null +++ b/tests/aig/cnt1.aag @@ -0,0 +1,3 @@ +aag 1 0 1 0 0 1 +2 3 +2 diff --git a/tests/aig/cnt1e.aag b/tests/aig/cnt1e.aag new file mode 100644 index 000000000..6db3f0ffd --- /dev/null +++ b/tests/aig/cnt1e.aag @@ -0,0 +1,8 @@ +aag 5 1 1 0 3 1 +2 +4 10 +4 +6 5 3 +8 4 2 +10 9 7 +b0 AIGER_NEVER diff --git a/tests/aig/empty.aag b/tests/aig/empty.aag new file mode 100644 index 000000000..40c0f00cb --- /dev/null +++ b/tests/aig/empty.aag @@ -0,0 +1 @@ +aag 0 0 0 0 0 diff --git a/tests/aig/false.aag b/tests/aig/false.aag new file mode 100644 index 000000000..421e64a91 --- /dev/null +++ b/tests/aig/false.aag @@ -0,0 +1,2 @@ +aag 0 0 0 1 0 +0 diff --git a/tests/aig/halfadder.aag b/tests/aig/halfadder.aag new file mode 100644 index 000000000..5bf54d38d --- /dev/null +++ b/tests/aig/halfadder.aag @@ -0,0 +1,14 @@ +aag 7 2 0 2 3 +2 +4 +6 +12 +6 13 15 +12 2 4 +14 3 5 +i0 x +i1 y +o0 s +o1 c +c +half adder diff --git a/tests/aig/inverter.aag b/tests/aig/inverter.aag new file mode 100644 index 000000000..ff7c28542 --- /dev/null +++ b/tests/aig/inverter.aag @@ -0,0 +1,3 @@ +aag 1 1 0 1 0 +2 +3 diff --git a/tests/aig/notcnt1.aag b/tests/aig/notcnt1.aag new file mode 100644 index 000000000..e92815f23 --- /dev/null +++ b/tests/aig/notcnt1.aag @@ -0,0 +1,4 @@ +aag 1 0 1 0 0 1 +2 3 +3 +b0 AIGER_NEVER diff --git a/tests/aig/notcnt1e.aag b/tests/aig/notcnt1e.aag new file mode 100644 index 000000000..141c864f7 --- /dev/null +++ b/tests/aig/notcnt1e.aag @@ -0,0 +1,8 @@ +aag 5 1 1 0 3 1 +2 +4 10 +5 +6 5 3 +8 4 2 +10 9 7 +b0 AIGER_NEVER diff --git a/tests/aig/or.aag b/tests/aig/or.aag new file mode 100644 index 000000000..f780e339f --- /dev/null +++ b/tests/aig/or.aag @@ -0,0 +1,5 @@ +aag 3 2 0 1 1 +2 +4 +7 +6 3 5 diff --git a/tests/aig/run-test.sh b/tests/aig/run-test.sh new file mode 100755 index 000000000..308578f01 --- /dev/null +++ b/tests/aig/run-test.sh @@ -0,0 +1,20 @@ +#!/bin/bash + +OPTIND=1 +seed="" # default to no seed specified +while getopts "S:" opt +do + case "$opt" in + S) arg="${OPTARG#"${OPTARG%%[![:space:]]*}"}" # remove leading space + seed="SEED=$arg" ;; + esac +done +shift "$((OPTIND-1))" + +# check for Icarus Verilog +if ! which iverilog > /dev/null ; then + echo "$0: Error: Icarus Verilog 'iverilog' not found." + exit 1 +fi + +exec ${MAKE:-make} -f ../tools/autotest.mk $seed *.aag EXTRA_FLAGS="-f aiger" diff --git a/tests/aig/toggle-re.aag b/tests/aig/toggle-re.aag new file mode 100644 index 000000000..b662bb386 --- /dev/null +++ b/tests/aig/toggle-re.aag @@ -0,0 +1,14 @@ +aag 7 2 1 2 4 +2 +4 +6 8 +6 +7 +8 4 10 +10 13 15 +12 2 6 +14 3 7 +i0 enable +i1 reset +o0 Q +o1 !Q diff --git a/tests/aig/toggle.aag b/tests/aig/toggle.aag new file mode 100644 index 000000000..09651012d --- /dev/null +++ b/tests/aig/toggle.aag @@ -0,0 +1,4 @@ +aag 1 0 1 2 0 +2 3 +2 +3 diff --git a/tests/aig/true.aag b/tests/aig/true.aag new file mode 100644 index 000000000..366893648 --- /dev/null +++ b/tests/aig/true.aag @@ -0,0 +1,2 @@ +aag 0 0 0 1 0 +1 diff --git a/tests/tools/autotest.sh b/tests/tools/autotest.sh index d6216244f..c01ce5611 100755 --- a/tests/tools/autotest.sh +++ b/tests/tools/autotest.sh @@ -86,8 +86,9 @@ shift $((OPTIND - 1)) for fn do - bn=${fn%.v} - if [ "$bn" == "$fn" ]; then + bn=${fn%.*} + ext=${fn##*.} + if [[ "$ext" != "v" ]] && [[ "$ext" != "aag" ]]; then echo "Invalid argument: $fn" >&2 exit 1 fi @@ -109,10 +110,14 @@ do fn=$(basename $fn) bn=$(basename $bn) - egrep -v '^\s*`timescale' ../$fn > ${bn}_ref.v + if [[ "$ext" == "v" ]]; then + egrep -v '^\s*`timescale' ../$fn > ${bn}_ref.${ext} + else + cp ../$fn ${bn}_ref.${ext} + fi if [ ! -f ../${bn}_tb.v ]; then - "$toolsdir"/../../yosys -f "$frontend $include_opts" -b "test_autotb $autotb_opts" -o ${bn}_tb.v ${bn}_ref.v + "$toolsdir"/../../yosys -f "$frontend $include_opts" -b "test_autotb $autotb_opts" -o ${bn}_tb.v ${bn}_ref.${ext} else cp ../${bn}_tb.v ${bn}_tb.v fi @@ -138,16 +143,16 @@ do fi if [ -n "$scriptfiles" ]; then - test_passes -f "$frontend $include_opts" ${bn}_ref.v $scriptfiles + test_passes -f "$frontend $include_opts" ${bn}_ref.${ext} $scriptfiles elif [ -n "$scriptopt" ]; then - test_passes -f "$frontend $include_opts" -p "$scriptopt" ${bn}_ref.v + test_passes -f "$frontend $include_opts" -p "$scriptopt" ${bn}_ref.${ext} elif [ "$frontend" = "verific" ]; then test_passes -p "verific -vlog2k ${bn}_ref.v; verific -import -all; opt; memory;;" elif [ "$frontend" = "verific_gates" ]; then test_passes -p "verific -vlog2k ${bn}_ref.v; verific -import -gates -all; opt; memory;;" else - test_passes -f "$frontend $include_opts" -p "hierarchy; proc; opt; memory; opt; fsm; opt -full -fine" ${bn}_ref.v - test_passes -f "$frontend $include_opts" -p "hierarchy; synth -run coarse; techmap; opt; abc -dff" ${bn}_ref.v + test_passes -f "$frontend $include_opts" -p "hierarchy; proc; opt; memory; opt; fsm; opt -full -fine" ${bn}_ref.${ext} + test_passes -f "$frontend $include_opts" -p "hierarchy; synth -run coarse; techmap; opt; abc -dff" ${bn}_ref.${ext} fi touch ../${bn}.log } -- cgit v1.2.3 From fdd55d064b16f9334c86bb15b1c32cfb45294802 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Wed, 6 Feb 2019 12:20:36 -0800 Subject: Rename ASCII tests --- tests/aig/and.aag | 5 ----- tests/aig/buffer.aag | 3 --- tests/aig/cnt1.aag | 3 --- tests/aig/cnt1e.aag | 8 -------- tests/aig/empty.aag | 1 - tests/aig/false.aag | 2 -- tests/aig/halfadder.aag | 14 -------------- tests/aig/inverter.aag | 3 --- tests/aig/notcnt1.aag | 4 ---- tests/aig/notcnt1e.aag | 8 -------- tests/aig/or.aag | 5 ----- tests/aig/run-test.sh | 20 -------------------- tests/aig/toggle-re.aag | 14 -------------- tests/aig/toggle.aag | 4 ---- tests/aig/true.aag | 2 -- tests/aiger/and.aag | 5 +++++ tests/aiger/buffer.aag | 3 +++ tests/aiger/cnt1.aag | 3 +++ tests/aiger/cnt1e.aag | 8 ++++++++ tests/aiger/empty.aag | 1 + tests/aiger/false.aag | 2 ++ tests/aiger/halfadder.aag | 14 ++++++++++++++ tests/aiger/inverter.aag | 3 +++ tests/aiger/notcnt1.aag | 4 ++++ tests/aiger/notcnt1e.aag | 8 ++++++++ tests/aiger/or.aag | 5 +++++ tests/aiger/run-test.sh | 20 ++++++++++++++++++++ tests/aiger/toggle-re.aag | 14 ++++++++++++++ tests/aiger/toggle.aag | 4 ++++ tests/aiger/true.aag | 2 ++ 30 files changed, 96 insertions(+), 96 deletions(-) delete mode 100644 tests/aig/and.aag delete mode 100644 tests/aig/buffer.aag delete mode 100644 tests/aig/cnt1.aag delete mode 100644 tests/aig/cnt1e.aag delete mode 100644 tests/aig/empty.aag delete mode 100644 tests/aig/false.aag delete mode 100644 tests/aig/halfadder.aag delete mode 100644 tests/aig/inverter.aag delete mode 100644 tests/aig/notcnt1.aag delete mode 100644 tests/aig/notcnt1e.aag delete mode 100644 tests/aig/or.aag delete mode 100755 tests/aig/run-test.sh delete mode 100644 tests/aig/toggle-re.aag delete mode 100644 tests/aig/toggle.aag delete mode 100644 tests/aig/true.aag create mode 100644 tests/aiger/and.aag create mode 100644 tests/aiger/buffer.aag create mode 100644 tests/aiger/cnt1.aag create mode 100644 tests/aiger/cnt1e.aag create mode 100644 tests/aiger/empty.aag create mode 100644 tests/aiger/false.aag create mode 100644 tests/aiger/halfadder.aag create mode 100644 tests/aiger/inverter.aag create mode 100644 tests/aiger/notcnt1.aag create mode 100644 tests/aiger/notcnt1e.aag create mode 100644 tests/aiger/or.aag create mode 100755 tests/aiger/run-test.sh create mode 100644 tests/aiger/toggle-re.aag create mode 100644 tests/aiger/toggle.aag create mode 100644 tests/aiger/true.aag (limited to 'tests') diff --git a/tests/aig/and.aag b/tests/aig/and.aag deleted file mode 100644 index d1ef2c5a5..000000000 --- a/tests/aig/and.aag +++ /dev/null @@ -1,5 +0,0 @@ -aag 3 2 0 1 1 -2 -4 -6 -6 2 4 diff --git a/tests/aig/buffer.aag b/tests/aig/buffer.aag deleted file mode 100644 index 94a6fb1ed..000000000 --- a/tests/aig/buffer.aag +++ /dev/null @@ -1,3 +0,0 @@ -aag 1 1 0 1 0 -2 -2 diff --git a/tests/aig/cnt1.aag b/tests/aig/cnt1.aag deleted file mode 100644 index ce4f28fcb..000000000 --- a/tests/aig/cnt1.aag +++ /dev/null @@ -1,3 +0,0 @@ -aag 1 0 1 0 0 1 -2 3 -2 diff --git a/tests/aig/cnt1e.aag b/tests/aig/cnt1e.aag deleted file mode 100644 index 6db3f0ffd..000000000 --- a/tests/aig/cnt1e.aag +++ /dev/null @@ -1,8 +0,0 @@ -aag 5 1 1 0 3 1 -2 -4 10 -4 -6 5 3 -8 4 2 -10 9 7 -b0 AIGER_NEVER diff --git a/tests/aig/empty.aag b/tests/aig/empty.aag deleted file mode 100644 index 40c0f00cb..000000000 --- a/tests/aig/empty.aag +++ /dev/null @@ -1 +0,0 @@ -aag 0 0 0 0 0 diff --git a/tests/aig/false.aag b/tests/aig/false.aag deleted file mode 100644 index 421e64a91..000000000 --- a/tests/aig/false.aag +++ /dev/null @@ -1,2 +0,0 @@ -aag 0 0 0 1 0 -0 diff --git a/tests/aig/halfadder.aag b/tests/aig/halfadder.aag deleted file mode 100644 index 5bf54d38d..000000000 --- a/tests/aig/halfadder.aag +++ /dev/null @@ -1,14 +0,0 @@ -aag 7 2 0 2 3 -2 -4 -6 -12 -6 13 15 -12 2 4 -14 3 5 -i0 x -i1 y -o0 s -o1 c -c -half adder diff --git a/tests/aig/inverter.aag b/tests/aig/inverter.aag deleted file mode 100644 index ff7c28542..000000000 --- a/tests/aig/inverter.aag +++ /dev/null @@ -1,3 +0,0 @@ -aag 1 1 0 1 0 -2 -3 diff --git a/tests/aig/notcnt1.aag b/tests/aig/notcnt1.aag deleted file mode 100644 index e92815f23..000000000 --- a/tests/aig/notcnt1.aag +++ /dev/null @@ -1,4 +0,0 @@ -aag 1 0 1 0 0 1 -2 3 -3 -b0 AIGER_NEVER diff --git a/tests/aig/notcnt1e.aag b/tests/aig/notcnt1e.aag deleted file mode 100644 index 141c864f7..000000000 --- a/tests/aig/notcnt1e.aag +++ /dev/null @@ -1,8 +0,0 @@ -aag 5 1 1 0 3 1 -2 -4 10 -5 -6 5 3 -8 4 2 -10 9 7 -b0 AIGER_NEVER diff --git a/tests/aig/or.aag b/tests/aig/or.aag deleted file mode 100644 index f780e339f..000000000 --- a/tests/aig/or.aag +++ /dev/null @@ -1,5 +0,0 @@ -aag 3 2 0 1 1 -2 -4 -7 -6 3 5 diff --git a/tests/aig/run-test.sh b/tests/aig/run-test.sh deleted file mode 100755 index 308578f01..000000000 --- a/tests/aig/run-test.sh +++ /dev/null @@ -1,20 +0,0 @@ -#!/bin/bash - -OPTIND=1 -seed="" # default to no seed specified -while getopts "S:" opt -do - case "$opt" in - S) arg="${OPTARG#"${OPTARG%%[![:space:]]*}"}" # remove leading space - seed="SEED=$arg" ;; - esac -done -shift "$((OPTIND-1))" - -# check for Icarus Verilog -if ! which iverilog > /dev/null ; then - echo "$0: Error: Icarus Verilog 'iverilog' not found." - exit 1 -fi - -exec ${MAKE:-make} -f ../tools/autotest.mk $seed *.aag EXTRA_FLAGS="-f aiger" diff --git a/tests/aig/toggle-re.aag b/tests/aig/toggle-re.aag deleted file mode 100644 index b662bb386..000000000 --- a/tests/aig/toggle-re.aag +++ /dev/null @@ -1,14 +0,0 @@ -aag 7 2 1 2 4 -2 -4 -6 8 -6 -7 -8 4 10 -10 13 15 -12 2 6 -14 3 7 -i0 enable -i1 reset -o0 Q -o1 !Q diff --git a/tests/aig/toggle.aag b/tests/aig/toggle.aag deleted file mode 100644 index 09651012d..000000000 --- a/tests/aig/toggle.aag +++ /dev/null @@ -1,4 +0,0 @@ -aag 1 0 1 2 0 -2 3 -2 -3 diff --git a/tests/aig/true.aag b/tests/aig/true.aag deleted file mode 100644 index 366893648..000000000 --- a/tests/aig/true.aag +++ /dev/null @@ -1,2 +0,0 @@ -aag 0 0 0 1 0 -1 diff --git a/tests/aiger/and.aag b/tests/aiger/and.aag new file mode 100644 index 000000000..d1ef2c5a5 --- /dev/null +++ b/tests/aiger/and.aag @@ -0,0 +1,5 @@ +aag 3 2 0 1 1 +2 +4 +6 +6 2 4 diff --git a/tests/aiger/buffer.aag b/tests/aiger/buffer.aag new file mode 100644 index 000000000..94a6fb1ed --- /dev/null +++ b/tests/aiger/buffer.aag @@ -0,0 +1,3 @@ +aag 1 1 0 1 0 +2 +2 diff --git a/tests/aiger/cnt1.aag b/tests/aiger/cnt1.aag new file mode 100644 index 000000000..ce4f28fcb --- /dev/null +++ b/tests/aiger/cnt1.aag @@ -0,0 +1,3 @@ +aag 1 0 1 0 0 1 +2 3 +2 diff --git a/tests/aiger/cnt1e.aag b/tests/aiger/cnt1e.aag new file mode 100644 index 000000000..6db3f0ffd --- /dev/null +++ b/tests/aiger/cnt1e.aag @@ -0,0 +1,8 @@ +aag 5 1 1 0 3 1 +2 +4 10 +4 +6 5 3 +8 4 2 +10 9 7 +b0 AIGER_NEVER diff --git a/tests/aiger/empty.aag b/tests/aiger/empty.aag new file mode 100644 index 000000000..40c0f00cb --- /dev/null +++ b/tests/aiger/empty.aag @@ -0,0 +1 @@ +aag 0 0 0 0 0 diff --git a/tests/aiger/false.aag b/tests/aiger/false.aag new file mode 100644 index 000000000..421e64a91 --- /dev/null +++ b/tests/aiger/false.aag @@ -0,0 +1,2 @@ +aag 0 0 0 1 0 +0 diff --git a/tests/aiger/halfadder.aag b/tests/aiger/halfadder.aag new file mode 100644 index 000000000..5bf54d38d --- /dev/null +++ b/tests/aiger/halfadder.aag @@ -0,0 +1,14 @@ +aag 7 2 0 2 3 +2 +4 +6 +12 +6 13 15 +12 2 4 +14 3 5 +i0 x +i1 y +o0 s +o1 c +c +half adder diff --git a/tests/aiger/inverter.aag b/tests/aiger/inverter.aag new file mode 100644 index 000000000..ff7c28542 --- /dev/null +++ b/tests/aiger/inverter.aag @@ -0,0 +1,3 @@ +aag 1 1 0 1 0 +2 +3 diff --git a/tests/aiger/notcnt1.aag b/tests/aiger/notcnt1.aag new file mode 100644 index 000000000..e92815f23 --- /dev/null +++ b/tests/aiger/notcnt1.aag @@ -0,0 +1,4 @@ +aag 1 0 1 0 0 1 +2 3 +3 +b0 AIGER_NEVER diff --git a/tests/aiger/notcnt1e.aag b/tests/aiger/notcnt1e.aag new file mode 100644 index 000000000..141c864f7 --- /dev/null +++ b/tests/aiger/notcnt1e.aag @@ -0,0 +1,8 @@ +aag 5 1 1 0 3 1 +2 +4 10 +5 +6 5 3 +8 4 2 +10 9 7 +b0 AIGER_NEVER diff --git a/tests/aiger/or.aag b/tests/aiger/or.aag new file mode 100644 index 000000000..f780e339f --- /dev/null +++ b/tests/aiger/or.aag @@ -0,0 +1,5 @@ +aag 3 2 0 1 1 +2 +4 +7 +6 3 5 diff --git a/tests/aiger/run-test.sh b/tests/aiger/run-test.sh new file mode 100755 index 000000000..308578f01 --- /dev/null +++ b/tests/aiger/run-test.sh @@ -0,0 +1,20 @@ +#!/bin/bash + +OPTIND=1 +seed="" # default to no seed specified +while getopts "S:" opt +do + case "$opt" in + S) arg="${OPTARG#"${OPTARG%%[![:space:]]*}"}" # remove leading space + seed="SEED=$arg" ;; + esac +done +shift "$((OPTIND-1))" + +# check for Icarus Verilog +if ! which iverilog > /dev/null ; then + echo "$0: Error: Icarus Verilog 'iverilog' not found." + exit 1 +fi + +exec ${MAKE:-make} -f ../tools/autotest.mk $seed *.aag EXTRA_FLAGS="-f aiger" diff --git a/tests/aiger/toggle-re.aag b/tests/aiger/toggle-re.aag new file mode 100644 index 000000000..b662bb386 --- /dev/null +++ b/tests/aiger/toggle-re.aag @@ -0,0 +1,14 @@ +aag 7 2 1 2 4 +2 +4 +6 8 +6 +7 +8 4 10 +10 13 15 +12 2 6 +14 3 7 +i0 enable +i1 reset +o0 Q +o1 !Q diff --git a/tests/aiger/toggle.aag b/tests/aiger/toggle.aag new file mode 100644 index 000000000..09651012d --- /dev/null +++ b/tests/aiger/toggle.aag @@ -0,0 +1,4 @@ +aag 1 0 1 2 0 +2 3 +2 +3 diff --git a/tests/aiger/true.aag b/tests/aiger/true.aag new file mode 100644 index 000000000..366893648 --- /dev/null +++ b/tests/aiger/true.aag @@ -0,0 +1,2 @@ +aag 0 0 0 1 0 +1 -- cgit v1.2.3 From 3f87cf86ccefe6e66f768fbf19c34db97cf7246d Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Wed, 6 Feb 2019 14:30:19 -0800 Subject: Revert most of autotest.sh; for non *.v use Yosys to translate --- tests/tools/autotest.sh | 16 +++++++++------- 1 file changed, 9 insertions(+), 7 deletions(-) (limited to 'tests') diff --git a/tests/tools/autotest.sh b/tests/tools/autotest.sh index c01ce5611..3bce003e1 100755 --- a/tests/tools/autotest.sh +++ b/tests/tools/autotest.sh @@ -113,16 +113,18 @@ do if [[ "$ext" == "v" ]]; then egrep -v '^\s*`timescale' ../$fn > ${bn}_ref.${ext} else - cp ../$fn ${bn}_ref.${ext} + "$toolsdir"/../../yosys -f "$frontend $include_opts" -b "verilog" -o ${bn}_ref.v ../${fn} + frontend="verilog" fi if [ ! -f ../${bn}_tb.v ]; then - "$toolsdir"/../../yosys -f "$frontend $include_opts" -b "test_autotb $autotb_opts" -o ${bn}_tb.v ${bn}_ref.${ext} + "$toolsdir"/../../yosys -f "$frontend $include_opts" -b "test_autotb $autotb_opts" -o ${bn}_tb.v ${bn}_ref.v else cp ../${bn}_tb.v ${bn}_tb.v fi if $genvcd; then sed -i 's,// \$dump,$dump,g' ${bn}_tb.v; fi - compile_and_run ${bn}_tb_ref ${bn}_out_ref ${bn}_tb.v ${bn}_ref.v $libs + compile_and_run ${bn}_tb_ref ${bn}_out_ref ${bn}_tb.v ${bn}_ref.v $libs \ + "$toolsdir"/../../techlibs/common/simlib.v if $genvcd; then mv testbench.vcd ${bn}_ref.vcd; fi test_count=0 @@ -143,16 +145,16 @@ do fi if [ -n "$scriptfiles" ]; then - test_passes -f "$frontend $include_opts" ${bn}_ref.${ext} $scriptfiles + test_passes -f "$frontend $include_opts" ${bn}_ref.v $scriptfiles elif [ -n "$scriptopt" ]; then - test_passes -f "$frontend $include_opts" -p "$scriptopt" ${bn}_ref.${ext} + test_passes -f "$frontend $include_opts" -p "$scriptopt" ${bn}_ref.v elif [ "$frontend" = "verific" ]; then test_passes -p "verific -vlog2k ${bn}_ref.v; verific -import -all; opt; memory;;" elif [ "$frontend" = "verific_gates" ]; then test_passes -p "verific -vlog2k ${bn}_ref.v; verific -import -gates -all; opt; memory;;" else - test_passes -f "$frontend $include_opts" -p "hierarchy; proc; opt; memory; opt; fsm; opt -full -fine" ${bn}_ref.${ext} - test_passes -f "$frontend $include_opts" -p "hierarchy; synth -run coarse; techmap; opt; abc -dff" ${bn}_ref.${ext} + test_passes -f "$frontend $include_opts" -p "hierarchy; proc; opt; memory; opt; fsm; opt -full -fine" ${bn}_ref.v + test_passes -f "$frontend $include_opts" -p "hierarchy; synth -run coarse; techmap; opt; abc -dff" ${bn}_ref.v fi touch ../${bn}.log } -- cgit v1.2.3 From 4e6c5e46725bb99e0c919a5f82ce5290da2ce2f9 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 8 Feb 2019 11:41:25 -0800 Subject: Add binary AIGs converted from AAG --- tests/aiger/and.aig | 3 +++ tests/aiger/buffer.aig | 2 ++ tests/aiger/cnt1.aig | 3 +++ tests/aiger/cnt1e.aig | 4 ++++ tests/aiger/empty.aig | 1 + tests/aiger/false.aig | 2 ++ tests/aiger/halfadder.aig | 9 +++++++++ tests/aiger/inverter.aig | 2 ++ tests/aiger/notcnt1.aig | 4 ++++ tests/aiger/notcnt1e.aig | 4 ++++ tests/aiger/or.aig | 3 +++ tests/aiger/toggle-re.aig | 8 ++++++++ tests/aiger/toggle.aig | 4 ++++ tests/aiger/true.aig | 2 ++ 14 files changed, 51 insertions(+) create mode 100644 tests/aiger/and.aig create mode 100644 tests/aiger/buffer.aig create mode 100644 tests/aiger/cnt1.aig create mode 100644 tests/aiger/cnt1e.aig create mode 100644 tests/aiger/empty.aig create mode 100644 tests/aiger/false.aig create mode 100644 tests/aiger/halfadder.aig create mode 100644 tests/aiger/inverter.aig create mode 100644 tests/aiger/notcnt1.aig create mode 100644 tests/aiger/notcnt1e.aig create mode 100644 tests/aiger/or.aig create mode 100644 tests/aiger/toggle-re.aig create mode 100644 tests/aiger/toggle.aig create mode 100644 tests/aiger/true.aig (limited to 'tests') diff --git a/tests/aiger/and.aig b/tests/aiger/and.aig new file mode 100644 index 000000000..da0fa0719 --- /dev/null +++ b/tests/aiger/and.aig @@ -0,0 +1,3 @@ +aig 3 2 0 1 1 +6 + \ No newline at end of file diff --git a/tests/aiger/buffer.aig b/tests/aiger/buffer.aig new file mode 100644 index 000000000..0c715fdeb --- /dev/null +++ b/tests/aiger/buffer.aig @@ -0,0 +1,2 @@ +aig 1 1 0 1 0 +2 diff --git a/tests/aiger/cnt1.aig b/tests/aiger/cnt1.aig new file mode 100644 index 000000000..8d0ba13b1 --- /dev/null +++ b/tests/aiger/cnt1.aig @@ -0,0 +1,3 @@ +aig 1 0 1 0 0 1 +3 +2 diff --git a/tests/aiger/cnt1e.aig b/tests/aiger/cnt1e.aig new file mode 100644 index 000000000..d8d159f11 --- /dev/null +++ b/tests/aiger/cnt1e.aig @@ -0,0 +1,4 @@ +aig 5 1 1 0 3 1 +10 +4 +b0 AIGER_NEVER diff --git a/tests/aiger/empty.aig b/tests/aiger/empty.aig new file mode 100644 index 000000000..a28373cd3 --- /dev/null +++ b/tests/aiger/empty.aig @@ -0,0 +1 @@ +aig 0 0 0 0 0 diff --git a/tests/aiger/false.aig b/tests/aiger/false.aig new file mode 100644 index 000000000..ad7d039fa --- /dev/null +++ b/tests/aiger/false.aig @@ -0,0 +1,2 @@ +aig 0 0 0 1 0 +0 diff --git a/tests/aiger/halfadder.aig b/tests/aiger/halfadder.aig new file mode 100644 index 000000000..83727ee63 --- /dev/null +++ b/tests/aiger/halfadder.aig @@ -0,0 +1,9 @@ +aig 5 2 0 2 3 +10 +6 +i0 x +i1 y +o0 s +o1 c +c +half adder diff --git a/tests/aiger/inverter.aig b/tests/aiger/inverter.aig new file mode 100644 index 000000000..525d82392 --- /dev/null +++ b/tests/aiger/inverter.aig @@ -0,0 +1,2 @@ +aig 1 1 0 1 0 +3 diff --git a/tests/aiger/notcnt1.aig b/tests/aiger/notcnt1.aig new file mode 100644 index 000000000..f8a667f1f --- /dev/null +++ b/tests/aiger/notcnt1.aig @@ -0,0 +1,4 @@ +aig 1 0 1 0 0 1 +3 +3 +b0 AIGER_NEVER diff --git a/tests/aiger/notcnt1e.aig b/tests/aiger/notcnt1e.aig new file mode 100644 index 000000000..7c85a7290 --- /dev/null +++ b/tests/aiger/notcnt1e.aig @@ -0,0 +1,4 @@ +aig 5 1 1 0 3 1 +10 +5 +b0 AIGER_NEVER diff --git a/tests/aiger/or.aig b/tests/aiger/or.aig new file mode 100644 index 000000000..75c9e4480 --- /dev/null +++ b/tests/aiger/or.aig @@ -0,0 +1,3 @@ +aig 3 2 0 1 1 +7 + \ No newline at end of file diff --git a/tests/aiger/toggle-re.aig b/tests/aiger/toggle-re.aig new file mode 100644 index 000000000..9d6730f21 --- /dev/null +++ b/tests/aiger/toggle-re.aig @@ -0,0 +1,8 @@ +aig 7 2 1 2 4 +14 +6 +7 +i0 enable +i1 reset +o0 Q +o1 !Q diff --git a/tests/aiger/toggle.aig b/tests/aiger/toggle.aig new file mode 100644 index 000000000..b69e21aaf --- /dev/null +++ b/tests/aiger/toggle.aig @@ -0,0 +1,4 @@ +aig 1 0 1 2 0 +3 +2 +3 diff --git a/tests/aiger/true.aig b/tests/aiger/true.aig new file mode 100644 index 000000000..10086f389 --- /dev/null +++ b/tests/aiger/true.aig @@ -0,0 +1,2 @@ +aig 0 0 0 1 0 +1 -- cgit v1.2.3 From 587872236ecd1ca2f2a466bccc8d41618feb0dfb Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 8 Feb 2019 12:41:59 -0800 Subject: Support and differentiate between ASCII and binary AIG testing --- tests/aiger/run-test.sh | 6 +++++- tests/tools/autotest.sh | 2 +- 2 files changed, 6 insertions(+), 2 deletions(-) (limited to 'tests') diff --git a/tests/aiger/run-test.sh b/tests/aiger/run-test.sh index 308578f01..e0a34f023 100755 --- a/tests/aiger/run-test.sh +++ b/tests/aiger/run-test.sh @@ -17,4 +17,8 @@ if ! which iverilog > /dev/null ; then exit 1 fi -exec ${MAKE:-make} -f ../tools/autotest.mk $seed *.aag EXTRA_FLAGS="-f aiger" +echo "===== AAG ======" +${MAKE:-make} -f ../tools/autotest.mk $seed *.aag EXTRA_FLAGS="-f aiger" + +echo "===== AIG ======" +exec ${MAKE:-make} -f ../tools/autotest.mk $seed *.aig EXTRA_FLAGS="-f aiger" diff --git a/tests/tools/autotest.sh b/tests/tools/autotest.sh index 3e1325b33..0ffa062e3 100755 --- a/tests/tools/autotest.sh +++ b/tests/tools/autotest.sh @@ -90,7 +90,7 @@ for fn do bn=${fn%.*} ext=${fn##*.} - if [[ "$ext" != "v" ]] && [[ "$ext" != "aag" ]]; then + if [[ "$ext" != "v" ]] && [[ "$ext" != "aag" ]] && [[ "$ext" != "aig" ]]; then echo "Invalid argument: $fn" >&2 exit 1 fi -- cgit v1.2.3 From 430a7548bca6046c812f713877253f8c3d81d805 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Sun, 17 Feb 2019 11:50:55 -0800 Subject: One more merge conflict --- tests/tools/autotest.sh | 7 +------ 1 file changed, 1 insertion(+), 6 deletions(-) (limited to 'tests') diff --git a/tests/tools/autotest.sh b/tests/tools/autotest.sh index 2722cba19..b5abc3570 100755 --- a/tests/tools/autotest.sh +++ b/tests/tools/autotest.sh @@ -134,18 +134,13 @@ do fn=$(basename $fn) bn=$(basename $bn) -<<<<<<< HEAD + rm -f ${bn}_ref.fir if [[ "$ext" == "v" ]]; then egrep -v '^\s*`timescale' ../$fn > ${bn}_ref.${ext} else "$toolsdir"/../../yosys -f "$frontend $include_opts" -b "verilog" -o ${bn}_ref.v ../${fn} frontend="verilog" fi -======= - rm -f ${bn}_ref.fir - - egrep -v '^\s*`timescale' ../$fn > ${bn}_ref.v ->>>>>>> e45f62b0c56717a23099425f078d1e56212aa632 if [ ! -f ../${bn}_tb.v ]; then "$toolsdir"/../../yosys -f "$frontend $include_opts" -b "test_autotb $autotb_opts" -o ${bn}_tb.v ${bn}_ref.v -- cgit v1.2.3 From d6c4dfb9020ee19eebe3adadca89b65627184d81 Mon Sep 17 00:00:00 2001 From: Jim Lawson Date: Mon, 4 Mar 2019 13:23:58 -0800 Subject: Ensure fid() calls make_id() for consistency; tests/simple/dff_init.v fails Mark dff_init.v as expected to fail since it uses "initial value". --- tests/simple/xfirrtl | 1 + 1 file changed, 1 insertion(+) (limited to 'tests') diff --git a/tests/simple/xfirrtl b/tests/simple/xfirrtl index 5bc75347b..50d693513 100644 --- a/tests/simple/xfirrtl +++ b/tests/simple/xfirrtl @@ -1,6 +1,7 @@ # This file contains the names of verilog files to exclude from verilog to FIRRTL regression tests due to known failures. arraycells.v inst id[0] of dff_different_styles.v +dff_init.v Initial value not supported generate.v combinational loop hierdefparam.v inst id[0] of i2c_master_tests.v $adff -- cgit v1.2.3 From a330c6836318d43d52cda68959f2b86c2b2ede9c Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Thu, 7 Mar 2019 22:44:37 -0800 Subject: Fix handling of task output ports in clocked always blocks, fixes #857 Signed-off-by: Clifford Wolf --- tests/simple/task_func.v | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) (limited to 'tests') diff --git a/tests/simple/task_func.v b/tests/simple/task_func.v index fa50c1d5c..f6e902f63 100644 --- a/tests/simple/task_func.v +++ b/tests/simple/task_func.v @@ -120,3 +120,22 @@ module task_func_test04(input [7:0] in, output [7:0] out1, out2, out3, out4); assign out3 = test3(in); assign out4 = test4(in); endmodule + +// ------------------------------------------------------------------- + +// https://github.com/YosysHQ/yosys/issues/857 +module task_func_test05(data_in,data_out,clk); + output reg data_out; + input data_in; + input clk; + + task myTask; + output out; + input in; + out = in; + endtask + + always @(posedge clk) begin + myTask(data_out,data_in); + end +endmodule -- cgit v1.2.3 From a5f4b836376e1457847da4946c1e12d2d41dc4f4 Mon Sep 17 00:00:00 2001 From: Zachary Snow Date: Mon, 18 Mar 2019 20:34:21 -0400 Subject: fix local name resolution in prefix constructs --- tests/simple/generate.v | 56 +++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 56 insertions(+) (limited to 'tests') diff --git a/tests/simple/generate.v b/tests/simple/generate.v index 24eb4462c..3c55682cb 100644 --- a/tests/simple/generate.v +++ b/tests/simple/generate.v @@ -90,5 +90,61 @@ generate endcase end endgenerate +endmodule + +// ------------------------------------------ + +module gen_test4(a, b); + +input [3:0] a; +output [3:0] b; + +genvar i; +generate + for (i=0; i < 3; i=i+1) begin : foo + localparam PREV = i - 1; + wire temp; + if (i == 0) + assign temp = a[0]; + else + assign temp = foo[PREV].temp & a[i]; + assign b[i] = temp; + end +endgenerate +endmodule + +// ------------------------------------------ + +module gen_test5(input_bits, out); + +parameter WIDTH = 256; +parameter CHUNK = 4; +input [WIDTH-1:0] input_bits; +output out; + +genvar step, i, j; +generate + for (step = 1; step <= WIDTH; step = step * CHUNK) begin : steps + localparam PREV = step / CHUNK; + localparam DIM = WIDTH / step; + for (i = 0; i < DIM; i = i + 1) begin : outer + localparam LAST_START = i * CHUNK; + for (j = 0; j < CHUNK; j = j + 1) begin : inner + wire temp; + if (step == 1) + assign temp = input_bits[i]; + else if (j == 0) + assign temp = steps[PREV].outer[LAST_START].val; + else + assign temp + = steps[step].outer[i].inner[j-1].temp + & steps[PREV].outer[LAST_START + j].val; + end + wire val; + assign val = steps[step].outer[i].inner[CHUNK - 1].temp; + end + end +endgenerate +assign out = steps[WIDTH].outer[0].val; endmodule -- cgit v1.2.3 From 3b3b77291a21ed23a2763c79335501beebb10746 Mon Sep 17 00:00:00 2001 From: Niels Moseley Date: Sun, 24 Mar 2019 22:54:18 +0100 Subject: Updated the liberty parser to accept [A:B] ranges (AST has not been updated). Liberty parser now also accepts key : value pair lines that do not end in ';'. --- tests/liberty/.gitignore | 2 + tests/liberty/busdef.lib | 81 +++++++++ tests/liberty/normal.lib | 360 +++++++++++++++++++++++++++++++++++++++ tests/liberty/run-test.sh | 10 ++ tests/liberty/semicolmissing.lib | 72 ++++++++ tests/liberty/small.v | 16 ++ 6 files changed, 541 insertions(+) create mode 100644 tests/liberty/.gitignore create mode 100644 tests/liberty/busdef.lib create mode 100644 tests/liberty/normal.lib create mode 100755 tests/liberty/run-test.sh create mode 100644 tests/liberty/semicolmissing.lib create mode 100644 tests/liberty/small.v (limited to 'tests') diff --git a/tests/liberty/.gitignore b/tests/liberty/.gitignore new file mode 100644 index 000000000..e6ec49c4a --- /dev/null +++ b/tests/liberty/.gitignore @@ -0,0 +1,2 @@ +*.log +test.ys diff --git a/tests/liberty/busdef.lib b/tests/liberty/busdef.lib new file mode 100644 index 000000000..b5e3d50b9 --- /dev/null +++ b/tests/liberty/busdef.lib @@ -0,0 +1,81 @@ +/********************************************/ +/* */ +/* Supergate cell library for Bench marking */ +/* */ +/* Symbiotic EDA GmbH / Moseley Instruments */ +/* Niels A. Moseley */ +/* */ +/* Process: none */ +/* */ +/* Date : 02-11-2018 */ +/* Version: 1.0 */ +/* */ +/********************************************/ + +library(supergate) { + technology (cmos); + revision : 1.0; + + time_unit : "1ps"; + pulling_resistance_unit : "1kohm"; + voltage_unit : "1V"; + current_unit : "1uA"; + + capacitive_load_unit(1,ff); + + default_inout_pin_cap : 7.0; + default_input_pin_cap : 7.0; + default_output_pin_cap : 0.0; + default_fanout_load : 1.0; + + default_wire_load_capacitance : 0.1; + default_wire_load_resistance : 1.0e-3; + default_wire_load_area : 0.0; + + nom_process : 1.0; + nom_temperature : 25.0; + nom_voltage : 1.2; + + delay_model : generic_cmos; + + type( IO_bus_3_to_0 ) { + base_type : array ; + data_type : bit ; + bit_width : 4; + bit_from : 3 ; + bit_to : 0 ; + downto : true ; + } + + cell (SRAM) { + area : 1 ; + memory() { + type : ram; + address_width : 4; + word_width : 4; + } + pin(CE1) { + direction : input; + capacitance : 0.021; + max_transition : 1.024; + switch_pin : true; + } + bus(I1) { + bus_type : IO_bus_3_to_0 ; + direction : input; + pin (I1[3:0]) { + timing() { + related_pin : "CE1" ; + timing_type : setup_rising ; + rise_constraint (scalar) { + values("0.0507786"); + } + fall_constraint (scalar) { + values("0.0507786"); + } + } + } + } + } + +} /* end */ diff --git a/tests/liberty/normal.lib b/tests/liberty/normal.lib new file mode 100644 index 000000000..1474e2b59 --- /dev/null +++ b/tests/liberty/normal.lib @@ -0,0 +1,360 @@ +/********************************************/ +/* */ +/* Supergate cell library for Bench marking */ +/* */ +/* Symbiotic EDA GmbH / Moseley Instruments */ +/* Niels A. Moseley */ +/* */ +/* Process: none */ +/* */ +/* Date : 02-11-2018 */ +/* Version: 1.0 */ +/* */ +/********************************************/ + +library(supergate) { + technology (cmos); + revision : 1.0; + + time_unit : "1ps"; + pulling_resistance_unit : "1kohm"; + voltage_unit : "1V"; + current_unit : "1uA"; + + capacitive_load_unit(1,ff); + + default_inout_pin_cap : 7.0; + default_input_pin_cap : 7.0; + default_output_pin_cap : 0.0; + default_fanout_load : 1.0; + + default_wire_load_capacitance : 0.1; + default_wire_load_resistance : 1.0e-3; + default_wire_load_area : 0.0; + + nom_process : 1.0; + nom_temperature : 25.0; + nom_voltage : 1.2; + + delay_model : generic_cmos; + + /* Inverter */ + cell (inv) { + area : 1; + pin(A) { + direction : input; + } + + pin(Y) { + direction : output; + function : "A'"; + } + } + + /* tri-state inverter */ + cell (tri_inv) { + area : 4; + pin(A) { + direction : input; + } + pin(S) { + direction : input; + } + pin(Z) { + direction : output; + function : "A'"; + three_State : "S'"; + } + } + + cell (buffer) { + area : 5; + pin(A) { + direction : input; + } + pin(Y) { + direction : output; + function : "A"; + } + } + + /* 2-input NAND gate */ + cell (nand2) { + area : 3; + pin(A) { + direction : input; + } + pin(B) { + direction : input; + } + pin(Y) { + direction: output; + function : "(A * B)'"; + } + } + + /* 2-input NOR gate */ + cell (nor2) { + area : 3; + pin(A) { + direction : input; + } + pin(B) { + direction : input; + } + pin(Y) { + direction: output; + function : "(A + B)'"; + } + } + + /* 2-input XOR */ + cell (xor2) { + area : 6; + pin(A) { + direction : input; + } + pin(B) { + direction : input; + } + pin(Y) { + direction: output; + function : "(A *B') + (A' * B)"; + } + } + + /* 2-input inverting MUX */ + cell (imux2) { + area : 5; + pin(A) { + direction : input; + } + pin(B) { + direction : input; + } + pin(S) { + direction : input; + } + pin(Y) { + direction: output; + function : "( (A * S) + (B * S') )'"; + } + } + + /* D-type flip-flop with asynchronous reset and preset */ + cell (dff) + { + area : 6; + ff("IQ", "IQN") { + next_state : "D"; + clocked_on : "CLK"; + clear : "RESET"; + preset : "PRESET"; + clear_preset_var1 : L; + clear_preset_var2 : L; + } + pin(D) { + direction : input; + } + pin(CLK) { + direction : input; + } + pin(RESET) { + direction : input; + } + pin(PRESET) { + direction : input; + } + pin(Q) { + direction: output; + function : "IQ"; + timing() { + timing_type : rising_edge; + intrinsic_rise : 65; + intrinsic_fall : 65; + rise_resistance : 0; + fall_resistance : 0; + related_pin : "CLK"; + } + timing () { + timing_type : clear; + timing_sense : positive_unate; + intrinsic_fall : 75; + related_pin : "RESET"; + } + timing () { + timing_type : preset; + timing_sense : negative_unate; + intrinsic_rise : 75; + related_pin : "PRESET"; + } + } + pin(QN) { + direction: output; + function : "IQN"; + timing() { + timing_type : rising_edge; + intrinsic_rise : 65; + intrinsic_fall : 65; + rise_resistance : 0; + fall_resistance : 0; + related_pin : "CLK"; + } + timing () { + timing_type : preset; + timing_sense : negative_unate; + intrinsic_rise : 75; + related_pin : "RESET"; + } + timing () { + timing_type : clear; + timing_sense : positive_unate; + intrinsic_fall : 75; + related_pin : "PRESET"; + } + } + } + + /* Latch */ + cell(latch) { + area : 5; + latch ("IQ","IQN") { + enable : "G"; + data_in : "D"; + } + + pin(D) { + direction : input; + } + pin(G) { + direction : input; + } + + pin(Q) { + direction : output; + function : "IQ"; + internal_node : "Q"; + + timing() { + timing_type : rising_edge; + intrinsic_rise : 65; + intrinsic_fall : 65; + rise_resistance : 0; + fall_resistance : 0; + related_pin : "G"; + } + + timing() { + timing_sense : positive_unate; + intrinsic_rise : 65; + intrinsic_fall : 65; + rise_resistance : 0; + fall_resistance : 0; + related_pin : "D"; + } + } + + pin(QN) { + direction : output; + function : "IQN"; + internal_node : "QN"; + + timing() { + timing_type : rising_edge; + intrinsic_rise : 65; + intrinsic_fall : 65; + rise_resistance : 0; + fall_resistance : 0; + related_pin : "G"; + } + + timing() { + timing_sense : negative_unate; + intrinsic_rise : 65; + intrinsic_fall : 65; + rise_resistance : 0; + fall_resistance : 0; + related_pin : "D"; + } + } + } + + /* 3 input AND-OR-INVERT gate */ + cell (aoi211) { + area : 3; + pin(A) { + direction : input; + } + pin(B) { + direction : input; + } + pin(C) { + direction : input; + } + pin(Y) { + direction: output; + function : "((A * B) + C)'"; + } + } + + + /* 3 input OR-AND-INVERT gate */ + cell (oai211) { + area : 3; + pin(A) { + direction : input; + } + pin(B) { + direction : input; + } + pin(C) { + direction : input; + } + pin(Y) { + direction: output; + function : "((A + B) * C)'"; + } + } + + /* half adder */ + cell (halfadder) { + area : 5; + pin(A) { + direction : input; + } + pin(B) { + direction : input; + } + pin(C) { + direction : output; + function : "(A * B)"; + } + pin(Y) { + direction: output; + function : "(A *B') + (A' * B)"; + } + } + + /* full adder */ + cell (fulladder) { + area : 8; + pin(A) { + direction : input; + } + pin(B) { + direction : input; + } + pin(CI) { + direction : input; + } + pin(CO) { + direction : output; + function : "(((A * B)+(B * CI))+(CI * A))"; + } + pin(Y) { + direction: output; + function : "((A^B)^CI)"; + } + } + +} /* end */ diff --git a/tests/liberty/run-test.sh b/tests/liberty/run-test.sh new file mode 100755 index 000000000..7e2ed2370 --- /dev/null +++ b/tests/liberty/run-test.sh @@ -0,0 +1,10 @@ +#!/bin/bash +set -e + +for x in *.lib; do + echo "Running $x.." + echo "read_verilog small.v" > test.ys + echo "synth -top small" >> test.ys + echo "dfflibmap -liberty ${x}" >> test.ys + ../../yosys -ql ${x%.lib}.log -s test.ys +done diff --git a/tests/liberty/semicolmissing.lib b/tests/liberty/semicolmissing.lib new file mode 100644 index 000000000..f7c20750a --- /dev/null +++ b/tests/liberty/semicolmissing.lib @@ -0,0 +1,72 @@ +/********************************************/ +/* */ +/* Supergate cell library for Bench marking */ +/* */ +/* Symbiotic EDA GmbH / Moseley Instruments */ +/* Niels A. Moseley */ +/* */ +/* Process: none */ +/* */ +/* Date : 24-03-2019 */ +/* Version: 1.0 */ +/* Version: 1.1 - Removed semicolons in */ +/* full adder */ +/* */ +/********************************************/ + +/* + semi colon is missing in full-adder specification + some TSMC liberty files are formatted this way.. +*/ + +library(supergate) { + technology (cmos); + revision : 1.0; + + time_unit : "1ps"; + pulling_resistance_unit : "1kohm"; + voltage_unit : "1V"; + current_unit : "1uA"; + + capacitive_load_unit(1,ff); + + default_inout_pin_cap : 7.0; + default_input_pin_cap : 7.0; + default_output_pin_cap : 0.0; + default_fanout_load : 1.0; + + default_wire_load_capacitance : 0.1; + default_wire_load_resistance : 1.0e-3; + default_wire_load_area : 0.0; + + nom_process : 1.0; + nom_temperature : 25.0; + nom_voltage : 1.2; + + delay_model : generic_cmos; + + /* full adder */ + cell (fulladder) { + area : 8 + pin(A) { + direction : input + } + pin(B) { + direction : input + } + pin(CI) { + direction : input + } + pin(CO) { + direction : output + function : "(((A * B)+(B * CI))+(CI * A))" + } + pin(Y) { + direction: output + function : "((A^B)^CI)" + } + } + +} /* end */ + + diff --git a/tests/liberty/small.v b/tests/liberty/small.v new file mode 100644 index 000000000..bd94be4fc --- /dev/null +++ b/tests/liberty/small.v @@ -0,0 +1,16 @@ +/** small, meaningless design to test loading of liberty files */ + +module small +( + input clk, + output reg[7:0] count +); + +initial count = 0; + +always @ (posedge clk) +begin + count <= count + 1'b1; +end + +endmodule -- cgit v1.2.3 From c863796e9ff91c76f0f8679b6871b8ffcb75edb6 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Tue, 26 Mar 2019 14:17:46 +0100 Subject: Fix "verific -extnets" for more complex situations Signed-off-by: Clifford Wolf --- tests/sva/extnets.sv | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) create mode 100644 tests/sva/extnets.sv (limited to 'tests') diff --git a/tests/sva/extnets.sv b/tests/sva/extnets.sv new file mode 100644 index 000000000..47312de7a --- /dev/null +++ b/tests/sva/extnets.sv @@ -0,0 +1,22 @@ +module top(input i, output o); + A A(); + B B(); + assign A.i = i; + assign o = B.o; + always @* assert(o == i); +endmodule + +module A; + wire i, y; +`ifdef FAIL + assign B.x = i; +`else + assign B.x = !i; +`endif + assign y = !B.y; +endmodule + +module B; + wire x, y, o; + assign y = x, o = A.y; +endmodule -- cgit v1.2.3 From 487cb45b87ce1cbcc8c2b8127e37d85dd192dceb Mon Sep 17 00:00:00 2001 From: Niels Moseley Date: Wed, 27 Mar 2019 15:15:53 +0100 Subject: Liberty file parser now accepts superfluous ; --- tests/liberty/normal.lib | 3 +-- tests/liberty/processdefs.lib | 48 ++++++++++++++++++++++++++++++++++++++++++ tests/liberty/semicolextra.lib | 48 ++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 97 insertions(+), 2 deletions(-) create mode 100644 tests/liberty/processdefs.lib create mode 100644 tests/liberty/semicolextra.lib (limited to 'tests') diff --git a/tests/liberty/normal.lib b/tests/liberty/normal.lib index 1474e2b59..4621194dd 100644 --- a/tests/liberty/normal.lib +++ b/tests/liberty/normal.lib @@ -142,8 +142,7 @@ library(supergate) { } /* D-type flip-flop with asynchronous reset and preset */ - cell (dff) - { + cell (dff) { area : 6; ff("IQ", "IQN") { next_state : "D"; diff --git a/tests/liberty/processdefs.lib b/tests/liberty/processdefs.lib new file mode 100644 index 000000000..37a6bbaf8 --- /dev/null +++ b/tests/liberty/processdefs.lib @@ -0,0 +1,48 @@ +/********************************************/ +/* */ +/* Supergate cell library for Bench marking */ +/* */ +/* Symbiotic EDA GmbH / Moseley Instruments */ +/* Niels A. Moseley */ +/* */ +/* Process: none */ +/* */ +/* Date : 25-03-2019 */ +/* Version: 1.0 */ +/* */ +/********************************************/ + +library(processdefs) { + technology (cmos); + revision : 1.0; + + time_unit : "1ps"; + pulling_resistance_unit : "1kohm"; + voltage_unit : "1V"; + current_unit : "1uA"; + + capacitive_load_unit(1,ff); + + default_inout_pin_cap : 7.0; + default_input_pin_cap : 7.0; + default_output_pin_cap : 0.0; + default_fanout_load : 1.0; + + default_wire_load_capacitance : 0.1; + default_wire_load_resistance : 1.0e-3; + default_wire_load_area : 0.0; + + nom_process : 1.0; + nom_temperature : 25.0; + nom_voltage : 1.2; + + delay_model : generic_cmos; + + define_cell_area(bond_pads,pad_slots) + input_voltage(cmos) { + vil : 0.3 * VDD ; + vih : 0.7 * VDD ; + vimin : -0.5 ; + vimax : VDD + 0.5 ; + } +} diff --git a/tests/liberty/semicolextra.lib b/tests/liberty/semicolextra.lib new file mode 100644 index 000000000..0144fa3ac --- /dev/null +++ b/tests/liberty/semicolextra.lib @@ -0,0 +1,48 @@ +/* + + Test case for https://www.reddit.com/r/yosys/comments/b5texg/yosys_fails_to_parse_apparentlycorrect_liberty/ + + fall_constraint (SETUP_HOLD) formatting. + +*/ + +library(supergate) { + technology (cmos); + revision : 1.0; + + cell (DFF) { + cell_footprint : dff; + area : 50; + pin(D) { + direction : input; + capacitance : 0.002; + timing() { + related_pin : "CK"; + timing_type : setup_rising; + + fall_constraint (SETUP_HOLD) { values ("0.4000, 0.3000, 0.2000, 0.1000, 0.0000", \ + "0.4000, 0.3000, 0.2000, 0.1000, 0.000", \ + "0.5000, 0.4000, 0.3000, 0.2000, 0.0000", \ + "0.7000, 0.6000, 0.5000, 0.4000, 0.2000", \ + "1.0000, 1.0000, 0.9000, 0.8000, 0.6000"); } ; + } + } + + pin(CK) { + direction : input; + clock : true; + capacitance : 0.00290; + } + + ff(IQ,IQN) { + clocked_on : "CK"; + next_state : "D"; + } + pin(Q) { + direction : output; + capacitance : 0.003; + max_capacitance : 0.3; + } + cell_leakage_power : 0.3; + } +} -- cgit v1.2.3 From ee130f67cdd2ea40defa873e9a6511329850bf8e Mon Sep 17 00:00:00 2001 From: Niels Moseley Date: Wed, 27 Mar 2019 15:16:19 +0100 Subject: Liberty file parser now accepts superfluous ; --- tests/liberty/semicolextra.lib | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'tests') diff --git a/tests/liberty/semicolextra.lib b/tests/liberty/semicolextra.lib index 0144fa3ac..6a7fa77cc 100644 --- a/tests/liberty/semicolextra.lib +++ b/tests/liberty/semicolextra.lib @@ -24,7 +24,7 @@ library(supergate) { "0.4000, 0.3000, 0.2000, 0.1000, 0.000", \ "0.5000, 0.4000, 0.3000, 0.2000, 0.0000", \ "0.7000, 0.6000, 0.5000, 0.4000, 0.2000", \ - "1.0000, 1.0000, 0.9000, 0.8000, 0.6000"); } ; + "1.0000, 1.0000, 0.9000, 0.8000, 0.6000"); }; } } -- cgit v1.2.3