From 5bba9c3640971e25544f2053b31eb152c138c3af Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 27 Feb 2020 16:55:55 -0800
Subject: ast: fixes #1710; do not generate RTLIL for unreachable ternary

---
 tests/various/bug1710.ys | 30 ++++++++++++++++++++++++++++++
 1 file changed, 30 insertions(+)
 create mode 100644 tests/various/bug1710.ys

(limited to 'tests')

diff --git a/tests/various/bug1710.ys b/tests/various/bug1710.ys
new file mode 100644
index 000000000..c2ecf3c90
--- /dev/null
+++ b/tests/various/bug1710.ys
@@ -0,0 +1,30 @@
+logger -werror "out of bounds"
+read_verilog <<EOT
+module Example;
+
+    parameter FLAG = 1;
+    wire [3:0] inp;
+
+    reg out1;
+    initial out1 = FLAG ? &inp[2:0] : &inp[4:0];
+
+    reg out2;
+    initial
+        if (FLAG)
+            out2 = &inp[2:0];
+        else
+            out2 = &inp[4:0];
+
+    wire out3;
+    assign out3 = FLAG ? &inp[2:0] : &inp[4:0];
+
+    wire out4;
+    generate
+        if (FLAG)
+            assign out4 = &inp[2:0];
+        else
+            assign out4 = &inp[4:0];
+    endgenerate
+
+endmodule
+EOT
-- 
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