From a09b260c015457ad9a9cadbe0931b411d748420d Mon Sep 17 00:00:00 2001
From: Alberto Gonzalez <boqwxp@airmail.cc>
Date: Mon, 16 Mar 2020 06:44:21 +0000
Subject: Add test for `exec` command.

---
 tests/various/exec.ys | 6 ++++++
 1 file changed, 6 insertions(+)
 create mode 100644 tests/various/exec.ys

(limited to 'tests')

diff --git a/tests/various/exec.ys b/tests/various/exec.ys
new file mode 100644
index 000000000..0eec00719
--- /dev/null
+++ b/tests/various/exec.ys
@@ -0,0 +1,6 @@
+exec -expect-return 0 -- exit 0
+exec -expect-return 27 -- exit 27
+exec -expect-stdout nana -expect-stdout api -not-expect-stdout giraffe -- echo "bananapie"
+
+logger -expect error "stdout did have a line" 1
+exec -not-expect-stdout giraffe -- echo "giraffe"
-- 
cgit v1.2.3


From 9f30d7f843f224942dad7ce0ef90d3a99ac05036 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Tue, 10 Mar 2020 16:13:44 -0700
Subject: opt_merge: speedup

---
 tests/opt/opt_merge_init.ys | 28 ++++++++++++++++++++
 tests/opt/opt_merge_keep.ys | 64 +++++++++++++++++++++++++++++++++++++++++++++
 2 files changed, 92 insertions(+)
 create mode 100644 tests/opt/opt_merge_keep.ys

(limited to 'tests')

diff --git a/tests/opt/opt_merge_init.ys b/tests/opt/opt_merge_init.ys
index a29c29df6..0176f09c7 100644
--- a/tests/opt/opt_merge_init.ys
+++ b/tests/opt/opt_merge_init.ys
@@ -20,6 +20,7 @@ endmodule
 EOT
 
 opt_merge
+select -assert-count 1 t:$dff
 select -assert-count 1 a:init=1'0
 
 
@@ -46,4 +47,31 @@ endmodule
 EOT
 
 opt_merge
+select -assert-count 1 t:$dff
 select -assert-count 1 a:init=2'bx1
+
+
+design -reset
+read_verilog -icells <<EOT
+module top(input clk, i, (* init = 1'b0 *) output o, /* NB: no init here! */ output p);
+  \$dff  #(
+    .CLK_POLARITY(1'h1),
+    .WIDTH(32'd1)
+  ) ffo  (
+    .CLK(clk),
+    .D(i),
+    .Q(o)
+  );
+  \$dff  #(
+    .CLK_POLARITY(1'h1),
+    .WIDTH(32'd1)
+  ) ffp  (
+    .CLK(clk),
+    .D(i),
+    .Q(p)
+  );
+endmodule
+EOT
+
+opt_merge
+select -assert-count 2 t:$dff
diff --git a/tests/opt/opt_merge_keep.ys b/tests/opt/opt_merge_keep.ys
new file mode 100644
index 000000000..2a9202901
--- /dev/null
+++ b/tests/opt/opt_merge_keep.ys
@@ -0,0 +1,64 @@
+read_verilog -icells <<EOT
+module top(input clk, i, output o, p);
+  (* keep *)
+  \$_DFF_P_ ffo  (
+    .C(clk),
+    .D(i),
+    .Q(o)
+  );
+  \$_DFF_P_ ffp  (
+    .C(clk),
+    .D(i),
+    .Q(p)
+  );
+endmodule
+EOT
+
+opt_merge
+select -assert-count 1 t:$_DFF_P_
+select -assert-count 1 a:keep
+
+
+design -reset
+read_verilog -icells <<EOT
+module top(input clk, i, output o, p);
+  \$_DFF_P_ ffo  (
+    .C(clk),
+    .D(i),
+    .Q(o)
+  );
+  (* keep *)
+  \$_DFF_P_ ffp  (
+    .C(clk),
+    .D(i),
+    .Q(p)
+  );
+endmodule
+EOT
+
+opt_merge
+select -assert-count 1 t:$_DFF_P_
+select -assert-count 1 a:keep
+
+
+design -reset
+read_verilog -icells <<EOT
+module top(input clk, i, output o, p);
+  (* keep *)
+  \$_DFF_P_ ffo  (
+    .C(clk),
+    .D(i),
+    .Q(o)
+  );
+  (* keep *)
+  \$_DFF_P_ ffp  (
+    .C(clk),
+    .D(i),
+    .Q(p)
+  );
+endmodule
+EOT
+
+opt_merge
+select -assert-count 2 t:$_DFF_P_
+select -assert-count 2 a:keep
-- 
cgit v1.2.3


From e91368a5f423b0e4188c13512816e0ecaf09a0d9 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Marcin=20Ko=C5=9Bcielnicki?= <mwk@0x04.net>
Date: Wed, 18 Mar 2020 20:58:36 +0100
Subject: fsm_extract: Initialize celltypes with full design.

Fixes #1781.
---
 tests/various/bug1781.ys | 33 +++++++++++++++++++++++++++++++++
 1 file changed, 33 insertions(+)
 create mode 100644 tests/various/bug1781.ys

(limited to 'tests')

diff --git a/tests/various/bug1781.ys b/tests/various/bug1781.ys
new file mode 100644
index 000000000..60dcc0830
--- /dev/null
+++ b/tests/various/bug1781.ys
@@ -0,0 +1,33 @@
+read_verilog <<EOT
+
+module top(input clk, input rst);
+
+reg [1:0] state;
+
+always @(posedge clk, posedge rst) begin
+	if (rst)
+		state <= 0;
+	else
+		case (state)
+			2'b00: state <= 2'b01;
+			2'b01: state <= 2'b10;
+			2'b10: state <= 2'b00;
+		endcase
+end
+
+sub sub_i(.i(state == 0));
+
+endmodule
+
+
+(* blackbox, keep *)
+module sub(input i);
+endmodule
+
+EOT
+
+proc
+fsm
+
+# Make sure there is a driver
+select -assert-any t:sub %ci %a w:* %i %ci c:* %i
-- 
cgit v1.2.3


From 5e2562f1a2e4cfa53c80f9ca6200aecc4cc6fd9b Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 19 Mar 2020 14:57:10 -0700
Subject: opt_expr: add $alu tests

---
 tests/opt/opt_expr_alu.ys | 63 +++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 63 insertions(+)
 create mode 100644 tests/opt/opt_expr_alu.ys

(limited to 'tests')

diff --git a/tests/opt/opt_expr_alu.ys b/tests/opt/opt_expr_alu.ys
new file mode 100644
index 000000000..a3361ca43
--- /dev/null
+++ b/tests/opt/opt_expr_alu.ys
@@ -0,0 +1,63 @@
+read_verilog <<EOT
+module test(input a, output [1:0] y);
+assign y = {a,1'b0} + 1'b1;
+endmodule
+EOT
+
+alumacc
+equiv_opt opt_expr -fine
+design -load postopt
+select -assert-count 1 t:$pos
+select -assert-count none t:$pos t:* %D
+
+
+design -reset
+read_verilog <<EOT
+module test(input a, output [1:0] y);
+assign y = {a,1'b1} + 1'b1;
+endmodule
+EOT
+
+alumacc
+select -assert-count 1 t:$alu
+select -assert-count none t:$alu t:* %D
+
+
+design -reset
+read_verilog <<EOT
+module test(input a, output [1:0] y);
+assign y = {a,1'b1} - 1'b1;
+endmodule
+EOT
+
+equiv_opt opt_expr -fine
+design -load postopt
+select -assert-count 1 t:$pos
+select -assert-count none t:$pos t:* %D
+
+
+design -reset
+read_verilog <<EOT
+module test(input a, output [3:0] y);
+assign y = {a,3'b101} - 1'b1;
+endmodule
+EOT
+
+equiv_opt opt_expr -fine
+design -load postopt
+select -assert-count 1 t:$pos
+select -assert-count none t:$pos t:* %D
+
+
+design -reset
+read_verilog <<EOT
+module test(input a, output [3:0] y);
+assign y = {a,3'b101} - 1'b1;
+endmodule
+EOT
+
+alumacc
+equiv_opt opt_expr -fine
+design -load postopt
+select -assert-count 1 t:$pos
+select -assert-count none t:$pos t:* %D
-- 
cgit v1.2.3


From 81ca776ea44e126b3946fcdd076c2d2e4d2ab34d Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 19 Mar 2020 16:59:11 -0700
Subject: opt_expr: add $xor/$xnor/$_XOR_/$_XNOR_ tests

---
 tests/opt/opt_expr_xor.ys | 40 ++++++++++++++++++++++++++++++++++++++++
 1 file changed, 40 insertions(+)
 create mode 100644 tests/opt/opt_expr_xor.ys

(limited to 'tests')

diff --git a/tests/opt/opt_expr_xor.ys b/tests/opt/opt_expr_xor.ys
new file mode 100644
index 000000000..a458c9a27
--- /dev/null
+++ b/tests/opt/opt_expr_xor.ys
@@ -0,0 +1,40 @@
+read_verilog <<EOT
+module top(input a, output [3:0] y);
+assign y[0] = a^1'b0;
+assign y[1] = 1'b1^a;
+assign y[2] = a~^1'b0;
+assign y[3] = 1'b1^~a;
+endmodule
+EOT
+design -save read
+select -assert-count 2 t:$xor
+select -assert-count 2 t:$xnor
+
+equiv_opt opt_expr
+design -load postopt
+select -assert-none t:$xor
+select -assert-none t:$xnor
+select -assert-count 2 t:$_NOT_
+
+
+design -load read
+simplemap
+equiv_opt opt_expr
+design -load postopt
+select -assert-none t:$_XOR_
+select -assert-none t:$_XNOR_ # NB: simplemap does $xnor -> $_XOR_+$_NOT_
+select -assert-count 3 t:$_NOT_
+
+
+design -reset
+read_verilog -icells <<EOT
+module top(input a, output [1:0] y);
+$_XNOR_ u0(.A(a), .B(1'b0), .Y(y[0]));
+$_XNOR_ u1(.A(1'b1), .B(a), .Y(y[1]));
+endmodule
+EOT
+select -assert-count 2 t:$_XNOR_
+equiv_opt opt_expr
+design -load postopt
+select -assert-none t:$_XNOR_ # NB: simplemap does $xnor -> $_XOR_+$_NOT_
+select -assert-count 1 t:$_NOT_
-- 
cgit v1.2.3


From 317c18fc6fe22f6b5ad4f0ac82f6abbcfaec2bca Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 20 Mar 2020 11:25:17 -0700
Subject: Simplify breaking tests/arch/*/fsm.ys tests

---
 tests/arch/anlogic/fsm.ys | 5 +----
 tests/arch/efinix/fsm.ys  | 5 ++---
 2 files changed, 3 insertions(+), 7 deletions(-)

(limited to 'tests')

diff --git a/tests/arch/anlogic/fsm.ys b/tests/arch/anlogic/fsm.ys
index 0bcc4e011..eb94177ad 100644
--- a/tests/arch/anlogic/fsm.ys
+++ b/tests/arch/anlogic/fsm.ys
@@ -10,9 +10,6 @@ sat -verify -prove-asserts -show-public -set-at 1 in_reset 1 -seq 20 -prove-skip
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd fsm # Constrain all select calls below inside the top module
 
-select -assert-count 1 t:AL_MAP_LUT2
-select -assert-count 5 t:AL_MAP_LUT5
-select -assert-count 1 t:AL_MAP_LUT6
 select -assert-count 6 t:AL_MAP_SEQ
 
-select -assert-none t:AL_MAP_LUT2 t:AL_MAP_LUT5 t:AL_MAP_LUT6 t:AL_MAP_SEQ %% t:* %D
+select -assert-none t:AL_MAP_LUT* t:AL_MAP_SEQ %% t:* %D
diff --git a/tests/arch/efinix/fsm.ys b/tests/arch/efinix/fsm.ys
index a2db2ad98..aef720d46 100644
--- a/tests/arch/efinix/fsm.ys
+++ b/tests/arch/efinix/fsm.ys
@@ -10,7 +10,6 @@ sat -verify -prove-asserts -show-public -set-at 1 in_reset 1 -seq 20 -prove-skip
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd fsm # Constrain all select calls below inside the top module
 
-select -assert-count 1  t:EFX_GBUFCE
-select -assert-count 6  t:EFX_FF
-select -assert-count 15 t:EFX_LUT4
+select -assert-count 1 t:EFX_GBUFCE
+select -assert-count 6 t:EFX_FF
 select -assert-none t:EFX_GBUFCE t:EFX_FF t:EFX_LUT4 %% t:* %D
-- 
cgit v1.2.3


From fa77fb857b42b32f3d518da8a590c406ddc8eee9 Mon Sep 17 00:00:00 2001
From: David Shah <dave@ds0.me>
Date: Fri, 20 Mar 2020 20:35:28 +0000
Subject: Add test for abc9+mince issue

Signed-off-by: David Shah <dave@ds0.me>
---
 tests/various/ice40_mince_abc9.ys | 17 +++++++++++++++++
 1 file changed, 17 insertions(+)
 create mode 100644 tests/various/ice40_mince_abc9.ys

(limited to 'tests')

diff --git a/tests/various/ice40_mince_abc9.ys b/tests/various/ice40_mince_abc9.ys
new file mode 100644
index 000000000..408e16f05
--- /dev/null
+++ b/tests/various/ice40_mince_abc9.ys
@@ -0,0 +1,17 @@
+read_verilog <<EOT
+
+module top(input clk, ce, input [2:0] a, b, output reg [2:0] q);
+
+	reg [2:0] aa, bb;
+
+	always @(posedge clk) begin
+		if (ce) begin
+			aa <= a;
+		end
+		bb <= b;
+		q <= aa + bb;
+	end
+endmodule
+EOT
+
+synth_ice40 -abc9 -dffe_min_ce_use 4
-- 
cgit v1.2.3


From 6274f0b075abba2af9193e2245eacee5cc66e4c5 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 20 Mar 2020 14:38:50 -0700
Subject: opt_expr: add failing $xnor test

---
 tests/opt/opt_expr_xor.ys | 14 +++++++++++++-
 1 file changed, 13 insertions(+), 1 deletion(-)

(limited to 'tests')

diff --git a/tests/opt/opt_expr_xor.ys b/tests/opt/opt_expr_xor.ys
index a458c9a27..21439fd53 100644
--- a/tests/opt/opt_expr_xor.ys
+++ b/tests/opt/opt_expr_xor.ys
@@ -14,7 +14,7 @@ equiv_opt opt_expr
 design -load postopt
 select -assert-none t:$xor
 select -assert-none t:$xnor
-select -assert-count 2 t:$_NOT_
+select -assert-count 2 t:$not
 
 
 design -load read
@@ -38,3 +38,15 @@ equiv_opt opt_expr
 design -load postopt
 select -assert-none t:$_XNOR_ # NB: simplemap does $xnor -> $_XOR_+$_NOT_
 select -assert-count 1 t:$_NOT_
+
+
+design -reset
+read_verilog <<EOT
+module top(input a, output [1:0] w, x, y, z);
+assign w = a^1'b0;
+assign x = a^1'b1;
+assign y = a~^1'b0;
+assign z = a~^1'b1;
+endmodule
+EOT
+equiv_opt opt_expr
-- 
cgit v1.2.3


From 6d8d6b402fafd31ef555415b9f4b9e17941337ea Mon Sep 17 00:00:00 2001
From: Peter <peter@crozier.com>
Date: Thu, 27 Feb 2020 16:59:19 +0000
Subject: Revert typedef tests to standard grammar.

---
 tests/svtypes/enum_simple.sv      |  5 +++--
 tests/svtypes/typedef_memory.sv   |  2 +-
 tests/svtypes/typedef_memory_2.sv |  2 +-
 tests/svtypes/typedef_package.sv  |  4 ++--
 tests/svtypes/typedef_param.sv    | 10 +++++-----
 tests/svtypes/typedef_scopes.sv   | 18 +++++++++---------
 tests/svtypes/typedef_simple.sv   | 10 +++++-----
 7 files changed, 26 insertions(+), 25 deletions(-)

(limited to 'tests')

diff --git a/tests/svtypes/enum_simple.sv b/tests/svtypes/enum_simple.sv
index ccaf50da0..4e4d5871c 100644
--- a/tests/svtypes/enum_simple.sv
+++ b/tests/svtypes/enum_simple.sv
@@ -5,8 +5,9 @@ module enum_simple(input clk, input rst);
 	typedef enum logic [1:0] {
 		ts0, ts1, ts2, ts3
 	} states_t;
-	(states_t) state;
-	(states_t) enum_const = ts1;
+	states_t state;
+	(states_t) state1;
+	states_t enum_const = ts1;
 
 	always @(posedge clk) begin
 		if (rst) begin
diff --git a/tests/svtypes/typedef_memory.sv b/tests/svtypes/typedef_memory.sv
index 577e484ad..37e63c1d0 100644
--- a/tests/svtypes/typedef_memory.sv
+++ b/tests/svtypes/typedef_memory.sv
@@ -1,7 +1,7 @@
 module top(input [3:0] addr, wdata, input clk, wen, output reg [3:0] rdata);
 	typedef logic [3:0] ram16x4_t[0:15];
 
-	(ram16x4_t) mem;
+	ram16x4_t mem;
 
 	always @(posedge clk) begin
 		if (wen) mem[addr] <= wdata;
diff --git a/tests/svtypes/typedef_memory_2.sv b/tests/svtypes/typedef_memory_2.sv
index f3089bf55..6d65131db 100644
--- a/tests/svtypes/typedef_memory_2.sv
+++ b/tests/svtypes/typedef_memory_2.sv
@@ -1,7 +1,7 @@
 module top(input [3:0] addr, wdata, input clk, wen, output reg [3:0] rdata);
 	typedef logic [3:0] nibble;
 
-	(nibble) mem[0:15];
+	nibble mem[0:15];
 
 	always @(posedge clk) begin
 		if (wen) mem[addr] <= wdata;
diff --git a/tests/svtypes/typedef_package.sv b/tests/svtypes/typedef_package.sv
index b766f10cf..57a78c53a 100644
--- a/tests/svtypes/typedef_package.sv
+++ b/tests/svtypes/typedef_package.sv
@@ -5,8 +5,8 @@ endpackage
 
 module top;
 
-	(* keep *) (pkg::uint8_t) a = 8'hAA;
-	(* keep *) (pkg::enum8_t) b_enum = pkg::bb;
+	(* keep *) pkg::uint8_t a = 8'hAA;
+	(* keep *) pkg::enum8_t b_enum = pkg::bb;
 
 	always @* assert(a == 8'hAA);
 	always @* assert(b_enum == 8'hBB);
diff --git a/tests/svtypes/typedef_param.sv b/tests/svtypes/typedef_param.sv
index ddbd471e0..d838dd828 100644
--- a/tests/svtypes/typedef_param.sv
+++ b/tests/svtypes/typedef_param.sv
@@ -6,12 +6,12 @@ module top;
 	typedef logic [1:0] uint2_t;
 	typedef logic signed [3:0] int4_t;
 	typedef logic signed [7:0] int8_t;
-	typedef (int8_t) char_t;
+	typedef int8_t char_t;
 
-	parameter (uint2_t) int2 = 2'b10;
-	localparam (int4_t) int4 = -1;
-	localparam (int8_t) int8 = int4;
-	localparam (char_t) ch = int8;
+	parameter uint2_t int2 = 2'b10;
+	localparam int4_t int4 = -1;
+	localparam int8_t int8 = int4;
+	localparam char_t ch = int8;
 
 
 	`STATIC_ASSERT(int2 == 2'b10);
diff --git a/tests/svtypes/typedef_scopes.sv b/tests/svtypes/typedef_scopes.sv
index 1c45c7057..d41a58147 100644
--- a/tests/svtypes/typedef_scopes.sv
+++ b/tests/svtypes/typedef_scopes.sv
@@ -4,30 +4,30 @@ typedef enum logic {s0, s1} outer_enum_t;
 
 module top;
 
-	(outer_uint4_t) u4_i = 8'hA5;
-	(outer_enum_t) enum4_i = s0;
+	outer_uint4_t u4_i = 8'hA5;
+	outer_enum_t enum4_i = s0;
 	always @(*) assert(u4_i == 4'h5);
 	always @(*) assert(enum4_i == 1'b0);
 
 	typedef logic [3:0] inner_type;
 	typedef enum logic [2:0] {s2=2, s3, s4} inner_enum_t;
-	(inner_type) inner_i1 = 8'h5A;
-	(inner_enum_t) inner_enum1 = s3;
+	inner_type inner_i1 = 8'h5A;
+	inner_enum_t inner_enum1 = s3;
 	always @(*) assert(inner_i1 == 4'hA);
 	always @(*) assert(inner_enum1 == 3'h3);
 
 	if (1) begin: genblock
 		typedef logic [7:0] inner_type;
-		parameter (inner_type) inner_const = 8'hA5;
+		parameter inner_type inner_const = 8'hA5;
  		typedef enum logic [2:0] {s5=5, s6, s7} inner_enum_t;
-		(inner_type) inner_gb_i = inner_const; //8'hA5;
- 		(inner_enum_t) inner_gb_enum1 = s7;
+		inner_type inner_gb_i = inner_const; //8'hA5;
+ 		inner_enum_t inner_gb_enum1 = s7;
 		always @(*) assert(inner_gb_i == 8'hA5);
  		always @(*) assert(inner_gb_enum1 == 3'h7);
 	end
 
-	(inner_type) inner_i2 = 8'h42;
-	(inner_enum_t) inner_enum2 = s4;
+	inner_type inner_i2 = 8'h42;
+	inner_enum_t inner_enum2 = s4;
 	always @(*) assert(inner_i2 == 4'h2);
 	always @(*) assert(inner_enum2 == 3'h4);
 
diff --git a/tests/svtypes/typedef_simple.sv b/tests/svtypes/typedef_simple.sv
index 7e760dee4..8f89910e5 100644
--- a/tests/svtypes/typedef_simple.sv
+++ b/tests/svtypes/typedef_simple.sv
@@ -3,12 +3,12 @@ module top;
 	typedef logic [1:0] uint2_t;
 	typedef logic signed [3:0] int4_t;
 	typedef logic signed [7:0] int8_t;
-	typedef (int8_t) char_t;
+	typedef int8_t char_t;
 
-	(* keep *) (uint2_t) int2 = 2'b10;
-	(* keep *) (int4_t) int4 = -1;
-	(* keep *) (int8_t) int8 = int4;
-	(* keep *) (char_t) ch = int8;
+	(* keep *) uint2_t int2 = 2'b10;
+	(* keep *) int4_t int4 = -1;
+	(* keep *) int8_t int8 = int4;
+	(* keep *) char_t ch = int8;
 
 
 	always @* assert(int2 == 2'b10);
-- 
cgit v1.2.3


From c2bf11e42a6de3f028ad0b484eb24b70618c6fc7 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Marcin=20Ko=C5=9Bcielnicki?= <mwk@0x04.net>
Date: Mon, 23 Mar 2020 11:07:03 +0100
Subject: techmap: Fix cell names with _TECHMAP_REPLACE_.*

Fixes #1804.
---
 tests/techmap/techmap_replace.ys | 18 ++++++++++++++++++
 1 file changed, 18 insertions(+)

(limited to 'tests')

diff --git a/tests/techmap/techmap_replace.ys b/tests/techmap/techmap_replace.ys
index c2f42d50b..8403586bd 100644
--- a/tests/techmap/techmap_replace.ys
+++ b/tests/techmap/techmap_replace.ys
@@ -16,3 +16,21 @@ EOT
 techmap -map %techmap
 select -assert-any w:s0.asdf
 select -assert-any c:s0.blah
+
+read_verilog <<EOT
+module sub(input i, output o, input j);
+wire _TECHMAP_REPLACE_.asdf = i ;
+barfoo _TECHMAP_REPLACE_.blah (i, o, j);
+endmodule
+EOT
+design -stash techmap
+
+read_verilog <<EOT
+module top(input i, output o);
+sub s0(i, o);
+endmodule
+EOT
+
+techmap -map %techmap
+select -assert-any w:s0.asdf
+select -assert-any c:s0.blah
-- 
cgit v1.2.3


From 1b333d49ef0144d6f440b1c6cc57a6a6e2d4a1de Mon Sep 17 00:00:00 2001
From: Alberto Gonzalez <boqwxp@airmail.cc>
Date: Mon, 23 Mar 2020 06:13:48 +0000
Subject: Add tests for `select` command warnings.

---
 tests/select/no_warn_prefixed_empty_select_arg.ys | 3 +++
 tests/select/run-test.sh                          | 6 ++++++
 tests/select/warn_empty_select_arg.ys             | 3 +++
 3 files changed, 12 insertions(+)
 create mode 100644 tests/select/no_warn_prefixed_empty_select_arg.ys
 create mode 100755 tests/select/run-test.sh
 create mode 100644 tests/select/warn_empty_select_arg.ys

(limited to 'tests')

diff --git a/tests/select/no_warn_prefixed_empty_select_arg.ys b/tests/select/no_warn_prefixed_empty_select_arg.ys
new file mode 100644
index 000000000..617e0d63e
--- /dev/null
+++ b/tests/select/no_warn_prefixed_empty_select_arg.ys
@@ -0,0 +1,3 @@
+logger -expect-no-warnings
+select n:foo/bar*
+select t:$assert
diff --git a/tests/select/run-test.sh b/tests/select/run-test.sh
new file mode 100755
index 000000000..44ce7e674
--- /dev/null
+++ b/tests/select/run-test.sh
@@ -0,0 +1,6 @@
+#!/bin/bash
+set -e
+for x in *.ys; do
+  echo "Running $x.."
+  ../../yosys -ql ${x%.ys}.log $x
+done
diff --git a/tests/select/warn_empty_select_arg.ys b/tests/select/warn_empty_select_arg.ys
new file mode 100644
index 000000000..55aca8eb6
--- /dev/null
+++ b/tests/select/warn_empty_select_arg.ys
@@ -0,0 +1,3 @@
+logger -expect warning "did not match any module." 1
+logger -expect warning "did not match any object." 1
+select foo/bar
-- 
cgit v1.2.3


From ca4e5dd56e1f007fa13c791ab179236103187c6f Mon Sep 17 00:00:00 2001
From: Alberto Gonzalez <boqwxp@airmail.cc>
Date: Mon, 23 Mar 2020 06:31:41 +0000
Subject: Suppress warnings for empty `select` arguments when `-count` or
 `-assert-*` options are set.

---
 tests/select/no_warn_assert.ys | 2 ++
 1 file changed, 2 insertions(+)
 create mode 100644 tests/select/no_warn_assert.ys

(limited to 'tests')

diff --git a/tests/select/no_warn_assert.ys b/tests/select/no_warn_assert.ys
new file mode 100644
index 000000000..889315826
--- /dev/null
+++ b/tests/select/no_warn_assert.ys
@@ -0,0 +1,2 @@
+logger -expect-no-warnings
+select -assert-count 0 top/t:ff4 top/w:d0 %co:+[d] %i
-- 
cgit v1.2.3


From 0da65d498b9f18ce0c09eedc19f16db2390e6dcb Mon Sep 17 00:00:00 2001
From: Alberto Gonzalez <boqwxp@airmail.cc>
Date: Mon, 23 Mar 2020 17:50:11 +0000
Subject: Do not warn on empty selection with prefixed `arg_memb`.

Co-Authored-By: N. Engelhardt <nak@symbioticeda.com>
---
 tests/select/no_warn_prefixed_arg_memb.ys | 5 +++++
 1 file changed, 5 insertions(+)
 create mode 100644 tests/select/no_warn_prefixed_arg_memb.ys

(limited to 'tests')

diff --git a/tests/select/no_warn_prefixed_arg_memb.ys b/tests/select/no_warn_prefixed_arg_memb.ys
new file mode 100644
index 000000000..596a6ed70
--- /dev/null
+++ b/tests/select/no_warn_prefixed_arg_memb.ys
@@ -0,0 +1,5 @@
+logger -expect-no-warnings
+read_verilog ../../examples/igloo2/example.v
+hierarchy
+proc
+select example/t:$add
-- 
cgit v1.2.3


From ecc22f7fedfa639482dbc55a05709da85116a60f Mon Sep 17 00:00:00 2001
From: Peter Crozier <peter@crozier.com>
Date: Mon, 23 Mar 2020 20:07:22 +0000
Subject: Support module/package/interface/block scope for typedef names.

---
 tests/svtypes/typedef_scopes.sv | 7 +++++++
 1 file changed, 7 insertions(+)

(limited to 'tests')

diff --git a/tests/svtypes/typedef_scopes.sv b/tests/svtypes/typedef_scopes.sv
index d41a58147..5507d84f2 100644
--- a/tests/svtypes/typedef_scopes.sv
+++ b/tests/svtypes/typedef_scopes.sv
@@ -31,5 +31,12 @@ module top;
 	always @(*) assert(inner_i2 == 4'h2);
 	always @(*) assert(inner_enum2 == 3'h4);
 
+endmodule
+
+typedef logic[7:0]  between_t;
 
+module other;
+	between_t a = 8'h42;
+	always @(*) assert(a == 8'h42);
 endmodule
+
-- 
cgit v1.2.3


From 044ca9dde409e3c91542fe95513d6641110f8462 Mon Sep 17 00:00:00 2001
From: Rupert Swarbrick <rswarbrick@lowrisc.org>
Date: Tue, 17 Mar 2020 09:34:31 +0000
Subject: Add support for SystemVerilog-style `define to Verilog frontend

This patch should support things like

  `define foo(a, b = 3, c)   a+b+c

  `foo(1, ,2)

which will evaluate to 1+3+2. It also spots mistakes like

  `foo(1)

(the 3rd argument doesn't have a default value, so a call site is
required to set it).

Most of the patch is a simple parser for the format in preproc.cc, but
I've also taken the opportunity to wrap up the "name -> definition"
map in a type, rather than use multiple std::map's.

Since this type needs to be visible to code that touches defines, I've
pulled it (and the frontend_verilog_preproc declaration) out into a
new file at frontends/verilog/preproc.h and included that where
necessary.

Finally, the patch adds a few tests in tests/various to check that we
are parsing everything correctly.
---
 tests/various/sv_defines.ys          | 33 +++++++++++++++++++++++++++++++++
 tests/various/sv_defines_dup.ys      |  5 +++++
 tests/various/sv_defines_mismatch.ys |  5 +++++
 tests/various/sv_defines_too_few.ys  |  7 +++++++
 4 files changed, 50 insertions(+)
 create mode 100644 tests/various/sv_defines.ys
 create mode 100644 tests/various/sv_defines_dup.ys
 create mode 100644 tests/various/sv_defines_mismatch.ys
 create mode 100644 tests/various/sv_defines_too_few.ys

(limited to 'tests')

diff --git a/tests/various/sv_defines.ys b/tests/various/sv_defines.ys
new file mode 100644
index 000000000..8e70ee0ee
--- /dev/null
+++ b/tests/various/sv_defines.ys
@@ -0,0 +1,33 @@
+# Check that basic macro expansions do what you'd expect
+
+read_verilog <<EOT
+`define empty_arglist()                      123
+`define one_arg(x)                           123+x
+`define opt_arg(x = 1)                       123+x
+`define two_args(x, y = (1+23))              x+y
+`define nested_comma(x = {31'b0, 1'b1}, y=3) x+y
+
+module top;
+  localparam a = `empty_arglist();
+  localparam b = `one_arg(10);
+  localparam c = `opt_arg(10);
+  localparam d = `opt_arg();
+  localparam e = `two_args(1,2);
+  localparam f = `two_args(1);
+  localparam g = `nested_comma(1, 2);
+  localparam h = `nested_comma({31'b0, (1'b0)});
+  localparam i = `nested_comma(, 1);
+
+  generate
+    if (a != 123) $error("a bad");
+    if (b != 133) $error("b bad");
+    if (c != 133) $error("c bad");
+    if (d != 124) $error("d bad");
+    if (e != 3)   $error("e bad");
+    if (f != 25)  $error("f bad");
+    if (g != 3)   $error("g bad");
+    if (h != 3)   $error("h bad");
+    if (i != 2)   $error("i bad");
+  endgenerate
+endmodule
+EOT
diff --git a/tests/various/sv_defines_dup.ys b/tests/various/sv_defines_dup.ys
new file mode 100644
index 000000000..38418ba8f
--- /dev/null
+++ b/tests/various/sv_defines_dup.ys
@@ -0,0 +1,5 @@
+# Check for duplicate arguments
+logger -expect error "Duplicate macro arguments with name `x'" 1
+read_verilog <<EOT
+`define duplicate_arg(x, x)
+EOT
diff --git a/tests/various/sv_defines_mismatch.ys b/tests/various/sv_defines_mismatch.ys
new file mode 100644
index 000000000..ab6e899de
--- /dev/null
+++ b/tests/various/sv_defines_mismatch.ys
@@ -0,0 +1,5 @@
+# Check that we spot mismatched brackets
+logger -expect error "Mismatched brackets in macro argument: \[ and }." 1
+read_verilog <<EOT
+`define foo(x=[1,2})
+EOT
diff --git a/tests/various/sv_defines_too_few.ys b/tests/various/sv_defines_too_few.ys
new file mode 100644
index 000000000..295884809
--- /dev/null
+++ b/tests/various/sv_defines_too_few.ys
@@ -0,0 +1,7 @@
+# Check that we don't allow passing too few arguments (and, while we're at it, check that passing "no"
+# arguments actually passes 1 empty argument).
+logger -expect error "Cannot expand macro `foo by giving only 1 argument \(argument 2 has no default\)." 1
+read_verilog <<EOT
+`define foo(x=1, y)
+`foo()
+EOT
-- 
cgit v1.2.3


From 3df66027e0de11913aac4b29d6b4ab79550bfb28 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Tue, 31 Mar 2020 11:51:31 -0700
Subject: Add dynamic slicing Verilog testcase

---
 tests/simple/dynslice.v | 12 ++++++++++++
 1 file changed, 12 insertions(+)
 create mode 100644 tests/simple/dynslice.v

(limited to 'tests')

diff --git a/tests/simple/dynslice.v b/tests/simple/dynslice.v
new file mode 100644
index 000000000..7236ac3a5
--- /dev/null
+++ b/tests/simple/dynslice.v
@@ -0,0 +1,12 @@
+module dynslice (
+    input clk ,
+    input [9:0] ctrl ,
+    input [15:0] din ,
+    input [3:0] sel ,
+    output reg [127:0] dout
+);
+always @(posedge clk)
+begin
+    dout[ctrl*sel+:16] <= din ;
+end
+endmodule
-- 
cgit v1.2.3


From 2d3753d730c99ab2c0253be119b04cec413e10ba Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Marcin=20Ko=C5=9Bcielnicki?= <mwk@0x04.net>
Date: Mon, 30 Mar 2020 15:35:31 +0200
Subject: iopadmap: Fix z assignment to inout port

Fixes #1841.
---
 tests/techmap/iopadmap.ys | 10 +++++++++-
 1 file changed, 9 insertions(+), 1 deletion(-)

(limited to 'tests')

diff --git a/tests/techmap/iopadmap.ys b/tests/techmap/iopadmap.ys
index 25ea94dfc..df029b3a0 100644
--- a/tests/techmap/iopadmap.ys
+++ b/tests/techmap/iopadmap.ys
@@ -55,13 +55,19 @@ obuf b (.i(i), .o(tmp));
 assign o = tmp;
 endmodule
 
+module k(inout o, o2);
+assign o = 1'bz;
+endmodule
+
 EOT
 
 opt_clean
 tribuf
 simplemap
-iopadmap -bits -inpad ibuf o:i -outpad obuf i:o -toutpad obuft oe:i:o -tinoutpad iobuf oe:o:i:io a b c d e f g h i j
+iopadmap -bits -inpad ibuf o:i -outpad obuf i:o -toutpad obuft oe:i:o -tinoutpad iobuf oe:o:i:io a b c d e f g h i j k
 opt_clean
+hierarchy -check
+check
 
 select -assert-count 1 a/t:ibuf
 select -assert-count 1 a/t:obuf
@@ -140,6 +146,8 @@ select -assert-count 0 i/t:obuf
 select -assert-count 1 j/t:ibuf
 select -assert-count 1 j/t:obuf
 
+select -assert-count 2 k/t:iobuf
+
 
 # Check that \init attributes get moved from output buffer
 #   to buffer input
-- 
cgit v1.2.3


From 9b6370067858aa37825e7a030cd204726f0b58f9 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 17 Jan 2020 10:51:27 -0800
Subject: techmap +/cmp2lcu.v for decomposing arithmetic compares to $lcu

---
 tests/techmap/cmp2lcu.ys | 24 ++++++++++++++++++++++++
 1 file changed, 24 insertions(+)
 create mode 100644 tests/techmap/cmp2lcu.ys

(limited to 'tests')

diff --git a/tests/techmap/cmp2lcu.ys b/tests/techmap/cmp2lcu.ys
new file mode 100644
index 000000000..e7a422e2f
--- /dev/null
+++ b/tests/techmap/cmp2lcu.ys
@@ -0,0 +1,24 @@
+read_verilog <<EOT
+module top(input [11:0] a, b, output gtu, gts, ltu, lts, geu, ges, leu, les);
+assign gtu = a > b;
+assign gts = $signed(a) > $signed(b);
+assign ltu = a < b;
+assign lts = $signed(a) < $signed(b);
+assign geu = a >= b;
+assign ges = $signed(a) >= $signed(b);
+assign leu = a <= b;
+assign les = $signed(a) <= $signed(b);
+endmodule
+EOT
+proc
+
+equiv_opt -assert techmap -map +/cmp2lcu.v -D LUT_WIDTH=6
+design -load postopt
+select -assert-count 8 t:$lcu
+select -assert-none t:$gt t:$ge t:$lt t:$le
+
+design -load preopt
+equiv_opt -assert techmap -map +/cmp2lcu.v -D LUT_WIDTH=4
+design -load postopt
+select -assert-count 8 t:$lcu
+select -assert-none t:$gt t:$ge t:$lt t:$le
-- 
cgit v1.2.3


From f68d723cdccdb1a604077e2a3526de2a5198123c Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Mon, 20 Jan 2020 16:42:08 -0800
Subject: Refactor +/cmp2lcu.v into recursive techmap

---
 tests/techmap/cmp2lcu.ys | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'tests')

diff --git a/tests/techmap/cmp2lcu.ys b/tests/techmap/cmp2lcu.ys
index e7a422e2f..620996549 100644
--- a/tests/techmap/cmp2lcu.ys
+++ b/tests/techmap/cmp2lcu.ys
@@ -1,5 +1,5 @@
 read_verilog <<EOT
-module top(input [11:0] a, b, output gtu, gts, ltu, lts, geu, ges, leu, les);
+module top(input [12:0] a, b, output gtu, gts, ltu, lts, geu, ges, leu, les);
 assign gtu = a > b;
 assign gts = $signed(a) > $signed(b);
 assign ltu = a < b;
-- 
cgit v1.2.3


From 92d70cafec026fb25bf45b020c138e5244bb8cdc Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Mon, 20 Jan 2020 16:42:17 -0800
Subject: +/cmp2lcu.v to work efficiently for fully/partially constant inputs

---
 tests/techmap/cmp2lcu.ys | 34 +++++++++++++++++++++++++++++++---
 1 file changed, 31 insertions(+), 3 deletions(-)

(limited to 'tests')

diff --git a/tests/techmap/cmp2lcu.ys b/tests/techmap/cmp2lcu.ys
index 620996549..7c8a63692 100644
--- a/tests/techmap/cmp2lcu.ys
+++ b/tests/techmap/cmp2lcu.ys
@@ -10,15 +10,43 @@ assign leu = a <= b;
 assign les = $signed(a) <= $signed(b);
 endmodule
 EOT
-proc
 
 equiv_opt -assert techmap -map +/cmp2lcu.v -D LUT_WIDTH=6
 design -load postopt
-select -assert-count 8 t:$lcu
+select -assert-count 8 t:$lcu r:WIDTH=5 %i
 select -assert-none t:$gt t:$ge t:$lt t:$le
 
 design -load preopt
 equiv_opt -assert techmap -map +/cmp2lcu.v -D LUT_WIDTH=4
 design -load postopt
-select -assert-count 8 t:$lcu
+select -assert-count 8 t:$lcu r:WIDTH=7 %i
+select -assert-none t:$gt t:$ge t:$lt t:$le
+
+
+design -reset
+read_verilog <<EOT
+module top(input [8:0] a, b, output gtu, gts, ltu, lts, geu, ges, leu, les);
+wire [13:0] c = {a[8:6], 3'b101, a[5:4], 2'b11, a[3:0]};
+wire [13:0] d = {b[8], 3'b101, b[7:4], 2'b01, b[3:0]};
+assign gtu = c > d;
+assign gts = $signed(c) > $signed(d);
+assign ltu = c < d;
+assign lts = $signed(c) < $signed(d);
+assign geu = c >= d;
+assign ges = $signed(c) >= $signed(d);
+assign leu = c <= d;
+assign les = $signed(c) <= $signed(d);
+endmodule
+EOT
+design -save gold
+
+equiv_opt -assert techmap -map +/cmp2lcu.v -D LUT_WIDTH=5
+design -load postopt
+select -assert-count 8 t:$lcu r:WIDTH=2 %i
+select -assert-none t:$gt t:$ge t:$lt t:$le
+
+design -load preopt
+equiv_opt -assert techmap -map +/cmp2lcu.v -D LUT_WIDTH=3
+design -load postopt
+select -assert-count 8 t:$lcu r:WIDTH=4 %i
 select -assert-none t:$gt t:$ge t:$lt t:$le
-- 
cgit v1.2.3