From 153ec0541c17ee8fad093c002a2724bc33dfe4b9 Mon Sep 17 00:00:00 2001 From: SergeyDegtyar Date: Tue, 20 Aug 2019 07:50:05 +0300 Subject: Add new tests for ice40 architecture --- tests/ice40/.gitignore | 1 + tests/ice40/add_sub.ys | 7 +++ tests/ice40/add_sub_tb.v | 47 ++++++++++++++++++++ tests/ice40/add_sub_top.v | 13 ++++++ tests/ice40/common.v | 47 ++++++++++++++++++++ tests/ice40/dffs.ys | 5 +++ tests/ice40/dffs_tb.v | 77 +++++++++++++++++++++++++++++++++ tests/ice40/dffs_top.v | 108 ++++++++++++++++++++++++++++++++++++++++++++++ tests/ice40/div_mod.ys | 5 +++ tests/ice40/div_mod_tb.v | 48 +++++++++++++++++++++ tests/ice40/div_mod_top.v | 13 ++++++ tests/ice40/latches.ys | 5 +++ tests/ice40/latches_tb.v | 59 +++++++++++++++++++++++++ tests/ice40/latches_top.v | 58 +++++++++++++++++++++++++ tests/ice40/memory.ys | 7 +++ tests/ice40/memory_tb.v | 81 ++++++++++++++++++++++++++++++++++ tests/ice40/memory_top.v | 21 +++++++++ tests/ice40/mul_pow.ys | 6 +++ tests/ice40/mul_pow_tb.v | 47 ++++++++++++++++++++ tests/ice40/mul_pow_top.v | 13 ++++++ tests/ice40/mux.ys | 5 +++ tests/ice40/mux_tb.v | 43 ++++++++++++++++++ tests/ice40/mux_top.v | 100 ++++++++++++++++++++++++++++++++++++++++++ tests/ice40/run-test.sh | 21 +++++++++ tests/ice40/tribuf.ys | 6 +++ tests/ice40/tribuf_tb.v | 34 +++++++++++++++ tests/ice40/tribuf_top.v | 23 ++++++++++ 27 files changed, 900 insertions(+) create mode 100644 tests/ice40/.gitignore create mode 100644 tests/ice40/add_sub.ys create mode 100644 tests/ice40/add_sub_tb.v create mode 100644 tests/ice40/add_sub_top.v create mode 100644 tests/ice40/common.v create mode 100644 tests/ice40/dffs.ys create mode 100644 tests/ice40/dffs_tb.v create mode 100644 tests/ice40/dffs_top.v create mode 100644 tests/ice40/div_mod.ys create mode 100644 tests/ice40/div_mod_tb.v create mode 100644 tests/ice40/div_mod_top.v create mode 100644 tests/ice40/latches.ys create mode 100644 tests/ice40/latches_tb.v create mode 100644 tests/ice40/latches_top.v create mode 100644 tests/ice40/memory.ys create mode 100644 tests/ice40/memory_tb.v create mode 100644 tests/ice40/memory_top.v create mode 100644 tests/ice40/mul_pow.ys create mode 100644 tests/ice40/mul_pow_tb.v create mode 100644 tests/ice40/mul_pow_top.v create mode 100644 tests/ice40/mux.ys create mode 100644 tests/ice40/mux_tb.v create mode 100644 tests/ice40/mux_top.v create mode 100755 tests/ice40/run-test.sh create mode 100644 tests/ice40/tribuf.ys create mode 100644 tests/ice40/tribuf_tb.v create mode 100644 tests/ice40/tribuf_top.v (limited to 'tests') diff --git a/tests/ice40/.gitignore b/tests/ice40/.gitignore new file mode 100644 index 000000000..397b4a762 --- /dev/null +++ b/tests/ice40/.gitignore @@ -0,0 +1 @@ +*.log diff --git a/tests/ice40/add_sub.ys b/tests/ice40/add_sub.ys new file mode 100644 index 000000000..58ad52a58 --- /dev/null +++ b/tests/ice40/add_sub.ys @@ -0,0 +1,7 @@ +equiv_opt -map ../../techlibs/ice40/cells_sim.v synth_ice40 +synth_ice40 +select -assert-count 12 t:SB_LUT4 +select -assert-count 7 t:SB_CARRY +select -assert-count 2 t:$logic_and +select -assert-count 2 t:$logic_or +write_verilog ./temp/add_sub_synth.v diff --git a/tests/ice40/add_sub_tb.v b/tests/ice40/add_sub_tb.v new file mode 100644 index 000000000..45e4f3154 --- /dev/null +++ b/tests/ice40/add_sub_tb.v @@ -0,0 +1,47 @@ +module testbench; + reg [7:0] in; + + wire [3:0] outA,outB; + wire [3:0] poutA,poutB; + + initial begin + // $dumpfile("testbench.vcd"); + // $dumpvars(0, testbench); + + #5 in = 0; + repeat (10000) begin + #5 in = in + 1; + end + + $display("OKAY"); + end + + top uut ( + .x(in[3:0]), + .y(in[7:4]), + .A(outA), + .B(outB) + ); + + + assign poutA = in[3:0] + in[7:4]; + assign poutB = in[3:0] - in[7:4]; + + check_comb add_test(outA, poutA); + check_comb sub_test(outB, poutB); + assert_comb sub0_test(outB[2], poutB[2]); + +endmodule + +module check_comb(input [3:0] test, input [3:0] pat); + always @* + begin + #1; + if (test != pat) + begin + $display("ERROR: ASSERTION FAILED in %m:",$time," ",test," ",pat); + $stop; + end + end +endmodule + diff --git a/tests/ice40/add_sub_top.v b/tests/ice40/add_sub_top.v new file mode 100644 index 000000000..177c32e30 --- /dev/null +++ b/tests/ice40/add_sub_top.v @@ -0,0 +1,13 @@ +module top +( + input [3:0] x, + input [3:0] y, + + output [3:0] A, + output [3:0] B + ); + +assign A = x + y; +assign B = x - y; + +endmodule diff --git a/tests/ice40/common.v b/tests/ice40/common.v new file mode 100644 index 000000000..5446f0817 --- /dev/null +++ b/tests/ice40/common.v @@ -0,0 +1,47 @@ +module assert_dff(input clk, input test, input pat); + always @(posedge clk) + begin + #1; + if (test != pat) + begin + $display("ERROR: ASSERTION FAILED in %m:",$time); + $stop; + end + end +endmodule + +module assert_tri(input en, input A, input B); + always @(posedge en) + begin + #1; + if (A !== B) + begin + $display("ERROR: ASSERTION FAILED in %m:",$time," ",A," ",B); + $stop; + end + end +endmodule + +module assert_Z(input clk, input A); + always @(posedge clk) + begin + #1; + if (A === 1'bZ) + begin + $display("ERROR: ASSERTION FAILED in %m:",$time," ",A); + $stop; + end + end +endmodule + +module assert_comb(input A, input B); + always @(*) + begin + #1; + if (A !== B) + begin + $display("ERROR: ASSERTION FAILED in %m:",$time," ",A," ",B); + $stop; + end + end +endmodule diff --git a/tests/ice40/dffs.ys b/tests/ice40/dffs.ys new file mode 100644 index 000000000..68410b4d8 --- /dev/null +++ b/tests/ice40/dffs.ys @@ -0,0 +1,5 @@ +equiv_opt -map ../../techlibs/ice40/cells_sim.v synth_ice40 +synth_ice40 +select -assert-count 2 t:SB_DFFR +select -assert-count 1 t:SB_DFFE +write_verilog ./temp/dffs_synth.v diff --git a/tests/ice40/dffs_tb.v b/tests/ice40/dffs_tb.v new file mode 100644 index 000000000..ed8f2eb2a --- /dev/null +++ b/tests/ice40/dffs_tb.v @@ -0,0 +1,77 @@ +module testbench; + reg clk; + + initial begin + // $dumpfile("testbench.vcd"); + // $dumpvars(0, testbench); + + #5 clk = 0; + repeat (10000) begin + #5 clk = 1; + #5 clk = 0; + end + + $display("OKAY"); + end + + + reg [2:0] dinA = 0; + wire doutB,doutB1,doutB2,doutB3,doutB4; + reg dff,ndff,adff,adffn,dffe = 0; + + top uut ( + .clk (clk ), + .a (dinA[0] ), + .pre (dinA[1] ), + .clr (dinA[2] ), + .b (doutB ), + .b1 (doutB1 ), + .b2 (doutB2 ), + .b3 (doutB3 ), + .b4 (doutB4 ) + ); + + always @(posedge clk) begin + #3; + dinA <= dinA + 1; + end + + always @( posedge clk, posedge dinA[1], posedge dinA[2] ) + if ( dinA[2] ) + dff <= 1'b0; + else if ( dinA[1] ) + dff <= 1'b1; + else + dff <= dinA[0]; + + always @( negedge clk, negedge dinA[1], negedge dinA[2] ) + if ( !dinA[2] ) + ndff <= 1'b0; + else if ( !dinA[1] ) + ndff <= 1'b1; + else + ndff <= dinA[0]; + + always @( posedge clk, posedge dinA[2] ) + if ( dinA[2] ) + adff <= 1'b0; + else + adff <= dinA[0]; + + always @( posedge clk, negedge dinA[2] ) + if ( !dinA[2] ) + adffn <= 1'b0; + else + adffn <= dinA[0]; + + always @( posedge clk ) + if ( dinA[2] ) + dffe <= dinA[0]; + + assert_dff dff_test(.clk(clk), .test(doutB), .pat(dff)); + assert_dff ndff_test(.clk(clk), .test(doutB1), .pat(ndff)); + assert_dff adff_test(.clk(clk), .test(doutB2), .pat(adff)); + assert_dff adffn_test(.clk(clk), .test(doutB3), .pat(adffn)); + assert_dff dffe_test(.clk(clk), .test(doutB4), .pat(dffe)); + +endmodule diff --git a/tests/ice40/dffs_top.v b/tests/ice40/dffs_top.v new file mode 100644 index 000000000..af7022c79 --- /dev/null +++ b/tests/ice40/dffs_top.v @@ -0,0 +1,108 @@ +module adff + ( input d, clk, clr, output reg q ); + initial begin + q = 0; + end + always @( posedge clk, posedge clr ) + if ( clr ) + q <= 1'b0; + else + q <= d; +endmodule + +module adffn + ( input d, clk, clr, output reg q ); + initial begin + q = 0; + end + always @( posedge clk, negedge clr ) + if ( !clr ) + q <= 1'b0; + else + q <= d; +endmodule + +module dffe + ( input d, clk, en, output reg q ); + initial begin + q = 0; + end + always @( posedge clk ) + if ( en ) + q <= d; +endmodule + +module dffsr + ( input d, clk, pre, clr, output reg q ); + initial begin + q = 0; + end + always @( posedge clk, posedge pre, posedge clr ) + if ( clr ) + q <= 1'b0; + else if ( pre ) + q <= 1'b1; + else + q <= d; +endmodule + +module ndffnsnr + ( input d, clk, pre, clr, output reg q ); + initial begin + q = 0; + end + always @( negedge clk, negedge pre, negedge clr ) + if ( !clr ) + q <= 1'b0; + else if ( !pre ) + q <= 1'b1; + else + q <= d; +endmodule + +module top ( +input clk, +input clr, +input pre, +input a, +output b,b1,b2,b3,b4 +); + +dffsr u_dffsr ( + .clk (clk ), + .clr (clr), + .pre (pre), + .d (a ), + .q (b ) + ); + +ndffnsnr u_ndffnsnr ( + .clk (clk ), + .clr (clr), + .pre (pre), + .d (a ), + .q (b1 ) + ); + +adff u_adff ( + .clk (clk ), + .clr (clr), + .d (a ), + .q (b2 ) + ); + +adffn u_adffn ( + .clk (clk ), + .clr (clr), + .d (a ), + .q (b3 ) + ); + +dffe u_dffe ( + .clk (clk ), + .en (clr), + .d (a ), + .q (b4 ) + ); + +endmodule diff --git a/tests/ice40/div_mod.ys b/tests/ice40/div_mod.ys new file mode 100644 index 000000000..28f31136b --- /dev/null +++ b/tests/ice40/div_mod.ys @@ -0,0 +1,5 @@ +synth_ice40 +equiv_opt -map ../../techlibs/ice40/cells_sim.v synth_ice40 +select -assert-count 89 t:SB_LUT4 +select -assert-count 66 t:SB_CARRY +write_verilog ./temp/div_mod_synth.v diff --git a/tests/ice40/div_mod_tb.v b/tests/ice40/div_mod_tb.v new file mode 100644 index 000000000..4296535c9 --- /dev/null +++ b/tests/ice40/div_mod_tb.v @@ -0,0 +1,48 @@ +module testbench; + reg [7:0] in; + + wire [3:0] outA,outB; + wire [3:0] poutA,poutB; + + initial begin + // $dumpfile("testbench.vcd"); + // $dumpvars(0, testbench); + + #5 in = 0; + repeat (10000) begin + #5 in = in + 1; + end + + $display("OKAY"); + end + + top uut ( + .x(in[3:0]), + .y(in[7:4]), + .A(outA), + .B(outB) + ); + + + assign poutA = in[3:0] % in[7:4]; + assign poutB = in[3:0] / in[7:4]; + + check_comb mod_test(in[7:4], outA, poutA); + check_comb div_test(in[7:4], outB, poutB); + //assert_comb div2_test(outB[2], poutB[2]); + +endmodule + +module check_comb(input [3:0] divisor, input [3:0] test, input [3:0] pat); + always @* + begin + #1; + if (divisor != 4'b0000) + if (test !== pat) + begin + $display("ERROR: ASSERTION FAILED in %m:",$time," ",test," ",pat); + $stop; + end + end +endmodule + diff --git a/tests/ice40/div_mod_top.v b/tests/ice40/div_mod_top.v new file mode 100644 index 000000000..64a36707d --- /dev/null +++ b/tests/ice40/div_mod_top.v @@ -0,0 +1,13 @@ +module top +( + input [3:0] x, + input [3:0] y, + + output [3:0] A, + output [3:0] B + ); + +assign A = x % y; +assign B = x / y; + +endmodule diff --git a/tests/ice40/latches.ys b/tests/ice40/latches.ys new file mode 100644 index 000000000..250ea0f84 --- /dev/null +++ b/tests/ice40/latches.ys @@ -0,0 +1,5 @@ +synth_ice40 +equiv_opt -map ../../techlibs/ice40/cells_sim.v synth_ice40 +proc +select -assert-count 5 t:SB_LUT4 +write_verilog ./temp/latches_synth.v diff --git a/tests/ice40/latches_tb.v b/tests/ice40/latches_tb.v new file mode 100644 index 000000000..47ae8670c --- /dev/null +++ b/tests/ice40/latches_tb.v @@ -0,0 +1,59 @@ +module testbench; + reg clk; + + initial begin + // $dumpfile("testbench.vcd"); + // $dumpvars(0, testbench); + + #5 clk = 0; + repeat (10000) begin + #5 clk = 1; + #5 clk = 0; + end + + $display("OKAY"); + end + + + reg [2:0] dinA = 0; + wire doutB,doutB1,doutB2; + reg lat,latn,latsr = 0; + + top uut ( + .clk (clk ), + .a (dinA[0] ), + .pre (dinA[1] ), + .clr (dinA[2] ), + .b (doutB ), + .b1 (doutB1 ), + .b2 (doutB2 ) + ); + + always @(posedge clk) begin + #3; + dinA <= dinA + 1; + end + + always @* + if ( clk ) + lat <= dinA[0]; + + + always @* + if ( !clk ) + latn <= dinA[0]; + + + always @* + if ( dinA[2] ) + latsr <= 1'b0; + else if ( dinA[1] ) + latsr <= 1'b1; + else if ( clk ) + latsr <= dinA[0]; + + assert_dff lat_test(.clk(clk), .test(doutB), .pat(lat)); + assert_dff latn_test(.clk(clk), .test(doutB1), .pat(latn)); + assert_dff latsr_test(.clk(clk), .test(doutB2), .pat(latsr)); + +endmodule diff --git a/tests/ice40/latches_top.v b/tests/ice40/latches_top.v new file mode 100644 index 000000000..9dc43e4c2 --- /dev/null +++ b/tests/ice40/latches_top.v @@ -0,0 +1,58 @@ +module latchp + ( input d, clk, en, output reg q ); + always @* + if ( en ) + q <= d; +endmodule + +module latchn + ( input d, clk, en, output reg q ); + always @* + if ( !en ) + q <= d; +endmodule + +module latchsr + ( input d, clk, en, clr, pre, output reg q ); + always @* + if ( clr ) + q <= 1'b0; + else if ( pre ) + q <= 1'b1; + else if ( en ) + q <= d; +endmodule + + +module top ( +input clk, +input clr, +input pre, +input a, +output b,b1,b2 +); + + +latchp u_latchp ( + .en (clk ), + .d (a ), + .q (b ) + ); + + +latchn u_latchn ( + .en (clk ), + .d (a ), + .q (b1 ) + ); + + +latchsr u_latchsr ( + .en (clk ), + .clr (clr), + .pre (pre), + .d (a ), + .q (b2 ) + ); + +endmodule diff --git a/tests/ice40/memory.ys b/tests/ice40/memory.ys new file mode 100644 index 000000000..0f030d77d --- /dev/null +++ b/tests/ice40/memory.ys @@ -0,0 +1,7 @@ +proc +memory +equiv_opt -map ../../techlibs/ice40/cells_sim.v synth_ice40 +synth_ice40 +select -assert-count 8 t:SB_DFF +select -assert-count 512 t:SB_DFFE +write_verilog ./temp/memory_synth.v diff --git a/tests/ice40/memory_tb.v b/tests/ice40/memory_tb.v new file mode 100644 index 000000000..5905f3ddd --- /dev/null +++ b/tests/ice40/memory_tb.v @@ -0,0 +1,81 @@ +module testbench; + reg clk; + + initial begin + // $dumpfile("testbench.vcd"); + // $dumpvars(0, testbench); + + #5 clk = 0; + repeat (10000) begin + #5 clk = 1; + #5 clk = 0; + end + + $display("OKAY"); + end + + + reg [7:0] data_a = 0; + reg [5:0] addr_a = 0; + reg we_a = 0; + reg re_a = 1; + wire [7:0] q_a; + reg mem_init = 0; + + reg [7:0] pq_a; + + top uut ( + .data_a(data_a), + .addr_a(addr_a), + .we_a(we_a), + .clk(clk), + .q_a(q_a) + ); + + always @(posedge clk) begin + #3; + data_a <= data_a + 17; + + addr_a <= addr_a + 1; + end + + always @(posedge addr_a) begin + #10; + if(addr_a > 6'h3E) + mem_init <= 1; + end + + always @(posedge clk) begin + //#3; + we_a <= !we_a; + end + + // Declare the RAM variable for check + reg [7:0] ram[63:0]; + + // Port A for check + always @ (posedge clk) + begin + if (we_a) + begin + ram[addr_a] <= data_a; + pq_a <= data_a; + end + pq_a <= ram[addr_a]; + end + + uut_mem_checker port_a_test(.clk(clk), .init(mem_init), .en(!we_a), .A(q_a), .B(pq_a)); + +endmodule + +module uut_mem_checker(input clk, input init, input en, input [7:0] A, input [7:0] B); + always @(posedge clk) + begin + #1; + if (en == 1 & init == 1 & A !== B) + begin + $display("ERROR: ASSERTION FAILED in %m:",$time," ",A," ",B); + $stop; + end + end +endmodule diff --git a/tests/ice40/memory_top.v b/tests/ice40/memory_top.v new file mode 100644 index 000000000..cb7753f7b --- /dev/null +++ b/tests/ice40/memory_top.v @@ -0,0 +1,21 @@ +module top +( + input [7:0] data_a, + input [6:1] addr_a, + input we_a, clk, + output reg [7:0] q_a +); + // Declare the RAM variable + reg [7:0] ram[63:0]; + + // Port A + always @ (posedge clk) + begin + if (we_a) + begin + ram[addr_a] <= data_a; + q_a <= data_a; + end + q_a <= ram[addr_a]; + end +endmodule diff --git a/tests/ice40/mul_pow.ys b/tests/ice40/mul_pow.ys new file mode 100644 index 000000000..486480506 --- /dev/null +++ b/tests/ice40/mul_pow.ys @@ -0,0 +1,6 @@ +equiv_opt -map ../../techlibs/ice40/cells_sim.v synth_ice40 +synth_ice40 +select -assert-count 15 t:SB_LUT4 +select -assert-count 4 t:SB_CARRY +select -assert-count 1 t:$pow +write_verilog ./temp/mul_pow_synth.v diff --git a/tests/ice40/mul_pow_tb.v b/tests/ice40/mul_pow_tb.v new file mode 100644 index 000000000..7e888474f --- /dev/null +++ b/tests/ice40/mul_pow_tb.v @@ -0,0 +1,47 @@ +module testbench; + reg [7:0] in; + + wire [3:0] outA,outB; + wire [3:0] poutA,poutB; + + initial begin + // $dumpfile("testbench.vcd"); + // $dumpvars(0, testbench); + + #5 in = 0; + repeat (10000) begin + #5 in = in + 1; + end + + $display("OKAY"); + end + + top uut ( + .x(in[3:0]), + .y(in[7:4]), + .A(outA), + .B(outB) + ); + + + assign poutA = in[3:0] * in[7:4]; + assign poutB = in[3:0] ** in[7:4]; + + check_comb mul_test(outA, poutA); + check_comb pow_test(outB, poutB); + assert_comb pow2_test(outB[2], poutB[2]); + +endmodule + +module check_comb(input [3:0] test, input [3:0] pat); + always @* + begin + #1; + if (test !== pat) + begin + $display("ERROR: ASSERTION FAILED in %m:",$time," ",test," ",pat); + $stop; + end + end +endmodule + diff --git a/tests/ice40/mul_pow_top.v b/tests/ice40/mul_pow_top.v new file mode 100644 index 000000000..6c256d96b --- /dev/null +++ b/tests/ice40/mul_pow_top.v @@ -0,0 +1,13 @@ +module top +( + input [3:0] x, + input [3:0] y, + + output [3:0] A, + output [3:0] B + ); + +assign A = x * y; +assign B = x ** y; + +endmodule diff --git a/tests/ice40/mux.ys b/tests/ice40/mux.ys new file mode 100644 index 000000000..5ae5a1f33 --- /dev/null +++ b/tests/ice40/mux.ys @@ -0,0 +1,5 @@ +equiv_opt -map ../../techlibs/ice40/cells_sim.v synth_ice40 +synth_ice40 +select -assert-count 20 t:SB_LUT4 +select -assert-count 1 t:SB_CARRY +write_verilog ./temp/mux_synth.v diff --git a/tests/ice40/mux_tb.v b/tests/ice40/mux_tb.v new file mode 100644 index 000000000..2b2da25e9 --- /dev/null +++ b/tests/ice40/mux_tb.v @@ -0,0 +1,43 @@ +module testbench; + reg clk; + + initial begin + // $dumpfile("testbench.vcd"); + // $dumpvars(0, testbench); + + #5 clk = 0; + repeat (10000) begin + #5 clk = 1; + #5 clk = 0; + end + + $display("OKAY"); + end + + + reg [15:0] D = 1; + reg [3:0] S = 0; + wire M2,M4,M8,M16; + + top uut ( + .S (S ), + .D (D ), + .M2 (M2 ), + .M4 (M4 ), + .M8 (M8 ), + .M16 (M16 ) + ); + + always @(posedge clk) begin + //#3; + D <= {D[14:0],D[15]}; + //D <= D <<< 1; + S <= S + 1; + end + + assert_tri m2_test(.en(clk), .A(D[0]|D[1]), .B(M2)); + assert_tri m4_test(.en(clk), .A(D[0]|D[1]|D[2]|D[3]), .B(M4)); + assert_tri m8_test(.en(clk), .A(!S[3]), .B(M8)); + assert_tri m16_test(.en(clk), .A(1'b1), .B(M16)); + +endmodule diff --git a/tests/ice40/mux_top.v b/tests/ice40/mux_top.v new file mode 100644 index 000000000..0814b733e --- /dev/null +++ b/tests/ice40/mux_top.v @@ -0,0 +1,100 @@ +module mux2 (S,A,B,Y); + input S; + input A,B; + output reg Y; + + always @(*) + Y = (S)? B : A; +endmodule + +module mux4 ( S, D, Y ); + +input[1:0] S; +input[3:0] D; +output Y; + +reg Y; +wire[1:0] S; +wire[3:0] D; + +always @* +begin + case( S ) + 0 : Y = D[0]; + 1 : Y = D[1]; + 2 : Y = D[2]; + 3 : Y = D[3]; + endcase +end + +endmodule + +module mux8 ( S, D, Y ); + +input[2:0] S; +input[7:0] D; +output Y; + +reg Y; +wire[2:0] S; +wire[7:0] D; + +always @* +begin + case( S ) + 0 : Y = D[0]; + 1 : Y = D[1]; + 2 : Y = D[2]; + 3 : Y = D[3]; + 4 : Y = D[4]; + 5 : Y = D[5]; + 6 : Y = D[6]; + 7 : Y = D[7]; + endcase +end + +endmodule + +module mux16 (D, S, Y); + input [15:0] D; + input [3:0] S; + output Y; + +assign Y = D[S]; + +endmodule + + +module top ( +input [3:0] S, +input [15:0] D, +output M2,M4,M8,M16 +); + +mux2 u_mux2 ( + .S (S[0]), + .A (D[0]), + .B (D[1]), + .Y (M2) + ); + + +mux4 u_mux4 ( + .S (S[1:0]), + .D (D[3:0]), + .Y (M4) + ); + +mux8 u_mux8 ( + .S (S[2:0]), + .D (D[7:0]), + .Y (M8) + ); + +mux16 u_mux16 ( + .S (S[3:0]), + .D (D[15:0]), + .Y (M16) + ); + +endmodule diff --git a/tests/ice40/run-test.sh b/tests/ice40/run-test.sh new file mode 100755 index 000000000..e839aa9f5 --- /dev/null +++ b/tests/ice40/run-test.sh @@ -0,0 +1,21 @@ +#!/bin/bash +set -e +if [ -f "../../../../../techlibs/common/simcells.v" ]; then + COMMON_PREFIX=../../../../../techlibs/common + TECHLIBS_PREFIX=../../../../../techlibs +else + COMMON_PREFIX=/usr/local/share/yosys + TECHLIBS_PREFIX=/usr/local/share/yosys +fi +for x in *_top.v; do + echo "Running $x.." + ../../yosys -q -s ${x%_top.v}.ys -l ./temp/${x%.v}.log $x + echo "Simulating $x.." + iverilog -o ./temp/${x%_top.v}_testbench ${x%_top.v}_tb.v ./temp/${x%_top.v}_synth.v common.v $COMMON_PREFIX/simcells.v $TECHLIBS_PREFIX/ice40/cells_sim.v + if ! vvp -N ./temp/${x%_top.v}_testbench > ./temp/${x%_top.v}_testbench.log 2>&1; then + grep 'ERROR' ./temp/${x%_top.v}_testbench.log + exit 0 + elif grep 'ERROR' ./temp/${x%_top.v}_testbench.log || ! grep 'OKAY' ./temp/${x%_top.v}_testbench.log; then + exit 0 + fi +done diff --git a/tests/ice40/tribuf.ys b/tests/ice40/tribuf.ys new file mode 100644 index 000000000..40ded734d --- /dev/null +++ b/tests/ice40/tribuf.ys @@ -0,0 +1,6 @@ +equiv_opt -map ../../techlibs/ice40/cells_sim.v synth_ice40 +synth_ice40 +select -assert-count 1 t:SB_LUT4 +select -assert-count 1 t:SB_CARRY +select -assert-count 1 t:$_TBUF_ +write_verilog ./temp/tribuf_synth.v diff --git a/tests/ice40/tribuf_tb.v b/tests/ice40/tribuf_tb.v new file mode 100644 index 000000000..16871b7b2 --- /dev/null +++ b/tests/ice40/tribuf_tb.v @@ -0,0 +1,34 @@ +module testbench; + reg en; + + initial begin + // $dumpfile("testbench.vcd"); + // $dumpvars(0, testbench); + + #5 en = 0; + repeat (10000) begin + #5 en = 1; + #5 en = 0; + end + + $display("OKAY"); + end + + + reg dinA = 0; + wire doutB; + + top uut ( + .en (en ), + .a (dinA ), + .b (doutB ) + ); + + always @(posedge en) begin + #3; + dinA <= !dinA; + end + + assert_tri b_test(.en(en), .A(dinA), .B(doutB)); + +endmodule diff --git a/tests/ice40/tribuf_top.v b/tests/ice40/tribuf_top.v new file mode 100644 index 000000000..b2b5e37d6 --- /dev/null +++ b/tests/ice40/tribuf_top.v @@ -0,0 +1,23 @@ +module tristate (en, i, o); + input en; + input i; + output reg o; + + always @(en or i) + o <= (en)? i : 1'bZ; +endmodule + + +module top ( +input en, +input a, +output b +); + +tristate u_tri ( + .en (en ), + .i (a ), + .o (b ) + ); + +endmodule -- cgit v1.2.3 From 71dd412ac55860cbf51d91d26088515978f70116 Mon Sep 17 00:00:00 2001 From: SergeyDegtyar Date: Tue, 20 Aug 2019 15:52:25 +0300 Subject: Fix tests; Remove simulation; - Add -map and -assert options for equiv_opt; !!! '-assert' option was commented for the next tests (unproven $equiv cells was found): - dffs; - div_mod; - latches; - mul_pow; - Add design -load; - Remove simulations; --- tests/ice40/add_sub.v | 13 ++++++ tests/ice40/add_sub.ys | 4 +- tests/ice40/add_sub_tb.v | 47 -------------------- tests/ice40/add_sub_top.v | 13 ------ tests/ice40/common.v | 47 -------------------- tests/ice40/dffs.v | 108 ++++++++++++++++++++++++++++++++++++++++++++++ tests/ice40/dffs.ys | 11 ++++- tests/ice40/dffs_tb.v | 77 --------------------------------- tests/ice40/dffs_top.v | 108 ---------------------------------------------- tests/ice40/div_mod.v | 13 ++++++ tests/ice40/div_mod.ys | 9 ++-- tests/ice40/div_mod_tb.v | 48 --------------------- tests/ice40/div_mod_top.v | 13 ------ tests/ice40/latches.v | 58 +++++++++++++++++++++++++ tests/ice40/latches.ys | 5 ++- tests/ice40/latches_tb.v | 59 ------------------------- tests/ice40/latches_top.v | 58 ------------------------- tests/ice40/memory.v | 21 +++++++++ tests/ice40/memory.ys | 5 ++- tests/ice40/memory_tb.v | 81 ---------------------------------- tests/ice40/memory_top.v | 21 --------- tests/ice40/mul_pow.v | 13 ++++++ tests/ice40/mul_pow.ys | 7 +-- tests/ice40/mul_pow_tb.v | 47 -------------------- tests/ice40/mul_pow_top.v | 13 ------ tests/ice40/mux.v | 100 ++++++++++++++++++++++++++++++++++++++++++ tests/ice40/mux.ys | 5 ++- tests/ice40/mux_tb.v | 43 ------------------ tests/ice40/mux_top.v | 100 ------------------------------------------ tests/ice40/run-test.sh | 19 +------- tests/ice40/tribuf.v | 23 ++++++++++ tests/ice40/tribuf.ys | 4 +- tests/ice40/tribuf_tb.v | 34 --------------- tests/ice40/tribuf_top.v | 23 ---------- 34 files changed, 382 insertions(+), 868 deletions(-) create mode 100644 tests/ice40/add_sub.v delete mode 100644 tests/ice40/add_sub_tb.v delete mode 100644 tests/ice40/add_sub_top.v delete mode 100644 tests/ice40/common.v create mode 100644 tests/ice40/dffs.v delete mode 100644 tests/ice40/dffs_tb.v delete mode 100644 tests/ice40/dffs_top.v create mode 100644 tests/ice40/div_mod.v delete mode 100644 tests/ice40/div_mod_tb.v delete mode 100644 tests/ice40/div_mod_top.v create mode 100644 tests/ice40/latches.v delete mode 100644 tests/ice40/latches_tb.v delete mode 100644 tests/ice40/latches_top.v create mode 100644 tests/ice40/memory.v delete mode 100644 tests/ice40/memory_tb.v delete mode 100644 tests/ice40/memory_top.v create mode 100644 tests/ice40/mul_pow.v delete mode 100644 tests/ice40/mul_pow_tb.v delete mode 100644 tests/ice40/mul_pow_top.v create mode 100644 tests/ice40/mux.v delete mode 100644 tests/ice40/mux_tb.v delete mode 100644 tests/ice40/mux_top.v create mode 100644 tests/ice40/tribuf.v delete mode 100644 tests/ice40/tribuf_tb.v delete mode 100644 tests/ice40/tribuf_top.v (limited to 'tests') diff --git a/tests/ice40/add_sub.v b/tests/ice40/add_sub.v new file mode 100644 index 000000000..177c32e30 --- /dev/null +++ b/tests/ice40/add_sub.v @@ -0,0 +1,13 @@ +module top +( + input [3:0] x, + input [3:0] y, + + output [3:0] A, + output [3:0] B + ); + +assign A = x + y; +assign B = x - y; + +endmodule diff --git a/tests/ice40/add_sub.ys b/tests/ice40/add_sub.ys index 58ad52a58..c2ee3a843 100644 --- a/tests/ice40/add_sub.ys +++ b/tests/ice40/add_sub.ys @@ -1,7 +1,7 @@ -equiv_opt -map ../../techlibs/ice40/cells_sim.v synth_ice40 synth_ice40 +equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 +design -load postopt select -assert-count 12 t:SB_LUT4 select -assert-count 7 t:SB_CARRY select -assert-count 2 t:$logic_and select -assert-count 2 t:$logic_or -write_verilog ./temp/add_sub_synth.v diff --git a/tests/ice40/add_sub_tb.v b/tests/ice40/add_sub_tb.v deleted file mode 100644 index 45e4f3154..000000000 --- a/tests/ice40/add_sub_tb.v +++ /dev/null @@ -1,47 +0,0 @@ -module testbench; - reg [7:0] in; - - wire [3:0] outA,outB; - wire [3:0] poutA,poutB; - - initial begin - // $dumpfile("testbench.vcd"); - // $dumpvars(0, testbench); - - #5 in = 0; - repeat (10000) begin - #5 in = in + 1; - end - - $display("OKAY"); - end - - top uut ( - .x(in[3:0]), - .y(in[7:4]), - .A(outA), - .B(outB) - ); - - - assign poutA = in[3:0] + in[7:4]; - assign poutB = in[3:0] - in[7:4]; - - check_comb add_test(outA, poutA); - check_comb sub_test(outB, poutB); - assert_comb sub0_test(outB[2], poutB[2]); - -endmodule - -module check_comb(input [3:0] test, input [3:0] pat); - always @* - begin - #1; - if (test != pat) - begin - $display("ERROR: ASSERTION FAILED in %m:",$time," ",test," ",pat); - $stop; - end - end -endmodule - diff --git a/tests/ice40/add_sub_top.v b/tests/ice40/add_sub_top.v deleted file mode 100644 index 177c32e30..000000000 --- a/tests/ice40/add_sub_top.v +++ /dev/null @@ -1,13 +0,0 @@ -module top -( - input [3:0] x, - input [3:0] y, - - output [3:0] A, - output [3:0] B - ); - -assign A = x + y; -assign B = x - y; - -endmodule diff --git a/tests/ice40/common.v b/tests/ice40/common.v deleted file mode 100644 index 5446f0817..000000000 --- a/tests/ice40/common.v +++ /dev/null @@ -1,47 +0,0 @@ -module assert_dff(input clk, input test, input pat); - always @(posedge clk) - begin - #1; - if (test != pat) - begin - $display("ERROR: ASSERTION FAILED in %m:",$time); - $stop; - end - end -endmodule - -module assert_tri(input en, input A, input B); - always @(posedge en) - begin - #1; - if (A !== B) - begin - $display("ERROR: ASSERTION FAILED in %m:",$time," ",A," ",B); - $stop; - end - end -endmodule - -module assert_Z(input clk, input A); - always @(posedge clk) - begin - #1; - if (A === 1'bZ) - begin - $display("ERROR: ASSERTION FAILED in %m:",$time," ",A); - $stop; - end - end -endmodule - -module assert_comb(input A, input B); - always @(*) - begin - #1; - if (A !== B) - begin - $display("ERROR: ASSERTION FAILED in %m:",$time," ",A," ",B); - $stop; - end - end -endmodule diff --git a/tests/ice40/dffs.v b/tests/ice40/dffs.v new file mode 100644 index 000000000..af7022c79 --- /dev/null +++ b/tests/ice40/dffs.v @@ -0,0 +1,108 @@ +module adff + ( input d, clk, clr, output reg q ); + initial begin + q = 0; + end + always @( posedge clk, posedge clr ) + if ( clr ) + q <= 1'b0; + else + q <= d; +endmodule + +module adffn + ( input d, clk, clr, output reg q ); + initial begin + q = 0; + end + always @( posedge clk, negedge clr ) + if ( !clr ) + q <= 1'b0; + else + q <= d; +endmodule + +module dffe + ( input d, clk, en, output reg q ); + initial begin + q = 0; + end + always @( posedge clk ) + if ( en ) + q <= d; +endmodule + +module dffsr + ( input d, clk, pre, clr, output reg q ); + initial begin + q = 0; + end + always @( posedge clk, posedge pre, posedge clr ) + if ( clr ) + q <= 1'b0; + else if ( pre ) + q <= 1'b1; + else + q <= d; +endmodule + +module ndffnsnr + ( input d, clk, pre, clr, output reg q ); + initial begin + q = 0; + end + always @( negedge clk, negedge pre, negedge clr ) + if ( !clr ) + q <= 1'b0; + else if ( !pre ) + q <= 1'b1; + else + q <= d; +endmodule + +module top ( +input clk, +input clr, +input pre, +input a, +output b,b1,b2,b3,b4 +); + +dffsr u_dffsr ( + .clk (clk ), + .clr (clr), + .pre (pre), + .d (a ), + .q (b ) + ); + +ndffnsnr u_ndffnsnr ( + .clk (clk ), + .clr (clr), + .pre (pre), + .d (a ), + .q (b1 ) + ); + +adff u_adff ( + .clk (clk ), + .clr (clr), + .d (a ), + .q (b2 ) + ); + +adffn u_adffn ( + .clk (clk ), + .clr (clr), + .d (a ), + .q (b3 ) + ); + +dffe u_dffe ( + .clk (clk ), + .en (clr), + .d (a ), + .q (b4 ) + ); + +endmodule diff --git a/tests/ice40/dffs.ys b/tests/ice40/dffs.ys index 68410b4d8..09b7bc25a 100644 --- a/tests/ice40/dffs.ys +++ b/tests/ice40/dffs.ys @@ -1,5 +1,12 @@ -equiv_opt -map ../../techlibs/ice40/cells_sim.v synth_ice40 +proc +flatten +dff2dffe synth_ice40 +#equiv_opt -assert -map +/ice40/cells_sim.v -map +/simcells.v synth_ice40 +equiv_opt -map +/ice40/cells_sim.v -map +/simcells.v synth_ice40 +design -load postopt select -assert-count 2 t:SB_DFFR select -assert-count 1 t:SB_DFFE -write_verilog ./temp/dffs_synth.v +select -assert-count 4 t:SB_LUT4 +select -assert-count 1 t:$_DFFSR_PPP_ +select -assert-count 1 t:$_DFFSR_NPP_ diff --git a/tests/ice40/dffs_tb.v b/tests/ice40/dffs_tb.v deleted file mode 100644 index ed8f2eb2a..000000000 --- a/tests/ice40/dffs_tb.v +++ /dev/null @@ -1,77 +0,0 @@ -module testbench; - reg clk; - - initial begin - // $dumpfile("testbench.vcd"); - // $dumpvars(0, testbench); - - #5 clk = 0; - repeat (10000) begin - #5 clk = 1; - #5 clk = 0; - end - - $display("OKAY"); - end - - - reg [2:0] dinA = 0; - wire doutB,doutB1,doutB2,doutB3,doutB4; - reg dff,ndff,adff,adffn,dffe = 0; - - top uut ( - .clk (clk ), - .a (dinA[0] ), - .pre (dinA[1] ), - .clr (dinA[2] ), - .b (doutB ), - .b1 (doutB1 ), - .b2 (doutB2 ), - .b3 (doutB3 ), - .b4 (doutB4 ) - ); - - always @(posedge clk) begin - #3; - dinA <= dinA + 1; - end - - always @( posedge clk, posedge dinA[1], posedge dinA[2] ) - if ( dinA[2] ) - dff <= 1'b0; - else if ( dinA[1] ) - dff <= 1'b1; - else - dff <= dinA[0]; - - always @( negedge clk, negedge dinA[1], negedge dinA[2] ) - if ( !dinA[2] ) - ndff <= 1'b0; - else if ( !dinA[1] ) - ndff <= 1'b1; - else - ndff <= dinA[0]; - - always @( posedge clk, posedge dinA[2] ) - if ( dinA[2] ) - adff <= 1'b0; - else - adff <= dinA[0]; - - always @( posedge clk, negedge dinA[2] ) - if ( !dinA[2] ) - adffn <= 1'b0; - else - adffn <= dinA[0]; - - always @( posedge clk ) - if ( dinA[2] ) - dffe <= dinA[0]; - - assert_dff dff_test(.clk(clk), .test(doutB), .pat(dff)); - assert_dff ndff_test(.clk(clk), .test(doutB1), .pat(ndff)); - assert_dff adff_test(.clk(clk), .test(doutB2), .pat(adff)); - assert_dff adffn_test(.clk(clk), .test(doutB3), .pat(adffn)); - assert_dff dffe_test(.clk(clk), .test(doutB4), .pat(dffe)); - -endmodule diff --git a/tests/ice40/dffs_top.v b/tests/ice40/dffs_top.v deleted file mode 100644 index af7022c79..000000000 --- a/tests/ice40/dffs_top.v +++ /dev/null @@ -1,108 +0,0 @@ -module adff - ( input d, clk, clr, output reg q ); - initial begin - q = 0; - end - always @( posedge clk, posedge clr ) - if ( clr ) - q <= 1'b0; - else - q <= d; -endmodule - -module adffn - ( input d, clk, clr, output reg q ); - initial begin - q = 0; - end - always @( posedge clk, negedge clr ) - if ( !clr ) - q <= 1'b0; - else - q <= d; -endmodule - -module dffe - ( input d, clk, en, output reg q ); - initial begin - q = 0; - end - always @( posedge clk ) - if ( en ) - q <= d; -endmodule - -module dffsr - ( input d, clk, pre, clr, output reg q ); - initial begin - q = 0; - end - always @( posedge clk, posedge pre, posedge clr ) - if ( clr ) - q <= 1'b0; - else if ( pre ) - q <= 1'b1; - else - q <= d; -endmodule - -module ndffnsnr - ( input d, clk, pre, clr, output reg q ); - initial begin - q = 0; - end - always @( negedge clk, negedge pre, negedge clr ) - if ( !clr ) - q <= 1'b0; - else if ( !pre ) - q <= 1'b1; - else - q <= d; -endmodule - -module top ( -input clk, -input clr, -input pre, -input a, -output b,b1,b2,b3,b4 -); - -dffsr u_dffsr ( - .clk (clk ), - .clr (clr), - .pre (pre), - .d (a ), - .q (b ) - ); - -ndffnsnr u_ndffnsnr ( - .clk (clk ), - .clr (clr), - .pre (pre), - .d (a ), - .q (b1 ) - ); - -adff u_adff ( - .clk (clk ), - .clr (clr), - .d (a ), - .q (b2 ) - ); - -adffn u_adffn ( - .clk (clk ), - .clr (clr), - .d (a ), - .q (b3 ) - ); - -dffe u_dffe ( - .clk (clk ), - .en (clr), - .d (a ), - .q (b4 ) - ); - -endmodule diff --git a/tests/ice40/div_mod.v b/tests/ice40/div_mod.v new file mode 100644 index 000000000..64a36707d --- /dev/null +++ b/tests/ice40/div_mod.v @@ -0,0 +1,13 @@ +module top +( + input [3:0] x, + input [3:0] y, + + output [3:0] A, + output [3:0] B + ); + +assign A = x % y; +assign B = x / y; + +endmodule diff --git a/tests/ice40/div_mod.ys b/tests/ice40/div_mod.ys index 28f31136b..f66cb99dd 100644 --- a/tests/ice40/div_mod.ys +++ b/tests/ice40/div_mod.ys @@ -1,5 +1,6 @@ synth_ice40 -equiv_opt -map ../../techlibs/ice40/cells_sim.v synth_ice40 -select -assert-count 89 t:SB_LUT4 -select -assert-count 66 t:SB_CARRY -write_verilog ./temp/div_mod_synth.v +#equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 +equiv_opt -map +/ice40/cells_sim.v synth_ice40 +design -load postopt +select -assert-count 85 t:SB_LUT4 +select -assert-count 54 t:SB_CARRY diff --git a/tests/ice40/div_mod_tb.v b/tests/ice40/div_mod_tb.v deleted file mode 100644 index 4296535c9..000000000 --- a/tests/ice40/div_mod_tb.v +++ /dev/null @@ -1,48 +0,0 @@ -module testbench; - reg [7:0] in; - - wire [3:0] outA,outB; - wire [3:0] poutA,poutB; - - initial begin - // $dumpfile("testbench.vcd"); - // $dumpvars(0, testbench); - - #5 in = 0; - repeat (10000) begin - #5 in = in + 1; - end - - $display("OKAY"); - end - - top uut ( - .x(in[3:0]), - .y(in[7:4]), - .A(outA), - .B(outB) - ); - - - assign poutA = in[3:0] % in[7:4]; - assign poutB = in[3:0] / in[7:4]; - - check_comb mod_test(in[7:4], outA, poutA); - check_comb div_test(in[7:4], outB, poutB); - //assert_comb div2_test(outB[2], poutB[2]); - -endmodule - -module check_comb(input [3:0] divisor, input [3:0] test, input [3:0] pat); - always @* - begin - #1; - if (divisor != 4'b0000) - if (test !== pat) - begin - $display("ERROR: ASSERTION FAILED in %m:",$time," ",test," ",pat); - $stop; - end - end -endmodule - diff --git a/tests/ice40/div_mod_top.v b/tests/ice40/div_mod_top.v deleted file mode 100644 index 64a36707d..000000000 --- a/tests/ice40/div_mod_top.v +++ /dev/null @@ -1,13 +0,0 @@ -module top -( - input [3:0] x, - input [3:0] y, - - output [3:0] A, - output [3:0] B - ); - -assign A = x % y; -assign B = x / y; - -endmodule diff --git a/tests/ice40/latches.v b/tests/ice40/latches.v new file mode 100644 index 000000000..9dc43e4c2 --- /dev/null +++ b/tests/ice40/latches.v @@ -0,0 +1,58 @@ +module latchp + ( input d, clk, en, output reg q ); + always @* + if ( en ) + q <= d; +endmodule + +module latchn + ( input d, clk, en, output reg q ); + always @* + if ( !en ) + q <= d; +endmodule + +module latchsr + ( input d, clk, en, clr, pre, output reg q ); + always @* + if ( clr ) + q <= 1'b0; + else if ( pre ) + q <= 1'b1; + else if ( en ) + q <= d; +endmodule + + +module top ( +input clk, +input clr, +input pre, +input a, +output b,b1,b2 +); + + +latchp u_latchp ( + .en (clk ), + .d (a ), + .q (b ) + ); + + +latchn u_latchn ( + .en (clk ), + .d (a ), + .q (b1 ) + ); + + +latchsr u_latchsr ( + .en (clk ), + .clr (clr), + .pre (pre), + .d (a ), + .q (b2 ) + ); + +endmodule diff --git a/tests/ice40/latches.ys b/tests/ice40/latches.ys index 250ea0f84..77037b1d5 100644 --- a/tests/ice40/latches.ys +++ b/tests/ice40/latches.ys @@ -1,5 +1,6 @@ synth_ice40 -equiv_opt -map ../../techlibs/ice40/cells_sim.v synth_ice40 +#equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 +equiv_opt -map +/ice40/cells_sim.v synth_ice40 +design -load postopt proc select -assert-count 5 t:SB_LUT4 -write_verilog ./temp/latches_synth.v diff --git a/tests/ice40/latches_tb.v b/tests/ice40/latches_tb.v deleted file mode 100644 index 47ae8670c..000000000 --- a/tests/ice40/latches_tb.v +++ /dev/null @@ -1,59 +0,0 @@ -module testbench; - reg clk; - - initial begin - // $dumpfile("testbench.vcd"); - // $dumpvars(0, testbench); - - #5 clk = 0; - repeat (10000) begin - #5 clk = 1; - #5 clk = 0; - end - - $display("OKAY"); - end - - - reg [2:0] dinA = 0; - wire doutB,doutB1,doutB2; - reg lat,latn,latsr = 0; - - top uut ( - .clk (clk ), - .a (dinA[0] ), - .pre (dinA[1] ), - .clr (dinA[2] ), - .b (doutB ), - .b1 (doutB1 ), - .b2 (doutB2 ) - ); - - always @(posedge clk) begin - #3; - dinA <= dinA + 1; - end - - always @* - if ( clk ) - lat <= dinA[0]; - - - always @* - if ( !clk ) - latn <= dinA[0]; - - - always @* - if ( dinA[2] ) - latsr <= 1'b0; - else if ( dinA[1] ) - latsr <= 1'b1; - else if ( clk ) - latsr <= dinA[0]; - - assert_dff lat_test(.clk(clk), .test(doutB), .pat(lat)); - assert_dff latn_test(.clk(clk), .test(doutB1), .pat(latn)); - assert_dff latsr_test(.clk(clk), .test(doutB2), .pat(latsr)); - -endmodule diff --git a/tests/ice40/latches_top.v b/tests/ice40/latches_top.v deleted file mode 100644 index 9dc43e4c2..000000000 --- a/tests/ice40/latches_top.v +++ /dev/null @@ -1,58 +0,0 @@ -module latchp - ( input d, clk, en, output reg q ); - always @* - if ( en ) - q <= d; -endmodule - -module latchn - ( input d, clk, en, output reg q ); - always @* - if ( !en ) - q <= d; -endmodule - -module latchsr - ( input d, clk, en, clr, pre, output reg q ); - always @* - if ( clr ) - q <= 1'b0; - else if ( pre ) - q <= 1'b1; - else if ( en ) - q <= d; -endmodule - - -module top ( -input clk, -input clr, -input pre, -input a, -output b,b1,b2 -); - - -latchp u_latchp ( - .en (clk ), - .d (a ), - .q (b ) - ); - - -latchn u_latchn ( - .en (clk ), - .d (a ), - .q (b1 ) - ); - - -latchsr u_latchsr ( - .en (clk ), - .clr (clr), - .pre (pre), - .d (a ), - .q (b2 ) - ); - -endmodule diff --git a/tests/ice40/memory.v b/tests/ice40/memory.v new file mode 100644 index 000000000..cb7753f7b --- /dev/null +++ b/tests/ice40/memory.v @@ -0,0 +1,21 @@ +module top +( + input [7:0] data_a, + input [6:1] addr_a, + input we_a, clk, + output reg [7:0] q_a +); + // Declare the RAM variable + reg [7:0] ram[63:0]; + + // Port A + always @ (posedge clk) + begin + if (we_a) + begin + ram[addr_a] <= data_a; + q_a <= data_a; + end + q_a <= ram[addr_a]; + end +endmodule diff --git a/tests/ice40/memory.ys b/tests/ice40/memory.ys index 0f030d77d..47d5526c1 100644 --- a/tests/ice40/memory.ys +++ b/tests/ice40/memory.ys @@ -1,7 +1,8 @@ proc memory -equiv_opt -map ../../techlibs/ice40/cells_sim.v synth_ice40 synth_ice40 +equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 +design -load postopt + select -assert-count 8 t:SB_DFF select -assert-count 512 t:SB_DFFE -write_verilog ./temp/memory_synth.v diff --git a/tests/ice40/memory_tb.v b/tests/ice40/memory_tb.v deleted file mode 100644 index 5905f3ddd..000000000 --- a/tests/ice40/memory_tb.v +++ /dev/null @@ -1,81 +0,0 @@ -module testbench; - reg clk; - - initial begin - // $dumpfile("testbench.vcd"); - // $dumpvars(0, testbench); - - #5 clk = 0; - repeat (10000) begin - #5 clk = 1; - #5 clk = 0; - end - - $display("OKAY"); - end - - - reg [7:0] data_a = 0; - reg [5:0] addr_a = 0; - reg we_a = 0; - reg re_a = 1; - wire [7:0] q_a; - reg mem_init = 0; - - reg [7:0] pq_a; - - top uut ( - .data_a(data_a), - .addr_a(addr_a), - .we_a(we_a), - .clk(clk), - .q_a(q_a) - ); - - always @(posedge clk) begin - #3; - data_a <= data_a + 17; - - addr_a <= addr_a + 1; - end - - always @(posedge addr_a) begin - #10; - if(addr_a > 6'h3E) - mem_init <= 1; - end - - always @(posedge clk) begin - //#3; - we_a <= !we_a; - end - - // Declare the RAM variable for check - reg [7:0] ram[63:0]; - - // Port A for check - always @ (posedge clk) - begin - if (we_a) - begin - ram[addr_a] <= data_a; - pq_a <= data_a; - end - pq_a <= ram[addr_a]; - end - - uut_mem_checker port_a_test(.clk(clk), .init(mem_init), .en(!we_a), .A(q_a), .B(pq_a)); - -endmodule - -module uut_mem_checker(input clk, input init, input en, input [7:0] A, input [7:0] B); - always @(posedge clk) - begin - #1; - if (en == 1 & init == 1 & A !== B) - begin - $display("ERROR: ASSERTION FAILED in %m:",$time," ",A," ",B); - $stop; - end - end -endmodule diff --git a/tests/ice40/memory_top.v b/tests/ice40/memory_top.v deleted file mode 100644 index cb7753f7b..000000000 --- a/tests/ice40/memory_top.v +++ /dev/null @@ -1,21 +0,0 @@ -module top -( - input [7:0] data_a, - input [6:1] addr_a, - input we_a, clk, - output reg [7:0] q_a -); - // Declare the RAM variable - reg [7:0] ram[63:0]; - - // Port A - always @ (posedge clk) - begin - if (we_a) - begin - ram[addr_a] <= data_a; - q_a <= data_a; - end - q_a <= ram[addr_a]; - end -endmodule diff --git a/tests/ice40/mul_pow.v b/tests/ice40/mul_pow.v new file mode 100644 index 000000000..6c256d96b --- /dev/null +++ b/tests/ice40/mul_pow.v @@ -0,0 +1,13 @@ +module top +( + input [3:0] x, + input [3:0] y, + + output [3:0] A, + output [3:0] B + ); + +assign A = x * y; +assign B = x ** y; + +endmodule diff --git a/tests/ice40/mul_pow.ys b/tests/ice40/mul_pow.ys index 486480506..2a6baa738 100644 --- a/tests/ice40/mul_pow.ys +++ b/tests/ice40/mul_pow.ys @@ -1,6 +1,7 @@ -equiv_opt -map ../../techlibs/ice40/cells_sim.v synth_ice40 synth_ice40 -select -assert-count 15 t:SB_LUT4 +#equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 +equiv_opt -map +/ice40/cells_sim.v synth_ice40 +design -load postopt +select -assert-count 16 t:SB_LUT4 select -assert-count 4 t:SB_CARRY select -assert-count 1 t:$pow -write_verilog ./temp/mul_pow_synth.v diff --git a/tests/ice40/mul_pow_tb.v b/tests/ice40/mul_pow_tb.v deleted file mode 100644 index 7e888474f..000000000 --- a/tests/ice40/mul_pow_tb.v +++ /dev/null @@ -1,47 +0,0 @@ -module testbench; - reg [7:0] in; - - wire [3:0] outA,outB; - wire [3:0] poutA,poutB; - - initial begin - // $dumpfile("testbench.vcd"); - // $dumpvars(0, testbench); - - #5 in = 0; - repeat (10000) begin - #5 in = in + 1; - end - - $display("OKAY"); - end - - top uut ( - .x(in[3:0]), - .y(in[7:4]), - .A(outA), - .B(outB) - ); - - - assign poutA = in[3:0] * in[7:4]; - assign poutB = in[3:0] ** in[7:4]; - - check_comb mul_test(outA, poutA); - check_comb pow_test(outB, poutB); - assert_comb pow2_test(outB[2], poutB[2]); - -endmodule - -module check_comb(input [3:0] test, input [3:0] pat); - always @* - begin - #1; - if (test !== pat) - begin - $display("ERROR: ASSERTION FAILED in %m:",$time," ",test," ",pat); - $stop; - end - end -endmodule - diff --git a/tests/ice40/mul_pow_top.v b/tests/ice40/mul_pow_top.v deleted file mode 100644 index 6c256d96b..000000000 --- a/tests/ice40/mul_pow_top.v +++ /dev/null @@ -1,13 +0,0 @@ -module top -( - input [3:0] x, - input [3:0] y, - - output [3:0] A, - output [3:0] B - ); - -assign A = x * y; -assign B = x ** y; - -endmodule diff --git a/tests/ice40/mux.v b/tests/ice40/mux.v new file mode 100644 index 000000000..0814b733e --- /dev/null +++ b/tests/ice40/mux.v @@ -0,0 +1,100 @@ +module mux2 (S,A,B,Y); + input S; + input A,B; + output reg Y; + + always @(*) + Y = (S)? B : A; +endmodule + +module mux4 ( S, D, Y ); + +input[1:0] S; +input[3:0] D; +output Y; + +reg Y; +wire[1:0] S; +wire[3:0] D; + +always @* +begin + case( S ) + 0 : Y = D[0]; + 1 : Y = D[1]; + 2 : Y = D[2]; + 3 : Y = D[3]; + endcase +end + +endmodule + +module mux8 ( S, D, Y ); + +input[2:0] S; +input[7:0] D; +output Y; + +reg Y; +wire[2:0] S; +wire[7:0] D; + +always @* +begin + case( S ) + 0 : Y = D[0]; + 1 : Y = D[1]; + 2 : Y = D[2]; + 3 : Y = D[3]; + 4 : Y = D[4]; + 5 : Y = D[5]; + 6 : Y = D[6]; + 7 : Y = D[7]; + endcase +end + +endmodule + +module mux16 (D, S, Y); + input [15:0] D; + input [3:0] S; + output Y; + +assign Y = D[S]; + +endmodule + + +module top ( +input [3:0] S, +input [15:0] D, +output M2,M4,M8,M16 +); + +mux2 u_mux2 ( + .S (S[0]), + .A (D[0]), + .B (D[1]), + .Y (M2) + ); + + +mux4 u_mux4 ( + .S (S[1:0]), + .D (D[3:0]), + .Y (M4) + ); + +mux8 u_mux8 ( + .S (S[2:0]), + .D (D[7:0]), + .Y (M8) + ); + +mux16 u_mux16 ( + .S (S[3:0]), + .D (D[15:0]), + .Y (M16) + ); + +endmodule diff --git a/tests/ice40/mux.ys b/tests/ice40/mux.ys index 5ae5a1f33..3da9ef433 100644 --- a/tests/ice40/mux.ys +++ b/tests/ice40/mux.ys @@ -1,5 +1,6 @@ -equiv_opt -map ../../techlibs/ice40/cells_sim.v synth_ice40 + synth_ice40 +equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 +design -load postopt select -assert-count 20 t:SB_LUT4 select -assert-count 1 t:SB_CARRY -write_verilog ./temp/mux_synth.v diff --git a/tests/ice40/mux_tb.v b/tests/ice40/mux_tb.v deleted file mode 100644 index 2b2da25e9..000000000 --- a/tests/ice40/mux_tb.v +++ /dev/null @@ -1,43 +0,0 @@ -module testbench; - reg clk; - - initial begin - // $dumpfile("testbench.vcd"); - // $dumpvars(0, testbench); - - #5 clk = 0; - repeat (10000) begin - #5 clk = 1; - #5 clk = 0; - end - - $display("OKAY"); - end - - - reg [15:0] D = 1; - reg [3:0] S = 0; - wire M2,M4,M8,M16; - - top uut ( - .S (S ), - .D (D ), - .M2 (M2 ), - .M4 (M4 ), - .M8 (M8 ), - .M16 (M16 ) - ); - - always @(posedge clk) begin - //#3; - D <= {D[14:0],D[15]}; - //D <= D <<< 1; - S <= S + 1; - end - - assert_tri m2_test(.en(clk), .A(D[0]|D[1]), .B(M2)); - assert_tri m4_test(.en(clk), .A(D[0]|D[1]|D[2]|D[3]), .B(M4)); - assert_tri m8_test(.en(clk), .A(!S[3]), .B(M8)); - assert_tri m16_test(.en(clk), .A(1'b1), .B(M16)); - -endmodule diff --git a/tests/ice40/mux_top.v b/tests/ice40/mux_top.v deleted file mode 100644 index 0814b733e..000000000 --- a/tests/ice40/mux_top.v +++ /dev/null @@ -1,100 +0,0 @@ -module mux2 (S,A,B,Y); - input S; - input A,B; - output reg Y; - - always @(*) - Y = (S)? B : A; -endmodule - -module mux4 ( S, D, Y ); - -input[1:0] S; -input[3:0] D; -output Y; - -reg Y; -wire[1:0] S; -wire[3:0] D; - -always @* -begin - case( S ) - 0 : Y = D[0]; - 1 : Y = D[1]; - 2 : Y = D[2]; - 3 : Y = D[3]; - endcase -end - -endmodule - -module mux8 ( S, D, Y ); - -input[2:0] S; -input[7:0] D; -output Y; - -reg Y; -wire[2:0] S; -wire[7:0] D; - -always @* -begin - case( S ) - 0 : Y = D[0]; - 1 : Y = D[1]; - 2 : Y = D[2]; - 3 : Y = D[3]; - 4 : Y = D[4]; - 5 : Y = D[5]; - 6 : Y = D[6]; - 7 : Y = D[7]; - endcase -end - -endmodule - -module mux16 (D, S, Y); - input [15:0] D; - input [3:0] S; - output Y; - -assign Y = D[S]; - -endmodule - - -module top ( -input [3:0] S, -input [15:0] D, -output M2,M4,M8,M16 -); - -mux2 u_mux2 ( - .S (S[0]), - .A (D[0]), - .B (D[1]), - .Y (M2) - ); - - -mux4 u_mux4 ( - .S (S[1:0]), - .D (D[3:0]), - .Y (M4) - ); - -mux8 u_mux8 ( - .S (S[2:0]), - .D (D[7:0]), - .Y (M8) - ); - -mux16 u_mux16 ( - .S (S[3:0]), - .D (D[15:0]), - .Y (M16) - ); - -endmodule diff --git a/tests/ice40/run-test.sh b/tests/ice40/run-test.sh index e839aa9f5..75e5f0609 100755 --- a/tests/ice40/run-test.sh +++ b/tests/ice40/run-test.sh @@ -1,21 +1,6 @@ #!/bin/bash set -e -if [ -f "../../../../../techlibs/common/simcells.v" ]; then - COMMON_PREFIX=../../../../../techlibs/common - TECHLIBS_PREFIX=../../../../../techlibs -else - COMMON_PREFIX=/usr/local/share/yosys - TECHLIBS_PREFIX=/usr/local/share/yosys -fi -for x in *_top.v; do +for x in *.v; do echo "Running $x.." - ../../yosys -q -s ${x%_top.v}.ys -l ./temp/${x%.v}.log $x - echo "Simulating $x.." - iverilog -o ./temp/${x%_top.v}_testbench ${x%_top.v}_tb.v ./temp/${x%_top.v}_synth.v common.v $COMMON_PREFIX/simcells.v $TECHLIBS_PREFIX/ice40/cells_sim.v - if ! vvp -N ./temp/${x%_top.v}_testbench > ./temp/${x%_top.v}_testbench.log 2>&1; then - grep 'ERROR' ./temp/${x%_top.v}_testbench.log - exit 0 - elif grep 'ERROR' ./temp/${x%_top.v}_testbench.log || ! grep 'OKAY' ./temp/${x%_top.v}_testbench.log; then - exit 0 - fi + ../../yosys -q -s ${x%.v}.ys -l ./temp/${x%.v}.log $x done diff --git a/tests/ice40/tribuf.v b/tests/ice40/tribuf.v new file mode 100644 index 000000000..b2b5e37d6 --- /dev/null +++ b/tests/ice40/tribuf.v @@ -0,0 +1,23 @@ +module tristate (en, i, o); + input en; + input i; + output reg o; + + always @(en or i) + o <= (en)? i : 1'bZ; +endmodule + + +module top ( +input en, +input a, +output b +); + +tristate u_tri ( + .en (en ), + .i (a ), + .o (b ) + ); + +endmodule diff --git a/tests/ice40/tribuf.ys b/tests/ice40/tribuf.ys index 40ded734d..b319e6622 100644 --- a/tests/ice40/tribuf.ys +++ b/tests/ice40/tribuf.ys @@ -1,6 +1,6 @@ -equiv_opt -map ../../techlibs/ice40/cells_sim.v synth_ice40 synth_ice40 +equiv_opt -assert -map +/ice40/cells_sim.v -map +/simcells.v synth_ice40 +design -load postopt select -assert-count 1 t:SB_LUT4 select -assert-count 1 t:SB_CARRY select -assert-count 1 t:$_TBUF_ -write_verilog ./temp/tribuf_synth.v diff --git a/tests/ice40/tribuf_tb.v b/tests/ice40/tribuf_tb.v deleted file mode 100644 index 16871b7b2..000000000 --- a/tests/ice40/tribuf_tb.v +++ /dev/null @@ -1,34 +0,0 @@ -module testbench; - reg en; - - initial begin - // $dumpfile("testbench.vcd"); - // $dumpvars(0, testbench); - - #5 en = 0; - repeat (10000) begin - #5 en = 1; - #5 en = 0; - end - - $display("OKAY"); - end - - - reg dinA = 0; - wire doutB; - - top uut ( - .en (en ), - .a (dinA ), - .b (doutB ) - ); - - always @(posedge en) begin - #3; - dinA <= !dinA; - end - - assert_tri b_test(.en(en), .A(dinA), .B(doutB)); - -endmodule diff --git a/tests/ice40/tribuf_top.v b/tests/ice40/tribuf_top.v deleted file mode 100644 index b2b5e37d6..000000000 --- a/tests/ice40/tribuf_top.v +++ /dev/null @@ -1,23 +0,0 @@ -module tristate (en, i, o); - input en; - input i; - output reg o; - - always @(en or i) - o <= (en)? i : 1'bZ; -endmodule - - -module top ( -input en, -input a, -output b -); - -tristate u_tri ( - .en (en ), - .i (a ), - .o (b ) - ); - -endmodule -- cgit v1.2.3 From fce8dc7db20d722646cea83ca841160d3d07445e Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Tue, 20 Aug 2019 20:05:16 -0700 Subject: Add test --- tests/techmap/recursive.v | 8 ++++++++ tests/techmap/recursive_map.v | 4 ++++ tests/techmap/recursive_runtest.sh | 3 +++ 3 files changed, 15 insertions(+) create mode 100644 tests/techmap/recursive.v create mode 100644 tests/techmap/recursive_map.v create mode 100644 tests/techmap/recursive_runtest.sh (limited to 'tests') diff --git a/tests/techmap/recursive.v b/tests/techmap/recursive.v new file mode 100644 index 000000000..d281b21d8 --- /dev/null +++ b/tests/techmap/recursive.v @@ -0,0 +1,8 @@ +module top; +sub s0(); +foo f0(); +endmodule + +module foo; +sub s0(); +endmodule diff --git a/tests/techmap/recursive_map.v b/tests/techmap/recursive_map.v new file mode 100644 index 000000000..934256552 --- /dev/null +++ b/tests/techmap/recursive_map.v @@ -0,0 +1,4 @@ +module sub; + sub _TECHMAP_REPLACE_ (); + bar f0(); +endmodule diff --git a/tests/techmap/recursive_runtest.sh b/tests/techmap/recursive_runtest.sh new file mode 100644 index 000000000..30c79bf03 --- /dev/null +++ b/tests/techmap/recursive_runtest.sh @@ -0,0 +1,3 @@ +set -ev + +../../yosys -p 'hierarchy -top top; techmap -map recursive_map.v -max_iter 1; select -assert-count 2 t:sub; select -assert-count 2 t:bar' recursive.v -- cgit v1.2.3 From b835ec37cbb56bc3b55fe53eb85375ad5ac98f27 Mon Sep 17 00:00:00 2001 From: SergeyDegtyar Date: Wed, 21 Aug 2019 07:53:34 +0300 Subject: Add temp directory --- tests/ice40/temp/.gitignore | 1 + 1 file changed, 1 insertion(+) create mode 100644 tests/ice40/temp/.gitignore (limited to 'tests') diff --git a/tests/ice40/temp/.gitignore b/tests/ice40/temp/.gitignore new file mode 100644 index 000000000..397b4a762 --- /dev/null +++ b/tests/ice40/temp/.gitignore @@ -0,0 +1 @@ +*.log -- cgit v1.2.3 From d945b8a357c567f5f3565983da09f24c0f295461 Mon Sep 17 00:00:00 2001 From: SergeyDegtyar Date: Wed, 21 Aug 2019 21:52:07 +0300 Subject: Fix all comments from PR --- tests/ice40/add_sub.ys | 17 ++++--- tests/ice40/adffs.v | 108 ++++++++++++++++++++++++++++++++++++++++++++ tests/ice40/adffs.ys | 9 ++++ tests/ice40/adffs_tb.v | 75 ++++++++++++++++++++++++++++++ tests/ice40/common.v | 47 +++++++++++++++++++ tests/ice40/dffs.v | 107 +------------------------------------------ tests/ice40/dffs.ys | 17 ++++--- tests/ice40/div_mod.ys | 15 +++--- tests/ice40/latches.ys | 7 ++- tests/ice40/latches_tb.v | 59 ++++++++++++++++++++++++ tests/ice40/memory.ys | 10 ++-- tests/ice40/memory_tb.v | 81 +++++++++++++++++++++++++++++++++ tests/ice40/mul.v | 12 +++++ tests/ice40/mul.ys | 9 ++++ tests/ice40/mul_pow.v | 13 ------ tests/ice40/mul_pow.ys | 7 --- tests/ice40/mux.ys | 2 +- tests/ice40/run-test.sh | 35 ++++++++++++-- tests/ice40/temp/.gitignore | 1 - tests/ice40/tribuf.v | 6 +-- tests/ice40/tribuf.ys | 12 +++-- 21 files changed, 477 insertions(+), 172 deletions(-) create mode 100644 tests/ice40/adffs.v create mode 100644 tests/ice40/adffs.ys create mode 100644 tests/ice40/adffs_tb.v create mode 100644 tests/ice40/common.v create mode 100644 tests/ice40/latches_tb.v create mode 100644 tests/ice40/memory_tb.v create mode 100644 tests/ice40/mul.v create mode 100644 tests/ice40/mul.ys delete mode 100644 tests/ice40/mul_pow.v delete mode 100644 tests/ice40/mul_pow.ys delete mode 100644 tests/ice40/temp/.gitignore (limited to 'tests') diff --git a/tests/ice40/add_sub.ys b/tests/ice40/add_sub.ys index c2ee3a843..84f31ec53 100644 --- a/tests/ice40/add_sub.ys +++ b/tests/ice40/add_sub.ys @@ -1,7 +1,10 @@ -synth_ice40 -equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 -design -load postopt -select -assert-count 12 t:SB_LUT4 -select -assert-count 7 t:SB_CARRY -select -assert-count 2 t:$logic_and -select -assert-count 2 t:$logic_or +read_verilog add_sub.v +hierarchy -top top +synth -flatten -run coarse # technology-independent coarse grained synthesis +equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check same as technology-dependent fine-grained synthesis +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module +select -assert-count 11 t:SB_LUT4 +select -assert-count 6 t:SB_CARRY +select -assert-none t:SB_LUT4 t:SB_CARRY %% t:* %D + diff --git a/tests/ice40/adffs.v b/tests/ice40/adffs.v new file mode 100644 index 000000000..af7022c79 --- /dev/null +++ b/tests/ice40/adffs.v @@ -0,0 +1,108 @@ +module adff + ( input d, clk, clr, output reg q ); + initial begin + q = 0; + end + always @( posedge clk, posedge clr ) + if ( clr ) + q <= 1'b0; + else + q <= d; +endmodule + +module adffn + ( input d, clk, clr, output reg q ); + initial begin + q = 0; + end + always @( posedge clk, negedge clr ) + if ( !clr ) + q <= 1'b0; + else + q <= d; +endmodule + +module dffe + ( input d, clk, en, output reg q ); + initial begin + q = 0; + end + always @( posedge clk ) + if ( en ) + q <= d; +endmodule + +module dffsr + ( input d, clk, pre, clr, output reg q ); + initial begin + q = 0; + end + always @( posedge clk, posedge pre, posedge clr ) + if ( clr ) + q <= 1'b0; + else if ( pre ) + q <= 1'b1; + else + q <= d; +endmodule + +module ndffnsnr + ( input d, clk, pre, clr, output reg q ); + initial begin + q = 0; + end + always @( negedge clk, negedge pre, negedge clr ) + if ( !clr ) + q <= 1'b0; + else if ( !pre ) + q <= 1'b1; + else + q <= d; +endmodule + +module top ( +input clk, +input clr, +input pre, +input a, +output b,b1,b2,b3,b4 +); + +dffsr u_dffsr ( + .clk (clk ), + .clr (clr), + .pre (pre), + .d (a ), + .q (b ) + ); + +ndffnsnr u_ndffnsnr ( + .clk (clk ), + .clr (clr), + .pre (pre), + .d (a ), + .q (b1 ) + ); + +adff u_adff ( + .clk (clk ), + .clr (clr), + .d (a ), + .q (b2 ) + ); + +adffn u_adffn ( + .clk (clk ), + .clr (clr), + .d (a ), + .q (b3 ) + ); + +dffe u_dffe ( + .clk (clk ), + .en (clr), + .d (a ), + .q (b4 ) + ); + +endmodule diff --git a/tests/ice40/adffs.ys b/tests/ice40/adffs.ys new file mode 100644 index 000000000..aee8cd6b4 --- /dev/null +++ b/tests/ice40/adffs.ys @@ -0,0 +1,9 @@ +read_verilog adffs.v +proc +dff2dffe +synth_ice40 +select -assert-count 2 t:SB_DFFR +select -assert-count 1 t:SB_DFFE +select -assert-count 4 t:SB_LUT4 +#select -assert-none t:SB_LUT4 t:SB_DFFR t:SB_DFFE t:$_DFFSR_NPP_ t:$_DFFSR_PPP_ %% t:* %D +write_verilog adffs_synth.v diff --git a/tests/ice40/adffs_tb.v b/tests/ice40/adffs_tb.v new file mode 100644 index 000000000..e049edabc --- /dev/null +++ b/tests/ice40/adffs_tb.v @@ -0,0 +1,75 @@ +module testbench; + reg clk; + + initial begin + // $dumpfile("testbench.vcd"); + // $dumpvars(0, testbench); + + #5 clk = 0; + repeat (10000) begin + #5 clk = 1; + #5 clk = 0; + end + + $display("OKAY"); + end + + + reg [2:0] dinA = 0; + wire doutB,doutB1,doutB2,doutB3,doutB4; + reg dff,ndff,adff,adffn,dffe = 0; + + top uut ( + .clk (clk ), + .a (dinA[0] ), + .pre (dinA[1] ), + .clr (dinA[2] ), + .b (doutB ), + .b1 (doutB1 ), + .b2 (doutB2 ) + ); + + always @(posedge clk) begin + #3; + dinA <= dinA + 1; + end + + always @( posedge clk, posedge dinA[1], posedge dinA[2] ) + if ( dinA[2] ) + dff <= 1'b0; + else if ( dinA[1] ) + dff <= 1'b1; + else + dff <= dinA[0]; + + always @( negedge clk, negedge dinA[1], negedge dinA[2] ) + if ( !dinA[2] ) + ndff <= 1'b0; + else if ( !dinA[1] ) + ndff <= 1'b1; + else + ndff <= dinA[0]; + + always @( posedge clk, posedge dinA[2] ) + if ( dinA[2] ) + adff <= 1'b0; + else + adff <= dinA[0]; + + always @( posedge clk, negedge dinA[2] ) + if ( !dinA[2] ) + adffn <= 1'b0; + else + adffn <= dinA[0]; + + always @( posedge clk ) + if ( dinA[2] ) + dffe <= dinA[0]; + + assert_dff dff_test(.clk(clk), .test(doutB), .pat(dff)); + assert_dff ndff_test(.clk(clk), .test(doutB1), .pat(ndff)); + assert_dff adff_test(.clk(clk), .test(doutB2), .pat(adff)); + //assert_dff adffn_test(.clk(clk), .test(doutB3), .pat(adffn)); + //assert_dff dffe_test(.clk(clk), .test(doutB4), .pat(dffe)); + +endmodule diff --git a/tests/ice40/common.v b/tests/ice40/common.v new file mode 100644 index 000000000..5446f0817 --- /dev/null +++ b/tests/ice40/common.v @@ -0,0 +1,47 @@ +module assert_dff(input clk, input test, input pat); + always @(posedge clk) + begin + #1; + if (test != pat) + begin + $display("ERROR: ASSERTION FAILED in %m:",$time); + $stop; + end + end +endmodule + +module assert_tri(input en, input A, input B); + always @(posedge en) + begin + #1; + if (A !== B) + begin + $display("ERROR: ASSERTION FAILED in %m:",$time," ",A," ",B); + $stop; + end + end +endmodule + +module assert_Z(input clk, input A); + always @(posedge clk) + begin + #1; + if (A === 1'bZ) + begin + $display("ERROR: ASSERTION FAILED in %m:",$time," ",A); + $stop; + end + end +endmodule + +module assert_comb(input A, input B); + always @(*) + begin + #1; + if (A !== B) + begin + $display("ERROR: ASSERTION FAILED in %m:",$time," ",A," ",B); + $stop; + end + end +endmodule diff --git a/tests/ice40/dffs.v b/tests/ice40/dffs.v index af7022c79..d57c8c97c 100644 --- a/tests/ice40/dffs.v +++ b/tests/ice40/dffs.v @@ -1,108 +1,5 @@ -module adff - ( input d, clk, clr, output reg q ); - initial begin - q = 0; - end - always @( posedge clk, posedge clr ) - if ( clr ) - q <= 1'b0; - else - q <= d; -endmodule - -module adffn - ( input d, clk, clr, output reg q ); - initial begin - q = 0; - end - always @( posedge clk, negedge clr ) - if ( !clr ) - q <= 1'b0; - else - q <= d; -endmodule - -module dffe - ( input d, clk, en, output reg q ); - initial begin - q = 0; - end +module top + ( input d, clk, output reg q ); always @( posedge clk ) - if ( en ) - q <= d; -endmodule - -module dffsr - ( input d, clk, pre, clr, output reg q ); - initial begin - q = 0; - end - always @( posedge clk, posedge pre, posedge clr ) - if ( clr ) - q <= 1'b0; - else if ( pre ) - q <= 1'b1; - else - q <= d; -endmodule - -module ndffnsnr - ( input d, clk, pre, clr, output reg q ); - initial begin - q = 0; - end - always @( negedge clk, negedge pre, negedge clr ) - if ( !clr ) - q <= 1'b0; - else if ( !pre ) - q <= 1'b1; - else q <= d; endmodule - -module top ( -input clk, -input clr, -input pre, -input a, -output b,b1,b2,b3,b4 -); - -dffsr u_dffsr ( - .clk (clk ), - .clr (clr), - .pre (pre), - .d (a ), - .q (b ) - ); - -ndffnsnr u_ndffnsnr ( - .clk (clk ), - .clr (clr), - .pre (pre), - .d (a ), - .q (b1 ) - ); - -adff u_adff ( - .clk (clk ), - .clr (clr), - .d (a ), - .q (b2 ) - ); - -adffn u_adffn ( - .clk (clk ), - .clr (clr), - .d (a ), - .q (b3 ) - ); - -dffe u_dffe ( - .clk (clk ), - .en (clr), - .d (a ), - .q (b4 ) - ); - -endmodule diff --git a/tests/ice40/dffs.ys b/tests/ice40/dffs.ys index 09b7bc25a..0fa0bc3eb 100644 --- a/tests/ice40/dffs.ys +++ b/tests/ice40/dffs.ys @@ -1,12 +1,11 @@ +read_verilog dffs.v proc flatten dff2dffe -synth_ice40 -#equiv_opt -assert -map +/ice40/cells_sim.v -map +/simcells.v synth_ice40 -equiv_opt -map +/ice40/cells_sim.v -map +/simcells.v synth_ice40 -design -load postopt -select -assert-count 2 t:SB_DFFR -select -assert-count 1 t:SB_DFFE -select -assert-count 4 t:SB_LUT4 -select -assert-count 1 t:$_DFFSR_PPP_ -select -assert-count 1 t:$_DFFSR_NPP_ +hierarchy -top top +synth -flatten -run coarse # technology-independent coarse grained synthesis +equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check same as technology-dependent fine-grained synthesis +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module +select -assert-count 1 t:SB_DFF +select -assert-none t:SB_DFF %% t:* %D diff --git a/tests/ice40/div_mod.ys b/tests/ice40/div_mod.ys index f66cb99dd..93285cede 100644 --- a/tests/ice40/div_mod.ys +++ b/tests/ice40/div_mod.ys @@ -1,6 +1,9 @@ -synth_ice40 -#equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 -equiv_opt -map +/ice40/cells_sim.v synth_ice40 -design -load postopt -select -assert-count 85 t:SB_LUT4 -select -assert-count 54 t:SB_CARRY +read_verilog div_mod.v +hierarchy -top top +synth -flatten -run coarse # technology-independent coarse grained synthesis +equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check same as technology-dependent fine-grained synthesis +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module +select -assert-count 88 t:SB_LUT4 +select -assert-count 65 t:SB_CARRY +select -assert-none t:SB_LUT4 t:SB_CARRY %% t:* %D diff --git a/tests/ice40/latches.ys b/tests/ice40/latches.ys index 77037b1d5..0abd7f195 100644 --- a/tests/ice40/latches.ys +++ b/tests/ice40/latches.ys @@ -1,6 +1,5 @@ +read_verilog latches.v synth_ice40 -#equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 -equiv_opt -map +/ice40/cells_sim.v synth_ice40 -design -load postopt -proc select -assert-count 5 t:SB_LUT4 +#select -assert-none t:SB_LUT4 %% t:* %D +write_verilog latches_synth.v diff --git a/tests/ice40/latches_tb.v b/tests/ice40/latches_tb.v new file mode 100644 index 000000000..47ae8670c --- /dev/null +++ b/tests/ice40/latches_tb.v @@ -0,0 +1,59 @@ +module testbench; + reg clk; + + initial begin + // $dumpfile("testbench.vcd"); + // $dumpvars(0, testbench); + + #5 clk = 0; + repeat (10000) begin + #5 clk = 1; + #5 clk = 0; + end + + $display("OKAY"); + end + + + reg [2:0] dinA = 0; + wire doutB,doutB1,doutB2; + reg lat,latn,latsr = 0; + + top uut ( + .clk (clk ), + .a (dinA[0] ), + .pre (dinA[1] ), + .clr (dinA[2] ), + .b (doutB ), + .b1 (doutB1 ), + .b2 (doutB2 ) + ); + + always @(posedge clk) begin + #3; + dinA <= dinA + 1; + end + + always @* + if ( clk ) + lat <= dinA[0]; + + + always @* + if ( !clk ) + latn <= dinA[0]; + + + always @* + if ( dinA[2] ) + latsr <= 1'b0; + else if ( dinA[1] ) + latsr <= 1'b1; + else if ( clk ) + latsr <= dinA[0]; + + assert_dff lat_test(.clk(clk), .test(doutB), .pat(lat)); + assert_dff latn_test(.clk(clk), .test(doutB1), .pat(latn)); + assert_dff latsr_test(.clk(clk), .test(doutB2), .pat(latsr)); + +endmodule diff --git a/tests/ice40/memory.ys b/tests/ice40/memory.ys index 47d5526c1..a0391e93d 100644 --- a/tests/ice40/memory.ys +++ b/tests/ice40/memory.ys @@ -1,8 +1,4 @@ -proc -memory +read_verilog memory.v synth_ice40 -equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 -design -load postopt - -select -assert-count 8 t:SB_DFF -select -assert-count 512 t:SB_DFFE +select -assert-count 1 t:SB_RAM40_4K +write_verilog memory_synth.v diff --git a/tests/ice40/memory_tb.v b/tests/ice40/memory_tb.v new file mode 100644 index 000000000..5905f3ddd --- /dev/null +++ b/tests/ice40/memory_tb.v @@ -0,0 +1,81 @@ +module testbench; + reg clk; + + initial begin + // $dumpfile("testbench.vcd"); + // $dumpvars(0, testbench); + + #5 clk = 0; + repeat (10000) begin + #5 clk = 1; + #5 clk = 0; + end + + $display("OKAY"); + end + + + reg [7:0] data_a = 0; + reg [5:0] addr_a = 0; + reg we_a = 0; + reg re_a = 1; + wire [7:0] q_a; + reg mem_init = 0; + + reg [7:0] pq_a; + + top uut ( + .data_a(data_a), + .addr_a(addr_a), + .we_a(we_a), + .clk(clk), + .q_a(q_a) + ); + + always @(posedge clk) begin + #3; + data_a <= data_a + 17; + + addr_a <= addr_a + 1; + end + + always @(posedge addr_a) begin + #10; + if(addr_a > 6'h3E) + mem_init <= 1; + end + + always @(posedge clk) begin + //#3; + we_a <= !we_a; + end + + // Declare the RAM variable for check + reg [7:0] ram[63:0]; + + // Port A for check + always @ (posedge clk) + begin + if (we_a) + begin + ram[addr_a] <= data_a; + pq_a <= data_a; + end + pq_a <= ram[addr_a]; + end + + uut_mem_checker port_a_test(.clk(clk), .init(mem_init), .en(!we_a), .A(q_a), .B(pq_a)); + +endmodule + +module uut_mem_checker(input clk, input init, input en, input [7:0] A, input [7:0] B); + always @(posedge clk) + begin + #1; + if (en == 1 & init == 1 & A !== B) + begin + $display("ERROR: ASSERTION FAILED in %m:",$time," ",A," ",B); + $stop; + end + end +endmodule diff --git a/tests/ice40/mul.v b/tests/ice40/mul.v new file mode 100644 index 000000000..c099db0d9 --- /dev/null +++ b/tests/ice40/mul.v @@ -0,0 +1,12 @@ +module top +( + input [3:0] x, + input [3:0] y, + + output [3:0] A, + output [3:0] B + ); + +assign A = x * y; + +endmodule diff --git a/tests/ice40/mul.ys b/tests/ice40/mul.ys new file mode 100644 index 000000000..35048d14a --- /dev/null +++ b/tests/ice40/mul.ys @@ -0,0 +1,9 @@ +read_verilog mul.v +hierarchy -top top +synth -flatten -run coarse # technology-independent coarse grained synthesis +equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 -dsp # equivalency check same as technology-dependent fine-grained synthesis +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module +select -assert-count 15 t:SB_LUT4 +select -assert-count 3 t:SB_CARRY +select -assert-none t:SB_LUT4 t:SB_CARRY %% t:* %D diff --git a/tests/ice40/mul_pow.v b/tests/ice40/mul_pow.v deleted file mode 100644 index 6c256d96b..000000000 --- a/tests/ice40/mul_pow.v +++ /dev/null @@ -1,13 +0,0 @@ -module top -( - input [3:0] x, - input [3:0] y, - - output [3:0] A, - output [3:0] B - ); - -assign A = x * y; -assign B = x ** y; - -endmodule diff --git a/tests/ice40/mul_pow.ys b/tests/ice40/mul_pow.ys deleted file mode 100644 index 2a6baa738..000000000 --- a/tests/ice40/mul_pow.ys +++ /dev/null @@ -1,7 +0,0 @@ -synth_ice40 -#equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 -equiv_opt -map +/ice40/cells_sim.v synth_ice40 -design -load postopt -select -assert-count 16 t:SB_LUT4 -select -assert-count 4 t:SB_CARRY -select -assert-count 1 t:$pow diff --git a/tests/ice40/mux.ys b/tests/ice40/mux.ys index 3da9ef433..9e3d87b7f 100644 --- a/tests/ice40/mux.ys +++ b/tests/ice40/mux.ys @@ -1,4 +1,4 @@ - +read_verilog mux.v synth_ice40 equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 design -load postopt diff --git a/tests/ice40/run-test.sh b/tests/ice40/run-test.sh index 75e5f0609..5bd9fb173 100755 --- a/tests/ice40/run-test.sh +++ b/tests/ice40/run-test.sh @@ -1,6 +1,33 @@ -#!/bin/bash set -e -for x in *.v; do - echo "Running $x.." - ../../yosys -q -s ${x%.v}.ys -l ./temp/${x%.v}.log $x +if [ -f "../../../../../techlibs/common/simcells.v" ]; then + COMMON_PREFIX=../../../../../techlibs/common + TECHLIBS_PREFIX=../../../../../techlibs +else + COMMON_PREFIX=/usr/local/share/yosys + TECHLIBS_PREFIX=/usr/local/share/yosys +fi +{ +echo "all::" +for x in *.ys; do + echo "all:: run-$x" + echo "run-$x:" + echo " @echo 'Running $x..'" + echo " @../../yosys -ql ${x%.ys}.log $x" done +for t in *_tb.v; do + echo "all:: run-$t" + echo "run-$t:" + echo " @echo 'Running $t..'" + echo " @iverilog -o ${t%_tb.v}_testbench $t ${t%_tb.v}_synth.v common.v $COMMON_PREFIX/simcells.v $TECHLIBS_PREFIX/ice40/cells_sim.v" + echo " @if ! vvp -N ${t%_tb.v}_testbench > ${t%_tb.v}_testbench.log 2>&1; then grep 'ERROR' ${t%_tb.v}_testbench.log; exit 0; elif grep 'ERROR' ${t%_tb.v}_testbench.log || ! grep 'OKAY' ${t%_tb.v}_testbench.log; then echo "FAIL"; exit 0; fi" +done +for s in *.sh; do + if [ "$s" != "run-test.sh" ]; then + echo "all:: run-$s" + echo "run-$s:" + echo " @echo 'Running $s..'" + echo " @bash $s" + fi +done +} > run-test.mk +exec ${MAKE:-make} -f run-test.mk diff --git a/tests/ice40/temp/.gitignore b/tests/ice40/temp/.gitignore deleted file mode 100644 index 397b4a762..000000000 --- a/tests/ice40/temp/.gitignore +++ /dev/null @@ -1 +0,0 @@ -*.log diff --git a/tests/ice40/tribuf.v b/tests/ice40/tribuf.v index b2b5e37d6..870a02584 100644 --- a/tests/ice40/tribuf.v +++ b/tests/ice40/tribuf.v @@ -1,10 +1,10 @@ module tristate (en, i, o); input en; input i; - output reg o; + output o; + + assign o = en ? i : 1'bz; - always @(en or i) - o <= (en)? i : 1'bZ; endmodule diff --git a/tests/ice40/tribuf.ys b/tests/ice40/tribuf.ys index b319e6622..9b7ea1eab 100644 --- a/tests/ice40/tribuf.ys +++ b/tests/ice40/tribuf.ys @@ -1,6 +1,8 @@ -synth_ice40 -equiv_opt -assert -map +/ice40/cells_sim.v -map +/simcells.v synth_ice40 -design -load postopt -select -assert-count 1 t:SB_LUT4 -select -assert-count 1 t:SB_CARRY +read_verilog tribuf.v +hierarchy -top top +synth -flatten -run coarse # technology-independent coarse grained synthesis +equiv_opt -map +/ice40/cells_sim.v synth_ice40 # equivalency check same as technology-dependent fine-grained synthesis +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module select -assert-count 1 t:$_TBUF_ +select -assert-none t:$_TBUF_ %% t:* %D -- cgit v1.2.3 From a6776ee35ee5404ca7d5b63fd2daccc46354112c Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Wed, 21 Aug 2019 13:36:01 -0700 Subject: mem2reg to preserve user attributes and src --- tests/various/mem2reg.ys | 13 +++++++++++++ 1 file changed, 13 insertions(+) create mode 100644 tests/various/mem2reg.ys (limited to 'tests') diff --git a/tests/various/mem2reg.ys b/tests/various/mem2reg.ys new file mode 100644 index 000000000..00389c700 --- /dev/null +++ b/tests/various/mem2reg.ys @@ -0,0 +1,13 @@ +read_verilog < Date: Wed, 21 Aug 2019 21:58:20 -0700 Subject: Add test --- tests/opt/opt_expr.ys | 14 ++++++++++++++ 1 file changed, 14 insertions(+) (limited to 'tests') diff --git a/tests/opt/opt_expr.ys b/tests/opt/opt_expr.ys index f0306efa1..4affc1ac8 100644 --- a/tests/opt/opt_expr.ys +++ b/tests/opt/opt_expr.ys @@ -221,3 +221,17 @@ check equiv_opt opt_expr -fine design -load postopt select -assert-count 1 t:$alu r:A_WIDTH=8 r:B_WIDTH=8 r:Y_WIDTH=9 %i %i %i + +########### + +design -reset +read_verilog -icells < Date: Thu, 22 Aug 2019 08:22:23 -0700 Subject: Handle $shift and Y_WIDTH > 1 as per @cliffordwolf --- tests/opt/opt_expr.ys | 44 +++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 43 insertions(+), 1 deletion(-) (limited to 'tests') diff --git a/tests/opt/opt_expr.ys b/tests/opt/opt_expr.ys index 4affc1ac8..02be20a62 100644 --- a/tests/opt/opt_expr.ys +++ b/tests/opt/opt_expr.ys @@ -226,7 +226,7 @@ select -assert-count 1 t:$alu r:A_WIDTH=8 r:B_WIDTH=8 r:Y_WIDTH=9 %i %i %i design -reset read_verilog -icells < Date: Thu, 22 Aug 2019 08:37:27 -0700 Subject: Respect opt_expr -keepdc as per @cliffordwolf --- tests/opt/opt_expr.ys | 14 ++++++++++++++ 1 file changed, 14 insertions(+) (limited to 'tests') diff --git a/tests/opt/opt_expr.ys b/tests/opt/opt_expr.ys index 02be20a62..ecc2c8da8 100644 --- a/tests/opt/opt_expr.ys +++ b/tests/opt/opt_expr.ys @@ -277,3 +277,17 @@ check equiv_opt opt_expr design -load postopt select -assert-count 1 t:$shift r:A_WIDTH=10 %i + +########### + +design -reset +read_verilog -icells < Date: Thu, 22 Aug 2019 12:17:25 -0700 Subject: Make multiplier wider, do not do tech independent synth --- tests/ice40/mul.v | 7 +++---- tests/ice40/mul.ys | 7 +++---- 2 files changed, 6 insertions(+), 8 deletions(-) (limited to 'tests') diff --git a/tests/ice40/mul.v b/tests/ice40/mul.v index c099db0d9..d5b48b1d7 100644 --- a/tests/ice40/mul.v +++ b/tests/ice40/mul.v @@ -1,10 +1,9 @@ module top ( - input [3:0] x, - input [3:0] y, + input [5:0] x, + input [5:0] y, - output [3:0] A, - output [3:0] B + output [11:0] A, ); assign A = x * y; diff --git a/tests/ice40/mul.ys b/tests/ice40/mul.ys index 35048d14a..adf1b3211 100644 --- a/tests/ice40/mul.ys +++ b/tests/ice40/mul.ys @@ -1,9 +1,8 @@ read_verilog mul.v hierarchy -top top -synth -flatten -run coarse # technology-independent coarse grained synthesis +#synth -flatten -run coarse # technology-independent coarse grained synthesis equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 -dsp # equivalency check same as technology-dependent fine-grained synthesis design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd top # Constrain all select calls below inside the top module -select -assert-count 15 t:SB_LUT4 -select -assert-count 3 t:SB_CARRY -select -assert-none t:SB_LUT4 t:SB_CARRY %% t:* %D +select -assert-count 1 t:SB_MAC16 +select -assert-none t:SB_MAC16 %% t:* %D -- cgit v1.2.3 From 9e537a76b5a0487e0788054091132d2fd7f1a0dd Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 22 Aug 2019 12:20:18 -0700 Subject: Move $dffe to dffs.{v,ys} --- tests/ice40/adffs.v | 10 ---------- tests/ice40/adffs.ys | 9 ++++++--- tests/ice40/dffs.v | 34 +++++++++++++++++++++++++++++++++- tests/ice40/dffs.ys | 6 ++---- 4 files changed, 41 insertions(+), 18 deletions(-) (limited to 'tests') diff --git a/tests/ice40/adffs.v b/tests/ice40/adffs.v index af7022c79..972184cfa 100644 --- a/tests/ice40/adffs.v +++ b/tests/ice40/adffs.v @@ -22,16 +22,6 @@ module adffn q <= d; endmodule -module dffe - ( input d, clk, en, output reg q ); - initial begin - q = 0; - end - always @( posedge clk ) - if ( en ) - q <= d; -endmodule - module dffsr ( input d, clk, pre, clr, output reg q ); initial begin diff --git a/tests/ice40/adffs.ys b/tests/ice40/adffs.ys index aee8cd6b4..d58ce1a82 100644 --- a/tests/ice40/adffs.ys +++ b/tests/ice40/adffs.ys @@ -1,8 +1,11 @@ read_verilog adffs.v proc -dff2dffe -synth_ice40 -select -assert-count 2 t:SB_DFFR +async2sync +synth -flatten -run coarse # technology-independent coarse grained synthesis +equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check same as technology-dependent fine-grained synthesis +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module +select -assert-count 1 t:SB_DFF select -assert-count 1 t:SB_DFFE select -assert-count 4 t:SB_LUT4 #select -assert-none t:SB_LUT4 t:SB_DFFR t:SB_DFFE t:$_DFFSR_NPP_ t:$_DFFSR_PPP_ %% t:* %D diff --git a/tests/ice40/dffs.v b/tests/ice40/dffs.v index d57c8c97c..d97840c43 100644 --- a/tests/ice40/dffs.v +++ b/tests/ice40/dffs.v @@ -1,5 +1,37 @@ -module top +module dff ( input d, clk, output reg q ); always @( posedge clk ) q <= d; endmodule + +module dffe + ( input d, clk, en, output reg q ); + initial begin + q = 0; + end + always @( posedge clk ) + if ( en ) + q <= d; +endmodule + +module top ( +input clk, +input en, +input a, +output b,b1, +); + +dff u_dff ( + .clk (clk ), + .d (a ), + .q (b ) + ); + +dffe u_ndffe ( + .clk (clk ), + .en (en), + .d (a ), + .q (b1 ) + ); + +endmodule diff --git a/tests/ice40/dffs.ys b/tests/ice40/dffs.ys index 0fa0bc3eb..ddd8e5734 100644 --- a/tests/ice40/dffs.ys +++ b/tests/ice40/dffs.ys @@ -1,11 +1,9 @@ read_verilog dffs.v -proc -flatten -dff2dffe hierarchy -top top synth -flatten -run coarse # technology-independent coarse grained synthesis equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check same as technology-dependent fine-grained synthesis design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd top # Constrain all select calls below inside the top module select -assert-count 1 t:SB_DFF -select -assert-none t:SB_DFF %% t:* %D +select -assert-count 1 t:SB_DFFE +select -assert-none t:SB_DFF t:SB_DFFE %% t:* %D -- cgit v1.2.3 From 388eb3288c907dbc8b2763ffc20b0b5fccba81ed Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 22 Aug 2019 12:21:54 -0700 Subject: Remove dffe instantation --- tests/ice40/adffs.v | 7 ------- 1 file changed, 7 deletions(-) (limited to 'tests') diff --git a/tests/ice40/adffs.v b/tests/ice40/adffs.v index 972184cfa..e09ef52e1 100644 --- a/tests/ice40/adffs.v +++ b/tests/ice40/adffs.v @@ -88,11 +88,4 @@ adffn u_adffn ( .q (b3 ) ); -dffe u_dffe ( - .clk (clk ), - .en (clr), - .d (a ), - .q (b4 ) - ); - endmodule -- cgit v1.2.3 From 9224b3bc1721ae45abf11594b3ab9a58e50aa86f Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 22 Aug 2019 12:30:49 -0700 Subject: Remove tech independent synthesis --- tests/ice40/add_sub.ys | 1 - tests/ice40/adffs.ys | 10 +++++----- tests/ice40/dffs.ys | 3 ++- tests/ice40/div_mod.ys | 2 +- tests/ice40/latches.ys | 5 +++-- tests/ice40/memory.ys | 1 + tests/ice40/mul.ys | 1 - tests/ice40/mux.ys | 8 +++++--- tests/ice40/tribuf.ys | 5 +++-- 9 files changed, 20 insertions(+), 16 deletions(-) (limited to 'tests') diff --git a/tests/ice40/add_sub.ys b/tests/ice40/add_sub.ys index 84f31ec53..8eeb221db 100644 --- a/tests/ice40/add_sub.ys +++ b/tests/ice40/add_sub.ys @@ -1,6 +1,5 @@ read_verilog add_sub.v hierarchy -top top -synth -flatten -run coarse # technology-independent coarse grained synthesis equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check same as technology-dependent fine-grained synthesis design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd top # Constrain all select calls below inside the top module diff --git a/tests/ice40/adffs.ys b/tests/ice40/adffs.ys index d58ce1a82..3c676e590 100644 --- a/tests/ice40/adffs.ys +++ b/tests/ice40/adffs.ys @@ -1,12 +1,12 @@ read_verilog adffs.v proc async2sync -synth -flatten -run coarse # technology-independent coarse grained synthesis +flatten equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check same as technology-dependent fine-grained synthesis design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd top # Constrain all select calls below inside the top module select -assert-count 1 t:SB_DFF -select -assert-count 1 t:SB_DFFE -select -assert-count 4 t:SB_LUT4 -#select -assert-none t:SB_LUT4 t:SB_DFFR t:SB_DFFE t:$_DFFSR_NPP_ t:$_DFFSR_PPP_ %% t:* %D -write_verilog adffs_synth.v +select -assert-count 1 t:SB_DFFN +select -assert-count 2 t:SB_DFFSR +select -assert-count 7 t:SB_LUT4 +select -assert-none t:SB_DFF t:SB_DFFN t:SB_DFFSR t:SB_LUT4 %% t:* %D diff --git a/tests/ice40/dffs.ys b/tests/ice40/dffs.ys index ddd8e5734..b14346f5a 100644 --- a/tests/ice40/dffs.ys +++ b/tests/ice40/dffs.ys @@ -1,6 +1,7 @@ read_verilog dffs.v hierarchy -top top -synth -flatten -run coarse # technology-independent coarse grained synthesis +proc +flatten equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check same as technology-dependent fine-grained synthesis design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd top # Constrain all select calls below inside the top module diff --git a/tests/ice40/div_mod.ys b/tests/ice40/div_mod.ys index 93285cede..613cad760 100644 --- a/tests/ice40/div_mod.ys +++ b/tests/ice40/div_mod.ys @@ -1,6 +1,6 @@ read_verilog div_mod.v hierarchy -top top -synth -flatten -run coarse # technology-independent coarse grained synthesis +flatten equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check same as technology-dependent fine-grained synthesis design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd top # Constrain all select calls below inside the top module diff --git a/tests/ice40/latches.ys b/tests/ice40/latches.ys index 0abd7f195..fe0d1f70e 100644 --- a/tests/ice40/latches.ys +++ b/tests/ice40/latches.ys @@ -1,5 +1,6 @@ read_verilog latches.v synth_ice40 -select -assert-count 5 t:SB_LUT4 -#select -assert-none t:SB_LUT4 %% t:* %D +cd top +select -assert-count 4 t:SB_LUT4 +select -assert-none t:SB_LUT4 %% t:* %D write_verilog latches_synth.v diff --git a/tests/ice40/memory.ys b/tests/ice40/memory.ys index a0391e93d..0a8c48dca 100644 --- a/tests/ice40/memory.ys +++ b/tests/ice40/memory.ys @@ -1,4 +1,5 @@ read_verilog memory.v synth_ice40 +cd top select -assert-count 1 t:SB_RAM40_4K write_verilog memory_synth.v diff --git a/tests/ice40/mul.ys b/tests/ice40/mul.ys index adf1b3211..aec7d0b1f 100644 --- a/tests/ice40/mul.ys +++ b/tests/ice40/mul.ys @@ -1,6 +1,5 @@ read_verilog mul.v hierarchy -top top -#synth -flatten -run coarse # technology-independent coarse grained synthesis equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 -dsp # equivalency check same as technology-dependent fine-grained synthesis design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd top # Constrain all select calls below inside the top module diff --git a/tests/ice40/mux.ys b/tests/ice40/mux.ys index 9e3d87b7f..63d22001f 100644 --- a/tests/ice40/mux.ys +++ b/tests/ice40/mux.ys @@ -1,6 +1,8 @@ read_verilog mux.v -synth_ice40 +proc +flatten equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 design -load postopt -select -assert-count 20 t:SB_LUT4 -select -assert-count 1 t:SB_CARRY +cd top +select -assert-count 19 t:SB_LUT4 +select -assert-none t:SB_LUT4 %% t:* %D diff --git a/tests/ice40/tribuf.ys b/tests/ice40/tribuf.ys index 9b7ea1eab..8049a37ab 100644 --- a/tests/ice40/tribuf.ys +++ b/tests/ice40/tribuf.ys @@ -1,7 +1,8 @@ read_verilog tribuf.v hierarchy -top top -synth -flatten -run coarse # technology-independent coarse grained synthesis -equiv_opt -map +/ice40/cells_sim.v synth_ice40 # equivalency check same as technology-dependent fine-grained synthesis +proc +flatten +equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check same as technology-dependent fine-grained synthesis design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd top # Constrain all select calls below inside the top module select -assert-count 1 t:$_TBUF_ -- cgit v1.2.3 From f9906eed68beab359ed83beee2bcf42ffac908c3 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 22 Aug 2019 12:35:35 -0700 Subject: Fix comments --- tests/ice40/add_sub.ys | 2 +- tests/ice40/adffs.ys | 4 ++-- tests/ice40/dffs.ys | 2 +- tests/ice40/div_mod.ys | 2 +- tests/ice40/memory.ys | 1 + tests/ice40/mul.ys | 2 +- tests/ice40/mux.ys | 6 +++--- tests/ice40/tribuf.ys | 2 +- 8 files changed, 11 insertions(+), 10 deletions(-) (limited to 'tests') diff --git a/tests/ice40/add_sub.ys b/tests/ice40/add_sub.ys index 8eeb221db..4a998d98d 100644 --- a/tests/ice40/add_sub.ys +++ b/tests/ice40/add_sub.ys @@ -1,6 +1,6 @@ read_verilog add_sub.v hierarchy -top top -equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check same as technology-dependent fine-grained synthesis +equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd top # Constrain all select calls below inside the top module select -assert-count 11 t:SB_LUT4 diff --git a/tests/ice40/adffs.ys b/tests/ice40/adffs.ys index 3c676e590..14b251c5c 100644 --- a/tests/ice40/adffs.ys +++ b/tests/ice40/adffs.ys @@ -1,8 +1,8 @@ read_verilog adffs.v proc -async2sync +async2sync # converts async flops to a 'sync' variant clocked by a 'super'-clock flatten -equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check same as technology-dependent fine-grained synthesis +equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd top # Constrain all select calls below inside the top module select -assert-count 1 t:SB_DFF diff --git a/tests/ice40/dffs.ys b/tests/ice40/dffs.ys index b14346f5a..ee7f884b1 100644 --- a/tests/ice40/dffs.ys +++ b/tests/ice40/dffs.ys @@ -2,7 +2,7 @@ read_verilog dffs.v hierarchy -top top proc flatten -equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check same as technology-dependent fine-grained synthesis +equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd top # Constrain all select calls below inside the top module select -assert-count 1 t:SB_DFF diff --git a/tests/ice40/div_mod.ys b/tests/ice40/div_mod.ys index 613cad760..96753b4ef 100644 --- a/tests/ice40/div_mod.ys +++ b/tests/ice40/div_mod.ys @@ -1,7 +1,7 @@ read_verilog div_mod.v hierarchy -top top flatten -equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check same as technology-dependent fine-grained synthesis +equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd top # Constrain all select calls below inside the top module select -assert-count 88 t:SB_LUT4 diff --git a/tests/ice40/memory.ys b/tests/ice40/memory.ys index 0a8c48dca..fa5d004b0 100644 --- a/tests/ice40/memory.ys +++ b/tests/ice40/memory.ys @@ -2,4 +2,5 @@ read_verilog memory.v synth_ice40 cd top select -assert-count 1 t:SB_RAM40_4K +select -assert-none t:SB_RAM40_4K %% t:* %D write_verilog memory_synth.v diff --git a/tests/ice40/mul.ys b/tests/ice40/mul.ys index aec7d0b1f..8a0822a84 100644 --- a/tests/ice40/mul.ys +++ b/tests/ice40/mul.ys @@ -1,6 +1,6 @@ read_verilog mul.v hierarchy -top top -equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 -dsp # equivalency check same as technology-dependent fine-grained synthesis +equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 -dsp # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd top # Constrain all select calls below inside the top module select -assert-count 1 t:SB_MAC16 diff --git a/tests/ice40/mux.ys b/tests/ice40/mux.ys index 63d22001f..182b49499 100644 --- a/tests/ice40/mux.ys +++ b/tests/ice40/mux.ys @@ -1,8 +1,8 @@ read_verilog mux.v proc flatten -equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 -design -load postopt -cd top +equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module select -assert-count 19 t:SB_LUT4 select -assert-none t:SB_LUT4 %% t:* %D diff --git a/tests/ice40/tribuf.ys b/tests/ice40/tribuf.ys index 8049a37ab..ef4266959 100644 --- a/tests/ice40/tribuf.ys +++ b/tests/ice40/tribuf.ys @@ -2,7 +2,7 @@ read_verilog tribuf.v hierarchy -top top proc flatten -equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check same as technology-dependent fine-grained synthesis +equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd top # Constrain all select calls below inside the top module select -assert-count 1 t:$_TBUF_ -- cgit v1.2.3 From 61087329efcfac45de6b69ded33f38c8f8817eef Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 22 Aug 2019 12:36:27 -0700 Subject: Fix tribuf test --- tests/ice40/tribuf.ys | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'tests') diff --git a/tests/ice40/tribuf.ys b/tests/ice40/tribuf.ys index ef4266959..d1e1b3108 100644 --- a/tests/ice40/tribuf.ys +++ b/tests/ice40/tribuf.ys @@ -2,7 +2,7 @@ read_verilog tribuf.v hierarchy -top top proc flatten -equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check +equiv_opt -assert -map +/ice40/cells_sim.v -map +/simcells.v synth_ice40 # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd top # Constrain all select calls below inside the top module select -assert-count 1 t:$_TBUF_ -- cgit v1.2.3 From 659a481482b59efd672034bff9e034fa6d47336c Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 22 Aug 2019 13:57:11 -0700 Subject: Remove unused output --- tests/ice40/adffs.v | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'tests') diff --git a/tests/ice40/adffs.v b/tests/ice40/adffs.v index e09ef52e1..93c8bf52c 100644 --- a/tests/ice40/adffs.v +++ b/tests/ice40/adffs.v @@ -55,7 +55,7 @@ input clk, input clr, input pre, input a, -output b,b1,b2,b3,b4 +output b,b1,b2,b3 ); dffsr u_dffsr ( -- cgit v1.2.3 From 8e3754bdb468842a784ef5eac8427a59055673c3 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 22 Aug 2019 13:57:19 -0700 Subject: Hide tri-state warning message for now --- tests/ice40/.gitignore | 1 + tests/ice40/run-test.sh | 2 +- 2 files changed, 2 insertions(+), 1 deletion(-) (limited to 'tests') diff --git a/tests/ice40/.gitignore b/tests/ice40/.gitignore index 397b4a762..1d329c933 100644 --- a/tests/ice40/.gitignore +++ b/tests/ice40/.gitignore @@ -1 +1,2 @@ *.log +/run-test.mk diff --git a/tests/ice40/run-test.sh b/tests/ice40/run-test.sh index 5bd9fb173..184d8f09b 100755 --- a/tests/ice40/run-test.sh +++ b/tests/ice40/run-test.sh @@ -12,7 +12,7 @@ for x in *.ys; do echo "all:: run-$x" echo "run-$x:" echo " @echo 'Running $x..'" - echo " @../../yosys -ql ${x%.ys}.log $x" + echo " @../../yosys -ql ${x%.ys}.log $x -w 'Yosys has only limited support for tri-state logic at the moment.'" done for t in *_tb.v; do echo "all:: run-$t" -- cgit v1.2.3 From 5061d239ae2d6881b898662f838a0f4cfc24ca88 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 22 Aug 2019 14:03:02 -0700 Subject: Fail if iverilog fails --- tests/ice40/run-test.sh | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'tests') diff --git a/tests/ice40/run-test.sh b/tests/ice40/run-test.sh index 184d8f09b..90a8a3c83 100755 --- a/tests/ice40/run-test.sh +++ b/tests/ice40/run-test.sh @@ -18,8 +18,8 @@ for t in *_tb.v; do echo "all:: run-$t" echo "run-$t:" echo " @echo 'Running $t..'" - echo " @iverilog -o ${t%_tb.v}_testbench $t ${t%_tb.v}_synth.v common.v $COMMON_PREFIX/simcells.v $TECHLIBS_PREFIX/ice40/cells_sim.v" - echo " @if ! vvp -N ${t%_tb.v}_testbench > ${t%_tb.v}_testbench.log 2>&1; then grep 'ERROR' ${t%_tb.v}_testbench.log; exit 0; elif grep 'ERROR' ${t%_tb.v}_testbench.log || ! grep 'OKAY' ${t%_tb.v}_testbench.log; then echo "FAIL"; exit 0; fi" + echo " @iverilog -o ${t%_tb.v}_testbench $t ${t%_tb.v}_synth.v common.v $TECHLIBS_PREFIX/ice40/cells_sim.v" + echo " @vvp -N ${t%_tb.v}_testbench" done for s in *.sh; do if [ "$s" != "run-test.sh" ]; then -- cgit v1.2.3 From 43e7c4917ad42b01d34b496c35798416a050aa61 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 22 Aug 2019 15:50:38 -0700 Subject: Do not print OKAY --- tests/ice40/latches_tb.v | 2 -- tests/ice40/memory_tb.v | 2 -- 2 files changed, 4 deletions(-) (limited to 'tests') diff --git a/tests/ice40/latches_tb.v b/tests/ice40/latches_tb.v index 47ae8670c..b0585264b 100644 --- a/tests/ice40/latches_tb.v +++ b/tests/ice40/latches_tb.v @@ -10,8 +10,6 @@ module testbench; #5 clk = 1; #5 clk = 0; end - - $display("OKAY"); end diff --git a/tests/ice40/memory_tb.v b/tests/ice40/memory_tb.v index 5905f3ddd..be69374eb 100644 --- a/tests/ice40/memory_tb.v +++ b/tests/ice40/memory_tb.v @@ -10,8 +10,6 @@ module testbench; #5 clk = 1; #5 clk = 0; end - - $display("OKAY"); end -- cgit v1.2.3 From 698a0e3aafcae48535c68996fccf002c0e0e3aea Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 22 Aug 2019 15:50:45 -0700 Subject: WIP for equivalency checking memories --- tests/ice40/memory.ys | 14 +++++++++++++- 1 file changed, 13 insertions(+), 1 deletion(-) (limited to 'tests') diff --git a/tests/ice40/memory.ys b/tests/ice40/memory.ys index fa5d004b0..9b7490cd8 100644 --- a/tests/ice40/memory.ys +++ b/tests/ice40/memory.ys @@ -1,5 +1,17 @@ read_verilog memory.v -synth_ice40 +hierarchy -top top +proc +memory -nomap +equiv_opt -run :prove -map +/ice40/cells_sim.v synth_ice40 +memory +opt -full + +# TODO +#equiv_opt -run prove: -assert null +miter -equiv -flatten -make_assert -make_outputs gold gate miter +#sat -verify -prove-asserts -tempinduct -show-inputs -show-outputs miter + +design -load postopt cd top select -assert-count 1 t:SB_RAM40_4K select -assert-none t:SB_RAM40_4K %% t:* %D -- cgit v1.2.3 From e7a8cdbccfa6f619f2e25c540b5af6d8e34ff431 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Wed, 12 Jun 2019 08:34:06 -0700 Subject: Add shregmap -tech xilinx test --- tests/various/shregmap.ys | 1 + 1 file changed, 1 insertion(+) (limited to 'tests') diff --git a/tests/various/shregmap.ys b/tests/various/shregmap.ys index 0e5fe882b..a717c54f1 100644 --- a/tests/various/shregmap.ys +++ b/tests/various/shregmap.ys @@ -64,3 +64,4 @@ sat -verify -prove-asserts -show-ports -seq 5 miter # design -load gate # stat + -- cgit v1.2.3 From 66607845eccb2e3bc17b017c4f6b109aeaecdf77 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 22 Aug 2019 16:18:07 -0700 Subject: Remove Xilinx test --- tests/various/shregmap.ys | 34 ---------------------------------- 1 file changed, 34 deletions(-) (limited to 'tests') diff --git a/tests/various/shregmap.ys b/tests/various/shregmap.ys index a717c54f1..16e5f40e1 100644 --- a/tests/various/shregmap.ys +++ b/tests/various/shregmap.ys @@ -31,37 +31,3 @@ sat -verify -prove-asserts -show-ports -seq 5 miter #design -load gate #stat - -########## - -design -load read -design -copy-to model $__XILINX_SHREG_ -hierarchy -top shregmap_variable_test -prep -design -save gold - -simplemap t:$dff t:$dffe -shregmap -tech xilinx - -#stat -# show -width -# write_verilog -noexpr -norename -select -assert-count 1 t:$_DFF_P_ -select -assert-count 2 t:$__XILINX_SHREG_ - -design -stash gate - -design -import gold -as gold -design -import gate -as gate -design -copy-from model -as $__XILINX_SHREG_ \$__XILINX_SHREG_ -prep - -miter -equiv -flatten -make_assert -make_outputs gold gate miter -sat -verify -prove-asserts -show-ports -seq 5 miter - -# design -load gold -# stat - -# design -load gate -# stat - -- cgit v1.2.3 From 2b37a093e95036b267481b2dae2046278eef4040 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 22 Aug 2019 16:42:19 -0700 Subject: In sat: 'x' in init attr should not override constant --- tests/sat/initval.v | 4 ++++ tests/sat/initval.ys | 2 +- 2 files changed, 5 insertions(+), 1 deletion(-) (limited to 'tests') diff --git a/tests/sat/initval.v b/tests/sat/initval.v index 5b661f8d6..d46ccae48 100644 --- a/tests/sat/initval.v +++ b/tests/sat/initval.v @@ -1,6 +1,7 @@ module test(input clk, input [3:0] bar, output [3:0] foo); reg [3:0] foo = 0; reg [3:0] last_bar = 0; + reg [3:0] asdf = 4'b1xxx; always @* foo[1:0] <= bar[1:0]; @@ -11,5 +12,8 @@ module test(input clk, input [3:0] bar, output [3:0] foo); always @(posedge clk) last_bar <= bar; + always @* + asdf[2:0] <= 3'b111; + assert property (foo == {last_bar[3:2], bar[1:0]}); endmodule diff --git a/tests/sat/initval.ys b/tests/sat/initval.ys index 2079d2f34..3d88aa971 100644 --- a/tests/sat/initval.ys +++ b/tests/sat/initval.ys @@ -1,4 +1,4 @@ read_verilog -sv initval.v -proc;; +proc; sat -seq 10 -prove-asserts -- cgit v1.2.3 From 51ffb093b5beeb5e2c687d2bf34b13d246f3fc7d Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 22 Aug 2019 16:42:19 -0700 Subject: In sat: 'x' in init attr should not override constant --- tests/sat/initval.v | 4 ++++ tests/sat/initval.ys | 2 +- 2 files changed, 5 insertions(+), 1 deletion(-) (limited to 'tests') diff --git a/tests/sat/initval.v b/tests/sat/initval.v index 5b661f8d6..d46ccae48 100644 --- a/tests/sat/initval.v +++ b/tests/sat/initval.v @@ -1,6 +1,7 @@ module test(input clk, input [3:0] bar, output [3:0] foo); reg [3:0] foo = 0; reg [3:0] last_bar = 0; + reg [3:0] asdf = 4'b1xxx; always @* foo[1:0] <= bar[1:0]; @@ -11,5 +12,8 @@ module test(input clk, input [3:0] bar, output [3:0] foo); always @(posedge clk) last_bar <= bar; + always @* + asdf[2:0] <= 3'b111; + assert property (foo == {last_bar[3:2], bar[1:0]}); endmodule diff --git a/tests/sat/initval.ys b/tests/sat/initval.ys index 2079d2f34..3d88aa971 100644 --- a/tests/sat/initval.ys +++ b/tests/sat/initval.ys @@ -1,4 +1,4 @@ read_verilog -sv initval.v -proc;; +proc; sat -seq 10 -prove-asserts -- cgit v1.2.3 From 36cf0a3dd5a9599b60eb449a2401454e7a7af6fd Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 22 Aug 2019 16:50:14 -0700 Subject: Remove adffs_tb.v --- tests/ice40/adffs_tb.v | 75 -------------------------------------------------- 1 file changed, 75 deletions(-) delete mode 100644 tests/ice40/adffs_tb.v (limited to 'tests') diff --git a/tests/ice40/adffs_tb.v b/tests/ice40/adffs_tb.v deleted file mode 100644 index e049edabc..000000000 --- a/tests/ice40/adffs_tb.v +++ /dev/null @@ -1,75 +0,0 @@ -module testbench; - reg clk; - - initial begin - // $dumpfile("testbench.vcd"); - // $dumpvars(0, testbench); - - #5 clk = 0; - repeat (10000) begin - #5 clk = 1; - #5 clk = 0; - end - - $display("OKAY"); - end - - - reg [2:0] dinA = 0; - wire doutB,doutB1,doutB2,doutB3,doutB4; - reg dff,ndff,adff,adffn,dffe = 0; - - top uut ( - .clk (clk ), - .a (dinA[0] ), - .pre (dinA[1] ), - .clr (dinA[2] ), - .b (doutB ), - .b1 (doutB1 ), - .b2 (doutB2 ) - ); - - always @(posedge clk) begin - #3; - dinA <= dinA + 1; - end - - always @( posedge clk, posedge dinA[1], posedge dinA[2] ) - if ( dinA[2] ) - dff <= 1'b0; - else if ( dinA[1] ) - dff <= 1'b1; - else - dff <= dinA[0]; - - always @( negedge clk, negedge dinA[1], negedge dinA[2] ) - if ( !dinA[2] ) - ndff <= 1'b0; - else if ( !dinA[1] ) - ndff <= 1'b1; - else - ndff <= dinA[0]; - - always @( posedge clk, posedge dinA[2] ) - if ( dinA[2] ) - adff <= 1'b0; - else - adff <= dinA[0]; - - always @( posedge clk, negedge dinA[2] ) - if ( !dinA[2] ) - adffn <= 1'b0; - else - adffn <= dinA[0]; - - always @( posedge clk ) - if ( dinA[2] ) - dffe <= dinA[0]; - - assert_dff dff_test(.clk(clk), .test(doutB), .pat(dff)); - assert_dff ndff_test(.clk(clk), .test(doutB1), .pat(ndff)); - assert_dff adff_test(.clk(clk), .test(doutB2), .pat(adff)); - //assert_dff adffn_test(.clk(clk), .test(doutB3), .pat(adffn)); - //assert_dff dffe_test(.clk(clk), .test(doutB4), .pat(dffe)); - -endmodule -- cgit v1.2.3 From fe1b2337fd7950e1d563be5b8ccbaa81688261e4 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 22 Aug 2019 16:57:59 -0700 Subject: Do not propagate mem2reg attribute through to result --- tests/various/mem2reg.ys | 1 + 1 file changed, 1 insertion(+) (limited to 'tests') diff --git a/tests/various/mem2reg.ys b/tests/various/mem2reg.ys index 00389c700..85d6267c5 100644 --- a/tests/various/mem2reg.ys +++ b/tests/various/mem2reg.ys @@ -11,3 +11,4 @@ proc cd top select -assert-count 1 m:data1 a:src=< Date: Fri, 23 Aug 2019 12:40:14 +0300 Subject: Fix path in run-test.sh --- tests/ice40/run-test.sh | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'tests') diff --git a/tests/ice40/run-test.sh b/tests/ice40/run-test.sh index 90a8a3c83..ddd6d349f 100755 --- a/tests/ice40/run-test.sh +++ b/tests/ice40/run-test.sh @@ -1,7 +1,7 @@ set -e -if [ -f "../../../../../techlibs/common/simcells.v" ]; then - COMMON_PREFIX=../../../../../techlibs/common - TECHLIBS_PREFIX=../../../../../techlibs +if [ -f "../../techlibs/common/simcells.v" ]; then + COMMON_PREFIX=../../techlibs/common + TECHLIBS_PREFIX=../../techlibs else COMMON_PREFIX=/usr/local/share/yosys TECHLIBS_PREFIX=/usr/local/share/yosys -- cgit v1.2.3 From 3c10f58d043432197fdf5169404710f8ab68db8c Mon Sep 17 00:00:00 2001 From: SergeyDegtyar Date: Fri, 23 Aug 2019 17:00:16 +0300 Subject: Fix run-test.sh; Add new test for dpram. --- tests/ice40/dpram.v | 20 ++++++++++++ tests/ice40/dpram.ys | 18 +++++++++++ tests/ice40/dpram_tb.v | 81 +++++++++++++++++++++++++++++++++++++++++++++++++ tests/ice40/run-test.sh | 2 +- 4 files changed, 120 insertions(+), 1 deletion(-) create mode 100644 tests/ice40/dpram.v create mode 100644 tests/ice40/dpram.ys create mode 100644 tests/ice40/dpram_tb.v (limited to 'tests') diff --git a/tests/ice40/dpram.v b/tests/ice40/dpram.v new file mode 100644 index 000000000..2e69d6b3b --- /dev/null +++ b/tests/ice40/dpram.v @@ -0,0 +1,20 @@ +module top (din, write_en, waddr, wclk, raddr, rclk, dout); +parameter addr_width = 8; +parameter data_width = 8; +input [addr_width-1:0] waddr, raddr; +input [data_width-1:0] din; +input write_en, wclk, rclk; +output [data_width-1:0] dout; +reg [data_width-1:0] dout; +reg [data_width-1:0] mem [(1< 6'h3E) + mem_init <= 1; + end + + always @(posedge clk) begin + //#3; + we_a <= !we_a; + end + + reg [7:0] mem [(1<<8)-1:0]; + + always @(posedge clk) // Write memory. + begin + if (we_a) + mem[addr_a] <= data_a; // Using write address bus. + end + always @(posedge clk) // Read memory. + begin + pq_a <= mem[addr_b]; // Using read address bus. + end + + top uut ( + .din(data_a), + .write_en(we_a), + .waddr(addr_a), + .wclk(clk), + .raddr(addr_b), + .rclk(clk), + .dout(q_a) + ); + + uut_mem_checker port_a_test(.clk(clk), .init(mem_init), .en(!we_a), .A(q_a), .B(pq_a)); + +endmodule + +module uut_mem_checker(input clk, input init, input en, input [7:0] A, input [7:0] B); + always @(posedge clk) + begin + #1; + if (en == 1 & init == 1 & A !== B) + begin + $display("ERROR: ASSERTION FAILED in %m:",$time," ",A," ",B); + $stop; + end + end +endmodule diff --git a/tests/ice40/run-test.sh b/tests/ice40/run-test.sh index ddd6d349f..75aa08339 100755 --- a/tests/ice40/run-test.sh +++ b/tests/ice40/run-test.sh @@ -16,7 +16,7 @@ for x in *.ys; do done for t in *_tb.v; do echo "all:: run-$t" - echo "run-$t:" + echo "run-$t: ${t%_tb.v}_synth.v" echo " @echo 'Running $t..'" echo " @iverilog -o ${t%_tb.v}_testbench $t ${t%_tb.v}_synth.v common.v $TECHLIBS_PREFIX/ice40/cells_sim.v" echo " @vvp -N ${t%_tb.v}_testbench" -- cgit v1.2.3 From c29380b381b68396342990822c63c36381f3ee3a Mon Sep 17 00:00:00 2001 From: SergeyDegtyar Date: Fri, 23 Aug 2019 18:55:01 +0300 Subject: Fix pull request --- tests/ice40/.gitignore | 2 ++ tests/ice40/run-test.sh | 14 +++++++------- 2 files changed, 9 insertions(+), 7 deletions(-) (limited to 'tests') diff --git a/tests/ice40/.gitignore b/tests/ice40/.gitignore index 1d329c933..9a71dca69 100644 --- a/tests/ice40/.gitignore +++ b/tests/ice40/.gitignore @@ -1,2 +1,4 @@ *.log /run-test.mk ++*_synth.v ++*_testbench diff --git a/tests/ice40/run-test.sh b/tests/ice40/run-test.sh index 75aa08339..bd9d35314 100755 --- a/tests/ice40/run-test.sh +++ b/tests/ice40/run-test.sh @@ -13,14 +13,14 @@ for x in *.ys; do echo "run-$x:" echo " @echo 'Running $x..'" echo " @../../yosys -ql ${x%.ys}.log $x -w 'Yosys has only limited support for tri-state logic at the moment.'" + + if [ -f "${x%.ys}_tb.v" ]; then + echo " @echo 'Running ${x%.ys}_tb.v..'" + echo " @iverilog -o ${x%.ys}_testbench $t ${x%.ys}_synth.v common.v $TECHLIBS_PREFIX/ice40/cells_sim.v" + echo " @vvp -N ${x%.ys}_testbench" + fi done -for t in *_tb.v; do - echo "all:: run-$t" - echo "run-$t: ${t%_tb.v}_synth.v" - echo " @echo 'Running $t..'" - echo " @iverilog -o ${t%_tb.v}_testbench $t ${t%_tb.v}_synth.v common.v $TECHLIBS_PREFIX/ice40/cells_sim.v" - echo " @vvp -N ${t%_tb.v}_testbench" -done + for s in *.sh; do if [ "$s" != "run-test.sh" ]; then echo "all:: run-$s" -- cgit v1.2.3 From 10c41a5cf51427d96f465113decb752e501e926e Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 23 Aug 2019 09:11:04 -0700 Subject: Blocking assignment --- tests/sat/initval.v | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'tests') diff --git a/tests/sat/initval.v b/tests/sat/initval.v index d46ccae48..fcec9dd8c 100644 --- a/tests/sat/initval.v +++ b/tests/sat/initval.v @@ -13,7 +13,7 @@ module test(input clk, input [3:0] bar, output [3:0] foo); last_bar <= bar; always @* - asdf[2:0] <= 3'b111; + asdf[2:0] = 3'b111; assert property (foo == {last_bar[3:2], bar[1:0]}); endmodule -- cgit v1.2.3 From d62c10d641c5af4b1d395caa042681788df1aae4 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 23 Aug 2019 11:09:50 -0700 Subject: tests/techmap/run-test.sh to cope with *.ys --- tests/techmap/.gitignore | 1 + tests/techmap/run-test.sh | 24 +++++++++++++++++------- 2 files changed, 18 insertions(+), 7 deletions(-) (limited to 'tests') diff --git a/tests/techmap/.gitignore b/tests/techmap/.gitignore index 397b4a762..cfed22fc5 100644 --- a/tests/techmap/.gitignore +++ b/tests/techmap/.gitignore @@ -1 +1,2 @@ *.log +/*.mk diff --git a/tests/techmap/run-test.sh b/tests/techmap/run-test.sh index e2fc11e52..96489ff15 100755 --- a/tests/techmap/run-test.sh +++ b/tests/techmap/run-test.sh @@ -1,10 +1,20 @@ -#!/bin/bash +#!/usr/bin/env bash set -e -for x in *_runtest.sh; do - echo "Running $x.." - if ! bash $x &> ${x%.sh}.log; then - tail ${x%.sh}.log - echo ERROR - exit 1 +{ +echo "all::" +for x in *.ys; do + echo "all:: run-$x" + echo "run-$x:" + echo " @echo 'Running $x..'" + echo " @../../yosys -ql ${x%.ys}.log $x" +done +for s in *.sh; do + if [ "$s" != "run-test.sh" ]; then + echo "all:: run-$s" + echo "run-$s:" + echo " @echo 'Running $s..'" + echo " @bash $s > ${s%.sh}.log 2>&1" fi done +} > run-test.mk +exec ${MAKE:-make} -f run-test.mk -- cgit v1.2.3 From 5628e2ec53c3a1d5f1828b8f522c5c09c9856b0d Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 23 Aug 2019 11:10:02 -0700 Subject: Add simple clkbufmap tests --- tests/techmap/clkbufmap.ys | 52 ++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 52 insertions(+) create mode 100644 tests/techmap/clkbufmap.ys (limited to 'tests') diff --git a/tests/techmap/clkbufmap.ys b/tests/techmap/clkbufmap.ys new file mode 100644 index 000000000..eb8970af4 --- /dev/null +++ b/tests/techmap/clkbufmap.ys @@ -0,0 +1,52 @@ +read_verilog < Date: Fri, 23 Aug 2019 11:15:26 -0700 Subject: Check clkbuf_inhibit=1 is ignored for custom selection --- tests/techmap/clkbufmap.ys | 1 + 1 file changed, 1 insertion(+) (limited to 'tests') diff --git a/tests/techmap/clkbufmap.ys b/tests/techmap/clkbufmap.ys index eb8970af4..46ff4d694 100644 --- a/tests/techmap/clkbufmap.ys +++ b/tests/techmap/clkbufmap.ys @@ -35,6 +35,7 @@ select -assert-count 1 t:clkbuf # ---------------------- design -load ref +setattr -set clkbuf_inhibit 1 w:clk1 setattr -set buffer_type "bufg" w:clk2 clkbufmap -buf clkbuf o:i w:* a:buffer_type=none a:buffer_type=bufr %u %d select -assert-count 1 w:clk1 %a %co t:clkbuf %i -- cgit v1.2.3 From dc87372a97d515563ccccd517ef8f35662870fe6 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Sat, 24 Aug 2019 15:05:44 -0700 Subject: Wire with init on FF part, 1'bx on non-FF part --- tests/sat/initval.v | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) (limited to 'tests') diff --git a/tests/sat/initval.v b/tests/sat/initval.v index fcec9dd8c..81f71b5ba 100644 --- a/tests/sat/initval.v +++ b/tests/sat/initval.v @@ -1,4 +1,4 @@ -module test(input clk, input [3:0] bar, output [3:0] foo); +module test(input clk, input [3:0] bar, output [3:0] foo, asdf); reg [3:0] foo = 0; reg [3:0] last_bar = 0; reg [3:0] asdf = 4'b1xxx; @@ -12,6 +12,8 @@ module test(input clk, input [3:0] bar, output [3:0] foo); always @(posedge clk) last_bar <= bar; + always @(posedge clk) + asdf[3] <= bar[3]; always @* asdf[2:0] = 3'b111; -- cgit v1.2.3 From 528f1c86877d247700bd9445e03c85b3eb437b5c Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Mon, 26 Aug 2019 13:45:16 -0700 Subject: Improve tests to check that clkbuf is connected to expected --- tests/techmap/clkbufmap.ys | 27 +++++++++++++++++++++------ 1 file changed, 21 insertions(+), 6 deletions(-) (limited to 'tests') diff --git a/tests/techmap/clkbufmap.ys b/tests/techmap/clkbufmap.ys index 46ff4d694..5847c3ce5 100644 --- a/tests/techmap/clkbufmap.ys +++ b/tests/techmap/clkbufmap.ys @@ -18,9 +18,15 @@ design -save ref design -load ref clkbufmap -buf clkbuf o:i -select -assert-count 1 w:clk1 %a %co t:clkbuf %i -select -assert-count 1 w:clk2 %a %co t:clkbuf %i select -assert-count 2 t:clkbuf +select -set clk1 w:clk1 %a %co t:clkbuf %i # Find 'clk1' fanouts that are 'clkbuf' +select -assert-count 1 @clk1 # Check there is one such fanout +select -assert-count 1 @clk1 %x:+[o] %co c:s* %i # Check that the 'o' of that clkbuf drives one fanout +select -assert-count 1 @clk1 %x:+[o] %co c:s0 %i # And that one fanout is 's0' +select -set clk2 w:clk2 %a %co t:clkbuf %i +select -assert-count 1 @clk2 +select -assert-count 1 @clk2 %x:+[o] %co c:s* %i +select -assert-count 1 @clk2 %x:+[o] %co c:s1 %i # ---------------------- @@ -28,9 +34,12 @@ design -load ref setattr -set clkbuf_inhibit 0 w:clk1 setattr -set clkbuf_inhibit 1 w:clk2 clkbufmap -buf clkbuf o:i -select -assert-count 1 w:clk1 %a %co t:clkbuf %i -select -assert-count 0 w:clk2 %a %co t:clkbuf %i select -assert-count 1 t:clkbuf +select -set clk1 w:clk1 %a %co t:clkbuf %i # Find 'clk1' fanouts that are 'clkbuf' +select -assert-count 1 @clk1 # Check there is one such fanout +select -assert-count 1 @clk1 %x:+[o] %co c:s* %i # Check that the 'o' of that clkbuf drives one fanout +select -assert-count 1 @clk1 %x:+[o] %co c:s0 %i # And that one fanout is 's0' +select -assert-count 0 w:clk2 %a %co t:clkbuf %i # ---------------------- @@ -38,9 +47,15 @@ design -load ref setattr -set clkbuf_inhibit 1 w:clk1 setattr -set buffer_type "bufg" w:clk2 clkbufmap -buf clkbuf o:i w:* a:buffer_type=none a:buffer_type=bufr %u %d -select -assert-count 1 w:clk1 %a %co t:clkbuf %i -select -assert-count 1 w:clk2 %a %co t:clkbuf %i select -assert-count 2 t:clkbuf +select -set clk1 w:clk1 %a %co t:clkbuf %i # Find 'clk1' fanouts that are 'clkbuf' +select -assert-count 1 @clk1 # Check there is one such fanout +select -assert-count 1 @clk1 %x:+[o] %co c:s* %i # Check that the 'o' of that clkbuf drives one fanout +select -assert-count 1 @clk1 %x:+[o] %co c:s0 %i # And that one fanout is 's0' +select -set clk2 w:clk2 %a %co t:clkbuf %i # Find 'clk1' fanouts that are 'clkbuf' +select -assert-count 1 @clk2 # Check there is one such fanout +select -assert-count 1 @clk2 %x:+[o] %co c:s* %i # Check that the 'o' of that clkbuf drives one fanout +select -assert-count 1 @clk2 %x:+[o] %co c:s1 %i # And that one fanout is 's0' # ---------------------- -- cgit v1.2.3 From 6b5e65919a6ec14d4bfc85f80d1f7492d5b86c16 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Mon, 26 Aug 2019 17:52:57 -0700 Subject: Revert "In sat: 'x' in init attr should not override constant" This reverts commit 2b37a093e95036b267481b2dae2046278eef4040. --- tests/sat/initval.v | 4 ---- tests/sat/initval.ys | 2 +- 2 files changed, 1 insertion(+), 5 deletions(-) (limited to 'tests') diff --git a/tests/sat/initval.v b/tests/sat/initval.v index d46ccae48..5b661f8d6 100644 --- a/tests/sat/initval.v +++ b/tests/sat/initval.v @@ -1,7 +1,6 @@ module test(input clk, input [3:0] bar, output [3:0] foo); reg [3:0] foo = 0; reg [3:0] last_bar = 0; - reg [3:0] asdf = 4'b1xxx; always @* foo[1:0] <= bar[1:0]; @@ -12,8 +11,5 @@ module test(input clk, input [3:0] bar, output [3:0] foo); always @(posedge clk) last_bar <= bar; - always @* - asdf[2:0] <= 3'b111; - assert property (foo == {last_bar[3:2], bar[1:0]}); endmodule diff --git a/tests/sat/initval.ys b/tests/sat/initval.ys index 3d88aa971..2079d2f34 100644 --- a/tests/sat/initval.ys +++ b/tests/sat/initval.ys @@ -1,4 +1,4 @@ read_verilog -sv initval.v -proc; +proc;; sat -seq 10 -prove-asserts -- cgit v1.2.3 From aad9bad32604645e2d61f0858234a1838e8b88eb Mon Sep 17 00:00:00 2001 From: SergeyDegtyar Date: Tue, 27 Aug 2019 13:56:26 +0300 Subject: Add tests for macc and rom; Test cases from https://www.latticesemi.com/-/media/LatticeSemi/Documents/UserManuals/EI/iCEcube201701UserGuide.ashx?document_id=52071; In both cases synthesized only LUTs and DFFs. --- tests/ice40/macc.v | 22 ++++++++++++++++++++++ tests/ice40/macc.ys | 10 ++++++++++ tests/ice40/rom.v | 15 +++++++++++++++ tests/ice40/rom.ys | 8 ++++++++ 4 files changed, 55 insertions(+) create mode 100644 tests/ice40/macc.v create mode 100644 tests/ice40/macc.ys create mode 100644 tests/ice40/rom.v create mode 100644 tests/ice40/rom.ys (limited to 'tests') diff --git a/tests/ice40/macc.v b/tests/ice40/macc.v new file mode 100644 index 000000000..115f8ce42 --- /dev/null +++ b/tests/ice40/macc.v @@ -0,0 +1,22 @@ +module top(clk,a,b,c,set); +parameter A_WIDTH = 4; +parameter B_WIDTH = 3; +input set; +input clk; +input signed [(A_WIDTH - 1):0] a; +input signed [(B_WIDTH - 1):0] b; +output signed [(A_WIDTH + B_WIDTH - 1):0] c; +reg [(A_WIDTH + B_WIDTH - 1):0] reg_tmp_c; +assign c = reg_tmp_c; +always @(posedge clk) +begin +if(set) +begin +reg_tmp_c <= 0; +end +else +begin +reg_tmp_c <= a * b + c; +end +end +endmodule diff --git a/tests/ice40/macc.ys b/tests/ice40/macc.ys new file mode 100644 index 000000000..233e7e890 --- /dev/null +++ b/tests/ice40/macc.ys @@ -0,0 +1,10 @@ +read_verilog macc.v +proc +hierarchy -top top +equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 -dsp # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module +select -assert-count 41 t:SB_LUT4 +select -assert-count 6 t:SB_CARRY +select -assert-count 7 t:SB_DFFSR +select -assert-none t:SB_LUT4 t:SB_CARRY t:SB_DFFSR %% t:* %D diff --git a/tests/ice40/rom.v b/tests/ice40/rom.v new file mode 100644 index 000000000..c31ca3b2b --- /dev/null +++ b/tests/ice40/rom.v @@ -0,0 +1,15 @@ +module top(data, addr); +output [3:0] data; +input [4:0] addr; +always @(addr) begin +case (addr) +0 : data = 'h4; +1 : data = 'h9; +2 : data = 'h1; +15 : data = 'h8; +16 : data = 'h1; +17 : data = 'h0; +default : data = 'h0; +endcase +end +endmodule diff --git a/tests/ice40/rom.ys b/tests/ice40/rom.ys new file mode 100644 index 000000000..41d214e2a --- /dev/null +++ b/tests/ice40/rom.ys @@ -0,0 +1,8 @@ +read_verilog rom.v +proc +flatten +equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module +select -assert-count 5 t:SB_LUT4 +select -assert-none t:SB_LUT4 %% t:* %D -- cgit v1.2.3 From 134d3fea909bae02f4f814e3d649658502b44b73 Mon Sep 17 00:00:00 2001 From: SergeyDegtyar Date: Tue, 27 Aug 2019 18:12:18 +0300 Subject: Add tests for ecp5 architecture. --- tests/ecp5/.gitignore | 4 ++ tests/ecp5/add_sub.v | 13 +++++++ tests/ecp5/add_sub.ys | 8 ++++ tests/ecp5/adffs.v | 91 +++++++++++++++++++++++++++++++++++++++++++ tests/ecp5/adffs.ys | 12 ++++++ tests/ecp5/common.v | 47 +++++++++++++++++++++++ tests/ecp5/dffs.v | 37 ++++++++++++++++++ tests/ecp5/dffs.ys | 10 +++++ tests/ecp5/div_mod.v | 13 +++++++ tests/ecp5/div_mod.ys | 12 ++++++ tests/ecp5/dpram.v | 20 ++++++++++ tests/ecp5/dpram.ys | 18 +++++++++ tests/ecp5/dpram_tb.v | 81 +++++++++++++++++++++++++++++++++++++++ tests/ecp5/latches.v | 58 ++++++++++++++++++++++++++++ tests/ecp5/latches.ys | 7 ++++ tests/ecp5/latches_tb.v | 57 +++++++++++++++++++++++++++ tests/ecp5/macc.v | 22 +++++++++++ tests/ecp5/macc.ys | 10 +++++ tests/ecp5/memory.v | 21 ++++++++++ tests/ecp5/memory.ys | 22 +++++++++++ tests/ecp5/memory_tb.v | 79 ++++++++++++++++++++++++++++++++++++++ tests/ecp5/mul.v | 11 ++++++ tests/ecp5/mul.ys | 11 ++++++ tests/ecp5/mux.v | 100 ++++++++++++++++++++++++++++++++++++++++++++++++ tests/ecp5/mux.ys | 11 ++++++ tests/ecp5/rom.v | 15 ++++++++ tests/ecp5/rom.ys | 9 +++++ tests/ecp5/run-test.sh | 33 ++++++++++++++++ tests/ecp5/tribuf.v | 23 +++++++++++ tests/ecp5/tribuf.ys | 9 +++++ 30 files changed, 864 insertions(+) create mode 100644 tests/ecp5/.gitignore create mode 100644 tests/ecp5/add_sub.v create mode 100644 tests/ecp5/add_sub.ys create mode 100644 tests/ecp5/adffs.v create mode 100644 tests/ecp5/adffs.ys create mode 100644 tests/ecp5/common.v create mode 100644 tests/ecp5/dffs.v create mode 100644 tests/ecp5/dffs.ys create mode 100644 tests/ecp5/div_mod.v create mode 100644 tests/ecp5/div_mod.ys create mode 100644 tests/ecp5/dpram.v create mode 100644 tests/ecp5/dpram.ys create mode 100644 tests/ecp5/dpram_tb.v create mode 100644 tests/ecp5/latches.v create mode 100644 tests/ecp5/latches.ys create mode 100644 tests/ecp5/latches_tb.v create mode 100644 tests/ecp5/macc.v create mode 100644 tests/ecp5/macc.ys create mode 100644 tests/ecp5/memory.v create mode 100644 tests/ecp5/memory.ys create mode 100644 tests/ecp5/memory_tb.v create mode 100644 tests/ecp5/mul.v create mode 100644 tests/ecp5/mul.ys create mode 100644 tests/ecp5/mux.v create mode 100644 tests/ecp5/mux.ys create mode 100644 tests/ecp5/rom.v create mode 100644 tests/ecp5/rom.ys create mode 100755 tests/ecp5/run-test.sh create mode 100644 tests/ecp5/tribuf.v create mode 100644 tests/ecp5/tribuf.ys (limited to 'tests') diff --git a/tests/ecp5/.gitignore b/tests/ecp5/.gitignore new file mode 100644 index 000000000..9a71dca69 --- /dev/null +++ b/tests/ecp5/.gitignore @@ -0,0 +1,4 @@ +*.log +/run-test.mk ++*_synth.v ++*_testbench diff --git a/tests/ecp5/add_sub.v b/tests/ecp5/add_sub.v new file mode 100644 index 000000000..177c32e30 --- /dev/null +++ b/tests/ecp5/add_sub.v @@ -0,0 +1,13 @@ +module top +( + input [3:0] x, + input [3:0] y, + + output [3:0] A, + output [3:0] B + ); + +assign A = x + y; +assign B = x - y; + +endmodule diff --git a/tests/ecp5/add_sub.ys b/tests/ecp5/add_sub.ys new file mode 100644 index 000000000..03aec6694 --- /dev/null +++ b/tests/ecp5/add_sub.ys @@ -0,0 +1,8 @@ +read_verilog add_sub.v +hierarchy -top top +equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module +select -assert-count 10 t:LUT4 +select -assert-none t:LUT4 %% t:* %D + diff --git a/tests/ecp5/adffs.v b/tests/ecp5/adffs.v new file mode 100644 index 000000000..93c8bf52c --- /dev/null +++ b/tests/ecp5/adffs.v @@ -0,0 +1,91 @@ +module adff + ( input d, clk, clr, output reg q ); + initial begin + q = 0; + end + always @( posedge clk, posedge clr ) + if ( clr ) + q <= 1'b0; + else + q <= d; +endmodule + +module adffn + ( input d, clk, clr, output reg q ); + initial begin + q = 0; + end + always @( posedge clk, negedge clr ) + if ( !clr ) + q <= 1'b0; + else + q <= d; +endmodule + +module dffsr + ( input d, clk, pre, clr, output reg q ); + initial begin + q = 0; + end + always @( posedge clk, posedge pre, posedge clr ) + if ( clr ) + q <= 1'b0; + else if ( pre ) + q <= 1'b1; + else + q <= d; +endmodule + +module ndffnsnr + ( input d, clk, pre, clr, output reg q ); + initial begin + q = 0; + end + always @( negedge clk, negedge pre, negedge clr ) + if ( !clr ) + q <= 1'b0; + else if ( !pre ) + q <= 1'b1; + else + q <= d; +endmodule + +module top ( +input clk, +input clr, +input pre, +input a, +output b,b1,b2,b3 +); + +dffsr u_dffsr ( + .clk (clk ), + .clr (clr), + .pre (pre), + .d (a ), + .q (b ) + ); + +ndffnsnr u_ndffnsnr ( + .clk (clk ), + .clr (clr), + .pre (pre), + .d (a ), + .q (b1 ) + ); + +adff u_adff ( + .clk (clk ), + .clr (clr), + .d (a ), + .q (b2 ) + ); + +adffn u_adffn ( + .clk (clk ), + .clr (clr), + .d (a ), + .q (b3 ) + ); + +endmodule diff --git a/tests/ecp5/adffs.ys b/tests/ecp5/adffs.ys new file mode 100644 index 000000000..5829fef5f --- /dev/null +++ b/tests/ecp5/adffs.ys @@ -0,0 +1,12 @@ +read_verilog adffs.v +proc +async2sync # converts async flops to a 'sync' variant clocked by a 'super'-clock +flatten +equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module +select -assert-count 1 t:DFF +select -assert-count 1 t:DFFN +select -assert-count 2 t:DFFSR +select -assert-count 7 t:LUT4 +select -assert-none t:DFF t:DFFN t:DFFSR t:LUT4 %% t:* %D diff --git a/tests/ecp5/common.v b/tests/ecp5/common.v new file mode 100644 index 000000000..5446f0817 --- /dev/null +++ b/tests/ecp5/common.v @@ -0,0 +1,47 @@ +module assert_dff(input clk, input test, input pat); + always @(posedge clk) + begin + #1; + if (test != pat) + begin + $display("ERROR: ASSERTION FAILED in %m:",$time); + $stop; + end + end +endmodule + +module assert_tri(input en, input A, input B); + always @(posedge en) + begin + #1; + if (A !== B) + begin + $display("ERROR: ASSERTION FAILED in %m:",$time," ",A," ",B); + $stop; + end + end +endmodule + +module assert_Z(input clk, input A); + always @(posedge clk) + begin + #1; + if (A === 1'bZ) + begin + $display("ERROR: ASSERTION FAILED in %m:",$time," ",A); + $stop; + end + end +endmodule + +module assert_comb(input A, input B); + always @(*) + begin + #1; + if (A !== B) + begin + $display("ERROR: ASSERTION FAILED in %m:",$time," ",A," ",B); + $stop; + end + end +endmodule diff --git a/tests/ecp5/dffs.v b/tests/ecp5/dffs.v new file mode 100644 index 000000000..d97840c43 --- /dev/null +++ b/tests/ecp5/dffs.v @@ -0,0 +1,37 @@ +module dff + ( input d, clk, output reg q ); + always @( posedge clk ) + q <= d; +endmodule + +module dffe + ( input d, clk, en, output reg q ); + initial begin + q = 0; + end + always @( posedge clk ) + if ( en ) + q <= d; +endmodule + +module top ( +input clk, +input en, +input a, +output b,b1, +); + +dff u_dff ( + .clk (clk ), + .d (a ), + .q (b ) + ); + +dffe u_ndffe ( + .clk (clk ), + .en (en), + .d (a ), + .q (b1 ) + ); + +endmodule diff --git a/tests/ecp5/dffs.ys b/tests/ecp5/dffs.ys new file mode 100644 index 000000000..07470c5ba --- /dev/null +++ b/tests/ecp5/dffs.ys @@ -0,0 +1,10 @@ +read_verilog dffs.v +hierarchy -top top +proc +flatten +equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module +select -assert-count 1 t:DFF +select -assert-count 1 t:DFFE +select -assert-none t:DFF t:DFFE %% t:* %D diff --git a/tests/ecp5/div_mod.v b/tests/ecp5/div_mod.v new file mode 100644 index 000000000..64a36707d --- /dev/null +++ b/tests/ecp5/div_mod.v @@ -0,0 +1,13 @@ +module top +( + input [3:0] x, + input [3:0] y, + + output [3:0] A, + output [3:0] B + ); + +assign A = x % y; +assign B = x / y; + +endmodule diff --git a/tests/ecp5/div_mod.ys b/tests/ecp5/div_mod.ys new file mode 100644 index 000000000..169c5978e --- /dev/null +++ b/tests/ecp5/div_mod.ys @@ -0,0 +1,12 @@ +read_verilog div_mod.v +hierarchy -top top +flatten +equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module + +select -assert-count 28 t:CCU2C +select -assert-count 45 t:L6MUX21 +select -assert-count 183 t:LUT4 +select -assert-count 79 t:PFUMX +select -assert-none t:LUT4 t:CCU2C t:L6MUX21 t:PFUMX %% t:* %D diff --git a/tests/ecp5/dpram.v b/tests/ecp5/dpram.v new file mode 100644 index 000000000..2e69d6b3b --- /dev/null +++ b/tests/ecp5/dpram.v @@ -0,0 +1,20 @@ +module top (din, write_en, waddr, wclk, raddr, rclk, dout); +parameter addr_width = 8; +parameter data_width = 8; +input [addr_width-1:0] waddr, raddr; +input [data_width-1:0] din; +input write_en, wclk, rclk; +output [data_width-1:0] dout; +reg [data_width-1:0] dout; +reg [data_width-1:0] mem [(1< 6'h3E) + mem_init <= 1; + end + + always @(posedge clk) begin + //#3; + we_a <= !we_a; + end + + reg [7:0] mem [(1<<8)-1:0]; + + always @(posedge clk) // Write memory. + begin + if (we_a) + mem[addr_a] <= data_a; // Using write address bus. + end + always @(posedge clk) // Read memory. + begin + pq_a <= mem[addr_b]; // Using read address bus. + end + + top uut ( + .din(data_a), + .write_en(we_a), + .waddr(addr_a), + .wclk(clk), + .raddr(addr_b), + .rclk(clk), + .dout(q_a) + ); + + uut_mem_checker port_a_test(.clk(clk), .init(mem_init), .en(!we_a), .A(q_a), .B(pq_a)); + +endmodule + +module uut_mem_checker(input clk, input init, input en, input [7:0] A, input [7:0] B); + always @(posedge clk) + begin + #1; + if (en == 1 & init == 1 & A !== B) + begin + $display("ERROR: ASSERTION FAILED in %m:",$time," ",A," ",B); + $stop; + end + end +endmodule diff --git a/tests/ecp5/latches.v b/tests/ecp5/latches.v new file mode 100644 index 000000000..9dc43e4c2 --- /dev/null +++ b/tests/ecp5/latches.v @@ -0,0 +1,58 @@ +module latchp + ( input d, clk, en, output reg q ); + always @* + if ( en ) + q <= d; +endmodule + +module latchn + ( input d, clk, en, output reg q ); + always @* + if ( !en ) + q <= d; +endmodule + +module latchsr + ( input d, clk, en, clr, pre, output reg q ); + always @* + if ( clr ) + q <= 1'b0; + else if ( pre ) + q <= 1'b1; + else if ( en ) + q <= d; +endmodule + + +module top ( +input clk, +input clr, +input pre, +input a, +output b,b1,b2 +); + + +latchp u_latchp ( + .en (clk ), + .d (a ), + .q (b ) + ); + + +latchn u_latchn ( + .en (clk ), + .d (a ), + .q (b1 ) + ); + + +latchsr u_latchsr ( + .en (clk ), + .clr (clr), + .pre (pre), + .d (a ), + .q (b2 ) + ); + +endmodule diff --git a/tests/ecp5/latches.ys b/tests/ecp5/latches.ys new file mode 100644 index 000000000..2c77304a1 --- /dev/null +++ b/tests/ecp5/latches.ys @@ -0,0 +1,7 @@ +read_verilog latches.v +synth_ecp5 +cd top +select -assert-count 4 t:LUT4 +select -assert-count 1 t:PFUMX +select -assert-none t:LUT4 t:PFUMX %% t:* %D +write_verilog latches_synth.v diff --git a/tests/ecp5/latches_tb.v b/tests/ecp5/latches_tb.v new file mode 100644 index 000000000..b0585264b --- /dev/null +++ b/tests/ecp5/latches_tb.v @@ -0,0 +1,57 @@ +module testbench; + reg clk; + + initial begin + // $dumpfile("testbench.vcd"); + // $dumpvars(0, testbench); + + #5 clk = 0; + repeat (10000) begin + #5 clk = 1; + #5 clk = 0; + end + end + + + reg [2:0] dinA = 0; + wire doutB,doutB1,doutB2; + reg lat,latn,latsr = 0; + + top uut ( + .clk (clk ), + .a (dinA[0] ), + .pre (dinA[1] ), + .clr (dinA[2] ), + .b (doutB ), + .b1 (doutB1 ), + .b2 (doutB2 ) + ); + + always @(posedge clk) begin + #3; + dinA <= dinA + 1; + end + + always @* + if ( clk ) + lat <= dinA[0]; + + + always @* + if ( !clk ) + latn <= dinA[0]; + + + always @* + if ( dinA[2] ) + latsr <= 1'b0; + else if ( dinA[1] ) + latsr <= 1'b1; + else if ( clk ) + latsr <= dinA[0]; + + assert_dff lat_test(.clk(clk), .test(doutB), .pat(lat)); + assert_dff latn_test(.clk(clk), .test(doutB1), .pat(latn)); + assert_dff latsr_test(.clk(clk), .test(doutB2), .pat(latsr)); + +endmodule diff --git a/tests/ecp5/macc.v b/tests/ecp5/macc.v new file mode 100644 index 000000000..115f8ce42 --- /dev/null +++ b/tests/ecp5/macc.v @@ -0,0 +1,22 @@ +module top(clk,a,b,c,set); +parameter A_WIDTH = 4; +parameter B_WIDTH = 3; +input set; +input clk; +input signed [(A_WIDTH - 1):0] a; +input signed [(B_WIDTH - 1):0] b; +output signed [(A_WIDTH + B_WIDTH - 1):0] c; +reg [(A_WIDTH + B_WIDTH - 1):0] reg_tmp_c; +assign c = reg_tmp_c; +always @(posedge clk) +begin +if(set) +begin +reg_tmp_c <= 0; +end +else +begin +reg_tmp_c <= a * b + c; +end +end +endmodule diff --git a/tests/ecp5/macc.ys b/tests/ecp5/macc.ys new file mode 100644 index 000000000..530877727 --- /dev/null +++ b/tests/ecp5/macc.ys @@ -0,0 +1,10 @@ +read_verilog macc.v +proc +hierarchy -top top +equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module +select -assert-count 41 t:LUT4 +select -assert-count 6 t:CARRY +select -assert-count 7 t:DFFSR +select -assert-none t:LUT4 t:CARRY t:DFFSR %% t:* %D diff --git a/tests/ecp5/memory.v b/tests/ecp5/memory.v new file mode 100644 index 000000000..cb7753f7b --- /dev/null +++ b/tests/ecp5/memory.v @@ -0,0 +1,21 @@ +module top +( + input [7:0] data_a, + input [6:1] addr_a, + input we_a, clk, + output reg [7:0] q_a +); + // Declare the RAM variable + reg [7:0] ram[63:0]; + + // Port A + always @ (posedge clk) + begin + if (we_a) + begin + ram[addr_a] <= data_a; + q_a <= data_a; + end + q_a <= ram[addr_a]; + end +endmodule diff --git a/tests/ecp5/memory.ys b/tests/ecp5/memory.ys new file mode 100644 index 000000000..9fdeb0d16 --- /dev/null +++ b/tests/ecp5/memory.ys @@ -0,0 +1,22 @@ +read_verilog memory.v +hierarchy -top top +proc +memory -nomap +equiv_opt -run :prove -map +/ecp5/cells_sim.v synth_ecp5 +memory +opt -full + +# TODO +#equiv_opt -run prove: -assert null +miter -equiv -flatten -make_assert -make_outputs gold gate miter +#sat -verify -prove-asserts -tempinduct -show-inputs -show-outputs miter + +design -load postopt +cd top +select -assert-count 24 t:L6MUX21 +select -assert-count 71 t:LUT4 +select -assert-count 32 t:PFUMX +select -assert-count 8 t:TRELLIS_DPR16X4 +select -assert-count 35 t:TRELLIS_FF +select -assert-none t:L6MUX21 t:LUT4 t:PFUMX t:TRELLIS_DPR16X4 t:TRELLIS_FF %% t:* %D +write_verilog memory_synth.v diff --git a/tests/ecp5/memory_tb.v b/tests/ecp5/memory_tb.v new file mode 100644 index 000000000..be69374eb --- /dev/null +++ b/tests/ecp5/memory_tb.v @@ -0,0 +1,79 @@ +module testbench; + reg clk; + + initial begin + // $dumpfile("testbench.vcd"); + // $dumpvars(0, testbench); + + #5 clk = 0; + repeat (10000) begin + #5 clk = 1; + #5 clk = 0; + end + end + + + reg [7:0] data_a = 0; + reg [5:0] addr_a = 0; + reg we_a = 0; + reg re_a = 1; + wire [7:0] q_a; + reg mem_init = 0; + + reg [7:0] pq_a; + + top uut ( + .data_a(data_a), + .addr_a(addr_a), + .we_a(we_a), + .clk(clk), + .q_a(q_a) + ); + + always @(posedge clk) begin + #3; + data_a <= data_a + 17; + + addr_a <= addr_a + 1; + end + + always @(posedge addr_a) begin + #10; + if(addr_a > 6'h3E) + mem_init <= 1; + end + + always @(posedge clk) begin + //#3; + we_a <= !we_a; + end + + // Declare the RAM variable for check + reg [7:0] ram[63:0]; + + // Port A for check + always @ (posedge clk) + begin + if (we_a) + begin + ram[addr_a] <= data_a; + pq_a <= data_a; + end + pq_a <= ram[addr_a]; + end + + uut_mem_checker port_a_test(.clk(clk), .init(mem_init), .en(!we_a), .A(q_a), .B(pq_a)); + +endmodule + +module uut_mem_checker(input clk, input init, input en, input [7:0] A, input [7:0] B); + always @(posedge clk) + begin + #1; + if (en == 1 & init == 1 & A !== B) + begin + $display("ERROR: ASSERTION FAILED in %m:",$time," ",A," ",B); + $stop; + end + end +endmodule diff --git a/tests/ecp5/mul.v b/tests/ecp5/mul.v new file mode 100644 index 000000000..d5b48b1d7 --- /dev/null +++ b/tests/ecp5/mul.v @@ -0,0 +1,11 @@ +module top +( + input [5:0] x, + input [5:0] y, + + output [11:0] A, + ); + +assign A = x * y; + +endmodule diff --git a/tests/ecp5/mul.ys b/tests/ecp5/mul.ys new file mode 100644 index 000000000..0e8d6908f --- /dev/null +++ b/tests/ecp5/mul.ys @@ -0,0 +1,11 @@ +read_verilog mul.v +hierarchy -top top +equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module +select -assert-count 6 t:CCU2C +select -assert-count 46 t:L6MUX21 +select -assert-count 169 t:LUT4 +select -assert-count 72 t:PFUMX + +select -assert-none t:CCU2C t:L6MUX21 t:LUT4 t:PFUMX %% t:* %D diff --git a/tests/ecp5/mux.v b/tests/ecp5/mux.v new file mode 100644 index 000000000..0814b733e --- /dev/null +++ b/tests/ecp5/mux.v @@ -0,0 +1,100 @@ +module mux2 (S,A,B,Y); + input S; + input A,B; + output reg Y; + + always @(*) + Y = (S)? B : A; +endmodule + +module mux4 ( S, D, Y ); + +input[1:0] S; +input[3:0] D; +output Y; + +reg Y; +wire[1:0] S; +wire[3:0] D; + +always @* +begin + case( S ) + 0 : Y = D[0]; + 1 : Y = D[1]; + 2 : Y = D[2]; + 3 : Y = D[3]; + endcase +end + +endmodule + +module mux8 ( S, D, Y ); + +input[2:0] S; +input[7:0] D; +output Y; + +reg Y; +wire[2:0] S; +wire[7:0] D; + +always @* +begin + case( S ) + 0 : Y = D[0]; + 1 : Y = D[1]; + 2 : Y = D[2]; + 3 : Y = D[3]; + 4 : Y = D[4]; + 5 : Y = D[5]; + 6 : Y = D[6]; + 7 : Y = D[7]; + endcase +end + +endmodule + +module mux16 (D, S, Y); + input [15:0] D; + input [3:0] S; + output Y; + +assign Y = D[S]; + +endmodule + + +module top ( +input [3:0] S, +input [15:0] D, +output M2,M4,M8,M16 +); + +mux2 u_mux2 ( + .S (S[0]), + .A (D[0]), + .B (D[1]), + .Y (M2) + ); + + +mux4 u_mux4 ( + .S (S[1:0]), + .D (D[3:0]), + .Y (M4) + ); + +mux8 u_mux8 ( + .S (S[2:0]), + .D (D[7:0]), + .Y (M8) + ); + +mux16 u_mux16 ( + .S (S[3:0]), + .D (D[15:0]), + .Y (M16) + ); + +endmodule diff --git a/tests/ecp5/mux.ys b/tests/ecp5/mux.ys new file mode 100644 index 000000000..47a965dd3 --- /dev/null +++ b/tests/ecp5/mux.ys @@ -0,0 +1,11 @@ +read_verilog mux.v +proc +flatten +equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module +select -assert-count 30 t:LUT4 +select -assert-count 7 t:L6MUX21 +select -assert-count 12 t:PFUMX + +select -assert-none t:LUT4 t:L6MUX21 t:PFUMX %% t:* %D diff --git a/tests/ecp5/rom.v b/tests/ecp5/rom.v new file mode 100644 index 000000000..c31ca3b2b --- /dev/null +++ b/tests/ecp5/rom.v @@ -0,0 +1,15 @@ +module top(data, addr); +output [3:0] data; +input [4:0] addr; +always @(addr) begin +case (addr) +0 : data = 'h4; +1 : data = 'h9; +2 : data = 'h1; +15 : data = 'h8; +16 : data = 'h1; +17 : data = 'h0; +default : data = 'h0; +endcase +end +endmodule diff --git a/tests/ecp5/rom.ys b/tests/ecp5/rom.ys new file mode 100644 index 000000000..8a52749a1 --- /dev/null +++ b/tests/ecp5/rom.ys @@ -0,0 +1,9 @@ +read_verilog rom.v +proc +flatten +equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module +select -assert-count 6 t:LUT4 +select -assert-count 3 t:PFUMX +select -assert-none t:LUT4 t:PFUMX %% t:* %D diff --git a/tests/ecp5/run-test.sh b/tests/ecp5/run-test.sh new file mode 100755 index 000000000..bd9d35314 --- /dev/null +++ b/tests/ecp5/run-test.sh @@ -0,0 +1,33 @@ +set -e +if [ -f "../../techlibs/common/simcells.v" ]; then + COMMON_PREFIX=../../techlibs/common + TECHLIBS_PREFIX=../../techlibs +else + COMMON_PREFIX=/usr/local/share/yosys + TECHLIBS_PREFIX=/usr/local/share/yosys +fi +{ +echo "all::" +for x in *.ys; do + echo "all:: run-$x" + echo "run-$x:" + echo " @echo 'Running $x..'" + echo " @../../yosys -ql ${x%.ys}.log $x -w 'Yosys has only limited support for tri-state logic at the moment.'" + + if [ -f "${x%.ys}_tb.v" ]; then + echo " @echo 'Running ${x%.ys}_tb.v..'" + echo " @iverilog -o ${x%.ys}_testbench $t ${x%.ys}_synth.v common.v $TECHLIBS_PREFIX/ice40/cells_sim.v" + echo " @vvp -N ${x%.ys}_testbench" + fi +done + +for s in *.sh; do + if [ "$s" != "run-test.sh" ]; then + echo "all:: run-$s" + echo "run-$s:" + echo " @echo 'Running $s..'" + echo " @bash $s" + fi +done +} > run-test.mk +exec ${MAKE:-make} -f run-test.mk diff --git a/tests/ecp5/tribuf.v b/tests/ecp5/tribuf.v new file mode 100644 index 000000000..870a02584 --- /dev/null +++ b/tests/ecp5/tribuf.v @@ -0,0 +1,23 @@ +module tristate (en, i, o); + input en; + input i; + output o; + + assign o = en ? i : 1'bz; + +endmodule + + +module top ( +input en, +input a, +output b +); + +tristate u_tri ( + .en (en ), + .i (a ), + .o (b ) + ); + +endmodule diff --git a/tests/ecp5/tribuf.ys b/tests/ecp5/tribuf.ys new file mode 100644 index 000000000..f454a0c02 --- /dev/null +++ b/tests/ecp5/tribuf.ys @@ -0,0 +1,9 @@ +read_verilog tribuf.v +hierarchy -top top +proc +flatten +equiv_opt -assert -map +/ecp5/cells_sim.v -map +/simcells.v synth_ecp5 # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module +select -assert-count 1 t:$_TBUF_ +select -assert-none t:$_TBUF_ %% t:* %D -- cgit v1.2.3 From 5fb4b12cb50b870b546d76f9c702678d8f0aa60a Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Marcin=20Ko=C5=9Bcielnicki?= Date: Tue, 27 Aug 2019 17:26:47 +0200 Subject: improve clkbuf_inhibit propagation upwards through hierarchy --- tests/techmap/clkbufmap.ys | 38 +++++++++++++++++++++++++++++++++----- 1 file changed, 33 insertions(+), 5 deletions(-) (limited to 'tests') diff --git a/tests/techmap/clkbufmap.ys b/tests/techmap/clkbufmap.ys index 5847c3ce5..f1277864e 100644 --- a/tests/techmap/clkbufmap.ys +++ b/tests/techmap/clkbufmap.ys @@ -3,11 +3,26 @@ module clkbuf (input i, (* clkbuf_driver *) output o); endmodule module dff ((* clkbuf_sink *) input clk, input d, output q); endmodule module dffe ((* clkbuf_sink *) input c, input d, e, output q); endmodule module latch (input e, d, output q); endmodule +module clkgen (output o); endmodule -module top(input clk1, clk2, clk3, d, e, output [2:0] q); +module top(input clk1, clk2, clk3, d, e, output [4:0] q); +wire clk4, clk5, clk6; dff s0 (.clk(clk1), .d(d), .q(q[0])); dffe s1 (.c(clk2), .d(d), .e(e), .q(q[1])); latch s2 (.e(clk3), .d(d), .q(q[2])); +sub s3 (.sclk4(clk4), .sclk5(clk5), .sclk6(clk6), .sd(d), .sq(q[3])); +dff s4 (.clk(clk4), .d(d), .q(q[4])); +dff s5 (.clk(clk5), .d(d), .q(q[4])); +dff s6 (.clk(clk6), .d(d), .q(q[4])); +endmodule + +module sub(output sclk4, output sclk5, output sclk6, input sd, output sq); +wire tmp; +clkgen s7(.o(sclk4)); +clkgen s8(.o(sclk5)); +clkgen s9(.o(tmp)); +clkbuf s10(.i(tmp), .o(sclk6)); +dff s11(.clk(sclk4), .d(sd), .q(sq)); endmodule EOT @@ -18,7 +33,8 @@ design -save ref design -load ref clkbufmap -buf clkbuf o:i -select -assert-count 2 t:clkbuf +select -assert-count 3 top/t:clkbuf +select -assert-count 2 sub/t:clkbuf select -set clk1 w:clk1 %a %co t:clkbuf %i # Find 'clk1' fanouts that are 'clkbuf' select -assert-count 1 @clk1 # Check there is one such fanout select -assert-count 1 @clk1 %x:+[o] %co c:s* %i # Check that the 'o' of that clkbuf drives one fanout @@ -27,6 +43,14 @@ select -set clk2 w:clk2 %a %co t:clkbuf %i select -assert-count 1 @clk2 select -assert-count 1 @clk2 %x:+[o] %co c:s* %i select -assert-count 1 @clk2 %x:+[o] %co c:s1 %i +select -set clk5 w:clk5 %a %ci t:clkbuf %i +select -assert-count 1 @clk5 +select -assert-count 1 @clk5 %x:+[o] %co c:s5 %i +select -assert-count 1 @clk5 %x:+[i] %ci c:s3 %i +select -set sclk4 w:sclk4 %a %ci t:clkbuf %i +select -assert-count 1 @sclk4 +select -assert-count 1 @sclk4 %x:+[o] %co c:s11 %i +select -assert-count 1 @sclk4 %x:+[i] %ci c:s7 %i # ---------------------- @@ -34,7 +58,7 @@ design -load ref setattr -set clkbuf_inhibit 0 w:clk1 setattr -set clkbuf_inhibit 1 w:clk2 clkbufmap -buf clkbuf o:i -select -assert-count 1 t:clkbuf +select -assert-count 2 top/t:clkbuf select -set clk1 w:clk1 %a %co t:clkbuf %i # Find 'clk1' fanouts that are 'clkbuf' select -assert-count 1 @clk1 # Check there is one such fanout select -assert-count 1 @clk1 %x:+[o] %co c:s* %i # Check that the 'o' of that clkbuf drives one fanout @@ -47,7 +71,8 @@ design -load ref setattr -set clkbuf_inhibit 1 w:clk1 setattr -set buffer_type "bufg" w:clk2 clkbufmap -buf clkbuf o:i w:* a:buffer_type=none a:buffer_type=bufr %u %d -select -assert-count 2 t:clkbuf +select -assert-count 3 top/t:clkbuf +select -assert-count 2 sub/t:clkbuf select -set clk1 w:clk1 %a %co t:clkbuf %i # Find 'clk1' fanouts that are 'clkbuf' select -assert-count 1 @clk1 # Check there is one such fanout select -assert-count 1 @clk1 %x:+[o] %co c:s* %i # Check that the 'o' of that clkbuf drives one fanout @@ -62,7 +87,10 @@ select -assert-count 1 @clk2 %x:+[o] %co c:s1 %i # And that one fanout is 's0 design -load ref setattr -set buffer_type "none" w:clk1 setattr -set buffer_type "bufr" w:clk2 +setattr -set buffer_type "bufr" w:sclk4 +setattr -set buffer_type "bufr" w:sclk5 clkbufmap -buf clkbuf o:i w:* a:buffer_type=none a:buffer_type=bufr %u %d select -assert-count 0 w:clk1 %a %co t:clkbuf %i select -assert-count 0 w:clk2 %a %co t:clkbuf %i -select -assert-count 0 t:clkbuf +select -assert-count 0 top/t:clkbuf +select -assert-count 1 sub/t:clkbuf -- cgit v1.2.3 From 980830f7b82f2a974f43580f61e917f99fbb4e7e Mon Sep 17 00:00:00 2001 From: SergeyDegtyar Date: Tue, 27 Aug 2019 18:28:05 +0300 Subject: Revert "Add tests for ecp5 architecture." This reverts commit 134d3fea909bae02f4f814e3d649658502b44b73. --- tests/ecp5/.gitignore | 4 -- tests/ecp5/add_sub.v | 13 ------- tests/ecp5/add_sub.ys | 8 ---- tests/ecp5/adffs.v | 91 ------------------------------------------- tests/ecp5/adffs.ys | 12 ------ tests/ecp5/common.v | 47 ----------------------- tests/ecp5/dffs.v | 37 ------------------ tests/ecp5/dffs.ys | 10 ----- tests/ecp5/div_mod.v | 13 ------- tests/ecp5/div_mod.ys | 12 ------ tests/ecp5/dpram.v | 20 ---------- tests/ecp5/dpram.ys | 18 --------- tests/ecp5/dpram_tb.v | 81 --------------------------------------- tests/ecp5/latches.v | 58 ---------------------------- tests/ecp5/latches.ys | 7 ---- tests/ecp5/latches_tb.v | 57 --------------------------- tests/ecp5/macc.v | 22 ----------- tests/ecp5/macc.ys | 10 ----- tests/ecp5/memory.v | 21 ---------- tests/ecp5/memory.ys | 22 ----------- tests/ecp5/memory_tb.v | 79 -------------------------------------- tests/ecp5/mul.v | 11 ------ tests/ecp5/mul.ys | 11 ------ tests/ecp5/mux.v | 100 ------------------------------------------------ tests/ecp5/mux.ys | 11 ------ tests/ecp5/rom.v | 15 -------- tests/ecp5/rom.ys | 9 ----- tests/ecp5/run-test.sh | 33 ---------------- tests/ecp5/tribuf.v | 23 ----------- tests/ecp5/tribuf.ys | 9 ----- 30 files changed, 864 deletions(-) delete mode 100644 tests/ecp5/.gitignore delete mode 100644 tests/ecp5/add_sub.v delete mode 100644 tests/ecp5/add_sub.ys delete mode 100644 tests/ecp5/adffs.v delete mode 100644 tests/ecp5/adffs.ys delete mode 100644 tests/ecp5/common.v delete mode 100644 tests/ecp5/dffs.v delete mode 100644 tests/ecp5/dffs.ys delete mode 100644 tests/ecp5/div_mod.v delete mode 100644 tests/ecp5/div_mod.ys delete mode 100644 tests/ecp5/dpram.v delete mode 100644 tests/ecp5/dpram.ys delete mode 100644 tests/ecp5/dpram_tb.v delete mode 100644 tests/ecp5/latches.v delete mode 100644 tests/ecp5/latches.ys delete mode 100644 tests/ecp5/latches_tb.v delete mode 100644 tests/ecp5/macc.v delete mode 100644 tests/ecp5/macc.ys delete mode 100644 tests/ecp5/memory.v delete mode 100644 tests/ecp5/memory.ys delete mode 100644 tests/ecp5/memory_tb.v delete mode 100644 tests/ecp5/mul.v delete mode 100644 tests/ecp5/mul.ys delete mode 100644 tests/ecp5/mux.v delete mode 100644 tests/ecp5/mux.ys delete mode 100644 tests/ecp5/rom.v delete mode 100644 tests/ecp5/rom.ys delete mode 100755 tests/ecp5/run-test.sh delete mode 100644 tests/ecp5/tribuf.v delete mode 100644 tests/ecp5/tribuf.ys (limited to 'tests') diff --git a/tests/ecp5/.gitignore b/tests/ecp5/.gitignore deleted file mode 100644 index 9a71dca69..000000000 --- a/tests/ecp5/.gitignore +++ /dev/null @@ -1,4 +0,0 @@ -*.log -/run-test.mk -+*_synth.v -+*_testbench diff --git a/tests/ecp5/add_sub.v b/tests/ecp5/add_sub.v deleted file mode 100644 index 177c32e30..000000000 --- a/tests/ecp5/add_sub.v +++ /dev/null @@ -1,13 +0,0 @@ -module top -( - input [3:0] x, - input [3:0] y, - - output [3:0] A, - output [3:0] B - ); - -assign A = x + y; -assign B = x - y; - -endmodule diff --git a/tests/ecp5/add_sub.ys b/tests/ecp5/add_sub.ys deleted file mode 100644 index 03aec6694..000000000 --- a/tests/ecp5/add_sub.ys +++ /dev/null @@ -1,8 +0,0 @@ -read_verilog add_sub.v -hierarchy -top top -equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check -design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) -cd top # Constrain all select calls below inside the top module -select -assert-count 10 t:LUT4 -select -assert-none t:LUT4 %% t:* %D - diff --git a/tests/ecp5/adffs.v b/tests/ecp5/adffs.v deleted file mode 100644 index 93c8bf52c..000000000 --- a/tests/ecp5/adffs.v +++ /dev/null @@ -1,91 +0,0 @@ -module adff - ( input d, clk, clr, output reg q ); - initial begin - q = 0; - end - always @( posedge clk, posedge clr ) - if ( clr ) - q <= 1'b0; - else - q <= d; -endmodule - -module adffn - ( input d, clk, clr, output reg q ); - initial begin - q = 0; - end - always @( posedge clk, negedge clr ) - if ( !clr ) - q <= 1'b0; - else - q <= d; -endmodule - -module dffsr - ( input d, clk, pre, clr, output reg q ); - initial begin - q = 0; - end - always @( posedge clk, posedge pre, posedge clr ) - if ( clr ) - q <= 1'b0; - else if ( pre ) - q <= 1'b1; - else - q <= d; -endmodule - -module ndffnsnr - ( input d, clk, pre, clr, output reg q ); - initial begin - q = 0; - end - always @( negedge clk, negedge pre, negedge clr ) - if ( !clr ) - q <= 1'b0; - else if ( !pre ) - q <= 1'b1; - else - q <= d; -endmodule - -module top ( -input clk, -input clr, -input pre, -input a, -output b,b1,b2,b3 -); - -dffsr u_dffsr ( - .clk (clk ), - .clr (clr), - .pre (pre), - .d (a ), - .q (b ) - ); - -ndffnsnr u_ndffnsnr ( - .clk (clk ), - .clr (clr), - .pre (pre), - .d (a ), - .q (b1 ) - ); - -adff u_adff ( - .clk (clk ), - .clr (clr), - .d (a ), - .q (b2 ) - ); - -adffn u_adffn ( - .clk (clk ), - .clr (clr), - .d (a ), - .q (b3 ) - ); - -endmodule diff --git a/tests/ecp5/adffs.ys b/tests/ecp5/adffs.ys deleted file mode 100644 index 5829fef5f..000000000 --- a/tests/ecp5/adffs.ys +++ /dev/null @@ -1,12 +0,0 @@ -read_verilog adffs.v -proc -async2sync # converts async flops to a 'sync' variant clocked by a 'super'-clock -flatten -equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check -design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) -cd top # Constrain all select calls below inside the top module -select -assert-count 1 t:DFF -select -assert-count 1 t:DFFN -select -assert-count 2 t:DFFSR -select -assert-count 7 t:LUT4 -select -assert-none t:DFF t:DFFN t:DFFSR t:LUT4 %% t:* %D diff --git a/tests/ecp5/common.v b/tests/ecp5/common.v deleted file mode 100644 index 5446f0817..000000000 --- a/tests/ecp5/common.v +++ /dev/null @@ -1,47 +0,0 @@ -module assert_dff(input clk, input test, input pat); - always @(posedge clk) - begin - #1; - if (test != pat) - begin - $display("ERROR: ASSERTION FAILED in %m:",$time); - $stop; - end - end -endmodule - -module assert_tri(input en, input A, input B); - always @(posedge en) - begin - #1; - if (A !== B) - begin - $display("ERROR: ASSERTION FAILED in %m:",$time," ",A," ",B); - $stop; - end - end -endmodule - -module assert_Z(input clk, input A); - always @(posedge clk) - begin - #1; - if (A === 1'bZ) - begin - $display("ERROR: ASSERTION FAILED in %m:",$time," ",A); - $stop; - end - end -endmodule - -module assert_comb(input A, input B); - always @(*) - begin - #1; - if (A !== B) - begin - $display("ERROR: ASSERTION FAILED in %m:",$time," ",A," ",B); - $stop; - end - end -endmodule diff --git a/tests/ecp5/dffs.v b/tests/ecp5/dffs.v deleted file mode 100644 index d97840c43..000000000 --- a/tests/ecp5/dffs.v +++ /dev/null @@ -1,37 +0,0 @@ -module dff - ( input d, clk, output reg q ); - always @( posedge clk ) - q <= d; -endmodule - -module dffe - ( input d, clk, en, output reg q ); - initial begin - q = 0; - end - always @( posedge clk ) - if ( en ) - q <= d; -endmodule - -module top ( -input clk, -input en, -input a, -output b,b1, -); - -dff u_dff ( - .clk (clk ), - .d (a ), - .q (b ) - ); - -dffe u_ndffe ( - .clk (clk ), - .en (en), - .d (a ), - .q (b1 ) - ); - -endmodule diff --git a/tests/ecp5/dffs.ys b/tests/ecp5/dffs.ys deleted file mode 100644 index 07470c5ba..000000000 --- a/tests/ecp5/dffs.ys +++ /dev/null @@ -1,10 +0,0 @@ -read_verilog dffs.v -hierarchy -top top -proc -flatten -equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check -design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) -cd top # Constrain all select calls below inside the top module -select -assert-count 1 t:DFF -select -assert-count 1 t:DFFE -select -assert-none t:DFF t:DFFE %% t:* %D diff --git a/tests/ecp5/div_mod.v b/tests/ecp5/div_mod.v deleted file mode 100644 index 64a36707d..000000000 --- a/tests/ecp5/div_mod.v +++ /dev/null @@ -1,13 +0,0 @@ -module top -( - input [3:0] x, - input [3:0] y, - - output [3:0] A, - output [3:0] B - ); - -assign A = x % y; -assign B = x / y; - -endmodule diff --git a/tests/ecp5/div_mod.ys b/tests/ecp5/div_mod.ys deleted file mode 100644 index 169c5978e..000000000 --- a/tests/ecp5/div_mod.ys +++ /dev/null @@ -1,12 +0,0 @@ -read_verilog div_mod.v -hierarchy -top top -flatten -equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check -design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) -cd top # Constrain all select calls below inside the top module - -select -assert-count 28 t:CCU2C -select -assert-count 45 t:L6MUX21 -select -assert-count 183 t:LUT4 -select -assert-count 79 t:PFUMX -select -assert-none t:LUT4 t:CCU2C t:L6MUX21 t:PFUMX %% t:* %D diff --git a/tests/ecp5/dpram.v b/tests/ecp5/dpram.v deleted file mode 100644 index 2e69d6b3b..000000000 --- a/tests/ecp5/dpram.v +++ /dev/null @@ -1,20 +0,0 @@ -module top (din, write_en, waddr, wclk, raddr, rclk, dout); -parameter addr_width = 8; -parameter data_width = 8; -input [addr_width-1:0] waddr, raddr; -input [data_width-1:0] din; -input write_en, wclk, rclk; -output [data_width-1:0] dout; -reg [data_width-1:0] dout; -reg [data_width-1:0] mem [(1< 6'h3E) - mem_init <= 1; - end - - always @(posedge clk) begin - //#3; - we_a <= !we_a; - end - - reg [7:0] mem [(1<<8)-1:0]; - - always @(posedge clk) // Write memory. - begin - if (we_a) - mem[addr_a] <= data_a; // Using write address bus. - end - always @(posedge clk) // Read memory. - begin - pq_a <= mem[addr_b]; // Using read address bus. - end - - top uut ( - .din(data_a), - .write_en(we_a), - .waddr(addr_a), - .wclk(clk), - .raddr(addr_b), - .rclk(clk), - .dout(q_a) - ); - - uut_mem_checker port_a_test(.clk(clk), .init(mem_init), .en(!we_a), .A(q_a), .B(pq_a)); - -endmodule - -module uut_mem_checker(input clk, input init, input en, input [7:0] A, input [7:0] B); - always @(posedge clk) - begin - #1; - if (en == 1 & init == 1 & A !== B) - begin - $display("ERROR: ASSERTION FAILED in %m:",$time," ",A," ",B); - $stop; - end - end -endmodule diff --git a/tests/ecp5/latches.v b/tests/ecp5/latches.v deleted file mode 100644 index 9dc43e4c2..000000000 --- a/tests/ecp5/latches.v +++ /dev/null @@ -1,58 +0,0 @@ -module latchp - ( input d, clk, en, output reg q ); - always @* - if ( en ) - q <= d; -endmodule - -module latchn - ( input d, clk, en, output reg q ); - always @* - if ( !en ) - q <= d; -endmodule - -module latchsr - ( input d, clk, en, clr, pre, output reg q ); - always @* - if ( clr ) - q <= 1'b0; - else if ( pre ) - q <= 1'b1; - else if ( en ) - q <= d; -endmodule - - -module top ( -input clk, -input clr, -input pre, -input a, -output b,b1,b2 -); - - -latchp u_latchp ( - .en (clk ), - .d (a ), - .q (b ) - ); - - -latchn u_latchn ( - .en (clk ), - .d (a ), - .q (b1 ) - ); - - -latchsr u_latchsr ( - .en (clk ), - .clr (clr), - .pre (pre), - .d (a ), - .q (b2 ) - ); - -endmodule diff --git a/tests/ecp5/latches.ys b/tests/ecp5/latches.ys deleted file mode 100644 index 2c77304a1..000000000 --- a/tests/ecp5/latches.ys +++ /dev/null @@ -1,7 +0,0 @@ -read_verilog latches.v -synth_ecp5 -cd top -select -assert-count 4 t:LUT4 -select -assert-count 1 t:PFUMX -select -assert-none t:LUT4 t:PFUMX %% t:* %D -write_verilog latches_synth.v diff --git a/tests/ecp5/latches_tb.v b/tests/ecp5/latches_tb.v deleted file mode 100644 index b0585264b..000000000 --- a/tests/ecp5/latches_tb.v +++ /dev/null @@ -1,57 +0,0 @@ -module testbench; - reg clk; - - initial begin - // $dumpfile("testbench.vcd"); - // $dumpvars(0, testbench); - - #5 clk = 0; - repeat (10000) begin - #5 clk = 1; - #5 clk = 0; - end - end - - - reg [2:0] dinA = 0; - wire doutB,doutB1,doutB2; - reg lat,latn,latsr = 0; - - top uut ( - .clk (clk ), - .a (dinA[0] ), - .pre (dinA[1] ), - .clr (dinA[2] ), - .b (doutB ), - .b1 (doutB1 ), - .b2 (doutB2 ) - ); - - always @(posedge clk) begin - #3; - dinA <= dinA + 1; - end - - always @* - if ( clk ) - lat <= dinA[0]; - - - always @* - if ( !clk ) - latn <= dinA[0]; - - - always @* - if ( dinA[2] ) - latsr <= 1'b0; - else if ( dinA[1] ) - latsr <= 1'b1; - else if ( clk ) - latsr <= dinA[0]; - - assert_dff lat_test(.clk(clk), .test(doutB), .pat(lat)); - assert_dff latn_test(.clk(clk), .test(doutB1), .pat(latn)); - assert_dff latsr_test(.clk(clk), .test(doutB2), .pat(latsr)); - -endmodule diff --git a/tests/ecp5/macc.v b/tests/ecp5/macc.v deleted file mode 100644 index 115f8ce42..000000000 --- a/tests/ecp5/macc.v +++ /dev/null @@ -1,22 +0,0 @@ -module top(clk,a,b,c,set); -parameter A_WIDTH = 4; -parameter B_WIDTH = 3; -input set; -input clk; -input signed [(A_WIDTH - 1):0] a; -input signed [(B_WIDTH - 1):0] b; -output signed [(A_WIDTH + B_WIDTH - 1):0] c; -reg [(A_WIDTH + B_WIDTH - 1):0] reg_tmp_c; -assign c = reg_tmp_c; -always @(posedge clk) -begin -if(set) -begin -reg_tmp_c <= 0; -end -else -begin -reg_tmp_c <= a * b + c; -end -end -endmodule diff --git a/tests/ecp5/macc.ys b/tests/ecp5/macc.ys deleted file mode 100644 index 530877727..000000000 --- a/tests/ecp5/macc.ys +++ /dev/null @@ -1,10 +0,0 @@ -read_verilog macc.v -proc -hierarchy -top top -equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check -design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) -cd top # Constrain all select calls below inside the top module -select -assert-count 41 t:LUT4 -select -assert-count 6 t:CARRY -select -assert-count 7 t:DFFSR -select -assert-none t:LUT4 t:CARRY t:DFFSR %% t:* %D diff --git a/tests/ecp5/memory.v b/tests/ecp5/memory.v deleted file mode 100644 index cb7753f7b..000000000 --- a/tests/ecp5/memory.v +++ /dev/null @@ -1,21 +0,0 @@ -module top -( - input [7:0] data_a, - input [6:1] addr_a, - input we_a, clk, - output reg [7:0] q_a -); - // Declare the RAM variable - reg [7:0] ram[63:0]; - - // Port A - always @ (posedge clk) - begin - if (we_a) - begin - ram[addr_a] <= data_a; - q_a <= data_a; - end - q_a <= ram[addr_a]; - end -endmodule diff --git a/tests/ecp5/memory.ys b/tests/ecp5/memory.ys deleted file mode 100644 index 9fdeb0d16..000000000 --- a/tests/ecp5/memory.ys +++ /dev/null @@ -1,22 +0,0 @@ -read_verilog memory.v -hierarchy -top top -proc -memory -nomap -equiv_opt -run :prove -map +/ecp5/cells_sim.v synth_ecp5 -memory -opt -full - -# TODO -#equiv_opt -run prove: -assert null -miter -equiv -flatten -make_assert -make_outputs gold gate miter -#sat -verify -prove-asserts -tempinduct -show-inputs -show-outputs miter - -design -load postopt -cd top -select -assert-count 24 t:L6MUX21 -select -assert-count 71 t:LUT4 -select -assert-count 32 t:PFUMX -select -assert-count 8 t:TRELLIS_DPR16X4 -select -assert-count 35 t:TRELLIS_FF -select -assert-none t:L6MUX21 t:LUT4 t:PFUMX t:TRELLIS_DPR16X4 t:TRELLIS_FF %% t:* %D -write_verilog memory_synth.v diff --git a/tests/ecp5/memory_tb.v b/tests/ecp5/memory_tb.v deleted file mode 100644 index be69374eb..000000000 --- a/tests/ecp5/memory_tb.v +++ /dev/null @@ -1,79 +0,0 @@ -module testbench; - reg clk; - - initial begin - // $dumpfile("testbench.vcd"); - // $dumpvars(0, testbench); - - #5 clk = 0; - repeat (10000) begin - #5 clk = 1; - #5 clk = 0; - end - end - - - reg [7:0] data_a = 0; - reg [5:0] addr_a = 0; - reg we_a = 0; - reg re_a = 1; - wire [7:0] q_a; - reg mem_init = 0; - - reg [7:0] pq_a; - - top uut ( - .data_a(data_a), - .addr_a(addr_a), - .we_a(we_a), - .clk(clk), - .q_a(q_a) - ); - - always @(posedge clk) begin - #3; - data_a <= data_a + 17; - - addr_a <= addr_a + 1; - end - - always @(posedge addr_a) begin - #10; - if(addr_a > 6'h3E) - mem_init <= 1; - end - - always @(posedge clk) begin - //#3; - we_a <= !we_a; - end - - // Declare the RAM variable for check - reg [7:0] ram[63:0]; - - // Port A for check - always @ (posedge clk) - begin - if (we_a) - begin - ram[addr_a] <= data_a; - pq_a <= data_a; - end - pq_a <= ram[addr_a]; - end - - uut_mem_checker port_a_test(.clk(clk), .init(mem_init), .en(!we_a), .A(q_a), .B(pq_a)); - -endmodule - -module uut_mem_checker(input clk, input init, input en, input [7:0] A, input [7:0] B); - always @(posedge clk) - begin - #1; - if (en == 1 & init == 1 & A !== B) - begin - $display("ERROR: ASSERTION FAILED in %m:",$time," ",A," ",B); - $stop; - end - end -endmodule diff --git a/tests/ecp5/mul.v b/tests/ecp5/mul.v deleted file mode 100644 index d5b48b1d7..000000000 --- a/tests/ecp5/mul.v +++ /dev/null @@ -1,11 +0,0 @@ -module top -( - input [5:0] x, - input [5:0] y, - - output [11:0] A, - ); - -assign A = x * y; - -endmodule diff --git a/tests/ecp5/mul.ys b/tests/ecp5/mul.ys deleted file mode 100644 index 0e8d6908f..000000000 --- a/tests/ecp5/mul.ys +++ /dev/null @@ -1,11 +0,0 @@ -read_verilog mul.v -hierarchy -top top -equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check -design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) -cd top # Constrain all select calls below inside the top module -select -assert-count 6 t:CCU2C -select -assert-count 46 t:L6MUX21 -select -assert-count 169 t:LUT4 -select -assert-count 72 t:PFUMX - -select -assert-none t:CCU2C t:L6MUX21 t:LUT4 t:PFUMX %% t:* %D diff --git a/tests/ecp5/mux.v b/tests/ecp5/mux.v deleted file mode 100644 index 0814b733e..000000000 --- a/tests/ecp5/mux.v +++ /dev/null @@ -1,100 +0,0 @@ -module mux2 (S,A,B,Y); - input S; - input A,B; - output reg Y; - - always @(*) - Y = (S)? B : A; -endmodule - -module mux4 ( S, D, Y ); - -input[1:0] S; -input[3:0] D; -output Y; - -reg Y; -wire[1:0] S; -wire[3:0] D; - -always @* -begin - case( S ) - 0 : Y = D[0]; - 1 : Y = D[1]; - 2 : Y = D[2]; - 3 : Y = D[3]; - endcase -end - -endmodule - -module mux8 ( S, D, Y ); - -input[2:0] S; -input[7:0] D; -output Y; - -reg Y; -wire[2:0] S; -wire[7:0] D; - -always @* -begin - case( S ) - 0 : Y = D[0]; - 1 : Y = D[1]; - 2 : Y = D[2]; - 3 : Y = D[3]; - 4 : Y = D[4]; - 5 : Y = D[5]; - 6 : Y = D[6]; - 7 : Y = D[7]; - endcase -end - -endmodule - -module mux16 (D, S, Y); - input [15:0] D; - input [3:0] S; - output Y; - -assign Y = D[S]; - -endmodule - - -module top ( -input [3:0] S, -input [15:0] D, -output M2,M4,M8,M16 -); - -mux2 u_mux2 ( - .S (S[0]), - .A (D[0]), - .B (D[1]), - .Y (M2) - ); - - -mux4 u_mux4 ( - .S (S[1:0]), - .D (D[3:0]), - .Y (M4) - ); - -mux8 u_mux8 ( - .S (S[2:0]), - .D (D[7:0]), - .Y (M8) - ); - -mux16 u_mux16 ( - .S (S[3:0]), - .D (D[15:0]), - .Y (M16) - ); - -endmodule diff --git a/tests/ecp5/mux.ys b/tests/ecp5/mux.ys deleted file mode 100644 index 47a965dd3..000000000 --- a/tests/ecp5/mux.ys +++ /dev/null @@ -1,11 +0,0 @@ -read_verilog mux.v -proc -flatten -equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check -design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) -cd top # Constrain all select calls below inside the top module -select -assert-count 30 t:LUT4 -select -assert-count 7 t:L6MUX21 -select -assert-count 12 t:PFUMX - -select -assert-none t:LUT4 t:L6MUX21 t:PFUMX %% t:* %D diff --git a/tests/ecp5/rom.v b/tests/ecp5/rom.v deleted file mode 100644 index c31ca3b2b..000000000 --- a/tests/ecp5/rom.v +++ /dev/null @@ -1,15 +0,0 @@ -module top(data, addr); -output [3:0] data; -input [4:0] addr; -always @(addr) begin -case (addr) -0 : data = 'h4; -1 : data = 'h9; -2 : data = 'h1; -15 : data = 'h8; -16 : data = 'h1; -17 : data = 'h0; -default : data = 'h0; -endcase -end -endmodule diff --git a/tests/ecp5/rom.ys b/tests/ecp5/rom.ys deleted file mode 100644 index 8a52749a1..000000000 --- a/tests/ecp5/rom.ys +++ /dev/null @@ -1,9 +0,0 @@ -read_verilog rom.v -proc -flatten -equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check -design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) -cd top # Constrain all select calls below inside the top module -select -assert-count 6 t:LUT4 -select -assert-count 3 t:PFUMX -select -assert-none t:LUT4 t:PFUMX %% t:* %D diff --git a/tests/ecp5/run-test.sh b/tests/ecp5/run-test.sh deleted file mode 100755 index bd9d35314..000000000 --- a/tests/ecp5/run-test.sh +++ /dev/null @@ -1,33 +0,0 @@ -set -e -if [ -f "../../techlibs/common/simcells.v" ]; then - COMMON_PREFIX=../../techlibs/common - TECHLIBS_PREFIX=../../techlibs -else - COMMON_PREFIX=/usr/local/share/yosys - TECHLIBS_PREFIX=/usr/local/share/yosys -fi -{ -echo "all::" -for x in *.ys; do - echo "all:: run-$x" - echo "run-$x:" - echo " @echo 'Running $x..'" - echo " @../../yosys -ql ${x%.ys}.log $x -w 'Yosys has only limited support for tri-state logic at the moment.'" - - if [ -f "${x%.ys}_tb.v" ]; then - echo " @echo 'Running ${x%.ys}_tb.v..'" - echo " @iverilog -o ${x%.ys}_testbench $t ${x%.ys}_synth.v common.v $TECHLIBS_PREFIX/ice40/cells_sim.v" - echo " @vvp -N ${x%.ys}_testbench" - fi -done - -for s in *.sh; do - if [ "$s" != "run-test.sh" ]; then - echo "all:: run-$s" - echo "run-$s:" - echo " @echo 'Running $s..'" - echo " @bash $s" - fi -done -} > run-test.mk -exec ${MAKE:-make} -f run-test.mk diff --git a/tests/ecp5/tribuf.v b/tests/ecp5/tribuf.v deleted file mode 100644 index 870a02584..000000000 --- a/tests/ecp5/tribuf.v +++ /dev/null @@ -1,23 +0,0 @@ -module tristate (en, i, o); - input en; - input i; - output o; - - assign o = en ? i : 1'bz; - -endmodule - - -module top ( -input en, -input a, -output b -); - -tristate u_tri ( - .en (en ), - .i (a ), - .o (b ) - ); - -endmodule diff --git a/tests/ecp5/tribuf.ys b/tests/ecp5/tribuf.ys deleted file mode 100644 index f454a0c02..000000000 --- a/tests/ecp5/tribuf.ys +++ /dev/null @@ -1,9 +0,0 @@ -read_verilog tribuf.v -hierarchy -top top -proc -flatten -equiv_opt -assert -map +/ecp5/cells_sim.v -map +/simcells.v synth_ecp5 # equivalency check -design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) -cd top # Constrain all select calls below inside the top module -select -assert-count 1 t:$_TBUF_ -select -assert-none t:$_TBUF_ %% t:* %D -- cgit v1.2.3 From 00387f39277ab817b3b17e72b59793e6d5dfcde8 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Tue, 27 Aug 2019 09:24:32 -0700 Subject: Revert to using clean --- tests/sat/initval.ys | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'tests') diff --git a/tests/sat/initval.ys b/tests/sat/initval.ys index 3d88aa971..2079d2f34 100644 --- a/tests/sat/initval.ys +++ b/tests/sat/initval.ys @@ -1,4 +1,4 @@ read_verilog -sv initval.v -proc; +proc;; sat -seq 10 -prove-asserts -- cgit v1.2.3 From 2270ead09fb4695442c66fe5c06445235f390f2b Mon Sep 17 00:00:00 2001 From: SergeyDegtyar Date: Wed, 28 Aug 2019 09:47:03 +0300 Subject: Add tests for ecp5 --- tests/ecp5/.gitignore | 2 + tests/ecp5/add_sub.v | 13 +++++++ tests/ecp5/add_sub.ys | 8 ++++ tests/ecp5/adffs.v | 91 +++++++++++++++++++++++++++++++++++++++++++ tests/ecp5/adffs.ys | 12 ++++++ tests/ecp5/common.v | 47 +++++++++++++++++++++++ tests/ecp5/dffs.v | 37 ++++++++++++++++++ tests/ecp5/dffs.ys | 10 +++++ tests/ecp5/div_mod.v | 13 +++++++ tests/ecp5/div_mod.ys | 12 ++++++ tests/ecp5/dpram.v | 20 ++++++++++ tests/ecp5/dpram.ys | 18 +++++++++ tests/ecp5/dpram_tb.v | 81 +++++++++++++++++++++++++++++++++++++++ tests/ecp5/latches.v | 58 ++++++++++++++++++++++++++++ tests/ecp5/latches.ys | 7 ++++ tests/ecp5/latches_tb.v | 57 +++++++++++++++++++++++++++ tests/ecp5/macc.v | 22 +++++++++++ tests/ecp5/macc.ys | 10 +++++ tests/ecp5/memory.v | 21 ++++++++++ tests/ecp5/memory.ys | 22 +++++++++++ tests/ecp5/memory_tb.v | 79 ++++++++++++++++++++++++++++++++++++++ tests/ecp5/mul.v | 11 ++++++ tests/ecp5/mul.ys | 11 ++++++ tests/ecp5/mux.v | 100 ++++++++++++++++++++++++++++++++++++++++++++++++ tests/ecp5/mux.ys | 11 ++++++ tests/ecp5/rom.v | 15 ++++++++ tests/ecp5/rom.ys | 9 +++++ tests/ecp5/run-test.sh | 33 ++++++++++++++++ tests/ecp5/tribuf.v | 23 +++++++++++ tests/ecp5/tribuf.ys | 9 +++++ 30 files changed, 862 insertions(+) create mode 100644 tests/ecp5/.gitignore create mode 100644 tests/ecp5/add_sub.v create mode 100644 tests/ecp5/add_sub.ys create mode 100644 tests/ecp5/adffs.v create mode 100644 tests/ecp5/adffs.ys create mode 100644 tests/ecp5/common.v create mode 100644 tests/ecp5/dffs.v create mode 100644 tests/ecp5/dffs.ys create mode 100644 tests/ecp5/div_mod.v create mode 100644 tests/ecp5/div_mod.ys create mode 100644 tests/ecp5/dpram.v create mode 100644 tests/ecp5/dpram.ys create mode 100644 tests/ecp5/dpram_tb.v create mode 100644 tests/ecp5/latches.v create mode 100644 tests/ecp5/latches.ys create mode 100644 tests/ecp5/latches_tb.v create mode 100644 tests/ecp5/macc.v create mode 100644 tests/ecp5/macc.ys create mode 100644 tests/ecp5/memory.v create mode 100644 tests/ecp5/memory.ys create mode 100644 tests/ecp5/memory_tb.v create mode 100644 tests/ecp5/mul.v create mode 100644 tests/ecp5/mul.ys create mode 100644 tests/ecp5/mux.v create mode 100644 tests/ecp5/mux.ys create mode 100644 tests/ecp5/rom.v create mode 100644 tests/ecp5/rom.ys create mode 100755 tests/ecp5/run-test.sh create mode 100644 tests/ecp5/tribuf.v create mode 100644 tests/ecp5/tribuf.ys (limited to 'tests') diff --git a/tests/ecp5/.gitignore b/tests/ecp5/.gitignore new file mode 100644 index 000000000..1d329c933 --- /dev/null +++ b/tests/ecp5/.gitignore @@ -0,0 +1,2 @@ +*.log +/run-test.mk diff --git a/tests/ecp5/add_sub.v b/tests/ecp5/add_sub.v new file mode 100644 index 000000000..177c32e30 --- /dev/null +++ b/tests/ecp5/add_sub.v @@ -0,0 +1,13 @@ +module top +( + input [3:0] x, + input [3:0] y, + + output [3:0] A, + output [3:0] B + ); + +assign A = x + y; +assign B = x - y; + +endmodule diff --git a/tests/ecp5/add_sub.ys b/tests/ecp5/add_sub.ys new file mode 100644 index 000000000..03aec6694 --- /dev/null +++ b/tests/ecp5/add_sub.ys @@ -0,0 +1,8 @@ +read_verilog add_sub.v +hierarchy -top top +equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module +select -assert-count 10 t:LUT4 +select -assert-none t:LUT4 %% t:* %D + diff --git a/tests/ecp5/adffs.v b/tests/ecp5/adffs.v new file mode 100644 index 000000000..93c8bf52c --- /dev/null +++ b/tests/ecp5/adffs.v @@ -0,0 +1,91 @@ +module adff + ( input d, clk, clr, output reg q ); + initial begin + q = 0; + end + always @( posedge clk, posedge clr ) + if ( clr ) + q <= 1'b0; + else + q <= d; +endmodule + +module adffn + ( input d, clk, clr, output reg q ); + initial begin + q = 0; + end + always @( posedge clk, negedge clr ) + if ( !clr ) + q <= 1'b0; + else + q <= d; +endmodule + +module dffsr + ( input d, clk, pre, clr, output reg q ); + initial begin + q = 0; + end + always @( posedge clk, posedge pre, posedge clr ) + if ( clr ) + q <= 1'b0; + else if ( pre ) + q <= 1'b1; + else + q <= d; +endmodule + +module ndffnsnr + ( input d, clk, pre, clr, output reg q ); + initial begin + q = 0; + end + always @( negedge clk, negedge pre, negedge clr ) + if ( !clr ) + q <= 1'b0; + else if ( !pre ) + q <= 1'b1; + else + q <= d; +endmodule + +module top ( +input clk, +input clr, +input pre, +input a, +output b,b1,b2,b3 +); + +dffsr u_dffsr ( + .clk (clk ), + .clr (clr), + .pre (pre), + .d (a ), + .q (b ) + ); + +ndffnsnr u_ndffnsnr ( + .clk (clk ), + .clr (clr), + .pre (pre), + .d (a ), + .q (b1 ) + ); + +adff u_adff ( + .clk (clk ), + .clr (clr), + .d (a ), + .q (b2 ) + ); + +adffn u_adffn ( + .clk (clk ), + .clr (clr), + .d (a ), + .q (b3 ) + ); + +endmodule diff --git a/tests/ecp5/adffs.ys b/tests/ecp5/adffs.ys new file mode 100644 index 000000000..5829fef5f --- /dev/null +++ b/tests/ecp5/adffs.ys @@ -0,0 +1,12 @@ +read_verilog adffs.v +proc +async2sync # converts async flops to a 'sync' variant clocked by a 'super'-clock +flatten +equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module +select -assert-count 1 t:DFF +select -assert-count 1 t:DFFN +select -assert-count 2 t:DFFSR +select -assert-count 7 t:LUT4 +select -assert-none t:DFF t:DFFN t:DFFSR t:LUT4 %% t:* %D diff --git a/tests/ecp5/common.v b/tests/ecp5/common.v new file mode 100644 index 000000000..5446f0817 --- /dev/null +++ b/tests/ecp5/common.v @@ -0,0 +1,47 @@ +module assert_dff(input clk, input test, input pat); + always @(posedge clk) + begin + #1; + if (test != pat) + begin + $display("ERROR: ASSERTION FAILED in %m:",$time); + $stop; + end + end +endmodule + +module assert_tri(input en, input A, input B); + always @(posedge en) + begin + #1; + if (A !== B) + begin + $display("ERROR: ASSERTION FAILED in %m:",$time," ",A," ",B); + $stop; + end + end +endmodule + +module assert_Z(input clk, input A); + always @(posedge clk) + begin + #1; + if (A === 1'bZ) + begin + $display("ERROR: ASSERTION FAILED in %m:",$time," ",A); + $stop; + end + end +endmodule + +module assert_comb(input A, input B); + always @(*) + begin + #1; + if (A !== B) + begin + $display("ERROR: ASSERTION FAILED in %m:",$time," ",A," ",B); + $stop; + end + end +endmodule diff --git a/tests/ecp5/dffs.v b/tests/ecp5/dffs.v new file mode 100644 index 000000000..d97840c43 --- /dev/null +++ b/tests/ecp5/dffs.v @@ -0,0 +1,37 @@ +module dff + ( input d, clk, output reg q ); + always @( posedge clk ) + q <= d; +endmodule + +module dffe + ( input d, clk, en, output reg q ); + initial begin + q = 0; + end + always @( posedge clk ) + if ( en ) + q <= d; +endmodule + +module top ( +input clk, +input en, +input a, +output b,b1, +); + +dff u_dff ( + .clk (clk ), + .d (a ), + .q (b ) + ); + +dffe u_ndffe ( + .clk (clk ), + .en (en), + .d (a ), + .q (b1 ) + ); + +endmodule diff --git a/tests/ecp5/dffs.ys b/tests/ecp5/dffs.ys new file mode 100644 index 000000000..07470c5ba --- /dev/null +++ b/tests/ecp5/dffs.ys @@ -0,0 +1,10 @@ +read_verilog dffs.v +hierarchy -top top +proc +flatten +equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module +select -assert-count 1 t:DFF +select -assert-count 1 t:DFFE +select -assert-none t:DFF t:DFFE %% t:* %D diff --git a/tests/ecp5/div_mod.v b/tests/ecp5/div_mod.v new file mode 100644 index 000000000..64a36707d --- /dev/null +++ b/tests/ecp5/div_mod.v @@ -0,0 +1,13 @@ +module top +( + input [3:0] x, + input [3:0] y, + + output [3:0] A, + output [3:0] B + ); + +assign A = x % y; +assign B = x / y; + +endmodule diff --git a/tests/ecp5/div_mod.ys b/tests/ecp5/div_mod.ys new file mode 100644 index 000000000..169c5978e --- /dev/null +++ b/tests/ecp5/div_mod.ys @@ -0,0 +1,12 @@ +read_verilog div_mod.v +hierarchy -top top +flatten +equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module + +select -assert-count 28 t:CCU2C +select -assert-count 45 t:L6MUX21 +select -assert-count 183 t:LUT4 +select -assert-count 79 t:PFUMX +select -assert-none t:LUT4 t:CCU2C t:L6MUX21 t:PFUMX %% t:* %D diff --git a/tests/ecp5/dpram.v b/tests/ecp5/dpram.v new file mode 100644 index 000000000..2e69d6b3b --- /dev/null +++ b/tests/ecp5/dpram.v @@ -0,0 +1,20 @@ +module top (din, write_en, waddr, wclk, raddr, rclk, dout); +parameter addr_width = 8; +parameter data_width = 8; +input [addr_width-1:0] waddr, raddr; +input [data_width-1:0] din; +input write_en, wclk, rclk; +output [data_width-1:0] dout; +reg [data_width-1:0] dout; +reg [data_width-1:0] mem [(1< 6'h3E) + mem_init <= 1; + end + + always @(posedge clk) begin + //#3; + we_a <= !we_a; + end + + reg [7:0] mem [(1<<8)-1:0]; + + always @(posedge clk) // Write memory. + begin + if (we_a) + mem[addr_a] <= data_a; // Using write address bus. + end + always @(posedge clk) // Read memory. + begin + pq_a <= mem[addr_b]; // Using read address bus. + end + + top uut ( + .din(data_a), + .write_en(we_a), + .waddr(addr_a), + .wclk(clk), + .raddr(addr_b), + .rclk(clk), + .dout(q_a) + ); + + uut_mem_checker port_a_test(.clk(clk), .init(mem_init), .en(!we_a), .A(q_a), .B(pq_a)); + +endmodule + +module uut_mem_checker(input clk, input init, input en, input [7:0] A, input [7:0] B); + always @(posedge clk) + begin + #1; + if (en == 1 & init == 1 & A !== B) + begin + $display("ERROR: ASSERTION FAILED in %m:",$time," ",A," ",B); + $stop; + end + end +endmodule diff --git a/tests/ecp5/latches.v b/tests/ecp5/latches.v new file mode 100644 index 000000000..9dc43e4c2 --- /dev/null +++ b/tests/ecp5/latches.v @@ -0,0 +1,58 @@ +module latchp + ( input d, clk, en, output reg q ); + always @* + if ( en ) + q <= d; +endmodule + +module latchn + ( input d, clk, en, output reg q ); + always @* + if ( !en ) + q <= d; +endmodule + +module latchsr + ( input d, clk, en, clr, pre, output reg q ); + always @* + if ( clr ) + q <= 1'b0; + else if ( pre ) + q <= 1'b1; + else if ( en ) + q <= d; +endmodule + + +module top ( +input clk, +input clr, +input pre, +input a, +output b,b1,b2 +); + + +latchp u_latchp ( + .en (clk ), + .d (a ), + .q (b ) + ); + + +latchn u_latchn ( + .en (clk ), + .d (a ), + .q (b1 ) + ); + + +latchsr u_latchsr ( + .en (clk ), + .clr (clr), + .pre (pre), + .d (a ), + .q (b2 ) + ); + +endmodule diff --git a/tests/ecp5/latches.ys b/tests/ecp5/latches.ys new file mode 100644 index 000000000..2c77304a1 --- /dev/null +++ b/tests/ecp5/latches.ys @@ -0,0 +1,7 @@ +read_verilog latches.v +synth_ecp5 +cd top +select -assert-count 4 t:LUT4 +select -assert-count 1 t:PFUMX +select -assert-none t:LUT4 t:PFUMX %% t:* %D +write_verilog latches_synth.v diff --git a/tests/ecp5/latches_tb.v b/tests/ecp5/latches_tb.v new file mode 100644 index 000000000..b0585264b --- /dev/null +++ b/tests/ecp5/latches_tb.v @@ -0,0 +1,57 @@ +module testbench; + reg clk; + + initial begin + // $dumpfile("testbench.vcd"); + // $dumpvars(0, testbench); + + #5 clk = 0; + repeat (10000) begin + #5 clk = 1; + #5 clk = 0; + end + end + + + reg [2:0] dinA = 0; + wire doutB,doutB1,doutB2; + reg lat,latn,latsr = 0; + + top uut ( + .clk (clk ), + .a (dinA[0] ), + .pre (dinA[1] ), + .clr (dinA[2] ), + .b (doutB ), + .b1 (doutB1 ), + .b2 (doutB2 ) + ); + + always @(posedge clk) begin + #3; + dinA <= dinA + 1; + end + + always @* + if ( clk ) + lat <= dinA[0]; + + + always @* + if ( !clk ) + latn <= dinA[0]; + + + always @* + if ( dinA[2] ) + latsr <= 1'b0; + else if ( dinA[1] ) + latsr <= 1'b1; + else if ( clk ) + latsr <= dinA[0]; + + assert_dff lat_test(.clk(clk), .test(doutB), .pat(lat)); + assert_dff latn_test(.clk(clk), .test(doutB1), .pat(latn)); + assert_dff latsr_test(.clk(clk), .test(doutB2), .pat(latsr)); + +endmodule diff --git a/tests/ecp5/macc.v b/tests/ecp5/macc.v new file mode 100644 index 000000000..115f8ce42 --- /dev/null +++ b/tests/ecp5/macc.v @@ -0,0 +1,22 @@ +module top(clk,a,b,c,set); +parameter A_WIDTH = 4; +parameter B_WIDTH = 3; +input set; +input clk; +input signed [(A_WIDTH - 1):0] a; +input signed [(B_WIDTH - 1):0] b; +output signed [(A_WIDTH + B_WIDTH - 1):0] c; +reg [(A_WIDTH + B_WIDTH - 1):0] reg_tmp_c; +assign c = reg_tmp_c; +always @(posedge clk) +begin +if(set) +begin +reg_tmp_c <= 0; +end +else +begin +reg_tmp_c <= a * b + c; +end +end +endmodule diff --git a/tests/ecp5/macc.ys b/tests/ecp5/macc.ys new file mode 100644 index 000000000..530877727 --- /dev/null +++ b/tests/ecp5/macc.ys @@ -0,0 +1,10 @@ +read_verilog macc.v +proc +hierarchy -top top +equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module +select -assert-count 41 t:LUT4 +select -assert-count 6 t:CARRY +select -assert-count 7 t:DFFSR +select -assert-none t:LUT4 t:CARRY t:DFFSR %% t:* %D diff --git a/tests/ecp5/memory.v b/tests/ecp5/memory.v new file mode 100644 index 000000000..cb7753f7b --- /dev/null +++ b/tests/ecp5/memory.v @@ -0,0 +1,21 @@ +module top +( + input [7:0] data_a, + input [6:1] addr_a, + input we_a, clk, + output reg [7:0] q_a +); + // Declare the RAM variable + reg [7:0] ram[63:0]; + + // Port A + always @ (posedge clk) + begin + if (we_a) + begin + ram[addr_a] <= data_a; + q_a <= data_a; + end + q_a <= ram[addr_a]; + end +endmodule diff --git a/tests/ecp5/memory.ys b/tests/ecp5/memory.ys new file mode 100644 index 000000000..9fdeb0d16 --- /dev/null +++ b/tests/ecp5/memory.ys @@ -0,0 +1,22 @@ +read_verilog memory.v +hierarchy -top top +proc +memory -nomap +equiv_opt -run :prove -map +/ecp5/cells_sim.v synth_ecp5 +memory +opt -full + +# TODO +#equiv_opt -run prove: -assert null +miter -equiv -flatten -make_assert -make_outputs gold gate miter +#sat -verify -prove-asserts -tempinduct -show-inputs -show-outputs miter + +design -load postopt +cd top +select -assert-count 24 t:L6MUX21 +select -assert-count 71 t:LUT4 +select -assert-count 32 t:PFUMX +select -assert-count 8 t:TRELLIS_DPR16X4 +select -assert-count 35 t:TRELLIS_FF +select -assert-none t:L6MUX21 t:LUT4 t:PFUMX t:TRELLIS_DPR16X4 t:TRELLIS_FF %% t:* %D +write_verilog memory_synth.v diff --git a/tests/ecp5/memory_tb.v b/tests/ecp5/memory_tb.v new file mode 100644 index 000000000..be69374eb --- /dev/null +++ b/tests/ecp5/memory_tb.v @@ -0,0 +1,79 @@ +module testbench; + reg clk; + + initial begin + // $dumpfile("testbench.vcd"); + // $dumpvars(0, testbench); + + #5 clk = 0; + repeat (10000) begin + #5 clk = 1; + #5 clk = 0; + end + end + + + reg [7:0] data_a = 0; + reg [5:0] addr_a = 0; + reg we_a = 0; + reg re_a = 1; + wire [7:0] q_a; + reg mem_init = 0; + + reg [7:0] pq_a; + + top uut ( + .data_a(data_a), + .addr_a(addr_a), + .we_a(we_a), + .clk(clk), + .q_a(q_a) + ); + + always @(posedge clk) begin + #3; + data_a <= data_a + 17; + + addr_a <= addr_a + 1; + end + + always @(posedge addr_a) begin + #10; + if(addr_a > 6'h3E) + mem_init <= 1; + end + + always @(posedge clk) begin + //#3; + we_a <= !we_a; + end + + // Declare the RAM variable for check + reg [7:0] ram[63:0]; + + // Port A for check + always @ (posedge clk) + begin + if (we_a) + begin + ram[addr_a] <= data_a; + pq_a <= data_a; + end + pq_a <= ram[addr_a]; + end + + uut_mem_checker port_a_test(.clk(clk), .init(mem_init), .en(!we_a), .A(q_a), .B(pq_a)); + +endmodule + +module uut_mem_checker(input clk, input init, input en, input [7:0] A, input [7:0] B); + always @(posedge clk) + begin + #1; + if (en == 1 & init == 1 & A !== B) + begin + $display("ERROR: ASSERTION FAILED in %m:",$time," ",A," ",B); + $stop; + end + end +endmodule diff --git a/tests/ecp5/mul.v b/tests/ecp5/mul.v new file mode 100644 index 000000000..d5b48b1d7 --- /dev/null +++ b/tests/ecp5/mul.v @@ -0,0 +1,11 @@ +module top +( + input [5:0] x, + input [5:0] y, + + output [11:0] A, + ); + +assign A = x * y; + +endmodule diff --git a/tests/ecp5/mul.ys b/tests/ecp5/mul.ys new file mode 100644 index 000000000..0e8d6908f --- /dev/null +++ b/tests/ecp5/mul.ys @@ -0,0 +1,11 @@ +read_verilog mul.v +hierarchy -top top +equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module +select -assert-count 6 t:CCU2C +select -assert-count 46 t:L6MUX21 +select -assert-count 169 t:LUT4 +select -assert-count 72 t:PFUMX + +select -assert-none t:CCU2C t:L6MUX21 t:LUT4 t:PFUMX %% t:* %D diff --git a/tests/ecp5/mux.v b/tests/ecp5/mux.v new file mode 100644 index 000000000..0814b733e --- /dev/null +++ b/tests/ecp5/mux.v @@ -0,0 +1,100 @@ +module mux2 (S,A,B,Y); + input S; + input A,B; + output reg Y; + + always @(*) + Y = (S)? B : A; +endmodule + +module mux4 ( S, D, Y ); + +input[1:0] S; +input[3:0] D; +output Y; + +reg Y; +wire[1:0] S; +wire[3:0] D; + +always @* +begin + case( S ) + 0 : Y = D[0]; + 1 : Y = D[1]; + 2 : Y = D[2]; + 3 : Y = D[3]; + endcase +end + +endmodule + +module mux8 ( S, D, Y ); + +input[2:0] S; +input[7:0] D; +output Y; + +reg Y; +wire[2:0] S; +wire[7:0] D; + +always @* +begin + case( S ) + 0 : Y = D[0]; + 1 : Y = D[1]; + 2 : Y = D[2]; + 3 : Y = D[3]; + 4 : Y = D[4]; + 5 : Y = D[5]; + 6 : Y = D[6]; + 7 : Y = D[7]; + endcase +end + +endmodule + +module mux16 (D, S, Y); + input [15:0] D; + input [3:0] S; + output Y; + +assign Y = D[S]; + +endmodule + + +module top ( +input [3:0] S, +input [15:0] D, +output M2,M4,M8,M16 +); + +mux2 u_mux2 ( + .S (S[0]), + .A (D[0]), + .B (D[1]), + .Y (M2) + ); + + +mux4 u_mux4 ( + .S (S[1:0]), + .D (D[3:0]), + .Y (M4) + ); + +mux8 u_mux8 ( + .S (S[2:0]), + .D (D[7:0]), + .Y (M8) + ); + +mux16 u_mux16 ( + .S (S[3:0]), + .D (D[15:0]), + .Y (M16) + ); + +endmodule diff --git a/tests/ecp5/mux.ys b/tests/ecp5/mux.ys new file mode 100644 index 000000000..47a965dd3 --- /dev/null +++ b/tests/ecp5/mux.ys @@ -0,0 +1,11 @@ +read_verilog mux.v +proc +flatten +equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module +select -assert-count 30 t:LUT4 +select -assert-count 7 t:L6MUX21 +select -assert-count 12 t:PFUMX + +select -assert-none t:LUT4 t:L6MUX21 t:PFUMX %% t:* %D diff --git a/tests/ecp5/rom.v b/tests/ecp5/rom.v new file mode 100644 index 000000000..c31ca3b2b --- /dev/null +++ b/tests/ecp5/rom.v @@ -0,0 +1,15 @@ +module top(data, addr); +output [3:0] data; +input [4:0] addr; +always @(addr) begin +case (addr) +0 : data = 'h4; +1 : data = 'h9; +2 : data = 'h1; +15 : data = 'h8; +16 : data = 'h1; +17 : data = 'h0; +default : data = 'h0; +endcase +end +endmodule diff --git a/tests/ecp5/rom.ys b/tests/ecp5/rom.ys new file mode 100644 index 000000000..8a52749a1 --- /dev/null +++ b/tests/ecp5/rom.ys @@ -0,0 +1,9 @@ +read_verilog rom.v +proc +flatten +equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module +select -assert-count 6 t:LUT4 +select -assert-count 3 t:PFUMX +select -assert-none t:LUT4 t:PFUMX %% t:* %D diff --git a/tests/ecp5/run-test.sh b/tests/ecp5/run-test.sh new file mode 100755 index 000000000..22c495784 --- /dev/null +++ b/tests/ecp5/run-test.sh @@ -0,0 +1,33 @@ +set -e +if [ -f "../../techlibs/common/simcells.v" ]; then + COMMON_PREFIX=../../techlibs/common + TECHLIBS_PREFIX=../../techlibs +else + COMMON_PREFIX=/usr/local/share/yosys + TECHLIBS_PREFIX=/usr/local/share/yosys +fi +{ +echo "all::" +for x in *.ys; do + echo "all:: run-$x" + echo "run-$x:" + echo " @echo 'Running $x..'" + echo " @../../yosys -ql ${x%.ys}.log $x -w 'Yosys has only limited support for tri-state logic at the moment.'" +done +for t in *_tb.v; do + echo "all:: run-$t" + echo "run-$t: ${t%_tb.v}_synth.v" + echo " @echo 'Running $t..'" + echo " @iverilog -o ${t%_tb.v}_testbench $t ${t%_tb.v}_synth.v common.v $TECHLIBS_PREFIX/ecp5/cells_sim.v" + echo " @vvp -N ${t%_tb.v}_testbench" +done +for s in *.sh; do + if [ "$s" != "run-test.sh" ]; then + echo "all:: run-$s" + echo "run-$s:" + echo " @echo 'Running $s..'" + echo " @bash $s" + fi +done +} > run-test.mk +exec ${MAKE:-make} -f run-test.mk diff --git a/tests/ecp5/tribuf.v b/tests/ecp5/tribuf.v new file mode 100644 index 000000000..870a02584 --- /dev/null +++ b/tests/ecp5/tribuf.v @@ -0,0 +1,23 @@ +module tristate (en, i, o); + input en; + input i; + output o; + + assign o = en ? i : 1'bz; + +endmodule + + +module top ( +input en, +input a, +output b +); + +tristate u_tri ( + .en (en ), + .i (a ), + .o (b ) + ); + +endmodule diff --git a/tests/ecp5/tribuf.ys b/tests/ecp5/tribuf.ys new file mode 100644 index 000000000..f454a0c02 --- /dev/null +++ b/tests/ecp5/tribuf.ys @@ -0,0 +1,9 @@ +read_verilog tribuf.v +hierarchy -top top +proc +flatten +equiv_opt -assert -map +/ecp5/cells_sim.v -map +/simcells.v synth_ecp5 # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module +select -assert-count 1 t:$_TBUF_ +select -assert-none t:$_TBUF_ %% t:* %D -- cgit v1.2.3 From fe58790f3789a79b867660031d7e3e28cb3fff20 Mon Sep 17 00:00:00 2001 From: SergeyDegtyar Date: Wed, 28 Aug 2019 09:49:58 +0300 Subject: Revert "Add tests for ecp5" This reverts commit 2270ead09fb4695442c66fe5c06445235f390f2b. --- tests/ecp5/.gitignore | 2 - tests/ecp5/add_sub.v | 13 ------- tests/ecp5/add_sub.ys | 8 ---- tests/ecp5/adffs.v | 91 ------------------------------------------- tests/ecp5/adffs.ys | 12 ------ tests/ecp5/common.v | 47 ----------------------- tests/ecp5/dffs.v | 37 ------------------ tests/ecp5/dffs.ys | 10 ----- tests/ecp5/div_mod.v | 13 ------- tests/ecp5/div_mod.ys | 12 ------ tests/ecp5/dpram.v | 20 ---------- tests/ecp5/dpram.ys | 18 --------- tests/ecp5/dpram_tb.v | 81 --------------------------------------- tests/ecp5/latches.v | 58 ---------------------------- tests/ecp5/latches.ys | 7 ---- tests/ecp5/latches_tb.v | 57 --------------------------- tests/ecp5/macc.v | 22 ----------- tests/ecp5/macc.ys | 10 ----- tests/ecp5/memory.v | 21 ---------- tests/ecp5/memory.ys | 22 ----------- tests/ecp5/memory_tb.v | 79 -------------------------------------- tests/ecp5/mul.v | 11 ------ tests/ecp5/mul.ys | 11 ------ tests/ecp5/mux.v | 100 ------------------------------------------------ tests/ecp5/mux.ys | 11 ------ tests/ecp5/rom.v | 15 -------- tests/ecp5/rom.ys | 9 ----- tests/ecp5/run-test.sh | 33 ---------------- tests/ecp5/tribuf.v | 23 ----------- tests/ecp5/tribuf.ys | 9 ----- 30 files changed, 862 deletions(-) delete mode 100644 tests/ecp5/.gitignore delete mode 100644 tests/ecp5/add_sub.v delete mode 100644 tests/ecp5/add_sub.ys delete mode 100644 tests/ecp5/adffs.v delete mode 100644 tests/ecp5/adffs.ys delete mode 100644 tests/ecp5/common.v delete mode 100644 tests/ecp5/dffs.v delete mode 100644 tests/ecp5/dffs.ys delete mode 100644 tests/ecp5/div_mod.v delete mode 100644 tests/ecp5/div_mod.ys delete mode 100644 tests/ecp5/dpram.v delete mode 100644 tests/ecp5/dpram.ys delete mode 100644 tests/ecp5/dpram_tb.v delete mode 100644 tests/ecp5/latches.v delete mode 100644 tests/ecp5/latches.ys delete mode 100644 tests/ecp5/latches_tb.v delete mode 100644 tests/ecp5/macc.v delete mode 100644 tests/ecp5/macc.ys delete mode 100644 tests/ecp5/memory.v delete mode 100644 tests/ecp5/memory.ys delete mode 100644 tests/ecp5/memory_tb.v delete mode 100644 tests/ecp5/mul.v delete mode 100644 tests/ecp5/mul.ys delete mode 100644 tests/ecp5/mux.v delete mode 100644 tests/ecp5/mux.ys delete mode 100644 tests/ecp5/rom.v delete mode 100644 tests/ecp5/rom.ys delete mode 100755 tests/ecp5/run-test.sh delete mode 100644 tests/ecp5/tribuf.v delete mode 100644 tests/ecp5/tribuf.ys (limited to 'tests') diff --git a/tests/ecp5/.gitignore b/tests/ecp5/.gitignore deleted file mode 100644 index 1d329c933..000000000 --- a/tests/ecp5/.gitignore +++ /dev/null @@ -1,2 +0,0 @@ -*.log -/run-test.mk diff --git a/tests/ecp5/add_sub.v b/tests/ecp5/add_sub.v deleted file mode 100644 index 177c32e30..000000000 --- a/tests/ecp5/add_sub.v +++ /dev/null @@ -1,13 +0,0 @@ -module top -( - input [3:0] x, - input [3:0] y, - - output [3:0] A, - output [3:0] B - ); - -assign A = x + y; -assign B = x - y; - -endmodule diff --git a/tests/ecp5/add_sub.ys b/tests/ecp5/add_sub.ys deleted file mode 100644 index 03aec6694..000000000 --- a/tests/ecp5/add_sub.ys +++ /dev/null @@ -1,8 +0,0 @@ -read_verilog add_sub.v -hierarchy -top top -equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check -design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) -cd top # Constrain all select calls below inside the top module -select -assert-count 10 t:LUT4 -select -assert-none t:LUT4 %% t:* %D - diff --git a/tests/ecp5/adffs.v b/tests/ecp5/adffs.v deleted file mode 100644 index 93c8bf52c..000000000 --- a/tests/ecp5/adffs.v +++ /dev/null @@ -1,91 +0,0 @@ -module adff - ( input d, clk, clr, output reg q ); - initial begin - q = 0; - end - always @( posedge clk, posedge clr ) - if ( clr ) - q <= 1'b0; - else - q <= d; -endmodule - -module adffn - ( input d, clk, clr, output reg q ); - initial begin - q = 0; - end - always @( posedge clk, negedge clr ) - if ( !clr ) - q <= 1'b0; - else - q <= d; -endmodule - -module dffsr - ( input d, clk, pre, clr, output reg q ); - initial begin - q = 0; - end - always @( posedge clk, posedge pre, posedge clr ) - if ( clr ) - q <= 1'b0; - else if ( pre ) - q <= 1'b1; - else - q <= d; -endmodule - -module ndffnsnr - ( input d, clk, pre, clr, output reg q ); - initial begin - q = 0; - end - always @( negedge clk, negedge pre, negedge clr ) - if ( !clr ) - q <= 1'b0; - else if ( !pre ) - q <= 1'b1; - else - q <= d; -endmodule - -module top ( -input clk, -input clr, -input pre, -input a, -output b,b1,b2,b3 -); - -dffsr u_dffsr ( - .clk (clk ), - .clr (clr), - .pre (pre), - .d (a ), - .q (b ) - ); - -ndffnsnr u_ndffnsnr ( - .clk (clk ), - .clr (clr), - .pre (pre), - .d (a ), - .q (b1 ) - ); - -adff u_adff ( - .clk (clk ), - .clr (clr), - .d (a ), - .q (b2 ) - ); - -adffn u_adffn ( - .clk (clk ), - .clr (clr), - .d (a ), - .q (b3 ) - ); - -endmodule diff --git a/tests/ecp5/adffs.ys b/tests/ecp5/adffs.ys deleted file mode 100644 index 5829fef5f..000000000 --- a/tests/ecp5/adffs.ys +++ /dev/null @@ -1,12 +0,0 @@ -read_verilog adffs.v -proc -async2sync # converts async flops to a 'sync' variant clocked by a 'super'-clock -flatten -equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check -design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) -cd top # Constrain all select calls below inside the top module -select -assert-count 1 t:DFF -select -assert-count 1 t:DFFN -select -assert-count 2 t:DFFSR -select -assert-count 7 t:LUT4 -select -assert-none t:DFF t:DFFN t:DFFSR t:LUT4 %% t:* %D diff --git a/tests/ecp5/common.v b/tests/ecp5/common.v deleted file mode 100644 index 5446f0817..000000000 --- a/tests/ecp5/common.v +++ /dev/null @@ -1,47 +0,0 @@ -module assert_dff(input clk, input test, input pat); - always @(posedge clk) - begin - #1; - if (test != pat) - begin - $display("ERROR: ASSERTION FAILED in %m:",$time); - $stop; - end - end -endmodule - -module assert_tri(input en, input A, input B); - always @(posedge en) - begin - #1; - if (A !== B) - begin - $display("ERROR: ASSERTION FAILED in %m:",$time," ",A," ",B); - $stop; - end - end -endmodule - -module assert_Z(input clk, input A); - always @(posedge clk) - begin - #1; - if (A === 1'bZ) - begin - $display("ERROR: ASSERTION FAILED in %m:",$time," ",A); - $stop; - end - end -endmodule - -module assert_comb(input A, input B); - always @(*) - begin - #1; - if (A !== B) - begin - $display("ERROR: ASSERTION FAILED in %m:",$time," ",A," ",B); - $stop; - end - end -endmodule diff --git a/tests/ecp5/dffs.v b/tests/ecp5/dffs.v deleted file mode 100644 index d97840c43..000000000 --- a/tests/ecp5/dffs.v +++ /dev/null @@ -1,37 +0,0 @@ -module dff - ( input d, clk, output reg q ); - always @( posedge clk ) - q <= d; -endmodule - -module dffe - ( input d, clk, en, output reg q ); - initial begin - q = 0; - end - always @( posedge clk ) - if ( en ) - q <= d; -endmodule - -module top ( -input clk, -input en, -input a, -output b,b1, -); - -dff u_dff ( - .clk (clk ), - .d (a ), - .q (b ) - ); - -dffe u_ndffe ( - .clk (clk ), - .en (en), - .d (a ), - .q (b1 ) - ); - -endmodule diff --git a/tests/ecp5/dffs.ys b/tests/ecp5/dffs.ys deleted file mode 100644 index 07470c5ba..000000000 --- a/tests/ecp5/dffs.ys +++ /dev/null @@ -1,10 +0,0 @@ -read_verilog dffs.v -hierarchy -top top -proc -flatten -equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check -design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) -cd top # Constrain all select calls below inside the top module -select -assert-count 1 t:DFF -select -assert-count 1 t:DFFE -select -assert-none t:DFF t:DFFE %% t:* %D diff --git a/tests/ecp5/div_mod.v b/tests/ecp5/div_mod.v deleted file mode 100644 index 64a36707d..000000000 --- a/tests/ecp5/div_mod.v +++ /dev/null @@ -1,13 +0,0 @@ -module top -( - input [3:0] x, - input [3:0] y, - - output [3:0] A, - output [3:0] B - ); - -assign A = x % y; -assign B = x / y; - -endmodule diff --git a/tests/ecp5/div_mod.ys b/tests/ecp5/div_mod.ys deleted file mode 100644 index 169c5978e..000000000 --- a/tests/ecp5/div_mod.ys +++ /dev/null @@ -1,12 +0,0 @@ -read_verilog div_mod.v -hierarchy -top top -flatten -equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check -design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) -cd top # Constrain all select calls below inside the top module - -select -assert-count 28 t:CCU2C -select -assert-count 45 t:L6MUX21 -select -assert-count 183 t:LUT4 -select -assert-count 79 t:PFUMX -select -assert-none t:LUT4 t:CCU2C t:L6MUX21 t:PFUMX %% t:* %D diff --git a/tests/ecp5/dpram.v b/tests/ecp5/dpram.v deleted file mode 100644 index 2e69d6b3b..000000000 --- a/tests/ecp5/dpram.v +++ /dev/null @@ -1,20 +0,0 @@ -module top (din, write_en, waddr, wclk, raddr, rclk, dout); -parameter addr_width = 8; -parameter data_width = 8; -input [addr_width-1:0] waddr, raddr; -input [data_width-1:0] din; -input write_en, wclk, rclk; -output [data_width-1:0] dout; -reg [data_width-1:0] dout; -reg [data_width-1:0] mem [(1< 6'h3E) - mem_init <= 1; - end - - always @(posedge clk) begin - //#3; - we_a <= !we_a; - end - - reg [7:0] mem [(1<<8)-1:0]; - - always @(posedge clk) // Write memory. - begin - if (we_a) - mem[addr_a] <= data_a; // Using write address bus. - end - always @(posedge clk) // Read memory. - begin - pq_a <= mem[addr_b]; // Using read address bus. - end - - top uut ( - .din(data_a), - .write_en(we_a), - .waddr(addr_a), - .wclk(clk), - .raddr(addr_b), - .rclk(clk), - .dout(q_a) - ); - - uut_mem_checker port_a_test(.clk(clk), .init(mem_init), .en(!we_a), .A(q_a), .B(pq_a)); - -endmodule - -module uut_mem_checker(input clk, input init, input en, input [7:0] A, input [7:0] B); - always @(posedge clk) - begin - #1; - if (en == 1 & init == 1 & A !== B) - begin - $display("ERROR: ASSERTION FAILED in %m:",$time," ",A," ",B); - $stop; - end - end -endmodule diff --git a/tests/ecp5/latches.v b/tests/ecp5/latches.v deleted file mode 100644 index 9dc43e4c2..000000000 --- a/tests/ecp5/latches.v +++ /dev/null @@ -1,58 +0,0 @@ -module latchp - ( input d, clk, en, output reg q ); - always @* - if ( en ) - q <= d; -endmodule - -module latchn - ( input d, clk, en, output reg q ); - always @* - if ( !en ) - q <= d; -endmodule - -module latchsr - ( input d, clk, en, clr, pre, output reg q ); - always @* - if ( clr ) - q <= 1'b0; - else if ( pre ) - q <= 1'b1; - else if ( en ) - q <= d; -endmodule - - -module top ( -input clk, -input clr, -input pre, -input a, -output b,b1,b2 -); - - -latchp u_latchp ( - .en (clk ), - .d (a ), - .q (b ) - ); - - -latchn u_latchn ( - .en (clk ), - .d (a ), - .q (b1 ) - ); - - -latchsr u_latchsr ( - .en (clk ), - .clr (clr), - .pre (pre), - .d (a ), - .q (b2 ) - ); - -endmodule diff --git a/tests/ecp5/latches.ys b/tests/ecp5/latches.ys deleted file mode 100644 index 2c77304a1..000000000 --- a/tests/ecp5/latches.ys +++ /dev/null @@ -1,7 +0,0 @@ -read_verilog latches.v -synth_ecp5 -cd top -select -assert-count 4 t:LUT4 -select -assert-count 1 t:PFUMX -select -assert-none t:LUT4 t:PFUMX %% t:* %D -write_verilog latches_synth.v diff --git a/tests/ecp5/latches_tb.v b/tests/ecp5/latches_tb.v deleted file mode 100644 index b0585264b..000000000 --- a/tests/ecp5/latches_tb.v +++ /dev/null @@ -1,57 +0,0 @@ -module testbench; - reg clk; - - initial begin - // $dumpfile("testbench.vcd"); - // $dumpvars(0, testbench); - - #5 clk = 0; - repeat (10000) begin - #5 clk = 1; - #5 clk = 0; - end - end - - - reg [2:0] dinA = 0; - wire doutB,doutB1,doutB2; - reg lat,latn,latsr = 0; - - top uut ( - .clk (clk ), - .a (dinA[0] ), - .pre (dinA[1] ), - .clr (dinA[2] ), - .b (doutB ), - .b1 (doutB1 ), - .b2 (doutB2 ) - ); - - always @(posedge clk) begin - #3; - dinA <= dinA + 1; - end - - always @* - if ( clk ) - lat <= dinA[0]; - - - always @* - if ( !clk ) - latn <= dinA[0]; - - - always @* - if ( dinA[2] ) - latsr <= 1'b0; - else if ( dinA[1] ) - latsr <= 1'b1; - else if ( clk ) - latsr <= dinA[0]; - - assert_dff lat_test(.clk(clk), .test(doutB), .pat(lat)); - assert_dff latn_test(.clk(clk), .test(doutB1), .pat(latn)); - assert_dff latsr_test(.clk(clk), .test(doutB2), .pat(latsr)); - -endmodule diff --git a/tests/ecp5/macc.v b/tests/ecp5/macc.v deleted file mode 100644 index 115f8ce42..000000000 --- a/tests/ecp5/macc.v +++ /dev/null @@ -1,22 +0,0 @@ -module top(clk,a,b,c,set); -parameter A_WIDTH = 4; -parameter B_WIDTH = 3; -input set; -input clk; -input signed [(A_WIDTH - 1):0] a; -input signed [(B_WIDTH - 1):0] b; -output signed [(A_WIDTH + B_WIDTH - 1):0] c; -reg [(A_WIDTH + B_WIDTH - 1):0] reg_tmp_c; -assign c = reg_tmp_c; -always @(posedge clk) -begin -if(set) -begin -reg_tmp_c <= 0; -end -else -begin -reg_tmp_c <= a * b + c; -end -end -endmodule diff --git a/tests/ecp5/macc.ys b/tests/ecp5/macc.ys deleted file mode 100644 index 530877727..000000000 --- a/tests/ecp5/macc.ys +++ /dev/null @@ -1,10 +0,0 @@ -read_verilog macc.v -proc -hierarchy -top top -equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check -design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) -cd top # Constrain all select calls below inside the top module -select -assert-count 41 t:LUT4 -select -assert-count 6 t:CARRY -select -assert-count 7 t:DFFSR -select -assert-none t:LUT4 t:CARRY t:DFFSR %% t:* %D diff --git a/tests/ecp5/memory.v b/tests/ecp5/memory.v deleted file mode 100644 index cb7753f7b..000000000 --- a/tests/ecp5/memory.v +++ /dev/null @@ -1,21 +0,0 @@ -module top -( - input [7:0] data_a, - input [6:1] addr_a, - input we_a, clk, - output reg [7:0] q_a -); - // Declare the RAM variable - reg [7:0] ram[63:0]; - - // Port A - always @ (posedge clk) - begin - if (we_a) - begin - ram[addr_a] <= data_a; - q_a <= data_a; - end - q_a <= ram[addr_a]; - end -endmodule diff --git a/tests/ecp5/memory.ys b/tests/ecp5/memory.ys deleted file mode 100644 index 9fdeb0d16..000000000 --- a/tests/ecp5/memory.ys +++ /dev/null @@ -1,22 +0,0 @@ -read_verilog memory.v -hierarchy -top top -proc -memory -nomap -equiv_opt -run :prove -map +/ecp5/cells_sim.v synth_ecp5 -memory -opt -full - -# TODO -#equiv_opt -run prove: -assert null -miter -equiv -flatten -make_assert -make_outputs gold gate miter -#sat -verify -prove-asserts -tempinduct -show-inputs -show-outputs miter - -design -load postopt -cd top -select -assert-count 24 t:L6MUX21 -select -assert-count 71 t:LUT4 -select -assert-count 32 t:PFUMX -select -assert-count 8 t:TRELLIS_DPR16X4 -select -assert-count 35 t:TRELLIS_FF -select -assert-none t:L6MUX21 t:LUT4 t:PFUMX t:TRELLIS_DPR16X4 t:TRELLIS_FF %% t:* %D -write_verilog memory_synth.v diff --git a/tests/ecp5/memory_tb.v b/tests/ecp5/memory_tb.v deleted file mode 100644 index be69374eb..000000000 --- a/tests/ecp5/memory_tb.v +++ /dev/null @@ -1,79 +0,0 @@ -module testbench; - reg clk; - - initial begin - // $dumpfile("testbench.vcd"); - // $dumpvars(0, testbench); - - #5 clk = 0; - repeat (10000) begin - #5 clk = 1; - #5 clk = 0; - end - end - - - reg [7:0] data_a = 0; - reg [5:0] addr_a = 0; - reg we_a = 0; - reg re_a = 1; - wire [7:0] q_a; - reg mem_init = 0; - - reg [7:0] pq_a; - - top uut ( - .data_a(data_a), - .addr_a(addr_a), - .we_a(we_a), - .clk(clk), - .q_a(q_a) - ); - - always @(posedge clk) begin - #3; - data_a <= data_a + 17; - - addr_a <= addr_a + 1; - end - - always @(posedge addr_a) begin - #10; - if(addr_a > 6'h3E) - mem_init <= 1; - end - - always @(posedge clk) begin - //#3; - we_a <= !we_a; - end - - // Declare the RAM variable for check - reg [7:0] ram[63:0]; - - // Port A for check - always @ (posedge clk) - begin - if (we_a) - begin - ram[addr_a] <= data_a; - pq_a <= data_a; - end - pq_a <= ram[addr_a]; - end - - uut_mem_checker port_a_test(.clk(clk), .init(mem_init), .en(!we_a), .A(q_a), .B(pq_a)); - -endmodule - -module uut_mem_checker(input clk, input init, input en, input [7:0] A, input [7:0] B); - always @(posedge clk) - begin - #1; - if (en == 1 & init == 1 & A !== B) - begin - $display("ERROR: ASSERTION FAILED in %m:",$time," ",A," ",B); - $stop; - end - end -endmodule diff --git a/tests/ecp5/mul.v b/tests/ecp5/mul.v deleted file mode 100644 index d5b48b1d7..000000000 --- a/tests/ecp5/mul.v +++ /dev/null @@ -1,11 +0,0 @@ -module top -( - input [5:0] x, - input [5:0] y, - - output [11:0] A, - ); - -assign A = x * y; - -endmodule diff --git a/tests/ecp5/mul.ys b/tests/ecp5/mul.ys deleted file mode 100644 index 0e8d6908f..000000000 --- a/tests/ecp5/mul.ys +++ /dev/null @@ -1,11 +0,0 @@ -read_verilog mul.v -hierarchy -top top -equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check -design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) -cd top # Constrain all select calls below inside the top module -select -assert-count 6 t:CCU2C -select -assert-count 46 t:L6MUX21 -select -assert-count 169 t:LUT4 -select -assert-count 72 t:PFUMX - -select -assert-none t:CCU2C t:L6MUX21 t:LUT4 t:PFUMX %% t:* %D diff --git a/tests/ecp5/mux.v b/tests/ecp5/mux.v deleted file mode 100644 index 0814b733e..000000000 --- a/tests/ecp5/mux.v +++ /dev/null @@ -1,100 +0,0 @@ -module mux2 (S,A,B,Y); - input S; - input A,B; - output reg Y; - - always @(*) - Y = (S)? B : A; -endmodule - -module mux4 ( S, D, Y ); - -input[1:0] S; -input[3:0] D; -output Y; - -reg Y; -wire[1:0] S; -wire[3:0] D; - -always @* -begin - case( S ) - 0 : Y = D[0]; - 1 : Y = D[1]; - 2 : Y = D[2]; - 3 : Y = D[3]; - endcase -end - -endmodule - -module mux8 ( S, D, Y ); - -input[2:0] S; -input[7:0] D; -output Y; - -reg Y; -wire[2:0] S; -wire[7:0] D; - -always @* -begin - case( S ) - 0 : Y = D[0]; - 1 : Y = D[1]; - 2 : Y = D[2]; - 3 : Y = D[3]; - 4 : Y = D[4]; - 5 : Y = D[5]; - 6 : Y = D[6]; - 7 : Y = D[7]; - endcase -end - -endmodule - -module mux16 (D, S, Y); - input [15:0] D; - input [3:0] S; - output Y; - -assign Y = D[S]; - -endmodule - - -module top ( -input [3:0] S, -input [15:0] D, -output M2,M4,M8,M16 -); - -mux2 u_mux2 ( - .S (S[0]), - .A (D[0]), - .B (D[1]), - .Y (M2) - ); - - -mux4 u_mux4 ( - .S (S[1:0]), - .D (D[3:0]), - .Y (M4) - ); - -mux8 u_mux8 ( - .S (S[2:0]), - .D (D[7:0]), - .Y (M8) - ); - -mux16 u_mux16 ( - .S (S[3:0]), - .D (D[15:0]), - .Y (M16) - ); - -endmodule diff --git a/tests/ecp5/mux.ys b/tests/ecp5/mux.ys deleted file mode 100644 index 47a965dd3..000000000 --- a/tests/ecp5/mux.ys +++ /dev/null @@ -1,11 +0,0 @@ -read_verilog mux.v -proc -flatten -equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check -design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) -cd top # Constrain all select calls below inside the top module -select -assert-count 30 t:LUT4 -select -assert-count 7 t:L6MUX21 -select -assert-count 12 t:PFUMX - -select -assert-none t:LUT4 t:L6MUX21 t:PFUMX %% t:* %D diff --git a/tests/ecp5/rom.v b/tests/ecp5/rom.v deleted file mode 100644 index c31ca3b2b..000000000 --- a/tests/ecp5/rom.v +++ /dev/null @@ -1,15 +0,0 @@ -module top(data, addr); -output [3:0] data; -input [4:0] addr; -always @(addr) begin -case (addr) -0 : data = 'h4; -1 : data = 'h9; -2 : data = 'h1; -15 : data = 'h8; -16 : data = 'h1; -17 : data = 'h0; -default : data = 'h0; -endcase -end -endmodule diff --git a/tests/ecp5/rom.ys b/tests/ecp5/rom.ys deleted file mode 100644 index 8a52749a1..000000000 --- a/tests/ecp5/rom.ys +++ /dev/null @@ -1,9 +0,0 @@ -read_verilog rom.v -proc -flatten -equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check -design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) -cd top # Constrain all select calls below inside the top module -select -assert-count 6 t:LUT4 -select -assert-count 3 t:PFUMX -select -assert-none t:LUT4 t:PFUMX %% t:* %D diff --git a/tests/ecp5/run-test.sh b/tests/ecp5/run-test.sh deleted file mode 100755 index 22c495784..000000000 --- a/tests/ecp5/run-test.sh +++ /dev/null @@ -1,33 +0,0 @@ -set -e -if [ -f "../../techlibs/common/simcells.v" ]; then - COMMON_PREFIX=../../techlibs/common - TECHLIBS_PREFIX=../../techlibs -else - COMMON_PREFIX=/usr/local/share/yosys - TECHLIBS_PREFIX=/usr/local/share/yosys -fi -{ -echo "all::" -for x in *.ys; do - echo "all:: run-$x" - echo "run-$x:" - echo " @echo 'Running $x..'" - echo " @../../yosys -ql ${x%.ys}.log $x -w 'Yosys has only limited support for tri-state logic at the moment.'" -done -for t in *_tb.v; do - echo "all:: run-$t" - echo "run-$t: ${t%_tb.v}_synth.v" - echo " @echo 'Running $t..'" - echo " @iverilog -o ${t%_tb.v}_testbench $t ${t%_tb.v}_synth.v common.v $TECHLIBS_PREFIX/ecp5/cells_sim.v" - echo " @vvp -N ${t%_tb.v}_testbench" -done -for s in *.sh; do - if [ "$s" != "run-test.sh" ]; then - echo "all:: run-$s" - echo "run-$s:" - echo " @echo 'Running $s..'" - echo " @bash $s" - fi -done -} > run-test.mk -exec ${MAKE:-make} -f run-test.mk diff --git a/tests/ecp5/tribuf.v b/tests/ecp5/tribuf.v deleted file mode 100644 index 870a02584..000000000 --- a/tests/ecp5/tribuf.v +++ /dev/null @@ -1,23 +0,0 @@ -module tristate (en, i, o); - input en; - input i; - output o; - - assign o = en ? i : 1'bz; - -endmodule - - -module top ( -input en, -input a, -output b -); - -tristate u_tri ( - .en (en ), - .i (a ), - .o (b ) - ); - -endmodule diff --git a/tests/ecp5/tribuf.ys b/tests/ecp5/tribuf.ys deleted file mode 100644 index f454a0c02..000000000 --- a/tests/ecp5/tribuf.ys +++ /dev/null @@ -1,9 +0,0 @@ -read_verilog tribuf.v -hierarchy -top top -proc -flatten -equiv_opt -assert -map +/ecp5/cells_sim.v -map +/simcells.v synth_ecp5 # equivalency check -design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) -cd top # Constrain all select calls below inside the top module -select -assert-count 1 t:$_TBUF_ -select -assert-none t:$_TBUF_ %% t:* %D -- cgit v1.2.3 From 975aaf190f0bbbeacc253397ccada6889c69e8f7 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Wed, 28 Aug 2019 09:24:19 -0700 Subject: Add xilinx_srl test --- tests/xilinx/run-test.sh | 20 ++++++++++++++ tests/xilinx/xilinx_srl.v | 40 +++++++++++++++++++++++++++ tests/xilinx/xilinx_srl.ys | 67 ++++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 127 insertions(+) create mode 100755 tests/xilinx/run-test.sh create mode 100644 tests/xilinx/xilinx_srl.v create mode 100644 tests/xilinx/xilinx_srl.ys (limited to 'tests') diff --git a/tests/xilinx/run-test.sh b/tests/xilinx/run-test.sh new file mode 100755 index 000000000..ea56b70f0 --- /dev/null +++ b/tests/xilinx/run-test.sh @@ -0,0 +1,20 @@ +#!/usr/bin/env bash +set -e +{ +echo "all::" +for x in *.ys; do + echo "all:: run-$x" + echo "run-$x:" + echo " @echo 'Running $x..'" + echo " @../../yosys -ql ${x%.ys}.log $x" +done +for s in *.sh; do + if [ "$s" != "run-test.sh" ]; then + echo "all:: run-$s" + echo "run-$s:" + echo " @echo 'Running $s..'" + echo " @bash $s" + fi +done +} > run-test.mk +exec ${MAKE:-make} -f run-test.mk diff --git a/tests/xilinx/xilinx_srl.v b/tests/xilinx/xilinx_srl.v new file mode 100644 index 000000000..bc2a15ab2 --- /dev/null +++ b/tests/xilinx/xilinx_srl.v @@ -0,0 +1,40 @@ +module xilinx_srl_static_test(input i, clk, output [1:0] q); +reg head = 1'b0; +reg [3:0] shift1 = 4'b0000; +reg [3:0] shift2 = 4'b0000; + +always @(posedge clk) begin + head <= i; + shift1 <= {shift1[2:0], head}; + shift2 <= {shift2[2:0], head}; +end + +assign q = {shift2[3], shift1[3]}; +endmodule + +module xilinx_srl_variable_test(input i, clk, input [1:0] l1, l2, output [1:0] q); +reg head = 1'b0; +reg [3:0] shift1 = 4'b0000; +reg [3:0] shift2 = 4'b0000; + +always @(posedge clk) begin + head <= i; + shift1 <= {shift1[2:0], head}; + shift2 <= {shift2[2:0], head}; +end + +assign q = {shift2[l2], shift1[l1]}; +endmodule + +module $__XILINX_SHREG_(input C, D, E, input [1:0] L, output Q); +parameter CLKPOL = 1; +parameter ENPOL = 1; +parameter DEPTH = 1; +parameter [DEPTH-1:0] INIT = {DEPTH{1'b0}}; +reg [DEPTH-1:0] r = INIT; +wire clk = C ^ CLKPOL; +always @(posedge C) + if (E) + r <= { r[DEPTH-2:0], D }; +assign Q = r[L]; +endmodule diff --git a/tests/xilinx/xilinx_srl.ys b/tests/xilinx/xilinx_srl.ys new file mode 100644 index 000000000..4e3c44a98 --- /dev/null +++ b/tests/xilinx/xilinx_srl.ys @@ -0,0 +1,67 @@ +read_verilog xilinx_srl.v +design -save read + +design -copy-to model $__XILINX_SHREG_ +hierarchy -top xilinx_srl_static_test +prep +design -save gold + +techmap +xilinx_srl -fixed +opt + +# stat +# show -width +select -assert-count 1 t:$_DFF_P_ +select -assert-count 2 t:$__XILINX_SHREG_ + +design -stash gate + +design -import gold -as gold +design -import gate -as gate +design -copy-from model -as $__XILINX_SHREG_ \$__XILINX_SHREG_ +prep + +miter -equiv -flatten -make_assert -make_outputs gold gate miter +dump gate +sat -verify -prove-asserts -show-ports -seq 5 miter + +#design -load gold +#stat + +#design -load gate +#stat + +########## + +design -load read +design -copy-to model $__XILINX_SHREG_ +hierarchy -top xilinx_srl_variable_test +prep +design -save gold + +simplemap t:$dff t:$dffe +xilinx_srl -variable +opt + +#stat +# show -width +# write_verilog -noexpr -norename +select -assert-count 1 t:$_DFF_P_ +select -assert-count 2 t:$__XILINX_SHREG_ + +design -stash gate + +design -import gold -as gold +design -import gate -as gate +design -copy-from model -as $__XILINX_SHREG_ \$__XILINX_SHREG_ +prep + +miter -equiv -flatten -make_assert -make_outputs gold gate miter +sat -verify -prove-asserts -show-ports -seq 5 miter + +# design -load gold +# stat + +# design -load gate +# stat -- cgit v1.2.3 From 2e9e745efa03363f9f0d5cc47696401d55a8e5d2 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Wed, 28 Aug 2019 09:26:08 -0700 Subject: Do not simplemap for variable test --- tests/xilinx/xilinx_srl.ys | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'tests') diff --git a/tests/xilinx/xilinx_srl.ys b/tests/xilinx/xilinx_srl.ys index 4e3c44a98..b8df0e55a 100644 --- a/tests/xilinx/xilinx_srl.ys +++ b/tests/xilinx/xilinx_srl.ys @@ -40,14 +40,14 @@ hierarchy -top xilinx_srl_variable_test prep design -save gold -simplemap t:$dff t:$dffe xilinx_srl -variable opt #stat # show -width # write_verilog -noexpr -norename -select -assert-count 1 t:$_DFF_P_ +select -assert-count 1 t:$dff +select -assert-count 1 t:$dff r:WIDTH=1 %i select -assert-count 2 t:$__XILINX_SHREG_ design -stash gate -- cgit v1.2.3 From 2f493fb465d398a6fb4f24ffcd4af50d7e158fa9 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Wed, 28 Aug 2019 09:55:09 -0700 Subject: Use test_pmgen for xilinx_srl --- tests/xilinx/pmgen_xilinx_srl.ys | 57 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 57 insertions(+) create mode 100644 tests/xilinx/pmgen_xilinx_srl.ys (limited to 'tests') diff --git a/tests/xilinx/pmgen_xilinx_srl.ys b/tests/xilinx/pmgen_xilinx_srl.ys new file mode 100644 index 000000000..ea2f20487 --- /dev/null +++ b/tests/xilinx/pmgen_xilinx_srl.ys @@ -0,0 +1,57 @@ +read_verilog -icells < Date: Wed, 28 Aug 2019 09:55:34 -0700 Subject: Add .gitignore --- tests/xilinx/.gitignore | 3 +++ 1 file changed, 3 insertions(+) create mode 100644 tests/xilinx/.gitignore (limited to 'tests') diff --git a/tests/xilinx/.gitignore b/tests/xilinx/.gitignore new file mode 100644 index 000000000..b48f808a1 --- /dev/null +++ b/tests/xilinx/.gitignore @@ -0,0 +1,3 @@ +/*.log +/*.out +/run-test.mk -- cgit v1.2.3 From ebd0a1875b74460da10d9b114e97c1468d8542db Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Wed, 28 Aug 2019 12:21:15 -0700 Subject: Use equiv_opt for latches --- tests/ice40/latches.ys | 11 +++++++++- tests/ice40/latches_tb.v | 57 ------------------------------------------------ 2 files changed, 10 insertions(+), 58 deletions(-) delete mode 100644 tests/ice40/latches_tb.v (limited to 'tests') diff --git a/tests/ice40/latches.ys b/tests/ice40/latches.ys index fe0d1f70e..f3562559e 100644 --- a/tests/ice40/latches.ys +++ b/tests/ice40/latches.ys @@ -1,6 +1,15 @@ read_verilog latches.v +design -save read + +proc +async2sync # converts latches to a 'sync' variant clocked by a 'super'-clock +flatten +synth_ice40 +equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) + +design -load read synth_ice40 cd top select -assert-count 4 t:SB_LUT4 select -assert-none t:SB_LUT4 %% t:* %D -write_verilog latches_synth.v diff --git a/tests/ice40/latches_tb.v b/tests/ice40/latches_tb.v deleted file mode 100644 index b0585264b..000000000 --- a/tests/ice40/latches_tb.v +++ /dev/null @@ -1,57 +0,0 @@ -module testbench; - reg clk; - - initial begin - // $dumpfile("testbench.vcd"); - // $dumpvars(0, testbench); - - #5 clk = 0; - repeat (10000) begin - #5 clk = 1; - #5 clk = 0; - end - end - - - reg [2:0] dinA = 0; - wire doutB,doutB1,doutB2; - reg lat,latn,latsr = 0; - - top uut ( - .clk (clk ), - .a (dinA[0] ), - .pre (dinA[1] ), - .clr (dinA[2] ), - .b (doutB ), - .b1 (doutB1 ), - .b2 (doutB2 ) - ); - - always @(posedge clk) begin - #3; - dinA <= dinA + 1; - end - - always @* - if ( clk ) - lat <= dinA[0]; - - - always @* - if ( !clk ) - latn <= dinA[0]; - - - always @* - if ( dinA[2] ) - latsr <= 1'b0; - else if ( dinA[1] ) - latsr <= 1'b1; - else if ( clk ) - latsr <= dinA[0]; - - assert_dff lat_test(.clk(clk), .test(doutB), .pat(lat)); - assert_dff latn_test(.clk(clk), .test(doutB1), .pat(latn)); - assert_dff latsr_test(.clk(clk), .test(doutB2), .pat(latsr)); - -endmodule -- cgit v1.2.3 From 87d5d9b8c80df696c836831df9d9eff6f20476fa Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Wed, 28 Aug 2019 12:30:35 -0700 Subject: Use equiv for memory and dpram --- tests/ice40/dpram.ys | 5 +-- tests/ice40/dpram_tb.v | 81 ------------------------------------------------- tests/ice40/memory.ys | 5 +-- tests/ice40/memory_tb.v | 79 ----------------------------------------------- 4 files changed, 2 insertions(+), 168 deletions(-) delete mode 100644 tests/ice40/dpram_tb.v delete mode 100644 tests/ice40/memory_tb.v (limited to 'tests') diff --git a/tests/ice40/dpram.ys b/tests/ice40/dpram.ys index 77364e5ae..4f6a253ea 100644 --- a/tests/ice40/dpram.ys +++ b/tests/ice40/dpram.ys @@ -6,13 +6,10 @@ equiv_opt -run :prove -map +/ice40/cells_sim.v synth_ice40 memory opt -full -# TODO -#equiv_opt -run prove: -assert null miter -equiv -flatten -make_assert -make_outputs gold gate miter -#sat -verify -prove-asserts -tempinduct -show-inputs -show-outputs miter +sat -verify -prove-asserts -seq 3 -set-init-zero -show-inputs -show-outputs miter design -load postopt cd top select -assert-count 1 t:SB_RAM40_4K select -assert-none t:SB_RAM40_4K %% t:* %D -write_verilog dpram_synth.v diff --git a/tests/ice40/dpram_tb.v b/tests/ice40/dpram_tb.v deleted file mode 100644 index dede64614..000000000 --- a/tests/ice40/dpram_tb.v +++ /dev/null @@ -1,81 +0,0 @@ -module testbench; - reg clk; - - initial begin - // $dumpfile("testbench.vcd"); - // $dumpvars(0, testbench); - - #5 clk = 0; - repeat (10000) begin - #5 clk = 1; - #5 clk = 0; - end - end - - - reg [7:0] data_a = 0; - reg [7:0] addr_a = 0; - reg [7:0] addr_b = 0; - reg we_a = 0; - reg re_a = 1; - wire [7:0] q_a; - reg mem_init = 0; - - reg [7:0] pq_a; - - always @(posedge clk) begin - #3; - data_a <= data_a + 17; - - addr_a <= addr_a + 1; - addr_b <= addr_b + 1; - end - - always @(posedge addr_a) begin - #10; - if(addr_a > 6'h3E) - mem_init <= 1; - end - - always @(posedge clk) begin - //#3; - we_a <= !we_a; - end - - reg [7:0] mem [(1<<8)-1:0]; - - always @(posedge clk) // Write memory. - begin - if (we_a) - mem[addr_a] <= data_a; // Using write address bus. - end - always @(posedge clk) // Read memory. - begin - pq_a <= mem[addr_b]; // Using read address bus. - end - - top uut ( - .din(data_a), - .write_en(we_a), - .waddr(addr_a), - .wclk(clk), - .raddr(addr_b), - .rclk(clk), - .dout(q_a) - ); - - uut_mem_checker port_a_test(.clk(clk), .init(mem_init), .en(!we_a), .A(q_a), .B(pq_a)); - -endmodule - -module uut_mem_checker(input clk, input init, input en, input [7:0] A, input [7:0] B); - always @(posedge clk) - begin - #1; - if (en == 1 & init == 1 & A !== B) - begin - $display("ERROR: ASSERTION FAILED in %m:",$time," ",A," ",B); - $stop; - end - end -endmodule diff --git a/tests/ice40/memory.ys b/tests/ice40/memory.ys index 9b7490cd8..a66afbae6 100644 --- a/tests/ice40/memory.ys +++ b/tests/ice40/memory.ys @@ -6,13 +6,10 @@ equiv_opt -run :prove -map +/ice40/cells_sim.v synth_ice40 memory opt -full -# TODO -#equiv_opt -run prove: -assert null miter -equiv -flatten -make_assert -make_outputs gold gate miter -#sat -verify -prove-asserts -tempinduct -show-inputs -show-outputs miter +sat -verify -prove-asserts -seq 5 -set-init-zero -show-inputs -show-outputs miter design -load postopt cd top select -assert-count 1 t:SB_RAM40_4K select -assert-none t:SB_RAM40_4K %% t:* %D -write_verilog memory_synth.v diff --git a/tests/ice40/memory_tb.v b/tests/ice40/memory_tb.v deleted file mode 100644 index be69374eb..000000000 --- a/tests/ice40/memory_tb.v +++ /dev/null @@ -1,79 +0,0 @@ -module testbench; - reg clk; - - initial begin - // $dumpfile("testbench.vcd"); - // $dumpvars(0, testbench); - - #5 clk = 0; - repeat (10000) begin - #5 clk = 1; - #5 clk = 0; - end - end - - - reg [7:0] data_a = 0; - reg [5:0] addr_a = 0; - reg we_a = 0; - reg re_a = 1; - wire [7:0] q_a; - reg mem_init = 0; - - reg [7:0] pq_a; - - top uut ( - .data_a(data_a), - .addr_a(addr_a), - .we_a(we_a), - .clk(clk), - .q_a(q_a) - ); - - always @(posedge clk) begin - #3; - data_a <= data_a + 17; - - addr_a <= addr_a + 1; - end - - always @(posedge addr_a) begin - #10; - if(addr_a > 6'h3E) - mem_init <= 1; - end - - always @(posedge clk) begin - //#3; - we_a <= !we_a; - end - - // Declare the RAM variable for check - reg [7:0] ram[63:0]; - - // Port A for check - always @ (posedge clk) - begin - if (we_a) - begin - ram[addr_a] <= data_a; - pq_a <= data_a; - end - pq_a <= ram[addr_a]; - end - - uut_mem_checker port_a_test(.clk(clk), .init(mem_init), .en(!we_a), .A(q_a), .B(pq_a)); - -endmodule - -module uut_mem_checker(input clk, input init, input en, input [7:0] A, input [7:0] B); - always @(posedge clk) - begin - #1; - if (en == 1 & init == 1 & A !== B) - begin - $display("ERROR: ASSERTION FAILED in %m:",$time," ",A," ",B); - $stop; - end - end -endmodule -- cgit v1.2.3 From b8a9f73089234ed699a4057b50fd739a90abea43 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Wed, 28 Aug 2019 12:36:20 -0700 Subject: Comment out *.sh used for testbenches as we have no more --- tests/ice40/run-test.sh | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) (limited to 'tests') diff --git a/tests/ice40/run-test.sh b/tests/ice40/run-test.sh index bd9d35314..941dcaecd 100755 --- a/tests/ice40/run-test.sh +++ b/tests/ice40/run-test.sh @@ -21,13 +21,13 @@ for x in *.ys; do fi done -for s in *.sh; do - if [ "$s" != "run-test.sh" ]; then - echo "all:: run-$s" - echo "run-$s:" - echo " @echo 'Running $s..'" - echo " @bash $s" - fi -done +#for s in *.sh; do +# if [ "$s" != "run-test.sh" ]; then +# echo "all:: run-$s" +# echo "run-$s:" +# echo " @echo 'Running $s..'" +# echo " @bash $s" +# fi +#done } > run-test.mk exec ${MAKE:-make} -f run-test.mk -- cgit v1.2.3 From dd42aa87b9b3bb041cbfe49079c6538f0a6d5646 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Wed, 28 Aug 2019 18:34:32 -0700 Subject: Add ice40_opt test --- tests/ice40/ice40_opt.ys | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) create mode 100644 tests/ice40/ice40_opt.ys (limited to 'tests') diff --git a/tests/ice40/ice40_opt.ys b/tests/ice40/ice40_opt.ys new file mode 100644 index 000000000..18e0d2b8a --- /dev/null +++ b/tests/ice40/ice40_opt.ys @@ -0,0 +1,24 @@ +read_verilog -icells -formal < Date: Wed, 28 Aug 2019 18:44:57 -0700 Subject: Add SB_CARRY to ice40_opt test --- tests/ice40/ice40_opt.ys | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) (limited to 'tests') diff --git a/tests/ice40/ice40_opt.ys b/tests/ice40/ice40_opt.ys index 18e0d2b8a..b17c69c91 100644 --- a/tests/ice40/ice40_opt.ys +++ b/tests/ice40/ice40_opt.ys @@ -1,5 +1,5 @@ read_verilog -icells -formal < Date: Wed, 28 Aug 2019 18:47:48 -0700 Subject: Add run-test.sh too --- tests/ice40/run-test.sh | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) create mode 100755 tests/ice40/run-test.sh (limited to 'tests') diff --git a/tests/ice40/run-test.sh b/tests/ice40/run-test.sh new file mode 100755 index 000000000..ea56b70f0 --- /dev/null +++ b/tests/ice40/run-test.sh @@ -0,0 +1,20 @@ +#!/usr/bin/env bash +set -e +{ +echo "all::" +for x in *.ys; do + echo "all:: run-$x" + echo "run-$x:" + echo " @echo 'Running $x..'" + echo " @../../yosys -ql ${x%.ys}.log $x" +done +for s in *.sh; do + if [ "$s" != "run-test.sh" ]; then + echo "all:: run-$s" + echo "run-$s:" + echo " @echo 'Running $s..'" + echo " @bash $s" + fi +done +} > run-test.mk +exec ${MAKE:-make} -f run-test.mk -- cgit v1.2.3 From 1fdb3fc98cdbd7126f07778397e3c334f45945df Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Wed, 28 Aug 2019 19:58:58 -0700 Subject: Add failing test --- tests/various/hierarchy_defer.ys | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) create mode 100644 tests/various/hierarchy_defer.ys (limited to 'tests') diff --git a/tests/various/hierarchy_defer.ys b/tests/various/hierarchy_defer.ys new file mode 100644 index 000000000..170bb8c5f --- /dev/null +++ b/tests/various/hierarchy_defer.ys @@ -0,0 +1,18 @@ +read -vlog2k < Date: Thu, 29 Aug 2019 10:49:46 +0300 Subject: Add comments for examples from Lattice user guide --- tests/ice40/dpram.v | 3 +++ tests/ice40/macc.v | 3 +++ tests/ice40/rom.v | 3 +++ 3 files changed, 9 insertions(+) (limited to 'tests') diff --git a/tests/ice40/dpram.v b/tests/ice40/dpram.v index 2e69d6b3b..3ea4c1f27 100644 --- a/tests/ice40/dpram.v +++ b/tests/ice40/dpram.v @@ -1,3 +1,6 @@ +/* +Example from: https://www.latticesemi.com/-/media/LatticeSemi/Documents/UserManuals/EI/iCEcube201701UserGuide.ashx?document_id=52071 [p. 72]. +*/ module top (din, write_en, waddr, wclk, raddr, rclk, dout); parameter addr_width = 8; parameter data_width = 8; diff --git a/tests/ice40/macc.v b/tests/ice40/macc.v index 115f8ce42..63a3d3a74 100644 --- a/tests/ice40/macc.v +++ b/tests/ice40/macc.v @@ -1,3 +1,6 @@ +/* +Example from: https://www.latticesemi.com/-/media/LatticeSemi/Documents/UserManuals/EI/iCEcube201701UserGuide.ashx?document_id=52071 [p. 77]. +*/ module top(clk,a,b,c,set); parameter A_WIDTH = 4; parameter B_WIDTH = 3; diff --git a/tests/ice40/rom.v b/tests/ice40/rom.v index c31ca3b2b..0a0f41f37 100644 --- a/tests/ice40/rom.v +++ b/tests/ice40/rom.v @@ -1,3 +1,6 @@ +/* +Example from: https://www.latticesemi.com/-/media/LatticeSemi/Documents/UserManuals/EI/iCEcube201701UserGuide.ashx?document_id=52071 [p. 74]. +*/ module top(data, addr); output [3:0] data; input [4:0] addr; -- cgit v1.2.3 From 67587bad7fb1adf14ca9598bb1a01d0ffda6a018 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 29 Aug 2019 09:10:20 -0700 Subject: Add constant expression attribute to test --- tests/various/hierarchy_defer.ys | 1 + 1 file changed, 1 insertion(+) (limited to 'tests') diff --git a/tests/various/hierarchy_defer.ys b/tests/various/hierarchy_defer.ys index 170bb8c5f..0bf4de44e 100644 --- a/tests/various/hierarchy_defer.ys +++ b/tests/various/hierarchy_defer.ys @@ -7,6 +7,7 @@ module top(input i, output o); sub s0(i, o); endmodule +(* constant_expression=1+1?2*2:3/3 *) module sub(input i, output o); assign o = ~i; endmodule -- cgit v1.2.3 From 6a111ad32487fb49c5d30db5697c794814ffa511 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 29 Aug 2019 17:24:48 -0700 Subject: Nicer formatting --- tests/simple_abc9/run-test.sh | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) (limited to 'tests') diff --git a/tests/simple_abc9/run-test.sh b/tests/simple_abc9/run-test.sh index 49ae23338..8df6994e3 100755 --- a/tests/simple_abc9/run-test.sh +++ b/tests/simple_abc9/run-test.sh @@ -20,4 +20,10 @@ fi cp ../simple/*.v . cp ../simple/*.sv . DOLLAR='?' -exec ${MAKE:-make} -f ../tools/autotest.mk $seed *.v EXTRA_FLAGS="-n 300 -p 'hierarchy; synth -run coarse; opt -full; techmap; abc9 -lut 4 -box ../abc.box; stat; check -assert; select -assert-none t:${DOLLAR}_NOT_ t:${DOLLAR}_AND_ %%'" +exec ${MAKE:-make} -f ../tools/autotest.mk $seed *.v EXTRA_FLAGS="-n 300 -p '\ + hierarchy; \ + synth -run coarse; \ + opt -full; \ + techmap; abc9 -lut 4 -box ../abc.box; \ + check -assert; \ + select -assert-none t:${DOLLAR}_NOT_ t:${DOLLAR}_AND_ %%'" -- cgit v1.2.3 From 20f4aea480e259272360f4c77667a9e1828986e8 Mon Sep 17 00:00:00 2001 From: SergeyDegtyar Date: Fri, 30 Aug 2019 08:53:35 +0300 Subject: Remove simulation from run-test.sh --- tests/ice40/run-test.sh | 6 ------ 1 file changed, 6 deletions(-) (limited to 'tests') diff --git a/tests/ice40/run-test.sh b/tests/ice40/run-test.sh index 941dcaecd..acfd582d2 100755 --- a/tests/ice40/run-test.sh +++ b/tests/ice40/run-test.sh @@ -13,12 +13,6 @@ for x in *.ys; do echo "run-$x:" echo " @echo 'Running $x..'" echo " @../../yosys -ql ${x%.ys}.log $x -w 'Yosys has only limited support for tri-state logic at the moment.'" - - if [ -f "${x%.ys}_tb.v" ]; then - echo " @echo 'Running ${x%.ys}_tb.v..'" - echo " @iverilog -o ${x%.ys}_testbench $t ${x%.ys}_synth.v common.v $TECHLIBS_PREFIX/ice40/cells_sim.v" - echo " @vvp -N ${x%.ys}_testbench" - fi done #for s in *.sh; do -- cgit v1.2.3 From 8e3abda19308bd4ac7e03d38f899831e853f4794 Mon Sep 17 00:00:00 2001 From: SergeyDegtyar Date: Fri, 30 Aug 2019 09:11:03 +0300 Subject: Remove simulation from run-test.sh (unnecessary paths) --- tests/ice40/run-test.sh | 25 +++++++++---------------- 1 file changed, 9 insertions(+), 16 deletions(-) (limited to 'tests') diff --git a/tests/ice40/run-test.sh b/tests/ice40/run-test.sh index acfd582d2..2c72ca3a9 100755 --- a/tests/ice40/run-test.sh +++ b/tests/ice40/run-test.sh @@ -1,11 +1,5 @@ +#!/usr/bin/env bash set -e -if [ -f "../../techlibs/common/simcells.v" ]; then - COMMON_PREFIX=../../techlibs/common - TECHLIBS_PREFIX=../../techlibs -else - COMMON_PREFIX=/usr/local/share/yosys - TECHLIBS_PREFIX=/usr/local/share/yosys -fi { echo "all::" for x in *.ys; do @@ -14,14 +8,13 @@ for x in *.ys; do echo " @echo 'Running $x..'" echo " @../../yosys -ql ${x%.ys}.log $x -w 'Yosys has only limited support for tri-state logic at the moment.'" done - -#for s in *.sh; do -# if [ "$s" != "run-test.sh" ]; then -# echo "all:: run-$s" -# echo "run-$s:" -# echo " @echo 'Running $s..'" -# echo " @bash $s" -# fi -#done +for s in *.sh; do + if [ "$s" != "run-test.sh" ]; then + echo "all:: run-$s" + echo "run-$s:" + echo " @echo 'Running $s..'" + echo " @bash $s" + fi +done } > run-test.mk exec ${MAKE:-make} -f run-test.mk -- cgit v1.2.3 From eb0a5b2293d005d3a6a2d680b40f1449a489204d Mon Sep 17 00:00:00 2001 From: SergeyDegtyar Date: Fri, 30 Aug 2019 09:17:32 +0300 Subject: Remove unnecessary common.v(assertions for testbenches). --- tests/ice40/common.v | 47 ----------------------------------------------- 1 file changed, 47 deletions(-) delete mode 100644 tests/ice40/common.v (limited to 'tests') diff --git a/tests/ice40/common.v b/tests/ice40/common.v deleted file mode 100644 index 5446f0817..000000000 --- a/tests/ice40/common.v +++ /dev/null @@ -1,47 +0,0 @@ -module assert_dff(input clk, input test, input pat); - always @(posedge clk) - begin - #1; - if (test != pat) - begin - $display("ERROR: ASSERTION FAILED in %m:",$time); - $stop; - end - end -endmodule - -module assert_tri(input en, input A, input B); - always @(posedge en) - begin - #1; - if (A !== B) - begin - $display("ERROR: ASSERTION FAILED in %m:",$time," ",A," ",B); - $stop; - end - end -endmodule - -module assert_Z(input clk, input A); - always @(posedge clk) - begin - #1; - if (A === 1'bZ) - begin - $display("ERROR: ASSERTION FAILED in %m:",$time," ",A); - $stop; - end - end -endmodule - -module assert_comb(input A, input B); - always @(*) - begin - #1; - if (A !== B) - begin - $display("ERROR: ASSERTION FAILED in %m:",$time," ",A," ",B); - $stop; - end - end -endmodule -- cgit v1.2.3 From d144748401df3f6d527771e6d30cc1eb1e08734e Mon Sep 17 00:00:00 2001 From: SergeyDegtyar Date: Fri, 30 Aug 2019 09:45:33 +0300 Subject: Add new tests. --- tests/ice40/alu.v | 19 +++++++++++++ tests/ice40/alu.ys | 11 ++++++++ tests/ice40/counter.v | 17 ++++++++++++ tests/ice40/counter.ys | 11 ++++++++ tests/ice40/fsm.v | 73 ++++++++++++++++++++++++++++++++++++++++++++++++++ tests/ice40/fsm.ys | 13 +++++++++ tests/ice40/logic.v | 18 +++++++++++++ tests/ice40/logic.ys | 7 +++++ tests/ice40/shifter.v | 22 +++++++++++++++ tests/ice40/shifter.ys | 9 +++++++ 10 files changed, 200 insertions(+) create mode 100644 tests/ice40/alu.v create mode 100644 tests/ice40/alu.ys create mode 100644 tests/ice40/counter.v create mode 100644 tests/ice40/counter.ys create mode 100644 tests/ice40/fsm.v create mode 100644 tests/ice40/fsm.ys create mode 100644 tests/ice40/logic.v create mode 100644 tests/ice40/logic.ys create mode 100644 tests/ice40/shifter.v create mode 100644 tests/ice40/shifter.ys (limited to 'tests') diff --git a/tests/ice40/alu.v b/tests/ice40/alu.v new file mode 100644 index 000000000..f82cc2e21 --- /dev/null +++ b/tests/ice40/alu.v @@ -0,0 +1,19 @@ +module top ( + input clock, + input [31:0] dinA, dinB, + input [2:0] opcode, + output reg [31:0] dout +); + always @(posedge clock) begin + case (opcode) + 0: dout <= dinA + dinB; + 1: dout <= dinA - dinB; + 2: dout <= dinA >> dinB; + 3: dout <= $signed(dinA) >>> dinB; + 4: dout <= dinA << dinB; + 5: dout <= dinA & dinB; + 6: dout <= dinA | dinB; + 7: dout <= dinA ^ dinB; + endcase + end +endmodule diff --git a/tests/ice40/alu.ys b/tests/ice40/alu.ys new file mode 100644 index 000000000..bd859efc4 --- /dev/null +++ b/tests/ice40/alu.ys @@ -0,0 +1,11 @@ +read_verilog alu.v +hierarchy -top top +proc +flatten +equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module +select -assert-count 62 t:SB_CARRY +select -assert-count 32 t:SB_DFF +select -assert-count 655 t:SB_LUT4 +select -assert-none t:SB_CARRY t:SB_DFF t:SB_LUT4 %% t:* %D diff --git a/tests/ice40/counter.v b/tests/ice40/counter.v new file mode 100644 index 000000000..52852f8ac --- /dev/null +++ b/tests/ice40/counter.v @@ -0,0 +1,17 @@ +module top ( +out, +clk, +reset +); + output [7:0] out; + input clk, reset; + reg [7:0] out; + + always @(posedge clk, posedge reset) + if (reset) begin + out <= 8'b0 ; + end else + out <= out + 1; + + +endmodule diff --git a/tests/ice40/counter.ys b/tests/ice40/counter.ys new file mode 100644 index 000000000..fb32e67a5 --- /dev/null +++ b/tests/ice40/counter.ys @@ -0,0 +1,11 @@ +read_verilog counter.v +hierarchy -top top +proc +flatten +equiv_opt -map +/ice40/cells_sim.v synth_ice40 # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module +select -assert-count 7 t:SB_CARRY +select -assert-count 8 t:SB_DFFR +select -assert-count 8 t:SB_LUT4 +select -assert-none t:SB_CARRY t:SB_DFFR t:SB_LUT4 %% t:* %D diff --git a/tests/ice40/fsm.v b/tests/ice40/fsm.v new file mode 100644 index 000000000..0605bd102 --- /dev/null +++ b/tests/ice40/fsm.v @@ -0,0 +1,73 @@ + module fsm ( + clock, + reset, + req_0, + req_1, + gnt_0, + gnt_1 + ); + input clock,reset,req_0,req_1; + output gnt_0,gnt_1; + wire clock,reset,req_0,req_1; + reg gnt_0,gnt_1; + + parameter SIZE = 3 ; + parameter IDLE = 3'b001,GNT0 = 3'b010,GNT1 = 3'b100,GNT2 = 3'b101 ; + + reg [SIZE-1:0] state; + reg [SIZE-1:0] next_state; + + always @ (posedge clock) + begin : FSM + if (reset == 1'b1) begin + state <= #1 IDLE; + gnt_0 <= 0; + gnt_1 <= 0; + end else + case(state) + IDLE : if (req_0 == 1'b1) begin + state <= #1 GNT0; + gnt_0 <= 1; + end else if (req_1 == 1'b1) begin + gnt_1 <= 1; + state <= #1 GNT0; + end else begin + state <= #1 IDLE; + end + GNT0 : if (req_0 == 1'b1) begin + state <= #1 GNT0; + end else begin + gnt_0 <= 0; + state <= #1 IDLE; + end + GNT1 : if (req_1 == 1'b1) begin + state <= #1 GNT2; + gnt_1 <= req_0; + end + GNT2 : if (req_0 == 1'b1) begin + state <= #1 GNT1; + gnt_1 <= req_1; + end + default : state <= #1 IDLE; + endcase + end + + endmodule + + module top ( +input clk, +input rst, +input a, +input b, +output g0, +output g1 +); + +fsm u_fsm ( .clock(clk), + .reset(rst), + .req_0(a), + .req_1(b), + .gnt_0(g0), + .gnt_1(g1)); + +endmodule diff --git a/tests/ice40/fsm.ys b/tests/ice40/fsm.ys new file mode 100644 index 000000000..4cc8629d6 --- /dev/null +++ b/tests/ice40/fsm.ys @@ -0,0 +1,13 @@ +read_verilog fsm.v +hierarchy -top top +proc +flatten +equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module + +select -assert-count 2 t:SB_DFFESR +select -assert-count 2 t:SB_DFFSR +select -assert-count 1 t:SB_DFFSS +select -assert-count 13 t:SB_LUT4 +select -assert-none t:SB_DFFESR t:SB_DFFSR t:SB_DFFSS t:SB_LUT4 %% t:* %D diff --git a/tests/ice40/logic.v b/tests/ice40/logic.v new file mode 100644 index 000000000..e5343cae0 --- /dev/null +++ b/tests/ice40/logic.v @@ -0,0 +1,18 @@ +module top +( + input [0:7] in, + output B1,B2,B3,B4,B5,B6,B7,B8,B9,B10 + ); + + assign B1 = in[0] & in[1]; + assign B2 = in[0] | in[1]; + assign B3 = in[0] ~& in[1]; + assign B4 = in[0] ~| in[1]; + assign B5 = in[0] ^ in[1]; + assign B6 = in[0] ~^ in[1]; + assign B7 = ~in[0]; + assign B8 = in[0]; + assign B9 = in[0:1] && in [2:3]; + assign B10 = in[0:1] || in [2:3]; + +endmodule diff --git a/tests/ice40/logic.ys b/tests/ice40/logic.ys new file mode 100644 index 000000000..fc5e5b1d8 --- /dev/null +++ b/tests/ice40/logic.ys @@ -0,0 +1,7 @@ +read_verilog logic.v +hierarchy -top top +equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module +select -assert-count 9 t:SB_LUT4 +select -assert-none t:SB_LUT4 %% t:* %D diff --git a/tests/ice40/shifter.v b/tests/ice40/shifter.v new file mode 100644 index 000000000..c55632552 --- /dev/null +++ b/tests/ice40/shifter.v @@ -0,0 +1,22 @@ +module top ( +out, +clk, +in +); + output [7:0] out; + input signed clk, in; + reg signed [7:0] out = 0; + + always @(posedge clk) + begin +`ifndef BUG + out <= out >> 1; + out[7] <= in; +`else + + out <= out << 1; + out[7] <= in; +`endif + end + +endmodule diff --git a/tests/ice40/shifter.ys b/tests/ice40/shifter.ys new file mode 100644 index 000000000..47d95d298 --- /dev/null +++ b/tests/ice40/shifter.ys @@ -0,0 +1,9 @@ +read_verilog shifter.v +hierarchy -top top +proc +flatten +equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module +select -assert-count 8 t:SB_DFF +select -assert-none t:SB_DFF %% t:* %D -- cgit v1.2.3 From 86f1375ecd3e6721a0e5da469672db890926914e Mon Sep 17 00:00:00 2001 From: SergeyDegtyar Date: Fri, 30 Aug 2019 12:38:28 +0300 Subject: Fix test for counter --- tests/ice40/counter.ys | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'tests') diff --git a/tests/ice40/counter.ys b/tests/ice40/counter.ys index fb32e67a5..c65c21622 100644 --- a/tests/ice40/counter.ys +++ b/tests/ice40/counter.ys @@ -5,7 +5,7 @@ flatten equiv_opt -map +/ice40/cells_sim.v synth_ice40 # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd top # Constrain all select calls below inside the top module -select -assert-count 7 t:SB_CARRY +select -assert-count 6 t:SB_CARRY select -assert-count 8 t:SB_DFFR select -assert-count 8 t:SB_LUT4 select -assert-none t:SB_CARRY t:SB_DFFR t:SB_LUT4 %% t:* %D -- cgit v1.2.3 From f4a48ce8e6785fe9828b8896b9a60a74580dc2eb Mon Sep 17 00:00:00 2001 From: SergeyDegtyar Date: Fri, 30 Aug 2019 13:22:11 +0300 Subject: fix div_mod test --- tests/ice40/div_mod.ys | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'tests') diff --git a/tests/ice40/div_mod.ys b/tests/ice40/div_mod.ys index 96753b4ef..f55490572 100644 --- a/tests/ice40/div_mod.ys +++ b/tests/ice40/div_mod.ys @@ -4,6 +4,6 @@ flatten equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd top # Constrain all select calls below inside the top module -select -assert-count 88 t:SB_LUT4 +select -assert-count 62 t:SB_LUT4 select -assert-count 65 t:SB_CARRY select -assert-none t:SB_LUT4 t:SB_CARRY %% t:* %D -- cgit v1.2.3 From 94a56c14b78a2872d65bb30371151e934a259275 Mon Sep 17 00:00:00 2001 From: SergeyDegtyar Date: Fri, 30 Aug 2019 14:17:03 +0300 Subject: div_mod test fix --- tests/ice40/div_mod.ys | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'tests') diff --git a/tests/ice40/div_mod.ys b/tests/ice40/div_mod.ys index f55490572..21cac7144 100644 --- a/tests/ice40/div_mod.ys +++ b/tests/ice40/div_mod.ys @@ -5,5 +5,5 @@ equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd top # Constrain all select calls below inside the top module select -assert-count 62 t:SB_LUT4 -select -assert-count 65 t:SB_CARRY +select -assert-count 41 t:SB_CARRY select -assert-none t:SB_LUT4 t:SB_CARRY %% t:* %D -- cgit v1.2.3 From 17c92dc679458a9ffabd76e2ce8e2491bd249110 Mon Sep 17 00:00:00 2001 From: SergeyDegtyar Date: Fri, 30 Aug 2019 15:22:46 +0300 Subject: Fix macc test --- tests/ice40/macc.ys | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'tests') diff --git a/tests/ice40/macc.ys b/tests/ice40/macc.ys index 233e7e890..d65c31b73 100644 --- a/tests/ice40/macc.ys +++ b/tests/ice40/macc.ys @@ -4,7 +4,7 @@ hierarchy -top top equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 -dsp # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd top # Constrain all select calls below inside the top module -select -assert-count 41 t:SB_LUT4 +select -assert-count 38 t:SB_LUT4 select -assert-count 6 t:SB_CARRY select -assert-count 7 t:SB_DFFSR select -assert-none t:SB_LUT4 t:SB_CARRY t:SB_DFFSR %% t:* %D -- cgit v1.2.3 From 53912ad649d6e9f447b9e4037255606783a0cf51 Mon Sep 17 00:00:00 2001 From: SergeyDegtyar Date: Fri, 30 Aug 2019 16:01:36 +0300 Subject: macc test fix --- tests/ice40/macc.ys | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'tests') diff --git a/tests/ice40/macc.ys b/tests/ice40/macc.ys index d65c31b73..fe5b5f662 100644 --- a/tests/ice40/macc.ys +++ b/tests/ice40/macc.ys @@ -5,6 +5,6 @@ equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 -dsp # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd top # Constrain all select calls below inside the top module select -assert-count 38 t:SB_LUT4 -select -assert-count 6 t:SB_CARRY +select -assert-count 3 t:SB_CARRY select -assert-count 7 t:SB_DFFSR select -assert-none t:SB_LUT4 t:SB_CARRY t:SB_DFFSR %% t:* %D -- cgit v1.2.3 From 76a52712dac4f28fbc3c5611911310d252cd91a6 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 30 Aug 2019 12:22:59 -0700 Subject: Improve tests/ice40/macc.ys for SB_MAC16 --- tests/ice40/macc.v | 4 ++-- tests/ice40/macc.ys | 13 ++++++++----- 2 files changed, 10 insertions(+), 7 deletions(-) (limited to 'tests') diff --git a/tests/ice40/macc.v b/tests/ice40/macc.v index 63a3d3a74..6c3676c83 100644 --- a/tests/ice40/macc.v +++ b/tests/ice40/macc.v @@ -2,8 +2,8 @@ Example from: https://www.latticesemi.com/-/media/LatticeSemi/Documents/UserManuals/EI/iCEcube201701UserGuide.ashx?document_id=52071 [p. 77]. */ module top(clk,a,b,c,set); -parameter A_WIDTH = 4; -parameter B_WIDTH = 3; +parameter A_WIDTH = 6 /*4*/; +parameter B_WIDTH = 6 /*3*/; input set; input clk; input signed [(A_WIDTH - 1):0] a; diff --git a/tests/ice40/macc.ys b/tests/ice40/macc.ys index fe5b5f662..0f4c19be5 100644 --- a/tests/ice40/macc.ys +++ b/tests/ice40/macc.ys @@ -1,10 +1,13 @@ read_verilog macc.v proc hierarchy -top top -equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 -dsp # equivalency check +#equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 -dsp # equivalency check + +equiv_opt -run :prove -map +/ice40/cells_sim.v synth_ice40 -dsp +async2sync +equiv_opt -run prove: -assert null + design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd top # Constrain all select calls below inside the top module -select -assert-count 38 t:SB_LUT4 -select -assert-count 3 t:SB_CARRY -select -assert-count 7 t:SB_DFFSR -select -assert-none t:SB_LUT4 t:SB_CARRY t:SB_DFFSR %% t:* %D +select -assert-count 1 t:SB_MAC16 +select -assert-none t:SB_MAC16 %% t:* %D -- cgit v1.2.3 From 4290548de35beba766bd7e0684e19de83a0cb2fa Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 30 Aug 2019 20:31:53 -0700 Subject: Make abc9 test a bit more interesting --- tests/various/abc9.v | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) (limited to 'tests') diff --git a/tests/various/abc9.v b/tests/various/abc9.v index a08b613a8..30ebd4e26 100644 --- a/tests/various/abc9.v +++ b/tests/various/abc9.v @@ -5,5 +5,7 @@ always @* endmodule module abc9_test028(input i, output o); -unknown u(~i, o); +wire w; +unknown u(~i, w); +unknown2 u2(w, o); endmodule -- cgit v1.2.3 From 69a5dea89ef8cbf8bcc1b761518738623e028e38 Mon Sep 17 00:00:00 2001 From: Emily Date: Tue, 3 Sep 2019 00:57:32 +0100 Subject: Use `command -v` rather than `which` --- tests/simple/run-test.sh | 2 +- tests/simple_abc9/run-test.sh | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) (limited to 'tests') diff --git a/tests/simple/run-test.sh b/tests/simple/run-test.sh index 967ac49f2..f20fd0d30 100755 --- a/tests/simple/run-test.sh +++ b/tests/simple/run-test.sh @@ -12,7 +12,7 @@ done shift "$((OPTIND-1))" # check for Icarus Verilog -if ! which iverilog > /dev/null ; then +if ! command -v iverilog > /dev/null ; then echo "$0: Error: Icarus Verilog 'iverilog' not found." exit 1 fi diff --git a/tests/simple_abc9/run-test.sh b/tests/simple_abc9/run-test.sh index 8df6994e3..0d4262005 100755 --- a/tests/simple_abc9/run-test.sh +++ b/tests/simple_abc9/run-test.sh @@ -12,7 +12,7 @@ done shift "$((OPTIND-1))" # check for Icarus Verilog -if ! which iverilog > /dev/null ; then +if ! command -v iverilog > /dev/null ; then echo "$0: Error: Icarus Verilog 'iverilog' not found." exit 1 fi -- cgit v1.2.3 From 81247168302a578add43e3e856eb74868dc5a1ba Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Tue, 3 Sep 2019 10:52:34 -0700 Subject: Add `read -noverific` before read --- tests/various/hierarchy_defer.ys | 1 + 1 file changed, 1 insertion(+) (limited to 'tests') diff --git a/tests/various/hierarchy_defer.ys b/tests/various/hierarchy_defer.ys index 0bf4de44e..baec52c9d 100644 --- a/tests/various/hierarchy_defer.ys +++ b/tests/various/hierarchy_defer.ys @@ -1,3 +1,4 @@ +read -noverific read -vlog2k < Date: Tue, 3 Sep 2019 12:17:26 -0700 Subject: Expand test with `hierarchy' without -auto-top --- tests/various/hierarchy_defer.ys | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'tests') diff --git a/tests/various/hierarchy_defer.ys b/tests/various/hierarchy_defer.ys index baec52c9d..70f5b70a3 100644 --- a/tests/various/hierarchy_defer.ys +++ b/tests/various/hierarchy_defer.ys @@ -13,8 +13,15 @@ module sub(input i, output o); assign o = ~i; endmodule EOT +design -save read hierarchy -auto-top select -assert-any top select -assert-any sub select -assert-none foo + +design -load read +hierarchy +select -assert-any top +select -assert-any sub +select -assert-none foo -- cgit v1.2.3 From 0cee66e7591b6315f9e7dce91b789c1f6b53138f Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Wed, 4 Sep 2019 12:34:44 -0700 Subject: Add peepopt_dffmuxext tests --- tests/simple/peepopt.v | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'tests') diff --git a/tests/simple/peepopt.v b/tests/simple/peepopt.v index 1bf427897..b4d113dba 100644 --- a/tests/simple/peepopt.v +++ b/tests/simple/peepopt.v @@ -11,3 +11,11 @@ wire [3:0] t; assign t = i * 3; assign o = t / 3; endmodule + +module peepopt_dffmuxext_signed(input clk, ce, input signed [1:0] i, output reg signed [3:0] o); + always @(posedge clk) if (ce) o <= i; +endmodule + +module peepopt_dffmuxext_unsigned(input clk, ce, input [1:0] i, output reg [3:0] o); + always @(posedge clk) if (ce) o <= i; +endmodule -- cgit v1.2.3 From 6fe1ca633d90fb238d2671dba3d7f772c263a497 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Wed, 4 Sep 2019 15:20:04 -0700 Subject: abc9 followed by clean otherwise netlist could be invalid for sim --- tests/simple_abc9/run-test.sh | 1 + 1 file changed, 1 insertion(+) (limited to 'tests') diff --git a/tests/simple_abc9/run-test.sh b/tests/simple_abc9/run-test.sh index 0d4262005..4d15a3253 100755 --- a/tests/simple_abc9/run-test.sh +++ b/tests/simple_abc9/run-test.sh @@ -25,5 +25,6 @@ exec ${MAKE:-make} -f ../tools/autotest.mk $seed *.v EXTRA_FLAGS="-n 300 -p '\ synth -run coarse; \ opt -full; \ techmap; abc9 -lut 4 -box ../abc.box; \ + clean; \ check -assert; \ select -assert-none t:${DOLLAR}_NOT_ t:${DOLLAR}_AND_ %%'" -- cgit v1.2.3 From 11f623cbe0057ee752f2545eb7100966afb08676 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 5 Sep 2019 08:25:09 -0700 Subject: Revert "abc9 followed by clean otherwise netlist could be invalid for sim" This reverts commit 6fe1ca633d90fb238d2671dba3d7f772c263a497. --- tests/simple_abc9/run-test.sh | 1 - 1 file changed, 1 deletion(-) (limited to 'tests') diff --git a/tests/simple_abc9/run-test.sh b/tests/simple_abc9/run-test.sh index 4d15a3253..0d4262005 100755 --- a/tests/simple_abc9/run-test.sh +++ b/tests/simple_abc9/run-test.sh @@ -25,6 +25,5 @@ exec ${MAKE:-make} -f ../tools/autotest.mk $seed *.v EXTRA_FLAGS="-n 300 -p '\ synth -run coarse; \ opt -full; \ techmap; abc9 -lut 4 -box ../abc.box; \ - clean; \ check -assert; \ select -assert-none t:${DOLLAR}_NOT_ t:${DOLLAR}_AND_ %%'" -- cgit v1.2.3 From ef0681ea4ca0b34689cbf14d5a4478e2785600d9 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 5 Sep 2019 08:43:22 -0700 Subject: simple/peepopt.v tests to various/peepopt.ys with equiv_opt & select --- tests/simple/peepopt.v | 21 ---------------- tests/various/peepopt.ys | 63 ++++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 63 insertions(+), 21 deletions(-) delete mode 100644 tests/simple/peepopt.v create mode 100644 tests/various/peepopt.ys (limited to 'tests') diff --git a/tests/simple/peepopt.v b/tests/simple/peepopt.v deleted file mode 100644 index b4d113dba..000000000 --- a/tests/simple/peepopt.v +++ /dev/null @@ -1,21 +0,0 @@ -module peepopt_shiftmul_0 #(parameter N=3, parameter W=3) (input [N*W-1:0] i, input [$clog2(N)-1:0] s, output [W-1:0] o); -assign o = i[s*W+:W]; -endmodule - -module peepopt_shiftmul_1 (output y, input [2:0] w); -assign y = 1'b1 >> (w * (3'b110)); -endmodule - -module peepopt_muldiv_0(input [1:0] i, output [1:0] o); -wire [3:0] t; -assign t = i * 3; -assign o = t / 3; -endmodule - -module peepopt_dffmuxext_signed(input clk, ce, input signed [1:0] i, output reg signed [3:0] o); - always @(posedge clk) if (ce) o <= i; -endmodule - -module peepopt_dffmuxext_unsigned(input clk, ce, input [1:0] i, output reg [3:0] o); - always @(posedge clk) if (ce) o <= i; -endmodule diff --git a/tests/various/peepopt.ys b/tests/various/peepopt.ys new file mode 100644 index 000000000..91db22423 --- /dev/null +++ b/tests/various/peepopt.ys @@ -0,0 +1,63 @@ +read_verilog <> (w * (3'b110)); +endmodule +EOT + +prep -nokeepdc +equiv_opt peepopt +design -load postopt +clean +select -assert-count 1 t:$shr +select -assert-count 1 t:$mul +select -assert-count 0 t:$shr t:$mul %% t:* %D + +#################### + +design -reset +read_verilog < Date: Fri, 6 Sep 2019 22:48:04 -0700 Subject: Usee equiv_opt -assert --- tests/various/peepopt.ys | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'tests') diff --git a/tests/various/peepopt.ys b/tests/various/peepopt.ys index 91db22423..a476133a2 100644 --- a/tests/various/peepopt.ys +++ b/tests/various/peepopt.ys @@ -5,7 +5,7 @@ endmodule EOT prep -nokeepdc -equiv_opt peepopt +equiv_opt -assert peepopt design -load postopt clean select -assert-count 1 t:$shiftx @@ -21,7 +21,7 @@ endmodule EOT prep -nokeepdc -equiv_opt peepopt +equiv_opt -assert peepopt design -load postopt clean select -assert-count 1 t:$shr @@ -40,7 +40,7 @@ endmodule EOT prep -nokeepdc -equiv_opt peepopt +equiv_opt -assert peepopt design -load postopt clean select -assert-count 0 t:* -- cgit v1.2.3 From e2c2d784c8217e4bcf29fb6b156b6a8285036b80 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 6 Sep 2019 22:48:23 -0700 Subject: Make one check $shift(x)? only; change testcase to be 8b --- tests/various/peepopt.ys | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'tests') diff --git a/tests/various/peepopt.ys b/tests/various/peepopt.ys index a476133a2..dcf3cacbd 100644 --- a/tests/various/peepopt.ys +++ b/tests/various/peepopt.ys @@ -16,7 +16,7 @@ select -assert-count 0 t:$shiftx t:* %D design -reset read_verilog <> (w * (3'b110)); +assign y = 1'b1 >> (w * (8'b110)); endmodule EOT @@ -25,7 +25,7 @@ equiv_opt -assert peepopt design -load postopt clean select -assert-count 1 t:$shr -select -assert-count 1 t:$mul +select -assert-count 0 t:$mul select -assert-count 0 t:$shr t:$mul %% t:* %D #################### -- cgit v1.2.3 From 97e1520b13231c8170cec73774eee7a22c5dc065 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 6 Sep 2019 22:50:03 -0700 Subject: Missing equiv_opt -assert --- tests/various/peepopt.ys | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'tests') diff --git a/tests/various/peepopt.ys b/tests/various/peepopt.ys index dcf3cacbd..33555264d 100644 --- a/tests/various/peepopt.ys +++ b/tests/various/peepopt.ys @@ -55,7 +55,7 @@ endmodule EOT prep -nokeepdc -equiv_opt peepopt +equiv_opt -assert peepopt design -load postopt clean select -assert-count 1 t:$dff r:WIDTH=2 %i -- cgit v1.2.3 From 173c7936c3c329917ca8eb929163a03aab51811e Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 6 Sep 2019 22:51:44 -0700 Subject: Add missing -assert to equiv_opt --- tests/opt/opt_expr.ys | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) (limited to 'tests') diff --git a/tests/opt/opt_expr.ys b/tests/opt/opt_expr.ys index ecc2c8da8..e0acead82 100644 --- a/tests/opt/opt_expr.ys +++ b/tests/opt/opt_expr.ys @@ -204,7 +204,7 @@ endmodule EOT check -equiv_opt opt_expr -fine +equiv_opt -assert opt_expr -fine design -load postopt select -assert-count 1 t:$alu r:A_WIDTH=4 r:B_WIDTH=4 r:Y_WIDTH=5 %i %i %i @@ -218,7 +218,7 @@ endmodule EOT check -equiv_opt opt_expr -fine +equiv_opt -assert opt_expr -fine design -load postopt select -assert-count 1 t:$alu r:A_WIDTH=8 r:B_WIDTH=8 r:Y_WIDTH=9 %i %i %i @@ -232,7 +232,7 @@ endmodule EOT check -equiv_opt opt_expr +equiv_opt -assert opt_expr design -load postopt select -assert-count 1 t:$shiftx r:A_WIDTH=3 %i @@ -246,7 +246,7 @@ endmodule EOT check -equiv_opt opt_expr +equiv_opt -assert opt_expr design -load postopt select -assert-count 1 t:$shiftx r:A_WIDTH=12 %i @@ -260,7 +260,7 @@ endmodule EOT check -equiv_opt opt_expr +equiv_opt -assert opt_expr design -load postopt select -assert-count 1 t:$shift r:A_WIDTH=3 %i @@ -274,7 +274,7 @@ endmodule EOT check -equiv_opt opt_expr +equiv_opt -assert opt_expr design -load postopt select -assert-count 1 t:$shift r:A_WIDTH=10 %i @@ -288,6 +288,6 @@ endmodule EOT check -equiv_opt opt_expr -keepdc +equiv_opt -assert opt_expr -keepdc design -load postopt select -assert-count 1 t:$shift r:A_WIDTH=13 %i -- cgit v1.2.3 From a82e8df7d37c02258d36223bb16833331dc8808e Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Marcin=20Ko=C5=9Bcielnicki?= Date: Fri, 16 Aug 2019 03:14:03 +0000 Subject: techmap: Add support for extracting init values of ports --- tests/techmap/wireinit.ys | 98 +++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 98 insertions(+) create mode 100644 tests/techmap/wireinit.ys (limited to 'tests') diff --git a/tests/techmap/wireinit.ys b/tests/techmap/wireinit.ys new file mode 100644 index 000000000..1396839fe --- /dev/null +++ b/tests/techmap/wireinit.ys @@ -0,0 +1,98 @@ +read_verilog < Date: Tue, 10 Sep 2019 08:47:16 +0800 Subject: tests: ice40: fix div_mod SB_LUT4 count This test is failing due to one of the changes present in this patchset. Adjust the test to match the newly-observed values. https://github.com/xobs/yosys/compare/smtbmc-msvc2-build-fixes...YosysHQ:xobs/pr1362 Signed-off-by: Sean Cross --- tests/ice40/div_mod.ys | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'tests') diff --git a/tests/ice40/div_mod.ys b/tests/ice40/div_mod.ys index 21cac7144..821d6c301 100644 --- a/tests/ice40/div_mod.ys +++ b/tests/ice40/div_mod.ys @@ -4,6 +4,6 @@ flatten equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd top # Constrain all select calls below inside the top module -select -assert-count 62 t:SB_LUT4 +select -assert-count 59 t:SB_LUT4 select -assert-count 41 t:SB_CARRY select -assert-none t:SB_LUT4 t:SB_CARRY %% t:* %D -- cgit v1.2.3 From 580faae8ad608981ef6ef6a99ca6b771dc0368ae Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Wed, 11 Sep 2019 00:07:17 -0700 Subject: Add unsigned case --- tests/various/peepopt.ys | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) (limited to 'tests') diff --git a/tests/various/peepopt.ys b/tests/various/peepopt.ys index 33555264d..e930015a4 100644 --- a/tests/various/peepopt.ys +++ b/tests/various/peepopt.ys @@ -47,6 +47,23 @@ select -assert-count 0 t:* #################### +design -reset +read_verilog < Date: Wed, 11 Sep 2019 00:14:06 -0700 Subject: proc instead of prep --- tests/various/peepopt.ys | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'tests') diff --git a/tests/various/peepopt.ys b/tests/various/peepopt.ys index e930015a4..2a660d5c9 100644 --- a/tests/various/peepopt.ys +++ b/tests/various/peepopt.ys @@ -54,7 +54,7 @@ module peepopt_dffmuxext_unsigned(input clk, ce, input [1:0] i, output reg [3:0] endmodule EOT -prep -nokeepdc +proc equiv_opt -assert peepopt design -load postopt clean @@ -71,7 +71,7 @@ module peepopt_dffmuxext_signed(input clk, ce, input signed [1:0] i, output reg endmodule EOT -prep -nokeepdc +proc equiv_opt -assert peepopt design -load postopt clean -- cgit v1.2.3 From c43e52d2d7d16c26b1a4a9c20fad83c9f4577910 Mon Sep 17 00:00:00 2001 From: David Shah Date: Wed, 11 Sep 2019 13:55:16 +0100 Subject: Add equiv_opt -multiclock Signed-off-by: David Shah --- tests/various/equiv_opt_multiclock.ys | 12 ++++++++++++ 1 file changed, 12 insertions(+) create mode 100644 tests/various/equiv_opt_multiclock.ys (limited to 'tests') diff --git a/tests/various/equiv_opt_multiclock.ys b/tests/various/equiv_opt_multiclock.ys new file mode 100644 index 000000000..81e36d018 --- /dev/null +++ b/tests/various/equiv_opt_multiclock.ys @@ -0,0 +1,12 @@ +read_verilog < Date: Tue, 10 Sep 2019 16:31:50 +0000 Subject: Add -match-init option to dff2dffs. --- tests/techmap/dff2dffs.ys | 50 +++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 50 insertions(+) create mode 100644 tests/techmap/dff2dffs.ys (limited to 'tests') diff --git a/tests/techmap/dff2dffs.ys b/tests/techmap/dff2dffs.ys new file mode 100644 index 000000000..13f1a3cf3 --- /dev/null +++ b/tests/techmap/dff2dffs.ys @@ -0,0 +1,50 @@ +read_verilog << EOT +module top(...); +input clk; +input d; +input sr; +output reg q0, q1, q2, q3, q4, q5; + +initial q0 = 1'b0; +initial q1 = 1'b0; +initial q2 = 1'b1; +initial q3 = 1'b1; +initial q4 = 1'bx; +initial q5 = 1'bx; + +always @(posedge clk) begin + q0 <= sr ? 1'b0 : d; + q1 <= sr ? 1'b1 : d; + q2 <= sr ? 1'b0 : d; + q3 <= sr ? 1'b1 : d; + q4 <= sr ? 1'b0 : d; + q5 <= sr ? 1'b1 : d; +end + +endmodule +EOT + +proc +simplemap +design -save ref + +dff2dffs +clean + +select -assert-count 1 w:q0 %x t:$__DFFS_PP0_ %i +select -assert-count 1 w:q1 %x t:$__DFFS_PP1_ %i +select -assert-count 1 w:q2 %x t:$__DFFS_PP0_ %i +select -assert-count 1 w:q3 %x t:$__DFFS_PP1_ %i +select -assert-count 1 w:q4 %x t:$__DFFS_PP0_ %i +select -assert-count 1 w:q5 %x t:$__DFFS_PP1_ %i + +design -load ref +dff2dffs -match-init +clean + +select -assert-count 1 w:q0 %x t:$__DFFS_PP0_ %i +select -assert-count 0 w:q1 %x t:$__DFFS_PP1_ %i +select -assert-count 0 w:q2 %x t:$__DFFS_PP0_ %i +select -assert-count 1 w:q3 %x t:$__DFFS_PP1_ %i +select -assert-count 1 w:q4 %x t:$__DFFS_PP0_ %i +select -assert-count 1 w:q5 %x t:$__DFFS_PP1_ %i -- cgit v1.2.3 From f46ef47893b4d2cb01fc5914fe0ee89d206f686f Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Wed, 11 Sep 2019 13:22:41 -0700 Subject: Add more tests --- tests/various/peepopt.ys | 32 ++++++++++++++++++++++++++++++++ 1 file changed, 32 insertions(+) (limited to 'tests') diff --git a/tests/various/peepopt.ys b/tests/various/peepopt.ys index 2a660d5c9..8dce679ff 100644 --- a/tests/various/peepopt.ys +++ b/tests/various/peepopt.ys @@ -78,3 +78,35 @@ clean select -assert-count 1 t:$dff r:WIDTH=2 %i select -assert-count 1 t:$mux r:WIDTH=2 %i select -assert-count 0 t:$dff t:$mux %% t:* %D + +################### + +design -reset +read_verilog < Date: Wed, 11 Sep 2019 13:36:37 -0700 Subject: Cope with presence of reset muxes too --- tests/various/peepopt.ys | 39 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 39 insertions(+) (limited to 'tests') diff --git a/tests/various/peepopt.ys b/tests/various/peepopt.ys index 8dce679ff..886c8cd9d 100644 --- a/tests/various/peepopt.ys +++ b/tests/various/peepopt.ys @@ -110,3 +110,42 @@ design -load postopt select -assert-count 1 t:$dff r:WIDTH=5 %i select -assert-count 1 t:$mux r:WIDTH=5 %i select -assert-count 0 t:$dff t:$mux %% t:* %D + +#################### + +design -reset +read_verilog < Date: Fri, 13 Sep 2019 16:33:18 -0700 Subject: Revert "Make one check $shift(x)? only; change testcase to be 8b" This reverts commit e2c2d784c8217e4bcf29fb6b156b6a8285036b80. --- tests/various/peepopt.ys | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'tests') diff --git a/tests/various/peepopt.ys b/tests/various/peepopt.ys index 886c8cd9d..abee9cc0a 100644 --- a/tests/various/peepopt.ys +++ b/tests/various/peepopt.ys @@ -16,7 +16,7 @@ select -assert-count 0 t:$shiftx t:* %D design -reset read_verilog <> (w * (8'b110)); +assign y = 1'b1 >> (w * (3'b110)); endmodule EOT @@ -25,7 +25,7 @@ equiv_opt -assert peepopt design -load postopt clean select -assert-count 1 t:$shr -select -assert-count 0 t:$mul +select -assert-count 1 t:$mul select -assert-count 0 t:$shr t:$mul %% t:* %D #################### -- cgit v1.2.3 From a2eee9ebefc6e8089c815b4355bc64d1ac3396b5 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 13 Sep 2019 16:41:10 -0700 Subject: Add counter-example from @cliffordwolf --- tests/various/peepopt.ys | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) (limited to 'tests') diff --git a/tests/various/peepopt.ys b/tests/various/peepopt.ys index abee9cc0a..7c1c3b5bc 100644 --- a/tests/various/peepopt.ys +++ b/tests/various/peepopt.ys @@ -30,6 +30,30 @@ select -assert-count 0 t:$shr t:$mul %% t:* %D #################### +design -reset +read_verilog <> (S*3); +endmodule +EOT + +prep +design -save gold +peepopt +design -stash gate + +design -import gold -as gold peepopt_shiftmul_2 +design -import gate -as gate peepopt_shiftmul_2 + +miter -equiv -make_assert -make_outputs -ignore_gold_x -flatten gold gate miter +sat -show-public -enable_undef -prove-asserts miter +select -assert-count 1 t:$shr +select -assert-count 1 t:$mul +select -assert-count 0 t:$shr t:$mul %% t:* %D +exit + +#################### + design -reset read_verilog < Date: Fri, 13 Sep 2019 18:19:07 -0700 Subject: Oops --- tests/various/peepopt.ys | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'tests') diff --git a/tests/various/peepopt.ys b/tests/various/peepopt.ys index 7c1c3b5bc..6bca62e2b 100644 --- a/tests/various/peepopt.ys +++ b/tests/various/peepopt.ys @@ -47,10 +47,10 @@ design -import gate -as gate peepopt_shiftmul_2 miter -equiv -make_assert -make_outputs -ignore_gold_x -flatten gold gate miter sat -show-public -enable_undef -prove-asserts miter +cd gate select -assert-count 1 t:$shr select -assert-count 1 t:$mul select -assert-count 0 t:$shr t:$mul %% t:* %D -exit #################### -- cgit v1.2.3 From c9f9518de4af34b2539d230c0894b04d174b755d Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Marcin=20Ko=C5=9Bcielnicki?= Date: Wed, 28 Aug 2019 14:58:14 +0000 Subject: Added extractinv pass --- tests/techmap/extractinv.ys | 41 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 41 insertions(+) create mode 100644 tests/techmap/extractinv.ys (limited to 'tests') diff --git a/tests/techmap/extractinv.ys b/tests/techmap/extractinv.ys new file mode 100644 index 000000000..6146f829a --- /dev/null +++ b/tests/techmap/extractinv.ys @@ -0,0 +1,41 @@ +read_verilog << EOT + +module ff4(...); +parameter [0:0] CLK_INV = 1'b0; +parameter [3:0] DATA_INV = 4'b0000; +(* invertible_pin = "CLK_INV" *) +input clk; +(* invertible_pin = "DATA_INV" *) +input [3:0] d; +output [3:0] q; +endmodule + +module inv(...); +output o; +input i; +endmodule + +module top(...); +input d0, d1, d2, d3; +input clk; +output q; +ff4 #(.DATA_INV(4'h5)) ff_inst (.clk(clk), .d({d3, d2, d1, d0}), .q(q)); +endmodule + +EOT + +extractinv -inv inv o:i +clean + +select -assert-count 2 top/t:inv +select -assert-count 2 top/t:inv top/t:ff4 %ci:+[d] %ci:+[o] %i + +select -assert-count 1 top/t:inv top/w:d0 %co:+[i] %i +select -assert-count 0 top/t:inv top/w:d1 %co:+[i] %i +select -assert-count 1 top/t:inv top/w:d2 %co:+[i] %i +select -assert-count 0 top/t:inv top/w:d3 %co:+[i] %i + +select -assert-count 0 top/t:ff4 top/w:d0 %co:+[d] %i +select -assert-count 1 top/t:ff4 top/w:d1 %co:+[d] %i +select -assert-count 0 top/t:ff4 top/w:d2 %co:+[d] %i +select -assert-count 1 top/t:ff4 top/w:d3 %co:+[d] %i -- cgit v1.2.3 From 6258e6a7e28ade2bdc7b6809675461326c873a45 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 20 Sep 2019 17:49:26 -0700 Subject: Add testcase --- tests/techmap/autopurge.ys | 43 +++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 43 insertions(+) create mode 100644 tests/techmap/autopurge.ys (limited to 'tests') diff --git a/tests/techmap/autopurge.ys b/tests/techmap/autopurge.ys new file mode 100644 index 000000000..4773d5ce3 --- /dev/null +++ b/tests/techmap/autopurge.ys @@ -0,0 +1,43 @@ +# https://github.com/YosysHQ/yosys/issues/1391 +read_verilog < Date: Fri, 20 Sep 2019 17:58:51 -0700 Subject: Hell let's add the original #1381 testcase too --- tests/techmap/autopurge.ys | 25 ++++++++++++++++++++++--- 1 file changed, 22 insertions(+), 3 deletions(-) (limited to 'tests') diff --git a/tests/techmap/autopurge.ys b/tests/techmap/autopurge.ys index 4773d5ce3..1eb99ec37 100644 --- a/tests/techmap/autopurge.ys +++ b/tests/techmap/autopurge.ys @@ -1,6 +1,6 @@ -# https://github.com/YosysHQ/yosys/issues/1391 +# https://github.com/YosysHQ/yosys/issues/1381 read_verilog < Date: Tue, 24 Sep 2019 14:55:32 +0300 Subject: adffs test update (equiv_opt -multiclock). --- tests/ice40/adffs.v | 18 +++++++----------- tests/ice40/adffs.ys | 13 ++++++------- 2 files changed, 13 insertions(+), 18 deletions(-) (limited to 'tests') diff --git a/tests/ice40/adffs.v b/tests/ice40/adffs.v index 93c8bf52c..05e68caf7 100644 --- a/tests/ice40/adffs.v +++ b/tests/ice40/adffs.v @@ -22,30 +22,26 @@ module adffn q <= d; endmodule -module dffsr +module dffs ( input d, clk, pre, clr, output reg q ); initial begin q = 0; end - always @( posedge clk, posedge pre, posedge clr ) - if ( clr ) - q <= 1'b0; - else if ( pre ) + always @( posedge clk ) + if ( pre ) q <= 1'b1; else q <= d; endmodule -module ndffnsnr +module ndffnr ( input d, clk, pre, clr, output reg q ); initial begin q = 0; end - always @( negedge clk, negedge pre, negedge clr ) + always @( negedge clk ) if ( !clr ) q <= 1'b0; - else if ( !pre ) - q <= 1'b1; else q <= d; endmodule @@ -58,7 +54,7 @@ input a, output b,b1,b2,b3 ); -dffsr u_dffsr ( +dffs u_dffs ( .clk (clk ), .clr (clr), .pre (pre), @@ -66,7 +62,7 @@ dffsr u_dffsr ( .q (b ) ); -ndffnsnr u_ndffnsnr ( +ndffnr u_ndffnr ( .clk (clk ), .clr (clr), .pre (pre), diff --git a/tests/ice40/adffs.ys b/tests/ice40/adffs.ys index 14b251c5c..f82da6b14 100644 --- a/tests/ice40/adffs.ys +++ b/tests/ice40/adffs.ys @@ -1,12 +1,11 @@ read_verilog adffs.v proc -async2sync # converts async flops to a 'sync' variant clocked by a 'super'-clock flatten -equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check +equiv_opt -multiclock -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd top # Constrain all select calls below inside the top module -select -assert-count 1 t:SB_DFF -select -assert-count 1 t:SB_DFFN -select -assert-count 2 t:SB_DFFSR -select -assert-count 7 t:SB_LUT4 -select -assert-none t:SB_DFF t:SB_DFFN t:SB_DFFSR t:SB_LUT4 %% t:* %D +select -assert-count 1 t:SB_DFFNSR +select -assert-count 2 t:SB_DFFR +select -assert-count 1 t:SB_DFFSS +select -assert-count 1 t:SB_LUT4 +select -assert-none t:SB_DFFNSR t:SB_DFFR t:SB_DFFSS t:SB_LUT4 %% t:* %D -- cgit v1.2.3 From b66364ada279c1fb81583003001b332dd4521f93 Mon Sep 17 00:00:00 2001 From: SergeyDegtyar Date: Wed, 25 Sep 2019 14:43:26 +0300 Subject: Change sync controls to async. --- tests/ice40/adffs.v | 8 ++++---- tests/ice40/adffs.ys | 8 ++++---- 2 files changed, 8 insertions(+), 8 deletions(-) (limited to 'tests') diff --git a/tests/ice40/adffs.v b/tests/ice40/adffs.v index 05e68caf7..09dc36001 100644 --- a/tests/ice40/adffs.v +++ b/tests/ice40/adffs.v @@ -27,7 +27,7 @@ module dffs initial begin q = 0; end - always @( posedge clk ) + always @( posedge clk, posedge pre ) if ( pre ) q <= 1'b1; else @@ -39,9 +39,9 @@ module ndffnr initial begin q = 0; end - always @( negedge clk ) - if ( !clr ) - q <= 1'b0; + always @( negedge clk, negedge pre ) + if ( !pre ) + q <= 1'b1; else q <= d; endmodule diff --git a/tests/ice40/adffs.ys b/tests/ice40/adffs.ys index f82da6b14..548060b66 100644 --- a/tests/ice40/adffs.ys +++ b/tests/ice40/adffs.ys @@ -4,8 +4,8 @@ flatten equiv_opt -multiclock -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd top # Constrain all select calls below inside the top module -select -assert-count 1 t:SB_DFFNSR +select -assert-count 1 t:SB_DFFNS select -assert-count 2 t:SB_DFFR -select -assert-count 1 t:SB_DFFSS -select -assert-count 1 t:SB_LUT4 -select -assert-none t:SB_DFFNSR t:SB_DFFR t:SB_DFFSS t:SB_LUT4 %% t:* %D +select -assert-count 1 t:SB_DFFS +select -assert-count 2 t:SB_LUT4 +select -assert-none t:SB_DFFNS t:SB_DFFR t:SB_DFFS t:SB_LUT4 %% t:* %D -- cgit v1.2.3 From 7f0eec8270dbef06e3e6970af20dae2d6f89f6b9 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Fri, 27 Sep 2019 11:31:55 +0200 Subject: Change order of parameters, to work on other os --- tests/ice40/run-test.sh | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'tests') diff --git a/tests/ice40/run-test.sh b/tests/ice40/run-test.sh index 2c72ca3a9..46716f9a0 100755 --- a/tests/ice40/run-test.sh +++ b/tests/ice40/run-test.sh @@ -6,7 +6,7 @@ for x in *.ys; do echo "all:: run-$x" echo "run-$x:" echo " @echo 'Running $x..'" - echo " @../../yosys -ql ${x%.ys}.log $x -w 'Yosys has only limited support for tri-state logic at the moment.'" + echo " @../../yosys -ql ${x%.ys}.log -w 'Yosys has only limited support for tri-state logic at the moment.' $x" done for s in *.sh; do if [ "$s" != "run-test.sh" ]; then -- cgit v1.2.3 From fd0e3a2c43d96ba31beede9865d5000230029994 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Marcin=20Ko=C5=9Bcielnicki?= Date: Fri, 27 Sep 2019 11:03:04 +0200 Subject: Fix _TECHMAP_REMOVEINIT_ handling. Previously, this wire was handled in the code that populated the "do or do not" techmap cache, resulting in init value removal being performed only for the first use of a given template. Fixes the problem identified in #1396. --- tests/techmap/wireinit.ys | 14 ++++++++++++-- 1 file changed, 12 insertions(+), 2 deletions(-) (limited to 'tests') diff --git a/tests/techmap/wireinit.ys b/tests/techmap/wireinit.ys index 1396839fe..89afaafb5 100644 --- a/tests/techmap/wireinit.ys +++ b/tests/techmap/wireinit.ys @@ -46,11 +46,13 @@ input clk; input d; output reg q0 = 0; output reg q1 = 1; +output reg qq0 = 0; output reg qx; always @(posedge clk) begin q0 <= d; q1 <= d; + qq0 <= q0; qx <= d; end endmodule @@ -64,16 +66,20 @@ simplemap techmap -map %map clean # Make sure the parameter was used properly. -select -assert-count 2 top/t:ffbb +select -assert-count 3 top/t:ffbb select -set ff0 top/w:q0 %ci t:ffbb %i +select -set ffq0 top/w:qq0 %ci t:ffbb %i select -set ffx top/w:qx %ci t:ffbb %i select -assert-count 1 @ff0 +select -assert-count 1 @ffq0 select -assert-count 1 @ffx select -assert-count 1 @ff0 r:INIT=1'b0 %i +select -assert-count 1 @ffq0 r:INIT=1'b0 %i select -assert-count 1 @ffx r:INIT=1'bx %i select -assert-count 0 top/w:q1 %ci t:ffbb %i # Make sure the init values are dropped from the wires iff mapping was performed. select -assert-count 0 top/w:q0 a:init %i +select -assert-count 0 top/w:qq0 a:init %i select -assert-count 1 top/w:q1 a:init=1'b1 %i select -assert-count 0 top/w:qx a:init %i @@ -84,15 +90,19 @@ simplemap techmap -map %map_noremove clean # Make sure the parameter was used properly. -select -assert-count 2 top/t:ffbb +select -assert-count 3 top/t:ffbb select -set ff0 top/w:q0 %ci t:ffbb %i +select -set ffq0 top/w:qq0 %ci t:ffbb %i select -set ffx top/w:qx %ci t:ffbb %i select -assert-count 1 @ff0 +select -assert-count 1 @ffq0 select -assert-count 1 @ffx select -assert-count 1 @ff0 r:INIT=1'b0 %i +select -assert-count 1 @ffq0 r:INIT=1'b0 %i select -assert-count 1 @ffx r:INIT=1'bx %i select -assert-count 0 top/w:q1 %ci t:ffbb %i # Make sure the init values are not dropped from the wires. select -assert-count 1 top/w:q0 a:init=1'b0 %i +select -assert-count 1 top/w:qq0 a:init=1'b0 %i select -assert-count 1 top/w:q1 a:init=1'b1 %i select -assert-count 0 top/w:qx a:init %i -- cgit v1.2.3