From a9674bd2eca5efac6e4f7b2871a01cbba80f64ec Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddieh@ece.ubc.ca>
Date: Wed, 6 Feb 2019 12:49:30 -0800
Subject: Add testcase

---
 tests/simple/dff_init.v | 10 ++++++++++
 1 file changed, 10 insertions(+)
 create mode 100644 tests/simple/dff_init.v

(limited to 'tests')

diff --git a/tests/simple/dff_init.v b/tests/simple/dff_init.v
new file mode 100644
index 000000000..aad378346
--- /dev/null
+++ b/tests/simple/dff_init.v
@@ -0,0 +1,10 @@
+module dff_test(n1, n1_inv, clk);
+  input clk;
+  (* init = 32'd0 *)
+  output n1;
+  reg n1 = 32'd0;
+  output n1_inv;
+  always @(posedge clk)
+      n1 <= n1_inv;
+  assign n1_inv = ~n1;
+endmodule
-- 
cgit v1.2.3


From 03cf1532a70d705ada69dcb8ae79ae405a86b7da Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddieh@ece.ubc.ca>
Date: Wed, 6 Feb 2019 14:02:11 -0800
Subject: Extend testcase

---
 tests/simple/dff_init.v | 36 ++++++++++++++++++++++++++++++++++--
 1 file changed, 34 insertions(+), 2 deletions(-)

(limited to 'tests')

diff --git a/tests/simple/dff_init.v b/tests/simple/dff_init.v
index aad378346..be947042e 100644
--- a/tests/simple/dff_init.v
+++ b/tests/simple/dff_init.v
@@ -1,6 +1,5 @@
-module dff_test(n1, n1_inv, clk);
+module dff0_test(n1, n1_inv, clk);
   input clk;
-  (* init = 32'd0 *)
   output n1;
   reg n1 = 32'd0;
   output n1_inv;
@@ -8,3 +7,36 @@ module dff_test(n1, n1_inv, clk);
       n1 <= n1_inv;
   assign n1_inv = ~n1;
 endmodule
+
+module dff1_test(n1, n1_inv, clk);
+  input clk;
+  (* init = 32'd1 *)
+  output n1;
+  reg n1 = 32'd1;
+  output n1_inv;
+  always @(posedge clk)
+      n1 <= n1_inv;
+  assign n1_inv = ~n1;
+endmodule
+
+module dff0a_test(n1, n1_inv, clk);
+  input clk;
+  (* init = 32'd0 *) // Must be consistent with reg initialiser below
+  output n1;
+  reg n1 = 32'd0;
+  output n1_inv;
+  always @(posedge clk)
+      n1 <= n1_inv;
+  assign n1_inv = ~n1;
+endmodule
+
+module dff1a_test(n1, n1_inv, clk);
+  input clk;
+  (* init = 32'd1 *) // Must be consistent with reg initialiser below
+  output n1;
+  reg n1 = 32'd1;
+  output n1_inv;
+  always @(posedge clk)
+      n1 <= n1_inv;
+  assign n1_inv = ~n1;
+endmodule
-- 
cgit v1.2.3


From 281f2aadcab01465f83a3f3a697eec42503e9f8b Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddieh@ece.ubc.ca>
Date: Wed, 6 Feb 2019 14:14:55 -0800
Subject: Add -B option to autotest.sh to append to backend_opts

---
 tests/tools/autotest.sh | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

(limited to 'tests')

diff --git a/tests/tools/autotest.sh b/tests/tools/autotest.sh
index d6216244f..800fa3ad5 100755
--- a/tests/tools/autotest.sh
+++ b/tests/tools/autotest.sh
@@ -22,7 +22,7 @@ if [ ! -f $toolsdir/cmp_tbdata -o $toolsdir/cmp_tbdata.c -nt $toolsdir/cmp_tbdat
 	( set -ex; ${CC:-gcc} -Wall -o $toolsdir/cmp_tbdata $toolsdir/cmp_tbdata.c; ) || exit 1
 fi
 
-while getopts xmGl:wkjvref:s:p:n:S:I: opt; do
+while getopts xmGl:wkjvref:s:p:n:S:I:B: opt; do
 	case "$opt" in
 		x)
 			use_xsim=true ;;
@@ -59,8 +59,10 @@ while getopts xmGl:wkjvref:s:p:n:S:I: opt; do
 			include_opts="$include_opts -I $OPTARG"
 			xinclude_opts="$xinclude_opts -i $OPTARG"
 			minclude_opts="$minclude_opts +incdir+$OPTARG" ;;
+        B)
+			backend_opts="$backend_opts $OPTARG" ;;
 		*)
-			echo "Usage: $0 [-x|-m] [-G] [-w] [-k] [-j] [-v] [-r] [-e] [-l libs] [-f frontend] [-s script] [-p cmdstring] [-n iters] [-S seed] [-I incdir] verilog-files\n" >&2
+			echo "Usage: $0 [-x|-m] [-G] [-w] [-k] [-j] [-v] [-r] [-e] [-l libs] [-f frontend] [-s script] [-p cmdstring] [-n iters] [-S seed] [-I incdir] [-B backend_opt] verilog-files\n" >&2
 			exit 1
 	esac
 done
-- 
cgit v1.2.3


From 115883f467cb79688ffb93c136a6ee61368765e8 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddieh@ece.ubc.ca>
Date: Wed, 6 Feb 2019 14:15:17 -0800
Subject: Add tests for simple cases using defparam

---
 tests/simple_defparam/run-test.sh | 21 +++++++++++++++++++++
 1 file changed, 21 insertions(+)
 create mode 100755 tests/simple_defparam/run-test.sh

(limited to 'tests')

diff --git a/tests/simple_defparam/run-test.sh b/tests/simple_defparam/run-test.sh
new file mode 100755
index 000000000..137e15076
--- /dev/null
+++ b/tests/simple_defparam/run-test.sh
@@ -0,0 +1,21 @@
+#!/bin/bash
+
+OPTIND=1
+seed=""    # default to no seed specified
+while getopts "S:" opt
+do
+    case "$opt" in
+	S) arg="${OPTARG#"${OPTARG%%[![:space:]]*}"}" # remove leading space
+	   seed="SEED=$arg" ;;
+    esac
+done
+shift "$((OPTIND-1))"
+
+# check for Icarus Verilog
+if ! which iverilog > /dev/null ; then
+  echo "$0: Error: Icarus Verilog 'iverilog' not found."
+  exit 1
+fi
+
+cp ../simple/*.v .
+exec ${MAKE:-make} -f ../tools/autotest.mk $seed *.v EXTRA_FLAGS="-B \"-defparam\""
-- 
cgit v1.2.3


From fc1c9aa11fbfbb1ea5b63e1830549d453ba01dfb Mon Sep 17 00:00:00 2001
From: Jim Lawson <ucbjrl@berkeley.edu>
Date: Fri, 15 Feb 2019 11:14:17 -0800
Subject: Update cells supported for verilog to FIRRTL conversion. Issue
 warning messages for missing parameterized modules and attempts to set
 initial values. Replace simple "if (cell-type)" with "else if" chain. Fix
 FIRRTL shift handling. Add support for parameterized modules, $shift,
 $shiftx. Handle default output file. Deal with no top module. Automatically
 run pmuxtree pass. Allow EXTRA_FLAGS and SEED parameters to be set in the
 environment for tests/tools/autotest.mk. Support FIRRTL regression testing in
 tests/tools/autotest.sh Add xfirrtl files to test directories to exclude
 files from FIRRTL regression tests that are known to fail.

---
 tests/asicworld/xfirrtl | 24 ++++++++++++++++++++++++
 tests/simple/xfirrtl    | 26 ++++++++++++++++++++++++++
 tests/tools/autotest.mk |  6 +++---
 tests/tools/autotest.sh | 43 +++++++++++++++++++++++++++++++++++++++----
 4 files changed, 92 insertions(+), 7 deletions(-)
 create mode 100644 tests/asicworld/xfirrtl
 create mode 100644 tests/simple/xfirrtl

(limited to 'tests')

diff --git a/tests/asicworld/xfirrtl b/tests/asicworld/xfirrtl
new file mode 100644
index 000000000..c782a2bd6
--- /dev/null
+++ b/tests/asicworld/xfirrtl
@@ -0,0 +1,24 @@
+# This file contains the names of verilog files to exclude from verilog to FIRRTL regression tests due to known failures.
+code_hdl_models_arbiter.v	error: reg rst; cannot be driven by primitives or continuous assignment.
+code_hdl_models_clk_div_45.v	yosys issue: 2nd PMUXTREE pass yields: ERROR: Negative edge clock on FF clk_div_45.$procdff$49.
+code_hdl_models_d_ff_gates.v	combinational loop
+code_hdl_models_d_latch_gates.v	combinational loop
+code_hdl_models_dff_async_reset.v	$adff
+code_hdl_models_tff_async_reset.v	$adff
+code_hdl_models_uart.v	$adff
+code_specman_switch_fabric.v	subfield assignment (bits() <= ...)
+code_tidbits_asyn_reset.v	$adff
+code_tidbits_reg_seq_example.v	$adff
+code_verilog_tutorial_always_example.v	empty module
+code_verilog_tutorial_escape_id.v	make_id issues (name begins with a digit)
+code_verilog_tutorial_explicit.v	firrtl backend bug (empty module)
+code_verilog_tutorial_first_counter.v	error: reg rst; cannot be driven by primitives or continuous assignment.
+code_verilog_tutorial_fsm_full.v	error: reg reset; cannot be driven by primitives or continuous assignment.
+code_verilog_tutorial_if_else.v	empty module (everything is under 'always @ (posedge clk)')
+[code_verilog_tutorial_n_out_primitive.v	empty module
+code_verilog_tutorial_parallel_if.v	empty module (everything is under 'always @ (posedge clk)')
+code_verilog_tutorial_simple_function.v	empty module (no hardware)
+code_verilog_tutorial_simple_if.v	empty module (everything is under 'always @ (posedge clk)')
+code_verilog_tutorial_task_global.v	empty module (everything is under 'always @ (posedge clk)')
+code_verilog_tutorial_v2k_reg.v		empty module
+code_verilog_tutorial_which_clock.v	 $adff
diff --git a/tests/simple/xfirrtl b/tests/simple/xfirrtl
new file mode 100644
index 000000000..00e89b389
--- /dev/null
+++ b/tests/simple/xfirrtl
@@ -0,0 +1,26 @@
+# This file contains the names of verilog files to exclude from verilog to FIRRTL regression tests due to known failures.
+arraycells.v	inst id[0] of
+dff_different_styles.v
+generate.v	combinational loop
+hierdefparam.v	inst id[0] of
+i2c_master_tests.v   $adff
+macros.v	drops modules
+mem2reg.v	drops modules
+mem_arst.v	$adff
+memory.v	$adff
+multiplier.v	inst id[0] of
+muxtree.v	drops modules
+omsp_dbg_uart.v	$adff
+operators.v	$pow
+paramods.v	subfield assignment (bits() <= ...)
+partsel.v	drops modules
+process.v	drops modules
+realexpr.v	drops modules
+scopes.v	original verilog issues ( -x where x isn't declared signed)
+sincos.v	$adff
+specify.v	no code (empty module generates error
+subbytes.v	$adff
+task_func.v	drops modules
+values.v	combinational loop
+vloghammer.v	combinational loop
+wreduce.v	original verilog issues ( -x where x isn't declared signed)
diff --git a/tests/tools/autotest.mk b/tests/tools/autotest.mk
index c68678929..e0f2bcdc1 100644
--- a/tests/tools/autotest.mk
+++ b/tests/tools/autotest.mk
@@ -1,7 +1,7 @@
 
-EXTRA_FLAGS=
-SEED=
-
+# Don't bother defining default values for SEED and EXTRA_FLAGS.
+# Their "natural" default values should be sufficient,
+#   and they may be overridden in the environment.
 ifneq ($(strip $(SEED)),)
 SEEDOPT=-S$(SEED)
 endif
diff --git a/tests/tools/autotest.sh b/tests/tools/autotest.sh
index d6216244f..218edf931 100755
--- a/tests/tools/autotest.sh
+++ b/tests/tools/autotest.sh
@@ -17,12 +17,18 @@ scriptfiles=""
 scriptopt=""
 toolsdir="$(cd $(dirname $0); pwd)"
 warn_iverilog_git=false
+# The following are used in verilog to firrtl regression tests.
+# Typically these will be passed as environment variables:
+#EXTRA_FLAGS="--firrtl2verilog 'java -cp /.../firrtl/utils/bin/firrtl.jar firrtl.Driver'"
+# The tests are skipped if firrtl2verilog is the empty string (the default).
+firrtl2verilog=""
+xfirrtl="../xfirrtl"
 
 if [ ! -f $toolsdir/cmp_tbdata -o $toolsdir/cmp_tbdata.c -nt $toolsdir/cmp_tbdata ]; then
 	( set -ex; ${CC:-gcc} -Wall -o $toolsdir/cmp_tbdata $toolsdir/cmp_tbdata.c; ) || exit 1
 fi
 
-while getopts xmGl:wkjvref:s:p:n:S:I: opt; do
+while getopts xmGl:wkjvref:s:p:n:S:I:-: opt; do
 	case "$opt" in
 		x)
 			use_xsim=true ;;
@@ -59,8 +65,24 @@ while getopts xmGl:wkjvref:s:p:n:S:I: opt; do
 			include_opts="$include_opts -I $OPTARG"
 			xinclude_opts="$xinclude_opts -i $OPTARG"
 			minclude_opts="$minclude_opts +incdir+$OPTARG" ;;
+		-)
+			case "${OPTARG}" in
+			    xfirrtl)
+			    	xfirrtl="${!OPTIND}"
+				OPTIND=$(( $OPTIND + 1 ))
+				;;
+			    firrtl2verilog)
+			    	firrtl2verilog="${!OPTIND}"
+				OPTIND=$(( $OPTIND + 1 ))
+				;;
+			    *)
+			    	if [ "$OPTERR" == 1 ] && [ "${optspec:0:1}" != ":" ]; then
+				    echo "Unknown option --${OPTARG}" >&2
+				fi
+				;;
+			esac;;
 		*)
-			echo "Usage: $0 [-x|-m] [-G] [-w] [-k] [-j] [-v] [-r] [-e] [-l libs] [-f frontend] [-s script] [-p cmdstring] [-n iters] [-S seed] [-I incdir] verilog-files\n" >&2
+			echo "Usage: $0 [-x|-m] [-G] [-w] [-k] [-j] [-v] [-r] [-e] [-l libs] [-f frontend] [-s script] [-p cmdstring] [-n iters] [-S seed] [-I incdir] [--xfirrtl FIRRTL test exclude file] [--firrtl2verilog command to generate verilog from firrtl] verilog-files\n" >&2
 			exit 1
 	esac
 done
@@ -109,6 +131,8 @@ do
 		fn=$(basename $fn)
 		bn=$(basename $bn)
 
+		rm -f ${bn}_ref.fir
+
 		egrep -v '^\s*`timescale' ../$fn > ${bn}_ref.v
 
 		if [ ! -f ../${bn}_tb.v ]; then
@@ -148,6 +172,13 @@ do
 		else
 			test_passes -f "$frontend $include_opts" -p "hierarchy; proc; opt; memory; opt; fsm; opt -full -fine" ${bn}_ref.v
 			test_passes -f "$frontend $include_opts" -p "hierarchy; synth -run coarse; techmap; opt; abc -dff" ${bn}_ref.v
+			if [ -n "$firrtl2verilog" ]; then
+			    if test -z "$xfirrtl" || ! grep "$fn" "$xfirrtl" ; then
+				"$toolsdir"/../../yosys -b "firrtl" -o ${bn}_ref.fir -f "$frontend $include_opts" -p "prep -nordff; proc; opt; memory; opt; fsm; opt -full -fine; pmuxtree" ${bn}_ref.v
+				$firrtl2verilog -i ${bn}_ref.fir -o ${bn}_ref.fir.v  -X verilog
+				test_passes -f "$frontend $include_opts" -p "hierarchy; proc; opt; memory; opt; fsm; opt -full -fine" ${bn}_ref.fir.v
+			    fi
+			fi
 		fi
 		touch ../${bn}.log
 	}
@@ -160,14 +191,18 @@ do
 		( set -ex; body; ) > ${bn}.err 2>&1
 	fi
 
+	did_firrtl=""
+	if [ -f ${bn}.out/${bn}_ref.fir ]; then
+	    did_firrtl="+FIRRTL "
+	fi
 	if [ -f ${bn}.log ]; then
 		mv ${bn}.err ${bn}.log
-		echo "${status_prefix}-> ok"
+		echo "${status_prefix}${did_firrtl}-> ok"
 	elif [ -f ${bn}.skip ]; then
 		mv ${bn}.err ${bn}.skip
 		echo "${status_prefix}-> skip"
 	else
-		echo "${status_prefix}-> ERROR!"
+		echo "${status_prefix}${did_firrtl}-> ERROR!"
 		if $warn_iverilog_git; then
 			echo "Note: Make sure that 'iverilog' is an up-to-date git checkout of Icarus Verilog."
 		fi
-- 
cgit v1.2.3


From 34153adef408bc226430f05d14cd4af9384359f9 Mon Sep 17 00:00:00 2001
From: Jim Lawson <ucbjrl@berkeley.edu>
Date: Fri, 15 Feb 2019 11:56:51 -0800
Subject: Append (instead of over-writing) EXTRA_FLAGS

---
 tests/asicworld/run-test.sh | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'tests')

diff --git a/tests/asicworld/run-test.sh b/tests/asicworld/run-test.sh
index d5708c456..c22ab6928 100755
--- a/tests/asicworld/run-test.sh
+++ b/tests/asicworld/run-test.sh
@@ -11,4 +11,4 @@ do
 done
 shift "$((OPTIND-1))"
 
-exec ${MAKE:-make} -f ../tools/autotest.mk $seed EXTRA_FLAGS="-e" *.v
+exec ${MAKE:-make} -f ../tools/autotest.mk $seed EXTRA_FLAGS+="-e" *.v
-- 
cgit v1.2.3


From 5c4a72c43ef61420b4b099d87949b0fdba0f4b55 Mon Sep 17 00:00:00 2001
From: Jim Lawson <ucbjrl@berkeley.edu>
Date: Tue, 19 Feb 2019 14:35:15 -0800
Subject: Fix normal (non-array) hierarchy -auto-top. Add simple test.

---
 tests/various/hierarchy.sh | 56 ++++++++++++++++++++++++++++++++++++++++++++++
 tests/various/run-test.sh  | 10 ++++++++-
 2 files changed, 65 insertions(+), 1 deletion(-)
 create mode 100644 tests/various/hierarchy.sh

(limited to 'tests')

diff --git a/tests/various/hierarchy.sh b/tests/various/hierarchy.sh
new file mode 100644
index 000000000..dcb4dc056
--- /dev/null
+++ b/tests/various/hierarchy.sh
@@ -0,0 +1,56 @@
+#!/usr/bin/env bash
+# Simple test of hierarchy -auto-top.
+
+set -e
+
+../../yosys -q -s - <<- EOY 2>&1 | grep "Automatically selected TOP as design top module"
+  read_verilog << EOV
+    module TOP(a, y);
+      input a;
+      output [31:0] y;
+
+      aoi12 p [31:0] (a, y);
+    endmodule
+
+    module aoi12(a, y);
+      input a;
+      output y;
+      assign y = ~a;
+    endmodule
+  EOV
+  hierarchy -auto-top
+EOY
+
+../../yosys -q -s - <<- EOY 2>&1 | grep "Automatically selected TOP as design top module"
+  read_verilog << EOV
+    module aoi12(a, y);
+      input a;
+      output y;
+      assign y = ~a;
+    endmodule
+
+    module TOP(a, y);
+      input a;
+      output [31:0] y;
+
+      aoi12 foo (a, y);
+    endmodule
+  EOV
+  hierarchy -auto-top
+EOY
+
+../../yosys -q -s - <<- EOY 2>&1 | grep "Automatically selected noTop as design top module."
+  read_verilog << EOV
+    module aoi12(a, y);
+      input a;
+      output y;
+      assign y = ~a;
+    endmodule
+
+    module noTop(a, y);
+      input a;
+      output [31:0] y;
+    endmodule
+  EOV
+  hierarchy -auto-top
+EOY
diff --git a/tests/various/run-test.sh b/tests/various/run-test.sh
index 67e1beb23..7cd1a8650 100755
--- a/tests/various/run-test.sh
+++ b/tests/various/run-test.sh
@@ -1,6 +1,14 @@
-#!/bin/bash
+#!/usr/bin/env bash
 set -e
 for x in *.ys; do
 	echo "Running $x.."
 	../../yosys -ql ${x%.ys}.log $x
 done
+# Run any .sh files in this directory (with the exception of the file - run-test.sh
+shell_tests=$(echo *.sh | sed -e 's/run-test.sh//')
+if [ "$shell_tests" ]; then
+    for s in $shell_tests; do
+        echo "Running $s.."
+        bash $s >& ${s%.sh}.log
+    done
+fi
-- 
cgit v1.2.3


From 4035ec8933cd187670788fb6eca5cefa80fe7170 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddieh@ece.ubc.ca>
Date: Wed, 20 Feb 2019 15:45:45 -0800
Subject: Remove simple_defparam tests

---
 tests/simple_defparam/run-test.sh | 21 ---------------------
 1 file changed, 21 deletions(-)
 delete mode 100755 tests/simple_defparam/run-test.sh

(limited to 'tests')

diff --git a/tests/simple_defparam/run-test.sh b/tests/simple_defparam/run-test.sh
deleted file mode 100755
index 137e15076..000000000
--- a/tests/simple_defparam/run-test.sh
+++ /dev/null
@@ -1,21 +0,0 @@
-#!/bin/bash
-
-OPTIND=1
-seed=""    # default to no seed specified
-while getopts "S:" opt
-do
-    case "$opt" in
-	S) arg="${OPTARG#"${OPTARG%%[![:space:]]*}"}" # remove leading space
-	   seed="SEED=$arg" ;;
-    esac
-done
-shift "$((OPTIND-1))"
-
-# check for Icarus Verilog
-if ! which iverilog > /dev/null ; then
-  echo "$0: Error: Icarus Verilog 'iverilog' not found."
-  exit 1
-fi
-
-cp ../simple/*.v .
-exec ${MAKE:-make} -f ../tools/autotest.mk $seed *.v EXTRA_FLAGS="-B \"-defparam\""
-- 
cgit v1.2.3


From 8e789da74c6702ededc668e3dbd899de8d0c2821 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddieh@ece.ubc.ca>
Date: Thu, 21 Feb 2019 09:22:29 -0800
Subject: Revert "Add -B option to autotest.sh to append to backend_opts"

This reverts commit 281f2aadcab01465f83a3f3a697eec42503e9f8b.
---
 tests/tools/autotest.sh | 6 ++----
 1 file changed, 2 insertions(+), 4 deletions(-)

(limited to 'tests')

diff --git a/tests/tools/autotest.sh b/tests/tools/autotest.sh
index 6fdd1e80a..218edf931 100755
--- a/tests/tools/autotest.sh
+++ b/tests/tools/autotest.sh
@@ -28,7 +28,7 @@ if [ ! -f $toolsdir/cmp_tbdata -o $toolsdir/cmp_tbdata.c -nt $toolsdir/cmp_tbdat
 	( set -ex; ${CC:-gcc} -Wall -o $toolsdir/cmp_tbdata $toolsdir/cmp_tbdata.c; ) || exit 1
 fi
 
-while getopts xmGl:wkjvref:s:p:n:S:I:B:-: opt; do
+while getopts xmGl:wkjvref:s:p:n:S:I:-: opt; do
 	case "$opt" in
 		x)
 			use_xsim=true ;;
@@ -65,8 +65,6 @@ while getopts xmGl:wkjvref:s:p:n:S:I:B:-: opt; do
 			include_opts="$include_opts -I $OPTARG"
 			xinclude_opts="$xinclude_opts -i $OPTARG"
 			minclude_opts="$minclude_opts +incdir+$OPTARG" ;;
-        B)
-			backend_opts="$backend_opts $OPTARG" ;;
 		-)
 			case "${OPTARG}" in
 			    xfirrtl)
@@ -84,7 +82,7 @@ while getopts xmGl:wkjvref:s:p:n:S:I:B:-: opt; do
 				;;
 			esac;;
 		*)
-			echo "Usage: $0 [-x|-m] [-G] [-w] [-k] [-j] [-v] [-r] [-e] [-l libs] [-f frontend] [-s script] [-p cmdstring] [-n iters] [-S seed] [-I incdir] [-B backend_opt] [--xfirrtl FIRRTL test exclude file] [--firrtl2verilog command to generate verilog from firrtl] verilog-files\n" >&2
+			echo "Usage: $0 [-x|-m] [-G] [-w] [-k] [-j] [-v] [-r] [-e] [-l libs] [-f frontend] [-s script] [-p cmdstring] [-n iters] [-S seed] [-I incdir] [--xfirrtl FIRRTL test exclude file] [--firrtl2verilog command to generate verilog from firrtl] verilog-files\n" >&2
 			exit 1
 	esac
 done
-- 
cgit v1.2.3


From 25680f6a078bb32f157bd580705656496717bafb Mon Sep 17 00:00:00 2001
From: Keith Rothman <537074+litghost@users.noreply.github.com>
Date: Fri, 22 Feb 2019 10:28:28 -0800
Subject: Fix WREDUCE on FF not fixing ARST_VALUE parameter.

Adds test case that fails without code change.

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
---
 tests/opt/opt_ff.v  | 21 +++++++++++++++++++++
 tests/opt/opt_ff.ys |  3 +++
 2 files changed, 24 insertions(+)
 create mode 100644 tests/opt/opt_ff.v
 create mode 100644 tests/opt/opt_ff.ys

(limited to 'tests')

diff --git a/tests/opt/opt_ff.v b/tests/opt/opt_ff.v
new file mode 100644
index 000000000..a01b64b61
--- /dev/null
+++ b/tests/opt/opt_ff.v
@@ -0,0 +1,21 @@
+module top(
+    input clk,
+    input rst,
+    input [2:0] a,
+    output [1:0] b
+);
+    reg [2:0] b_reg;
+    initial begin
+        b_reg <= 3'b0;
+    end
+
+    assign b = b_reg[1:0];
+    always @(posedge clk or posedge rst) begin
+        if(rst) begin
+            b_reg <= 3'b0;
+        end else begin
+            b_reg <= a;
+        end
+    end
+endmodule
+
diff --git a/tests/opt/opt_ff.ys b/tests/opt/opt_ff.ys
new file mode 100644
index 000000000..704c7acf3
--- /dev/null
+++ b/tests/opt/opt_ff.ys
@@ -0,0 +1,3 @@
+read_verilog opt_ff.v
+synth_ice40
+ice40_unlut
-- 
cgit v1.2.3


From 71bcc4c644b0dafa760ff8b6d7bd1109836be621 Mon Sep 17 00:00:00 2001
From: Jim Lawson <ucbjrl@berkeley.edu>
Date: Fri, 22 Feb 2019 16:06:10 -0800
Subject: Address requested changes - don't require non-$ name. Suppress
 warning if name does begin with a `$`. Fix hierachy tests so they have
 something to grep. Announce hierarchy test types.

---
 tests/various/hierarchy.sh | 9 ++++++---
 tests/various/run-test.sh  | 2 +-
 2 files changed, 7 insertions(+), 4 deletions(-)

(limited to 'tests')

diff --git a/tests/various/hierarchy.sh b/tests/various/hierarchy.sh
index dcb4dc056..d33a247be 100644
--- a/tests/various/hierarchy.sh
+++ b/tests/various/hierarchy.sh
@@ -3,7 +3,8 @@
 
 set -e
 
-../../yosys -q -s - <<- EOY 2>&1 | grep "Automatically selected TOP as design top module"
+echo -n "  TOP first - "
+../../yosys -s - <<- EOY | grep "Automatically selected TOP as design top module"
   read_verilog << EOV
     module TOP(a, y);
       input a;
@@ -21,7 +22,8 @@ set -e
   hierarchy -auto-top
 EOY
 
-../../yosys -q -s - <<- EOY 2>&1 | grep "Automatically selected TOP as design top module"
+echo -n "  TOP last - "
+../../yosys -s - <<- EOY | grep "Automatically selected TOP as design top module"
   read_verilog << EOV
     module aoi12(a, y);
       input a;
@@ -39,7 +41,8 @@ EOY
   hierarchy -auto-top
 EOY
 
-../../yosys -q -s - <<- EOY 2>&1 | grep "Automatically selected noTop as design top module."
+echo -n "  no explicit top - "
+../../yosys -s - <<- EOY | grep "Automatically selected noTop as design top module."
   read_verilog << EOV
     module aoi12(a, y);
       input a;
diff --git a/tests/various/run-test.sh b/tests/various/run-test.sh
index 7cd1a8650..d49553ede 100755
--- a/tests/various/run-test.sh
+++ b/tests/various/run-test.sh
@@ -9,6 +9,6 @@ shell_tests=$(echo *.sh | sed -e 's/run-test.sh//')
 if [ "$shell_tests" ]; then
     for s in $shell_tests; do
         echo "Running $s.."
-        bash $s >& ${s%.sh}.log
+        bash $s
     done
 fi
-- 
cgit v1.2.3


From 1816fe06af9ab2c50bd293dc10359238acc88f12 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Sun, 24 Feb 2019 20:09:41 +0100
Subject: Fix handling of defparam for when default_nettype is none

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 tests/simple/hierdefparam.v | 2 ++
 1 file changed, 2 insertions(+)

(limited to 'tests')

diff --git a/tests/simple/hierdefparam.v b/tests/simple/hierdefparam.v
index ff92c38bd..c9368ca7a 100644
--- a/tests/simple/hierdefparam.v
+++ b/tests/simple/hierdefparam.v
@@ -1,3 +1,5 @@
+`default_nettype none
+
 module hierdefparam_top(input [7:0] A, output [7:0] Y);
   generate begin:foo
     hierdefparam_a mod_a(.A(A), .Y(Y));
-- 
cgit v1.2.3