From 81964d6d6f09050858886d5e0c9c6e20f4f80a53 Mon Sep 17 00:00:00 2001 From: Patrick Urban Date: Mon, 25 Oct 2021 11:10:00 +0200 Subject: synth_gatemate: Update pass * remove `write_edif` and `write_blif` options * remove redundant `abc` call before muxcover * update style --- tests/arch/gatemate/mux.ys | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) (limited to 'tests') diff --git a/tests/arch/gatemate/mux.ys b/tests/arch/gatemate/mux.ys index 28396482b..320ff33d7 100644 --- a/tests/arch/gatemate/mux.ys +++ b/tests/arch/gatemate/mux.ys @@ -7,8 +7,10 @@ proc equiv_opt -assert -map +/gatemate/cells_sim.v synth_gatemate -noiopad # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd mux4 # Constrain all select calls below inside the top module -select -assert-count 1 t:CC_MX4 -select -assert-none t:CC_MX4 %% t:* %D +select -assert-max 1 t:CC_LUT2 +select -assert-max 2 t:CC_LUT4 +select -assert-max 1 t:CC_MX2 +select -assert-none t:CC_LUT2 t:CC_LUT4 t:CC_MX2 %% t:* %D design -load read hierarchy -top mux8 @@ -16,5 +18,7 @@ proc equiv_opt -assert -map +/gatemate/cells_sim.v synth_gatemate -noiopad # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd mux8 # Constrain all select calls below inside the top module -select -assert-count 1 t:CC_MX8 -select -assert-none t:CC_MX8 %% t:* %D +select -assert-max 1 t:CC_LUT3 +select -assert-max 5 t:CC_LUT4 +select -assert-max 1 t:CC_MX2 +select -assert-none t:CC_LUT3 t:CC_LUT4 t:CC_MX2 %% t:* %D -- cgit v1.2.3