From 7cfdf4ffa7698fa40aae401c2b8b159a6e37011a Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Wed, 12 Feb 2020 12:16:01 -0800 Subject: verilog: fix $specify3 check --- tests/various/specify.v | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'tests') diff --git a/tests/various/specify.v b/tests/various/specify.v index 5d44d78f7..e4dd132f1 100644 --- a/tests/various/specify.v +++ b/tests/various/specify.v @@ -37,3 +37,10 @@ specify (posedge clk *> (q +: d)) = (3,1); endspecify endmodule + +module test3(input clk, input [1:0] d, output [1:0] q); +specify + (posedge clk => (q +: d)) = (3,1); + (posedge clk *> (q +: d)) = (3,1); +endspecify +endmodule -- cgit v1.2.3