From 75335344295a51c11bb72e0add10e365a34ccc1d Mon Sep 17 00:00:00 2001
From: Kamil Rakoczy <krakoczy@antmicro.com>
Date: Thu, 11 Feb 2021 12:53:07 +0100
Subject: Add missing is_signed to type_atom

Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
---
 tests/verilog/atom_type_signedness.ys | 19 +++++++++++++++++++
 1 file changed, 19 insertions(+)
 create mode 100644 tests/verilog/atom_type_signedness.ys

(limited to 'tests')

diff --git a/tests/verilog/atom_type_signedness.ys b/tests/verilog/atom_type_signedness.ys
new file mode 100644
index 000000000..22bbe6efc
--- /dev/null
+++ b/tests/verilog/atom_type_signedness.ys
@@ -0,0 +1,19 @@
+read_verilog -dump_ast1 -dump_ast2 -sv <<EOT
+module dut();
+
+enum integer  { uInteger  = -10 } a;
+enum int      { uInt      = -11 } b;
+enum shortint { uShortInt = -12 } c;
+enum byte     { uByte     = -13 } d;
+
+always_comb begin
+  assert(-10 == uInteger);
+  assert(-11 == uInt);
+  assert(-12 == uShortInt);
+  assert(-13 == uByte);
+end
+endmodule
+EOT
+hierarchy; proc; opt
+select -module dut
+sat -verify -seq 1 -tempinduct -prove-asserts -show-all
-- 
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