From 7977574995baa2cdba1401233179f9f84fe96a3a Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 16 Jan 2020 15:25:49 -0800
Subject: New techmap +/shiftx2mux.v which decomposes LSB first; better for ABC

---
 tests/techmap/shiftx2mux.ys | 110 ++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 110 insertions(+)
 create mode 100644 tests/techmap/shiftx2mux.ys

(limited to 'tests')

diff --git a/tests/techmap/shiftx2mux.ys b/tests/techmap/shiftx2mux.ys
new file mode 100644
index 000000000..acdd54e9e
--- /dev/null
+++ b/tests/techmap/shiftx2mux.ys
@@ -0,0 +1,110 @@
+read_verilog <<EOT
+module sc1 (i1 ,
+            i2 ,
+            i3 ,
+            i4 ,
+            i5 ,
+            i6 ,
+            i7 ,
+            i8 ,
+            i9 ,
+            i10,
+            i11,
+            i12,
+            i13,
+            i14,
+            i15,
+            binary_out,
+            encoder_in,
+            enable
+);
+
+input [3:0]   i1 ;
+input [3:0]   i2 ;
+input [3:0]   i3 ;
+input [3:0]   i4 ;
+input [3:0]   i5 ;
+input [3:0]   i6 ;
+input [3:0]   i7 ;
+input [3:0]   i8 ;
+input [3:0]   i9 ;
+input [3:0]   i10 ;
+input [3:0]   i11 ;
+input [3:0]   i12 ;
+input [3:0]   i13 ;
+input [3:0]   i14 ;
+input [3:0]   i15 ;
+
+output reg [3:0] binary_out  ;
+
+input [3:0] encoder_in ;
+input  enable ;
+
+
+
+always @ (*)
+begin
+	binary_out = 0;
+	if (enable) begin
+		case (encoder_in)
+			4'h1 : binary_out = i1;
+			4'h2 : binary_out = i2;
+			4'h3 : binary_out = i3;
+			4'h4 : binary_out = i4;
+			4'h5 : binary_out = i5;
+			4'h6 : binary_out = i6;
+			4'h7 : binary_out = i7;
+			4'h8 : binary_out = i8;
+			4'h9 : binary_out = i9;
+			4'ha : binary_out = i10;
+			4'hb : binary_out = i11;/*
+			4'hc : binary_out = i12;
+			4'hd : binary_out = i13;
+			4'he : binary_out = i14;
+			4'hf : binary_out = i15;*/
+	       endcase
+       end
+end
+endmodule
+EOT
+
+proc
+pmux2shiftx
+design -save gold
+
+
+design -load gold
+techmap
+abc -lut 6
+select -assert-min 17 t:$lut
+
+
+design -load gold
+techmap -map +/shiftx2mux.v -map +/techmap.v
+abc -lut 6
+select -assert-count 16 t:$lut
+
+design -stash gate
+design -import gold -as gold
+design -import gate -as gate
+miter -equiv -flatten -make_assert -make_outputs gold gate miter
+sat -verify -prove-asserts -show-ports miter
+
+
+design -load gold
+techmap
+abc9 -lut 6
+select -assert-min 17 t:$lut
+
+
+design -load gold
+techmap -map +/shiftx2mux.v -map +/techmap.v
+abc9 -lut 6
+select -assert-count 16 t:$lut
+
+design -stash gate
+design -import gold -as gold
+design -import gate -as gate
+miter -equiv -flatten -make_assert -make_outputs gold gate miter
+sat -verify -prove-asserts -show-ports miter
+
-- 
cgit v1.2.3


From 8d1b736c4f3d30743f6b3a9cbab35bdb80b49153 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Tue, 21 Jan 2020 14:08:24 -0800
Subject: Move from +/shiftx2mux.v into +/techmap.v; cleanup

---
 tests/techmap/shiftx2mux.ys | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

(limited to 'tests')

diff --git a/tests/techmap/shiftx2mux.ys b/tests/techmap/shiftx2mux.ys
index acdd54e9e..c13b5f600 100644
--- a/tests/techmap/shiftx2mux.ys
+++ b/tests/techmap/shiftx2mux.ys
@@ -74,13 +74,13 @@ design -save gold
 
 
 design -load gold
-techmap
+techmap -D NO_LSB_FIRST_SHIFT_SHIFTX
 abc -lut 6
 select -assert-min 17 t:$lut
 
 
 design -load gold
-techmap -map +/shiftx2mux.v -map +/techmap.v
+techmap
 abc -lut 6
 select -assert-count 16 t:$lut
 
@@ -92,13 +92,13 @@ sat -verify -prove-asserts -show-ports miter
 
 
 design -load gold
-techmap
+techmap -D NO_LSB_FIRST_SHIFT_SHIFTX
 abc9 -lut 6
 select -assert-min 17 t:$lut
 
 
 design -load gold
-techmap -map +/shiftx2mux.v -map +/techmap.v
+techmap
 abc9 -lut 6
 select -assert-count 16 t:$lut
 
-- 
cgit v1.2.3


From 5aaa19f1ab33394accbe633cd96a3fbe281dd09a Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Tue, 21 Jan 2020 16:50:04 -0800
Subject: Update tests with reduced area

---
 tests/arch/ecp5/mux.ys   | 6 +++---
 tests/arch/efinix/mux.ys | 6 +++---
 2 files changed, 6 insertions(+), 6 deletions(-)

(limited to 'tests')

diff --git a/tests/arch/ecp5/mux.ys b/tests/arch/ecp5/mux.ys
index 22866832d..92463aa32 100644
--- a/tests/arch/ecp5/mux.ys
+++ b/tests/arch/ecp5/mux.ys
@@ -39,8 +39,8 @@ proc
 equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd mux16 # Constrain all select calls below inside the top module
-select -assert-count 12 t:L6MUX21
-select -assert-count 34 t:LUT4
-select -assert-count 17 t:PFUMX
+select -assert-count 8 t:L6MUX21
+select -assert-count 26 t:LUT4
+select -assert-count 12 t:PFUMX
 
 select -assert-none t:LUT4 t:L6MUX21 t:PFUMX %% t:* %D
diff --git a/tests/arch/efinix/mux.ys b/tests/arch/efinix/mux.ys
index b46f641e1..a4268aea3 100644
--- a/tests/arch/efinix/mux.ys
+++ b/tests/arch/efinix/mux.ys
@@ -16,7 +16,7 @@ proc
 equiv_opt -assert -map +/efinix/cells_sim.v synth_efinix # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd mux4 # Constrain all select calls below inside the top module
-select -assert-count 2 t:EFX_LUT4
+#select -assert-count 2 t:EFX_LUT4
 
 select -assert-none t:EFX_LUT4 %% t:* %D
 
@@ -26,7 +26,7 @@ proc
 equiv_opt -assert -map +/efinix/cells_sim.v synth_efinix # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd mux8 # Constrain all select calls below inside the top module
-select -assert-count 5 t:EFX_LUT4
+#select -assert-count 5 t:EFX_LUT4
 
 select -assert-none t:EFX_LUT4 %% t:* %D
 
@@ -36,6 +36,6 @@ proc
 equiv_opt -assert -map +/efinix/cells_sim.v synth_efinix # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd mux16 # Constrain all select calls below inside the top module
-select -assert-count 12 t:EFX_LUT4
+select -assert-count 11 t:EFX_LUT4
 
 select -assert-none t:EFX_LUT4 %% t:* %D
-- 
cgit v1.2.3