From 6b5e65919a6ec14d4bfc85f80d1f7492d5b86c16 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Mon, 26 Aug 2019 17:52:57 -0700 Subject: Revert "In sat: 'x' in init attr should not override constant" This reverts commit 2b37a093e95036b267481b2dae2046278eef4040. --- tests/sat/initval.v | 4 ---- tests/sat/initval.ys | 2 +- 2 files changed, 1 insertion(+), 5 deletions(-) (limited to 'tests') diff --git a/tests/sat/initval.v b/tests/sat/initval.v index d46ccae48..5b661f8d6 100644 --- a/tests/sat/initval.v +++ b/tests/sat/initval.v @@ -1,7 +1,6 @@ module test(input clk, input [3:0] bar, output [3:0] foo); reg [3:0] foo = 0; reg [3:0] last_bar = 0; - reg [3:0] asdf = 4'b1xxx; always @* foo[1:0] <= bar[1:0]; @@ -12,8 +11,5 @@ module test(input clk, input [3:0] bar, output [3:0] foo); always @(posedge clk) last_bar <= bar; - always @* - asdf[2:0] <= 3'b111; - assert property (foo == {last_bar[3:2], bar[1:0]}); endmodule diff --git a/tests/sat/initval.ys b/tests/sat/initval.ys index 3d88aa971..2079d2f34 100644 --- a/tests/sat/initval.ys +++ b/tests/sat/initval.ys @@ -1,4 +1,4 @@ read_verilog -sv initval.v -proc; +proc;; sat -seq 10 -prove-asserts -- cgit v1.2.3