From 6b58c1820c7bbacb4730af40e10592823b0eb15c Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 13 Feb 2020 13:27:15 -0800
Subject: verilog: improve specify support when not in -specify mode

---
 tests/various/specify.v  | 2 --
 tests/various/specify.ys | 2 +-
 2 files changed, 1 insertion(+), 3 deletions(-)

(limited to 'tests')

diff --git a/tests/various/specify.v b/tests/various/specify.v
index aa8aca4bc..5655ded21 100644
--- a/tests/various/specify.v
+++ b/tests/various/specify.v
@@ -7,11 +7,9 @@ module test (
 		if (EN) Q <= D;
 
 	specify
-`ifndef SKIP_UNSUPPORTED_IGN_PARSER_CONSTRUCTS
 		if (EN) (posedge CLK *> (Q : D)) = (1, 2:3:4);
 		$setup(D, posedge CLK &&& EN, 5);
 		$hold(posedge CLK, D &&& EN, 6);
-`endif
 	endspecify
 endmodule
 
diff --git a/tests/various/specify.ys b/tests/various/specify.ys
index 00597e1e2..a2b6038e4 100644
--- a/tests/various/specify.ys
+++ b/tests/various/specify.ys
@@ -55,4 +55,4 @@ equiv_induct -seq 5
 equiv_status -assert
 design -reset
 
-read_verilog -DSKIP_UNSUPPORTED_IGN_PARSER_CONSTRUCTS specify.v
+read_verilog specify.v
-- 
cgit v1.2.3