From 6a163b5ddd378ba847054ad9226af8ca569c977a Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 17 Jan 2020 17:07:03 -0800
Subject: xilinx_dsp: another typo; move xilinx specific test

---
 tests/arch/xilinx/bug1462.ys | 11 +++++++++++
 tests/various/bug1462.ys     | 11 -----------
 2 files changed, 11 insertions(+), 11 deletions(-)
 create mode 100644 tests/arch/xilinx/bug1462.ys
 delete mode 100644 tests/various/bug1462.ys

(limited to 'tests')

diff --git a/tests/arch/xilinx/bug1462.ys b/tests/arch/xilinx/bug1462.ys
new file mode 100644
index 000000000..15cab5121
--- /dev/null
+++ b/tests/arch/xilinx/bug1462.ys
@@ -0,0 +1,11 @@
+read_verilog << EOF
+module top(...);
+input wire [31:0] A;
+output wire [31:0] P;
+
+assign P = A * 32'h12300000;
+
+endmodule
+EOF
+
+synth_xilinx
diff --git a/tests/various/bug1462.ys b/tests/various/bug1462.ys
deleted file mode 100644
index 15cab5121..000000000
--- a/tests/various/bug1462.ys
+++ /dev/null
@@ -1,11 +0,0 @@
-read_verilog << EOF
-module top(...);
-input wire [31:0] A;
-output wire [31:0] P;
-
-assign P = A * 32'h12300000;
-
-endmodule
-EOF
-
-synth_xilinx
-- 
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