From 07c4a7d4388cdacaa15512dd2f6f0f9e9fcb31f5 Mon Sep 17 00:00:00 2001 From: Bogdan Vukobratovic Date: Fri, 26 Jul 2019 11:36:48 +0200 Subject: Implement opt_share This pass identifies arithmetic operators that share an operand and whose results are used in mutually exclusive cases controlled by a multiplexer, and merges them together by multiplexing the other operands --- tests/opt/opt_share_cat.v | 15 +++++++++++++++ tests/opt/opt_share_cat.ys | 9 +++++++++ tests/opt/opt_share_mux_tree.v | 19 +++++++++++++++++++ tests/opt/opt_share_mux_tree.ys | 10 ++++++++++ 4 files changed, 53 insertions(+) create mode 100644 tests/opt/opt_share_cat.v create mode 100644 tests/opt/opt_share_cat.ys create mode 100644 tests/opt/opt_share_mux_tree.v create mode 100644 tests/opt/opt_share_mux_tree.ys (limited to 'tests') diff --git a/tests/opt/opt_share_cat.v b/tests/opt/opt_share_cat.v new file mode 100644 index 000000000..c32073360 --- /dev/null +++ b/tests/opt/opt_share_cat.v @@ -0,0 +1,15 @@ +module add_sub( + input [15:0] a, + input [15:0] b, + input [15:0] c, + input [15:0] d, + input sel, + output [63:0] res, + ); + + reg [31: 0] cat1 = {a+b, c+d}; + reg [31: 0] cat2 = {a-b, c-d}; + + assign res = {b, sel ? cat1 : cat2, a}; + +endmodule diff --git a/tests/opt/opt_share_cat.ys b/tests/opt/opt_share_cat.ys new file mode 100644 index 000000000..c3f2f5a2f --- /dev/null +++ b/tests/opt/opt_share_cat.ys @@ -0,0 +1,9 @@ +read_verilog opt_share_cat.v +prep -flatten +opt +pmuxtree +opt_share +opt_clean + +select -assert-count 2 t:$sub +select -assert-count 0 t:$add diff --git a/tests/opt/opt_share_mux_tree.v b/tests/opt/opt_share_mux_tree.v new file mode 100644 index 000000000..807ed2978 --- /dev/null +++ b/tests/opt/opt_share_mux_tree.v @@ -0,0 +1,19 @@ +module add_sub( + input [15:0] a, + input [15:0] b, + input [15:0] c, + input [1:0] sel, + output reg [15:0] res + ); + + + always @* begin + case(sel) + 0: res = a + b; + 1: res = a - b; + 2: res = a + c; + default: res = 16'bx; + endcase + end + +endmodule diff --git a/tests/opt/opt_share_mux_tree.ys b/tests/opt/opt_share_mux_tree.ys new file mode 100644 index 000000000..94d6aa7d2 --- /dev/null +++ b/tests/opt/opt_share_mux_tree.ys @@ -0,0 +1,10 @@ +read_verilog opt_share_mux_tree.v +prep -flatten +opt +pmuxtree +opt_share; +opt_share; +opt_clean + +select -assert-count 1 t:$add +select -assert-count 0 t:$sub -- cgit v1.2.3 From c075486c59155d16ed278922a3752366a95246ff Mon Sep 17 00:00:00 2001 From: Bogdan Vukobratovic Date: Sun, 28 Jul 2019 16:03:54 +0200 Subject: Reimplement opt_share to work on $alu and $pmux --- tests/opt/opt_share_add_sub.v | 10 ++++++++++ tests/opt/opt_share_add_sub.ys | 13 +++++++++++++ tests/opt/opt_share_cat.v | 2 +- tests/opt/opt_share_cat.ys | 18 +++++++++++------- tests/opt/opt_share_cat_multiuser.v | 22 ++++++++++++++++++++++ tests/opt/opt_share_cat_multiuser.ys | 13 +++++++++++++ tests/opt/opt_share_diff_port_widths.v | 21 +++++++++++++++++++++ tests/opt/opt_share_diff_port_widths.ys | 13 +++++++++++++ tests/opt/opt_share_extend.v | 19 +++++++++++++++++++ tests/opt/opt_share_extend.ys | 13 +++++++++++++ tests/opt/opt_share_large_pmux_cat.v | 22 ++++++++++++++++++++++ tests/opt/opt_share_large_pmux_cat.ys | 13 +++++++++++++ tests/opt/opt_share_large_pmux_cat_multipart.v | 25 +++++++++++++++++++++++++ tests/opt/opt_share_large_pmux_cat_multipart.ys | 15 +++++++++++++++ tests/opt/opt_share_large_pmux_multipart.v | 24 ++++++++++++++++++++++++ tests/opt/opt_share_large_pmux_multipart.ys | 13 +++++++++++++ tests/opt/opt_share_large_pmux_part.v | 22 ++++++++++++++++++++++ tests/opt/opt_share_large_pmux_part.ys | 13 +++++++++++++ tests/opt/opt_share_mux_tree.v | 2 +- tests/opt/opt_share_mux_tree.ys | 19 +++++++++++-------- 20 files changed, 295 insertions(+), 17 deletions(-) create mode 100644 tests/opt/opt_share_add_sub.v create mode 100644 tests/opt/opt_share_add_sub.ys create mode 100644 tests/opt/opt_share_cat_multiuser.v create mode 100644 tests/opt/opt_share_cat_multiuser.ys create mode 100644 tests/opt/opt_share_diff_port_widths.v create mode 100644 tests/opt/opt_share_diff_port_widths.ys create mode 100644 tests/opt/opt_share_extend.v create mode 100644 tests/opt/opt_share_extend.ys create mode 100644 tests/opt/opt_share_large_pmux_cat.v create mode 100644 tests/opt/opt_share_large_pmux_cat.ys create mode 100644 tests/opt/opt_share_large_pmux_cat_multipart.v create mode 100644 tests/opt/opt_share_large_pmux_cat_multipart.ys create mode 100644 tests/opt/opt_share_large_pmux_multipart.v create mode 100644 tests/opt/opt_share_large_pmux_multipart.ys create mode 100644 tests/opt/opt_share_large_pmux_part.v create mode 100644 tests/opt/opt_share_large_pmux_part.ys (limited to 'tests') diff --git a/tests/opt/opt_share_add_sub.v b/tests/opt/opt_share_add_sub.v new file mode 100644 index 000000000..30e093a39 --- /dev/null +++ b/tests/opt/opt_share_add_sub.v @@ -0,0 +1,10 @@ +module opt_share_test( + input [15:0] a, + input [15:0] b, + input sel, + output [15:0] res, + ); + + assign res = {sel ? a + b : a - b}; + +endmodule diff --git a/tests/opt/opt_share_add_sub.ys b/tests/opt/opt_share_add_sub.ys new file mode 100644 index 000000000..4a5406791 --- /dev/null +++ b/tests/opt/opt_share_add_sub.ys @@ -0,0 +1,13 @@ +read_verilog opt_share_add_sub.v +proc;; +copy opt_share_test merged + +alumacc merged +opt merged +opt_share merged +opt_clean merged + +miter -equiv -flatten -ignore_gold_x -make_outputs -make_outcmp opt_share_test merged miter +sat -set-def-inputs -verify -prove trigger 0 -show-inputs -show-outputs miter + +select -assert-count 1 -module merged t:$alu diff --git a/tests/opt/opt_share_cat.v b/tests/opt/opt_share_cat.v index c32073360..605dcfe59 100644 --- a/tests/opt/opt_share_cat.v +++ b/tests/opt/opt_share_cat.v @@ -1,4 +1,4 @@ -module add_sub( +module opt_share_test( input [15:0] a, input [15:0] b, input [15:0] c, diff --git a/tests/opt/opt_share_cat.ys b/tests/opt/opt_share_cat.ys index c3f2f5a2f..7de69bfde 100644 --- a/tests/opt/opt_share_cat.ys +++ b/tests/opt/opt_share_cat.ys @@ -1,9 +1,13 @@ read_verilog opt_share_cat.v -prep -flatten -opt -pmuxtree -opt_share -opt_clean +proc;; +copy opt_share_test merged -select -assert-count 2 t:$sub -select -assert-count 0 t:$add +alumacc merged +opt merged +opt_share merged +opt_clean merged + +miter -equiv -flatten -ignore_gold_x -make_outputs -make_outcmp opt_share_test merged miter +sat -set-def-inputs -verify -prove trigger 0 -show-inputs -show-outputs miter + +select -assert-count 2 -module merged t:$alu diff --git a/tests/opt/opt_share_cat_multiuser.v b/tests/opt/opt_share_cat_multiuser.v new file mode 100644 index 000000000..9ac0ceec8 --- /dev/null +++ b/tests/opt/opt_share_cat_multiuser.v @@ -0,0 +1,22 @@ +module opt_share_test( + input [15:0] a, + input [15:0] b, + input [15:0] c, + input [15:0] d, + input sel, + output reg [47:0] res, + ); + + wire [15:0] add_res = a+b; + wire [15:0] sub_res = a-b; + wire [31: 0] cat1 = {add_res, c+d}; + wire [31: 0] cat2 = {sub_res, c-d}; + + always @* begin + case(sel) + 0: res = {cat1, add_res}; + 1: res = {cat2, add_res}; + endcase + end + +endmodule diff --git a/tests/opt/opt_share_cat_multiuser.ys b/tests/opt/opt_share_cat_multiuser.ys new file mode 100644 index 000000000..6a82fbd79 --- /dev/null +++ b/tests/opt/opt_share_cat_multiuser.ys @@ -0,0 +1,13 @@ +read_verilog opt_share_cat_multiuser.v +proc;; +copy opt_share_test merged + +alumacc merged +opt merged +opt_share merged +opt_clean merged + +miter -equiv -flatten -ignore_gold_x -make_outputs -make_outcmp opt_share_test merged miter +sat -set-def-inputs -verify -prove trigger 0 -show-inputs -show-outputs miter + +select -assert-count 3 -module merged t:$alu diff --git a/tests/opt/opt_share_diff_port_widths.v b/tests/opt/opt_share_diff_port_widths.v new file mode 100644 index 000000000..5e2971e30 --- /dev/null +++ b/tests/opt/opt_share_diff_port_widths.v @@ -0,0 +1,21 @@ +module opt_share_test( + input [15:0] a, + input [15:0] b, + input [15:0] c, + input [1:0] sel, + output reg [15:0] res + ); + + wire [15:0] add0_res = a+b; + wire [15:0] add1_res = a+c; + + always @* begin + case(sel) + 0: res = add0_res[10:0]; + 1: res = add1_res[10:0]; + 2: res = a - b; + default: res = 32'bx; + endcase + end + +endmodule diff --git a/tests/opt/opt_share_diff_port_widths.ys b/tests/opt/opt_share_diff_port_widths.ys new file mode 100644 index 000000000..ec5e9f7b0 --- /dev/null +++ b/tests/opt/opt_share_diff_port_widths.ys @@ -0,0 +1,13 @@ +read_verilog opt_share_diff_port_widths.v +proc;; +copy opt_share_test merged + +alumacc merged +opt merged +opt_share merged +opt_clean merged + +miter -equiv -flatten -ignore_gold_x -make_outputs -make_outcmp opt_share_test merged miter +sat -set-def-inputs -verify -prove trigger 0 -show-inputs -show-outputs miter + +select -assert-count 2 -module merged t:$alu diff --git a/tests/opt/opt_share_extend.v b/tests/opt/opt_share_extend.v new file mode 100644 index 000000000..5ed6bde6f --- /dev/null +++ b/tests/opt/opt_share_extend.v @@ -0,0 +1,19 @@ +module opt_share_test( + input signed [7:0] a, + input signed [10:0] b, + input signed [15:0] c, + input [1:0] sel, + output reg signed [15:0] res + ); + + + always @* begin + case(sel) + 0: res = a + b; + 1: res = a - b; + 2: res = a + c; + default: res = 16'bx; + endcase + end + +endmodule diff --git a/tests/opt/opt_share_extend.ys b/tests/opt/opt_share_extend.ys new file mode 100644 index 000000000..c553ee0fb --- /dev/null +++ b/tests/opt/opt_share_extend.ys @@ -0,0 +1,13 @@ +read_verilog opt_share_extend.v +proc;; +copy opt_share_test merged + +alumacc merged +opt merged +opt_share merged +opt_clean merged + +miter -equiv -flatten -ignore_gold_x -make_outputs -make_outcmp opt_share_test merged miter +sat -set-def-inputs -verify -prove trigger 0 -show-inputs -show-outputs miter + +select -assert-count 1 -module merged t:$alu diff --git a/tests/opt/opt_share_large_pmux_cat.v b/tests/opt/opt_share_large_pmux_cat.v new file mode 100644 index 000000000..6208c796b --- /dev/null +++ b/tests/opt/opt_share_large_pmux_cat.v @@ -0,0 +1,22 @@ +module opt_share_test( + input [15:0] a, + input [15:0] b, + input [15:0] c, + input [2:0] sel, + output reg [31:0] res + ); + + + always @* begin + case(sel) + 0: res = {a + b, a}; + 1: res = {a - b, b}; + 2: res = {a + c, c}; + 3: res = {a - c, a}; + 4: res = {b, b}; + 5: res = {c, c}; + default: res = 32'bx; + endcase + end + +endmodule diff --git a/tests/opt/opt_share_large_pmux_cat.ys b/tests/opt/opt_share_large_pmux_cat.ys new file mode 100644 index 000000000..4186ca52e --- /dev/null +++ b/tests/opt/opt_share_large_pmux_cat.ys @@ -0,0 +1,13 @@ +read_verilog opt_share_large_pmux_cat.v +proc;; +copy opt_share_test merged + +alumacc merged +opt merged +opt_share merged +opt_clean merged + +miter -equiv -flatten -ignore_gold_x -make_outputs -make_outcmp opt_share_test merged miter +sat -set-def-inputs -verify -prove trigger 0 -show-inputs -show-outputs miter + +select -assert-count 1 -module merged t:$alu diff --git a/tests/opt/opt_share_large_pmux_cat_multipart.v b/tests/opt/opt_share_large_pmux_cat_multipart.v new file mode 100644 index 000000000..f97971bf6 --- /dev/null +++ b/tests/opt/opt_share_large_pmux_cat_multipart.v @@ -0,0 +1,25 @@ +module opt_share_test( + input [15:0] a, + input [15:0] b, + input [15:0] c, + input [15:0] d, + input [2:0] sel, + output reg [31:0] res + ); + + wire [15:0] add0_res = a+d; + + always @* begin + case(sel) + 0: res = {add0_res, a}; + 1: res = {a - b, add0_res[7], 15'b0}; + 2: res = {b-a, b}; + 3: res = {d, b - c}; + 4: res = {d, b - a}; + 5: res = {c, d}; + 6: res = {a - c, b-d}; + default: res = 32'bx; + endcase + end + +endmodule diff --git a/tests/opt/opt_share_large_pmux_cat_multipart.ys b/tests/opt/opt_share_large_pmux_cat_multipart.ys new file mode 100644 index 000000000..54d200dc7 --- /dev/null +++ b/tests/opt/opt_share_large_pmux_cat_multipart.ys @@ -0,0 +1,15 @@ +read_verilog opt_share_large_pmux_cat_multipart.v +proc;; +copy opt_share_test merged + +alumacc merged +opt merged + +opt_share merged +opt_clean merged +opt -full + +miter -equiv -flatten -ignore_gold_x -make_outputs -make_outcmp opt_share_test merged miter +sat -set-def-inputs -verify -prove trigger 0 -show-inputs -show-outputs miter + +select -assert-count 4 -module merged t:$alu diff --git a/tests/opt/opt_share_large_pmux_multipart.v b/tests/opt/opt_share_large_pmux_multipart.v new file mode 100644 index 000000000..e7ba318ef --- /dev/null +++ b/tests/opt/opt_share_large_pmux_multipart.v @@ -0,0 +1,24 @@ +module opt_share_test( + input [15:0] a, + input [15:0] b, + input [15:0] c, + input [15:0] d, + input [2:0] sel, + output reg [15:0] res + ); + + + always @* begin + case(sel) + 0: res = a + d; + 1: res = a - b; + 2: res = b; + 3: res = b - c; + 4: res = b - a; + 5: res = c; + 6: res = a - c; + default: res = 16'bx; + endcase + end + +endmodule diff --git a/tests/opt/opt_share_large_pmux_multipart.ys b/tests/opt/opt_share_large_pmux_multipart.ys new file mode 100644 index 000000000..11182df1a --- /dev/null +++ b/tests/opt/opt_share_large_pmux_multipart.ys @@ -0,0 +1,13 @@ +read_verilog opt_share_large_pmux_multipart.v +proc;; +copy opt_share_test merged + +alumacc merged +opt merged +opt_share merged +opt_clean merged + +miter -equiv -flatten -ignore_gold_x -make_outputs -make_outcmp opt_share_test merged miter +sat -set-def-inputs -verify -prove trigger 0 -show-inputs -show-outputs miter + +select -assert-count 2 -module merged t:$alu diff --git a/tests/opt/opt_share_large_pmux_part.v b/tests/opt/opt_share_large_pmux_part.v new file mode 100644 index 000000000..138be0cd6 --- /dev/null +++ b/tests/opt/opt_share_large_pmux_part.v @@ -0,0 +1,22 @@ +module opt_share_test( + input [15:0] a, + input [15:0] b, + input [15:0] c, + input [2:0] sel, + output reg [15:0] res + ); + + + always @* begin + case(sel) + 0: res = a + b; + 1: res = a - b; + 2: res = a + c; + 3: res = a - c; + 4: res = b; + 5: res = c; + default: res = 16'bx; + endcase + end + +endmodule diff --git a/tests/opt/opt_share_large_pmux_part.ys b/tests/opt/opt_share_large_pmux_part.ys new file mode 100644 index 000000000..6b594a3d6 --- /dev/null +++ b/tests/opt/opt_share_large_pmux_part.ys @@ -0,0 +1,13 @@ +read_verilog opt_share_large_pmux_part.v +proc;; +copy opt_share_test merged + +alumacc merged +opt merged +opt_share merged +opt_clean merged + +miter -equiv -flatten -ignore_gold_x -make_outputs -make_outcmp opt_share_test merged miter +sat -set-def-inputs -verify -prove trigger 0 -show-inputs -show-outputs miter + +select -assert-count 1 -module merged t:$alu diff --git a/tests/opt/opt_share_mux_tree.v b/tests/opt/opt_share_mux_tree.v index 807ed2978..c90826204 100644 --- a/tests/opt/opt_share_mux_tree.v +++ b/tests/opt/opt_share_mux_tree.v @@ -1,4 +1,4 @@ -module add_sub( +module opt_share_test( input [15:0] a, input [15:0] b, input [15:0] c, diff --git a/tests/opt/opt_share_mux_tree.ys b/tests/opt/opt_share_mux_tree.ys index 94d6aa7d2..58473039f 100644 --- a/tests/opt/opt_share_mux_tree.ys +++ b/tests/opt/opt_share_mux_tree.ys @@ -1,10 +1,13 @@ read_verilog opt_share_mux_tree.v -prep -flatten -opt -pmuxtree -opt_share; -opt_share; -opt_clean +proc;; +copy opt_share_test merged -select -assert-count 1 t:$add -select -assert-count 0 t:$sub +alumacc merged +opt merged +opt_share merged +opt_clean merged + +miter -equiv -flatten -ignore_gold_x -make_outputs -make_outcmp opt_share_test merged miter +sat -set-def-inputs -verify -prove trigger 0 -show-inputs -show-outputs miter + +select -assert-count 1 -module merged t:$alu -- cgit v1.2.3 From 280c4e7794543e99244aafffc62a2dd4454bcb06 Mon Sep 17 00:00:00 2001 From: Bogdan Vukobratovic Date: Sat, 3 Aug 2019 12:28:46 +0200 Subject: Fix spacing in opt_share tests, change wording in opt_share help --- tests/opt/opt_share_add_sub.v | 12 ++++---- tests/opt/opt_share_cat.v | 20 ++++++------- tests/opt/opt_share_cat_multiuser.v | 34 +++++++++++----------- tests/opt/opt_share_diff_port_widths.v | 32 ++++++++++----------- tests/opt/opt_share_extend.v | 29 +++++++++---------- tests/opt/opt_share_large_pmux_cat.v | 35 +++++++++++----------- tests/opt/opt_share_large_pmux_cat_multipart.v | 40 +++++++++++++------------- tests/opt/opt_share_large_pmux_multipart.v | 39 ++++++++++++------------- tests/opt/opt_share_large_pmux_part.v | 35 +++++++++++----------- tests/opt/opt_share_mux_tree.v | 29 +++++++++---------- 10 files changed, 150 insertions(+), 155 deletions(-) (limited to 'tests') diff --git a/tests/opt/opt_share_add_sub.v b/tests/opt/opt_share_add_sub.v index 30e093a39..1c2665cf0 100644 --- a/tests/opt/opt_share_add_sub.v +++ b/tests/opt/opt_share_add_sub.v @@ -1,10 +1,10 @@ module opt_share_test( - input [15:0] a, - input [15:0] b, - input sel, - output [15:0] res, - ); + input [15:0] a, + input [15:0] b, + input sel, + output [15:0] res, + ); - assign res = {sel ? a + b : a - b}; + assign res = {sel ? a + b : a - b}; endmodule diff --git a/tests/opt/opt_share_cat.v b/tests/opt/opt_share_cat.v index 605dcfe59..7b6f626b9 100644 --- a/tests/opt/opt_share_cat.v +++ b/tests/opt/opt_share_cat.v @@ -1,15 +1,15 @@ module opt_share_test( - input [15:0] a, - input [15:0] b, - input [15:0] c, - input [15:0] d, - input sel, - output [63:0] res, - ); + input [15:0] a, + input [15:0] b, + input [15:0] c, + input [15:0] d, + input sel, + output [63:0] res, + ); - reg [31: 0] cat1 = {a+b, c+d}; - reg [31: 0] cat2 = {a-b, c-d}; + reg [31: 0] cat1 = {a+b, c+d}; + reg [31: 0] cat2 = {a-b, c-d}; - assign res = {b, sel ? cat1 : cat2, a}; + assign res = {b, sel ? cat1 : cat2, a}; endmodule diff --git a/tests/opt/opt_share_cat_multiuser.v b/tests/opt/opt_share_cat_multiuser.v index 9ac0ceec8..f77f912e9 100644 --- a/tests/opt/opt_share_cat_multiuser.v +++ b/tests/opt/opt_share_cat_multiuser.v @@ -1,22 +1,22 @@ module opt_share_test( - input [15:0] a, - input [15:0] b, - input [15:0] c, - input [15:0] d, - input sel, - output reg [47:0] res, - ); + input [15:0] a, + input [15:0] b, + input [15:0] c, + input [15:0] d, + input sel, + output reg [47:0] res, + ); - wire [15:0] add_res = a+b; - wire [15:0] sub_res = a-b; - wire [31: 0] cat1 = {add_res, c+d}; - wire [31: 0] cat2 = {sub_res, c-d}; + wire [15:0] add_res = a+b; + wire [15:0] sub_res = a-b; + wire [31: 0] cat1 = {add_res, c+d}; + wire [31: 0] cat2 = {sub_res, c-d}; - always @* begin - case(sel) - 0: res = {cat1, add_res}; - 1: res = {cat2, add_res}; - endcase - end + always @* begin + case(sel) + 0: res = {cat1, add_res}; + 1: res = {cat2, add_res}; + endcase + end endmodule diff --git a/tests/opt/opt_share_diff_port_widths.v b/tests/opt/opt_share_diff_port_widths.v index 5e2971e30..e57ab7a83 100644 --- a/tests/opt/opt_share_diff_port_widths.v +++ b/tests/opt/opt_share_diff_port_widths.v @@ -1,21 +1,21 @@ module opt_share_test( - input [15:0] a, - input [15:0] b, - input [15:0] c, - input [1:0] sel, - output reg [15:0] res - ); + input [15:0] a, + input [15:0] b, + input [15:0] c, + input [1:0] sel, + output reg [15:0] res + ); - wire [15:0] add0_res = a+b; - wire [15:0] add1_res = a+c; + wire [15:0] add0_res = a+b; + wire [15:0] add1_res = a+c; - always @* begin - case(sel) - 0: res = add0_res[10:0]; - 1: res = add1_res[10:0]; - 2: res = a - b; - default: res = 32'bx; - endcase - end + always @* begin + case(sel) + 0: res = add0_res[10:0]; + 1: res = add1_res[10:0]; + 2: res = a - b; + default: res = 32'bx; + endcase + end endmodule diff --git a/tests/opt/opt_share_extend.v b/tests/opt/opt_share_extend.v index 5ed6bde6f..60ce1a2f3 100644 --- a/tests/opt/opt_share_extend.v +++ b/tests/opt/opt_share_extend.v @@ -1,19 +1,18 @@ module opt_share_test( - input signed [7:0] a, - input signed [10:0] b, - input signed [15:0] c, - input [1:0] sel, - output reg signed [15:0] res - ); + input signed [7:0] a, + input signed [10:0] b, + input signed [15:0] c, + input [1:0] sel, + output reg signed [15:0] res + ); - - always @* begin - case(sel) - 0: res = a + b; - 1: res = a - b; - 2: res = a + c; - default: res = 16'bx; - endcase - end + always @* begin + case(sel) + 0: res = a + b; + 1: res = a - b; + 2: res = a + c; + default: res = 16'bx; + endcase + end endmodule diff --git a/tests/opt/opt_share_large_pmux_cat.v b/tests/opt/opt_share_large_pmux_cat.v index 6208c796b..0667e6080 100644 --- a/tests/opt/opt_share_large_pmux_cat.v +++ b/tests/opt/opt_share_large_pmux_cat.v @@ -1,22 +1,21 @@ module opt_share_test( - input [15:0] a, - input [15:0] b, - input [15:0] c, - input [2:0] sel, - output reg [31:0] res - ); + input [15:0] a, + input [15:0] b, + input [15:0] c, + input [2:0] sel, + output reg [31:0] res + ); - - always @* begin - case(sel) - 0: res = {a + b, a}; - 1: res = {a - b, b}; - 2: res = {a + c, c}; - 3: res = {a - c, a}; - 4: res = {b, b}; - 5: res = {c, c}; - default: res = 32'bx; - endcase - end + always @* begin + case(sel) + 0: res = {a + b, a}; + 1: res = {a - b, b}; + 2: res = {a + c, c}; + 3: res = {a - c, a}; + 4: res = {b, b}; + 5: res = {c, c}; + default: res = 32'bx; + endcase + end endmodule diff --git a/tests/opt/opt_share_large_pmux_cat_multipart.v b/tests/opt/opt_share_large_pmux_cat_multipart.v index f97971bf6..f26505d3a 100644 --- a/tests/opt/opt_share_large_pmux_cat_multipart.v +++ b/tests/opt/opt_share_large_pmux_cat_multipart.v @@ -1,25 +1,25 @@ module opt_share_test( - input [15:0] a, - input [15:0] b, - input [15:0] c, - input [15:0] d, - input [2:0] sel, - output reg [31:0] res - ); + input [15:0] a, + input [15:0] b, + input [15:0] c, + input [15:0] d, + input [2:0] sel, + output reg [31:0] res + ); - wire [15:0] add0_res = a+d; + wire [15:0] add0_res = a+d; - always @* begin - case(sel) - 0: res = {add0_res, a}; - 1: res = {a - b, add0_res[7], 15'b0}; - 2: res = {b-a, b}; - 3: res = {d, b - c}; - 4: res = {d, b - a}; - 5: res = {c, d}; - 6: res = {a - c, b-d}; - default: res = 32'bx; - endcase - end + always @* begin + case(sel) + 0: res = {add0_res, a}; + 1: res = {a - b, add0_res[7], 15'b0}; + 2: res = {b-a, b}; + 3: res = {d, b - c}; + 4: res = {d, b - a}; + 5: res = {c, d}; + 6: res = {a - c, b-d}; + default: res = 32'bx; + endcase + end endmodule diff --git a/tests/opt/opt_share_large_pmux_multipart.v b/tests/opt/opt_share_large_pmux_multipart.v index e7ba318ef..1c460292f 100644 --- a/tests/opt/opt_share_large_pmux_multipart.v +++ b/tests/opt/opt_share_large_pmux_multipart.v @@ -1,24 +1,23 @@ module opt_share_test( - input [15:0] a, - input [15:0] b, - input [15:0] c, - input [15:0] d, - input [2:0] sel, - output reg [15:0] res - ); + input [15:0] a, + input [15:0] b, + input [15:0] c, + input [15:0] d, + input [2:0] sel, + output reg [15:0] res + ); - - always @* begin - case(sel) - 0: res = a + d; - 1: res = a - b; - 2: res = b; - 3: res = b - c; - 4: res = b - a; - 5: res = c; - 6: res = a - c; - default: res = 16'bx; - endcase - end + always @* begin + case(sel) + 0: res = a + d; + 1: res = a - b; + 2: res = b; + 3: res = b - c; + 4: res = b - a; + 5: res = c; + 6: res = a - c; + default: res = 16'bx; + endcase + end endmodule diff --git a/tests/opt/opt_share_large_pmux_part.v b/tests/opt/opt_share_large_pmux_part.v index 138be0cd6..f9dd17446 100644 --- a/tests/opt/opt_share_large_pmux_part.v +++ b/tests/opt/opt_share_large_pmux_part.v @@ -1,22 +1,21 @@ module opt_share_test( - input [15:0] a, - input [15:0] b, - input [15:0] c, - input [2:0] sel, - output reg [15:0] res - ); + input [15:0] a, + input [15:0] b, + input [15:0] c, + input [2:0] sel, + output reg [15:0] res + ); - - always @* begin - case(sel) - 0: res = a + b; - 1: res = a - b; - 2: res = a + c; - 3: res = a - c; - 4: res = b; - 5: res = c; - default: res = 16'bx; - endcase - end + always @* begin + case(sel) + 0: res = a + b; + 1: res = a - b; + 2: res = a + c; + 3: res = a - c; + 4: res = b; + 5: res = c; + default: res = 16'bx; + endcase + end endmodule diff --git a/tests/opt/opt_share_mux_tree.v b/tests/opt/opt_share_mux_tree.v index c90826204..4a26afb46 100644 --- a/tests/opt/opt_share_mux_tree.v +++ b/tests/opt/opt_share_mux_tree.v @@ -1,19 +1,18 @@ module opt_share_test( - input [15:0] a, - input [15:0] b, - input [15:0] c, - input [1:0] sel, - output reg [15:0] res - ); + input [15:0] a, + input [15:0] b, + input [15:0] c, + input [1:0] sel, + output reg [15:0] res + ); - - always @* begin - case(sel) - 0: res = a + b; - 1: res = a - b; - 2: res = a + c; - default: res = 16'bx; - endcase - end + always @* begin + case(sel) + 0: res = a + b; + 1: res = a - b; + 2: res = a + c; + default: res = 16'bx; + endcase + end endmodule -- cgit v1.2.3 From d8be5ce6ba11ec78d0f7925d488fad09a3eaba2c Mon Sep 17 00:00:00 2001 From: Bogdan Vukobratovic Date: Sat, 3 Aug 2019 12:35:46 +0200 Subject: Tabs to spaces in opt_share examples --- tests/opt/opt_share_add_sub.v | 12 ++++---- tests/opt/opt_share_cat.v | 20 ++++++------- tests/opt/opt_share_cat_multiuser.v | 34 +++++++++++----------- tests/opt/opt_share_diff_port_widths.v | 32 ++++++++++----------- tests/opt/opt_share_extend.v | 28 +++++++++--------- tests/opt/opt_share_large_pmux_cat.v | 34 +++++++++++----------- tests/opt/opt_share_large_pmux_cat_multipart.v | 40 +++++++++++++------------- tests/opt/opt_share_large_pmux_multipart.v | 38 ++++++++++++------------ tests/opt/opt_share_large_pmux_part.v | 34 +++++++++++----------- tests/opt/opt_share_mux_tree.v | 28 +++++++++--------- 10 files changed, 150 insertions(+), 150 deletions(-) (limited to 'tests') diff --git a/tests/opt/opt_share_add_sub.v b/tests/opt/opt_share_add_sub.v index 1c2665cf0..d918f27cc 100644 --- a/tests/opt/opt_share_add_sub.v +++ b/tests/opt/opt_share_add_sub.v @@ -1,10 +1,10 @@ module opt_share_test( - input [15:0] a, - input [15:0] b, - input sel, - output [15:0] res, - ); + input [15:0] a, + input [15:0] b, + input sel, + output [15:0] res, + ); - assign res = {sel ? a + b : a - b}; + assign res = {sel ? a + b : a - b}; endmodule diff --git a/tests/opt/opt_share_cat.v b/tests/opt/opt_share_cat.v index 7b6f626b9..7fb97fef5 100644 --- a/tests/opt/opt_share_cat.v +++ b/tests/opt/opt_share_cat.v @@ -1,15 +1,15 @@ module opt_share_test( - input [15:0] a, - input [15:0] b, - input [15:0] c, - input [15:0] d, - input sel, - output [63:0] res, - ); + input [15:0] a, + input [15:0] b, + input [15:0] c, + input [15:0] d, + input sel, + output [63:0] res, + ); - reg [31: 0] cat1 = {a+b, c+d}; - reg [31: 0] cat2 = {a-b, c-d}; + reg [31: 0] cat1 = {a+b, c+d}; + reg [31: 0] cat2 = {a-b, c-d}; - assign res = {b, sel ? cat1 : cat2, a}; + assign res = {b, sel ? cat1 : cat2, a}; endmodule diff --git a/tests/opt/opt_share_cat_multiuser.v b/tests/opt/opt_share_cat_multiuser.v index f77f912e9..b250689d9 100644 --- a/tests/opt/opt_share_cat_multiuser.v +++ b/tests/opt/opt_share_cat_multiuser.v @@ -1,22 +1,22 @@ module opt_share_test( - input [15:0] a, - input [15:0] b, - input [15:0] c, - input [15:0] d, - input sel, - output reg [47:0] res, - ); + input [15:0] a, + input [15:0] b, + input [15:0] c, + input [15:0] d, + input sel, + output reg [47:0] res, + ); - wire [15:0] add_res = a+b; - wire [15:0] sub_res = a-b; - wire [31: 0] cat1 = {add_res, c+d}; - wire [31: 0] cat2 = {sub_res, c-d}; + wire [15:0] add_res = a+b; + wire [15:0] sub_res = a-b; + wire [31: 0] cat1 = {add_res, c+d}; + wire [31: 0] cat2 = {sub_res, c-d}; - always @* begin - case(sel) - 0: res = {cat1, add_res}; - 1: res = {cat2, add_res}; - endcase - end + always @* begin + case(sel) + 0: res = {cat1, add_res}; + 1: res = {cat2, add_res}; + endcase + end endmodule diff --git a/tests/opt/opt_share_diff_port_widths.v b/tests/opt/opt_share_diff_port_widths.v index e57ab7a83..1a37c80a6 100644 --- a/tests/opt/opt_share_diff_port_widths.v +++ b/tests/opt/opt_share_diff_port_widths.v @@ -1,21 +1,21 @@ module opt_share_test( - input [15:0] a, - input [15:0] b, - input [15:0] c, - input [1:0] sel, - output reg [15:0] res - ); + input [15:0] a, + input [15:0] b, + input [15:0] c, + input [1:0] sel, + output reg [15:0] res + ); - wire [15:0] add0_res = a+b; - wire [15:0] add1_res = a+c; + wire [15:0] add0_res = a+b; + wire [15:0] add1_res = a+c; - always @* begin - case(sel) - 0: res = add0_res[10:0]; - 1: res = add1_res[10:0]; - 2: res = a - b; - default: res = 32'bx; - endcase - end + always @* begin + case(sel) + 0: res = add0_res[10:0]; + 1: res = add1_res[10:0]; + 2: res = a - b; + default: res = 32'bx; + endcase + end endmodule diff --git a/tests/opt/opt_share_extend.v b/tests/opt/opt_share_extend.v index 60ce1a2f3..d39f19069 100644 --- a/tests/opt/opt_share_extend.v +++ b/tests/opt/opt_share_extend.v @@ -1,18 +1,18 @@ module opt_share_test( - input signed [7:0] a, - input signed [10:0] b, - input signed [15:0] c, - input [1:0] sel, - output reg signed [15:0] res - ); + input signed [7:0] a, + input signed [10:0] b, + input signed [15:0] c, + input [1:0] sel, + output reg signed [15:0] res + ); - always @* begin - case(sel) - 0: res = a + b; - 1: res = a - b; - 2: res = a + c; - default: res = 16'bx; - endcase - end + always @* begin + case(sel) + 0: res = a + b; + 1: res = a - b; + 2: res = a + c; + default: res = 16'bx; + endcase + end endmodule diff --git a/tests/opt/opt_share_large_pmux_cat.v b/tests/opt/opt_share_large_pmux_cat.v index 0667e6080..416ba3766 100644 --- a/tests/opt/opt_share_large_pmux_cat.v +++ b/tests/opt/opt_share_large_pmux_cat.v @@ -1,21 +1,21 @@ module opt_share_test( - input [15:0] a, - input [15:0] b, - input [15:0] c, - input [2:0] sel, - output reg [31:0] res - ); + input [15:0] a, + input [15:0] b, + input [15:0] c, + input [2:0] sel, + output reg [31:0] res + ); - always @* begin - case(sel) - 0: res = {a + b, a}; - 1: res = {a - b, b}; - 2: res = {a + c, c}; - 3: res = {a - c, a}; - 4: res = {b, b}; - 5: res = {c, c}; - default: res = 32'bx; - endcase - end + always @* begin + case(sel) + 0: res = {a + b, a}; + 1: res = {a - b, b}; + 2: res = {a + c, c}; + 3: res = {a - c, a}; + 4: res = {b, b}; + 5: res = {c, c}; + default: res = 32'bx; + endcase + end endmodule diff --git a/tests/opt/opt_share_large_pmux_cat_multipart.v b/tests/opt/opt_share_large_pmux_cat_multipart.v index f26505d3a..34d2bd9a8 100644 --- a/tests/opt/opt_share_large_pmux_cat_multipart.v +++ b/tests/opt/opt_share_large_pmux_cat_multipart.v @@ -1,25 +1,25 @@ module opt_share_test( - input [15:0] a, - input [15:0] b, - input [15:0] c, - input [15:0] d, - input [2:0] sel, - output reg [31:0] res - ); + input [15:0] a, + input [15:0] b, + input [15:0] c, + input [15:0] d, + input [2:0] sel, + output reg [31:0] res + ); - wire [15:0] add0_res = a+d; + wire [15:0] add0_res = a+d; - always @* begin - case(sel) - 0: res = {add0_res, a}; - 1: res = {a - b, add0_res[7], 15'b0}; - 2: res = {b-a, b}; - 3: res = {d, b - c}; - 4: res = {d, b - a}; - 5: res = {c, d}; - 6: res = {a - c, b-d}; - default: res = 32'bx; - endcase - end + always @* begin + case(sel) + 0: res = {add0_res, a}; + 1: res = {a - b, add0_res[7], 15'b0}; + 2: res = {b-a, b}; + 3: res = {d, b - c}; + 4: res = {d, b - a}; + 5: res = {c, d}; + 6: res = {a - c, b-d}; + default: res = 32'bx; + endcase + end endmodule diff --git a/tests/opt/opt_share_large_pmux_multipart.v b/tests/opt/opt_share_large_pmux_multipart.v index 1c460292f..535adf96f 100644 --- a/tests/opt/opt_share_large_pmux_multipart.v +++ b/tests/opt/opt_share_large_pmux_multipart.v @@ -1,23 +1,23 @@ module opt_share_test( - input [15:0] a, - input [15:0] b, - input [15:0] c, - input [15:0] d, - input [2:0] sel, - output reg [15:0] res - ); + input [15:0] a, + input [15:0] b, + input [15:0] c, + input [15:0] d, + input [2:0] sel, + output reg [15:0] res + ); - always @* begin - case(sel) - 0: res = a + d; - 1: res = a - b; - 2: res = b; - 3: res = b - c; - 4: res = b - a; - 5: res = c; - 6: res = a - c; - default: res = 16'bx; - endcase - end + always @* begin + case(sel) + 0: res = a + d; + 1: res = a - b; + 2: res = b; + 3: res = b - c; + 4: res = b - a; + 5: res = c; + 6: res = a - c; + default: res = 16'bx; + endcase + end endmodule diff --git a/tests/opt/opt_share_large_pmux_part.v b/tests/opt/opt_share_large_pmux_part.v index f9dd17446..a9008fb5a 100644 --- a/tests/opt/opt_share_large_pmux_part.v +++ b/tests/opt/opt_share_large_pmux_part.v @@ -1,21 +1,21 @@ module opt_share_test( - input [15:0] a, - input [15:0] b, - input [15:0] c, - input [2:0] sel, - output reg [15:0] res - ); + input [15:0] a, + input [15:0] b, + input [15:0] c, + input [2:0] sel, + output reg [15:0] res + ); - always @* begin - case(sel) - 0: res = a + b; - 1: res = a - b; - 2: res = a + c; - 3: res = a - c; - 4: res = b; - 5: res = c; - default: res = 16'bx; - endcase - end + always @* begin + case(sel) + 0: res = a + b; + 1: res = a - b; + 2: res = a + c; + 3: res = a - c; + 4: res = b; + 5: res = c; + default: res = 16'bx; + endcase + end endmodule diff --git a/tests/opt/opt_share_mux_tree.v b/tests/opt/opt_share_mux_tree.v index 4a26afb46..cc5ae4eb9 100644 --- a/tests/opt/opt_share_mux_tree.v +++ b/tests/opt/opt_share_mux_tree.v @@ -1,18 +1,18 @@ module opt_share_test( - input [15:0] a, - input [15:0] b, - input [15:0] c, - input [1:0] sel, - output reg [15:0] res - ); + input [15:0] a, + input [15:0] b, + input [15:0] c, + input [1:0] sel, + output reg [15:0] res + ); - always @* begin - case(sel) - 0: res = a + b; - 1: res = a - b; - 2: res = a + c; - default: res = 16'bx; - endcase - end + always @* begin + case(sel) + 0: res = a + b; + 1: res = a - b; + 2: res = a + c; + default: res = 16'bx; + endcase + end endmodule -- cgit v1.2.3 From 6a796accc09bc2c8ef98c068185de13d3e01890a Mon Sep 17 00:00:00 2001 From: Bogdan Vukobratovic Date: Sun, 4 Aug 2019 19:06:38 +0200 Subject: Support various binary operators in opt_share --- tests/opt_share/.gitignore | 1 + tests/opt_share/generate.py | 86 +++++++++++++++++++++++++++++++++++++++++++++ tests/opt_share/run-test.sh | 39 ++++++++++++++++++++ 3 files changed, 126 insertions(+) create mode 100644 tests/opt_share/.gitignore create mode 100644 tests/opt_share/generate.py create mode 100755 tests/opt_share/run-test.sh (limited to 'tests') diff --git a/tests/opt_share/.gitignore b/tests/opt_share/.gitignore new file mode 100644 index 000000000..9c595a6fb --- /dev/null +++ b/tests/opt_share/.gitignore @@ -0,0 +1 @@ +temp diff --git a/tests/opt_share/generate.py b/tests/opt_share/generate.py new file mode 100644 index 000000000..2ec92f7de --- /dev/null +++ b/tests/opt_share/generate.py @@ -0,0 +1,86 @@ +#!/usr/bin/env python3 + +import argparse +import sys +import random +from contextlib import contextmanager + + +@contextmanager +def redirect_stdout(new_target): + old_target, sys.stdout = sys.stdout, new_target + try: + yield new_target + finally: + sys.stdout = old_target + + +def random_plus_x(): + return "%s x" % random.choice(['+', '+', '+', '-', '-', '|', '&', '^']) + + +def maybe_plus_x(expr): + if random.randint(0, 4) == 0: + return "(%s %s)" % (expr, random_plus_x()) + else: + return expr + + +parser = argparse.ArgumentParser( + formatter_class=argparse.ArgumentDefaultsHelpFormatter) +parser.add_argument('-S', '--seed', type=int, help='seed for PRNG') +parser.add_argument('-c', + '--count', + type=int, + default=100, + help='number of test cases to generate') +args = parser.parse_args() + +if args.seed is not None: + print("PRNG seed: %d" % args.seed) + random.seed(args.seed) + +for idx in range(args.count): + with open('temp/uut_%05d.v' % idx, 'w') as f: + with redirect_stdout(f): + print('module uut_%05d(a, b, c, s, y);' % (idx)) + op = random.choice([ + random.choice(['+', '-', '*', '/', '%']), + random.choice(['<', '<=', '==', '!=', '===', '!==', '>=', + '>']), + random.choice(['<<', '>>', '<<<', '>>>']), + random.choice(['|', '&', '^', '~^', '||', '&&']), + ]) + print(' input%s [%d:0] a;' % (random.choice(['', ' signed']), 8)) + print(' input%s [%d:0] b;' % (random.choice(['', ' signed']), 8)) + print(' input%s [%d:0] c;' % (random.choice(['', ' signed']), 8)) + print(' input s;') + print(' output [%d:0] y;' % 8) + ops1 = ['a', 'b'] + ops2 = ['a', 'c'] + random.shuffle(ops1) + random.shuffle(ops2) + cast1 = random.choice(['', '$signed', '$unsigned']) + cast2 = random.choice(['', '$signed', '$unsigned']) + print(' assign y = (s ? %s(%s %s %s) : %s(%s %s %s));' % + (cast1, ops1[0], op, ops1[1], + cast2, ops2[0], op, ops2[1])) + print('endmodule') + + with open('temp/uut_%05d.ys' % idx, 'w') as f: + with redirect_stdout(f): + print('read_verilog temp/uut_%05d.v' % idx) + print('proc;;') + print('copy uut_%05d gold' % idx) + print('rename uut_%05d gate' % idx) + print('tee -a temp/all_share_log.txt log') + print('tee -a temp/all_share_log.txt log #job# uut_%05d' % idx) + print('tee -a temp/all_share_log.txt opt gate') + print('tee -a temp/all_share_log.txt opt_share gate') + print('tee -a temp/all_share_log.txt opt_clean gate') + print( + 'miter -equiv -flatten -ignore_gold_x -make_outputs -make_outcmp gold gate miter' + ) + print( + 'sat -set-def-inputs -verify -prove trigger 0 -show-inputs -show-outputs miter' + ) diff --git a/tests/opt_share/run-test.sh b/tests/opt_share/run-test.sh new file mode 100755 index 000000000..e01552646 --- /dev/null +++ b/tests/opt_share/run-test.sh @@ -0,0 +1,39 @@ +#!/bin/bash + +# run this test many times: +# time bash -c 'for ((i=0; i<100; i++)); do echo "-- $i --"; bash run-test.sh || exit 1; done' + +set -e + +OPTIND=1 +count=100 +seed="" # default to no seed specified +while getopts "c:S:" opt +do + case "$opt" in + c) count="$OPTARG" ;; + S) seed="-S $OPTARG" ;; + esac +done +shift "$((OPTIND-1))" + +rm -rf temp +mkdir -p temp +echo "generating tests.." +python3 generate.py -c $count $seed + +echo "running tests.." +for i in $( ls temp/*.ys | sed 's,[^0-9],,g; s,^0*\(.\),\1,g;' ); do + echo -n "[$i]" + idx=$( printf "%05d" $i ) + ../../yosys -ql temp/uut_${idx}.log temp/uut_${idx}.ys +done +echo + +failed_share=$( echo $( gawk '/^#job#/ { j=$2; db[j]=0; } /^Removing [246] cells/ { delete db[j]; } END { for (j in db) print(j); }' temp/all_share_log.txt ) ) +if [ -n "$failed_share" ]; then + echo "Resource sharing failed for the following test cases: $failed_share" + false +fi + +exit 0 -- cgit v1.2.3 From 067b44938c1fd3e24fc9478b96a47bac7152c111 Mon Sep 17 00:00:00 2001 From: Bogdan Vukobratovic Date: Wed, 7 Aug 2019 09:30:58 +0200 Subject: Fix wrong results when opt_share called before opt_clean --- tests/opt/opt_share_large_pmux_cat_multipart.ys | 1 - 1 file changed, 1 deletion(-) (limited to 'tests') diff --git a/tests/opt/opt_share_large_pmux_cat_multipart.ys b/tests/opt/opt_share_large_pmux_cat_multipart.ys index 54d200dc7..610bb8c6c 100644 --- a/tests/opt/opt_share_large_pmux_cat_multipart.ys +++ b/tests/opt/opt_share_large_pmux_cat_multipart.ys @@ -7,7 +7,6 @@ opt merged opt_share merged opt_clean merged -opt -full miter -equiv -flatten -ignore_gold_x -make_outputs -make_outcmp opt_share_test merged miter sat -set-def-inputs -verify -prove trigger 0 -show-inputs -show-outputs miter -- cgit v1.2.3 From 12c692f6eda7367527fde2a8aad49447a73aa643 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Mon, 12 Aug 2019 12:06:45 -0700 Subject: Revert "Merge pull request #1280 from YosysHQ/revert-1266-eddie/ice40_full_adder" This reverts commit c851dc13108021834533094a8a3236da6d9e0161, reversing changes made to f54bf1631ff37a83733c162e6ebd188c1d5ea18f. --- tests/opt/opt_expr.ys | 223 +++++++++++++++++++++++++++++++++++++++++++++ tests/opt/opt_ff.v | 21 ----- tests/opt/opt_ff.ys | 3 - tests/opt/opt_ff_sat.v | 12 --- tests/opt/opt_ff_sat.ys | 5 - tests/opt/opt_lut.ys | 4 +- tests/opt/opt_rmdff.v | 50 ++++++++++ tests/opt/opt_rmdff.ys | 26 ++++++ tests/opt/opt_rmdff_sat.v | 12 +++ tests/opt/opt_rmdff_sat.ys | 5 + tests/various/opt_expr.ys | 223 --------------------------------------------- tests/various/opt_rmdff.v | 50 ---------- tests/various/opt_rmdff.ys | 26 ------ tests/various/wreduce.ys | 33 ++++++- 14 files changed, 349 insertions(+), 344 deletions(-) create mode 100644 tests/opt/opt_expr.ys delete mode 100644 tests/opt/opt_ff.v delete mode 100644 tests/opt/opt_ff.ys delete mode 100644 tests/opt/opt_ff_sat.v delete mode 100644 tests/opt/opt_ff_sat.ys create mode 100644 tests/opt/opt_rmdff.v create mode 100644 tests/opt/opt_rmdff.ys create mode 100644 tests/opt/opt_rmdff_sat.v create mode 100644 tests/opt/opt_rmdff_sat.ys delete mode 100644 tests/various/opt_expr.ys delete mode 100644 tests/various/opt_rmdff.v delete mode 100644 tests/various/opt_rmdff.ys (limited to 'tests') diff --git a/tests/opt/opt_expr.ys b/tests/opt/opt_expr.ys new file mode 100644 index 000000000..f0306efa1 --- /dev/null +++ b/tests/opt/opt_expr.ys @@ -0,0 +1,223 @@ + +read_verilog < Date: Fri, 16 Aug 2019 14:22:46 +0200 Subject: Do not use Verific in tests/various/write_gzip.ys Signed-off-by: Clifford Wolf --- tests/various/write_gzip.ys | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'tests') diff --git a/tests/various/write_gzip.ys b/tests/various/write_gzip.ys index 030ec318e..524ecc33e 100644 --- a/tests/various/write_gzip.ys +++ b/tests/various/write_gzip.ys @@ -1,4 +1,4 @@ -read -vlog2k < Date: Sat, 17 Aug 2019 14:05:10 +0200 Subject: Add test for pmtest_test "reduce" demo pattern Signed-off-by: Clifford Wolf --- tests/various/pmgen_reduce.ys | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) create mode 100644 tests/various/pmgen_reduce.ys (limited to 'tests') diff --git a/tests/various/pmgen_reduce.ys b/tests/various/pmgen_reduce.ys new file mode 100644 index 000000000..c214d3f25 --- /dev/null +++ b/tests/various/pmgen_reduce.ys @@ -0,0 +1,21 @@ +test_pmgen -generate reduce +hierarchy -top pmtest_test_pmgen_pm_reduce +flatten; opt_clean + +design -save gold +test_pmgen -reduce_chain +design -stash gate + +design -copy-from gold -as gold pmtest_test_pmgen_pm_reduce +design -copy-from gate -as gate pmtest_test_pmgen_pm_reduce +miter -equiv -flatten -make_assert gold gate miter +sat -verify -prove-asserts miter + +design -load gold +test_pmgen -reduce_tree +design -stash gate + +design -copy-from gold -as gold pmtest_test_pmgen_pm_reduce +design -copy-from gate -as gate pmtest_test_pmgen_pm_reduce +miter -equiv -flatten -make_assert gold gate miter +sat -verify -prove-asserts miter -- cgit v1.2.3 From 9e940f127691fe9e4fc3c4c92f6f0dc306aa9fb8 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sat, 17 Aug 2019 14:37:07 +0200 Subject: Speed up "make test" and related cleanups Signed-off-by: Clifford Wolf --- tests/fsm/run-test.sh | 2 +- tests/simple_abc9/run-test.sh | 3 ++- tests/various/.gitignore | 1 + tests/various/run-test.sh | 16 ++++++++++++---- tests/various/shregmap.ys | 10 +++++----- 5 files changed, 21 insertions(+), 11 deletions(-) (limited to 'tests') diff --git a/tests/fsm/run-test.sh b/tests/fsm/run-test.sh index cf506470d..fbdcbf048 100755 --- a/tests/fsm/run-test.sh +++ b/tests/fsm/run-test.sh @@ -6,7 +6,7 @@ set -e OPTIND=1 -count=100 +count=50 seed="" # default to no seed specified while getopts "c:S:" opt do diff --git a/tests/simple_abc9/run-test.sh b/tests/simple_abc9/run-test.sh index 4935d41ad..49ae23338 100755 --- a/tests/simple_abc9/run-test.sh +++ b/tests/simple_abc9/run-test.sh @@ -18,5 +18,6 @@ if ! which iverilog > /dev/null ; then fi cp ../simple/*.v . +cp ../simple/*.sv . DOLLAR='?' -exec ${MAKE:-make} -f ../tools/autotest.mk $seed *.v EXTRA_FLAGS="-p 'hierarchy; synth -run coarse; opt -full; techmap; abc9 -lut 4 -box ../abc.box; stat; check -assert; select -assert-none t:${DOLLAR}_NOT_ t:${DOLLAR}_AND_ %%'" +exec ${MAKE:-make} -f ../tools/autotest.mk $seed *.v EXTRA_FLAGS="-n 300 -p 'hierarchy; synth -run coarse; opt -full; techmap; abc9 -lut 4 -box ../abc.box; stat; check -assert; select -assert-none t:${DOLLAR}_NOT_ t:${DOLLAR}_AND_ %%'" diff --git a/tests/various/.gitignore b/tests/various/.gitignore index 31078b298..4b286fd61 100644 --- a/tests/various/.gitignore +++ b/tests/various/.gitignore @@ -2,3 +2,4 @@ /*.out /write_gzip.v /write_gzip.v.gz +/run-test.mk diff --git a/tests/various/run-test.sh b/tests/various/run-test.sh index 92b905765..ea56b70f0 100755 --- a/tests/various/run-test.sh +++ b/tests/various/run-test.sh @@ -1,12 +1,20 @@ #!/usr/bin/env bash set -e +{ +echo "all::" for x in *.ys; do - echo "Running $x.." - ../../yosys -ql ${x%.ys}.log $x + echo "all:: run-$x" + echo "run-$x:" + echo " @echo 'Running $x..'" + echo " @../../yosys -ql ${x%.ys}.log $x" done for s in *.sh; do if [ "$s" != "run-test.sh" ]; then - echo "Running $s.." - bash $s + echo "all:: run-$s" + echo "run-$s:" + echo " @echo 'Running $s..'" + echo " @bash $s" fi done +} > run-test.mk +exec ${MAKE:-make} -f run-test.mk diff --git a/tests/various/shregmap.ys b/tests/various/shregmap.ys index d644a88aa..5c9c78dd2 100644 --- a/tests/various/shregmap.ys +++ b/tests/various/shregmap.ys @@ -45,7 +45,7 @@ shregmap -tech xilinx stat # show -width -write_verilog -noexpr -norename +# write_verilog -noexpr -norename select -assert-count 1 t:$_DFF_P_ select -assert-count 2 t:$__XILINX_SHREG_ @@ -59,8 +59,8 @@ prep miter -equiv -flatten -make_assert -make_outputs gold gate miter sat -verify -prove-asserts -show-ports -seq 5 miter -design -load gold -stat +# design -load gold +# stat -design -load gate -stat +# design -load gate +# stat -- cgit v1.2.3 From f5170a7eda6fddaf482896a2ad67da4bb3131d7b Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Sun, 18 Aug 2019 21:28:45 -0700 Subject: Removal of more `stat` calls from tests --- tests/various/muxpack.ys | 30 +++++++++++++++--------------- tests/various/opt_rmdff.ys | 10 +++++----- tests/various/shregmap.ys | 12 ++++++------ 3 files changed, 26 insertions(+), 26 deletions(-) (limited to 'tests') diff --git a/tests/various/muxpack.ys b/tests/various/muxpack.ys index af23fcec8..3e90419af 100644 --- a/tests/various/muxpack.ys +++ b/tests/various/muxpack.ys @@ -6,7 +6,7 @@ prep design -save gold muxpack opt -stat +#stat select -assert-count 0 t:$mux select -assert-count 1 t:$pmux design -stash gate @@ -21,7 +21,7 @@ prep design -save gold muxpack opt -stat +#stat select -assert-count 0 t:$mux select -assert-count 1 t:$pmux design -stash gate @@ -52,7 +52,7 @@ prep design -save gold muxpack opt -stat +#stat select -assert-count 0 t:$mux select -assert-count 2 t:$pmux design -stash gate @@ -67,7 +67,7 @@ prep design -save gold muxpack opt -stat +#stat select -assert-count 0 t:$mux select -assert-count 1 t:$pmux design -stash gate @@ -82,7 +82,7 @@ prep design -save gold muxpack opt -stat +#stat select -assert-count 0 t:$mux select -assert-count 1 t:$pmux design -stash gate @@ -97,7 +97,7 @@ prep design -save gold muxpack opt -stat +#stat select -assert-count 0 t:$mux select -assert-count 1 t:$pmux design -stash gate @@ -112,7 +112,7 @@ prep design -save gold muxpack opt -stat +#stat select -assert-count 0 t:$mux select -assert-count 1 t:$pmux design -stash gate @@ -127,7 +127,7 @@ prep design -save gold muxpack opt -stat +#stat select -assert-count 0 t:$mux select -assert-count 1 t:$pmux design -stash gate @@ -142,7 +142,7 @@ prep design -save gold muxpack opt -stat +#stat select -assert-count 7 t:$mux select -assert-count 0 t:$pmux design -stash gate @@ -157,7 +157,7 @@ prep design -save gold muxpack opt -stat +#stat select -assert-count 4 t:$mux select -assert-count 0 t:$pmux design -stash gate @@ -172,7 +172,7 @@ prep design -save gold muxpack opt -stat +#stat select -assert-count 3 t:$mux select -assert-count 0 t:$pmux design -stash gate @@ -204,7 +204,7 @@ prep design -save gold muxpack opt -stat +#stat select -assert-count 0 t:$mux select -assert-count 2 t:$pmux design -stash gate @@ -222,7 +222,7 @@ opt -fast -mux_undef select -assert-count 2 t:$pmux muxpack opt -stat +#stat select -assert-count 0 t:$mux select -assert-count 1 t:$pmux design -stash gate @@ -240,7 +240,7 @@ opt -fast -mux_undef select -assert-count 2 t:$pmux muxpack opt -stat +#stat select -assert-count 0 t:$mux select -assert-count 2 t:$pmux design -stash gate @@ -258,7 +258,7 @@ opt -fast -mux_undef select -assert-count 2 t:$pmux muxpack opt -stat +#stat select -assert-count 0 t:$mux select -assert-count 2 t:$pmux design -stash gate diff --git a/tests/various/opt_rmdff.ys b/tests/various/opt_rmdff.ys index 081f81782..83a162f44 100644 --- a/tests/various/opt_rmdff.ys +++ b/tests/various/opt_rmdff.ys @@ -19,8 +19,8 @@ hierarchy -top equiv equiv_simple -undef equiv_status -assert -design -load gold -stat - -design -load gate -stat +#design -load gold +#stat +# +#design -load gate +#stat diff --git a/tests/various/shregmap.ys b/tests/various/shregmap.ys index 5c9c78dd2..0e5fe882b 100644 --- a/tests/various/shregmap.ys +++ b/tests/various/shregmap.ys @@ -11,7 +11,7 @@ shregmap -init opt -stat +# stat # show -width select -assert-count 1 t:$_DFF_P_ select -assert-count 2 t:$__SHREG_DFF_P_ @@ -26,11 +26,11 @@ prep miter -equiv -flatten -make_assert -make_outputs gold gate miter sat -verify -prove-asserts -show-ports -seq 5 miter -design -load gold -stat +#design -load gold +#stat -design -load gate -stat +#design -load gate +#stat ########## @@ -43,7 +43,7 @@ design -save gold simplemap t:$dff t:$dffe shregmap -tech xilinx -stat +#stat # show -width # write_verilog -noexpr -norename select -assert-count 1 t:$_DFF_P_ -- cgit v1.2.3 From 21699e5840b71433eb242d9c60f1635908717f5e Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Mon, 19 Aug 2019 13:04:57 +0200 Subject: Add *.sv to tests/simple_abc9/.gitignore Signed-off-by: Clifford Wolf --- tests/simple_abc9/.gitignore | 1 + 1 file changed, 1 insertion(+) (limited to 'tests') diff --git a/tests/simple_abc9/.gitignore b/tests/simple_abc9/.gitignore index 598951333..2355aea29 100644 --- a/tests/simple_abc9/.gitignore +++ b/tests/simple_abc9/.gitignore @@ -1,3 +1,4 @@ *.v +*.sv *.log *.out -- cgit v1.2.3 From 4a942ba7b9bb76f207adf23369f46d31f7607b75 Mon Sep 17 00:00:00 2001 From: whitequark Date: Mon, 19 Aug 2019 16:44:23 +0000 Subject: proc_clean: fix order of switch insertion. Fixes #1268. --- tests/proc/.gitignore | 1 + tests/proc/bug_1268.v | 23 +++++++++++++++++++++++ tests/proc/bug_1268.ys | 5 +++++ tests/proc/run-test.sh | 6 ++++++ 4 files changed, 35 insertions(+) create mode 100644 tests/proc/.gitignore create mode 100644 tests/proc/bug_1268.v create mode 100644 tests/proc/bug_1268.ys create mode 100755 tests/proc/run-test.sh (limited to 'tests') diff --git a/tests/proc/.gitignore b/tests/proc/.gitignore new file mode 100644 index 000000000..397b4a762 --- /dev/null +++ b/tests/proc/.gitignore @@ -0,0 +1 @@ +*.log diff --git a/tests/proc/bug_1268.v b/tests/proc/bug_1268.v new file mode 100644 index 000000000..698ac937a --- /dev/null +++ b/tests/proc/bug_1268.v @@ -0,0 +1,23 @@ +module gold (input clock, ctrl, din, output reg dout); + always @(posedge clock) begin + if (1'b1) begin + if (1'b0) begin end else begin + dout <= 0; + end + if (ctrl) + dout <= din; + end + end +endmodule + +module gate (input clock, ctrl, din, output reg dout); + always @(posedge clock) begin + if (1'b1) begin + if (1'b0) begin end else begin + dout <= 0; + end + end + if (ctrl) + dout <= din; + end +endmodule diff --git a/tests/proc/bug_1268.ys b/tests/proc/bug_1268.ys new file mode 100644 index 000000000..b73e94449 --- /dev/null +++ b/tests/proc/bug_1268.ys @@ -0,0 +1,5 @@ +read_verilog bug_1268.v +proc +equiv_make gold gate equiv +equiv_induct +equiv_status -assert diff --git a/tests/proc/run-test.sh b/tests/proc/run-test.sh new file mode 100755 index 000000000..44ce7e674 --- /dev/null +++ b/tests/proc/run-test.sh @@ -0,0 +1,6 @@ +#!/bin/bash +set -e +for x in *.ys; do + echo "Running $x.." + ../../yosys -ql ${x%.ys}.log $x +done -- cgit v1.2.3 From 6ffb910d12a93e64182b52a58e69386851f2d595 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Tue, 20 Aug 2019 11:38:21 +0200 Subject: Add test case for real parameters Signed-off-by: Clifford Wolf --- tests/simple/realexpr.v | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) (limited to 'tests') diff --git a/tests/simple/realexpr.v b/tests/simple/realexpr.v index 5b756e6be..74ed8faa5 100644 --- a/tests/simple/realexpr.v +++ b/tests/simple/realexpr.v @@ -1,4 +1,3 @@ - module demo_001(y1, y2, y3, y4); output [7:0] y1, y2, y3, y4; @@ -22,3 +21,13 @@ module demo_002(y0, y1, y2, y3); assign y3 = 1 ? -1 : 'd0; endmodule +module demo_003(output A, B); + parameter real p = 0; + assign A = (p==1.0); + assign B = (p!="1.000000"); +endmodule + +module demo_004(output A, B, C, D); + demo_003 #(1.0) demo_real (A, B); + demo_003 #(1) demo_int (C, D); +endmodule -- cgit v1.2.3 From fce8dc7db20d722646cea83ca841160d3d07445e Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Tue, 20 Aug 2019 20:05:16 -0700 Subject: Add test --- tests/techmap/recursive.v | 8 ++++++++ tests/techmap/recursive_map.v | 4 ++++ tests/techmap/recursive_runtest.sh | 3 +++ 3 files changed, 15 insertions(+) create mode 100644 tests/techmap/recursive.v create mode 100644 tests/techmap/recursive_map.v create mode 100644 tests/techmap/recursive_runtest.sh (limited to 'tests') diff --git a/tests/techmap/recursive.v b/tests/techmap/recursive.v new file mode 100644 index 000000000..d281b21d8 --- /dev/null +++ b/tests/techmap/recursive.v @@ -0,0 +1,8 @@ +module top; +sub s0(); +foo f0(); +endmodule + +module foo; +sub s0(); +endmodule diff --git a/tests/techmap/recursive_map.v b/tests/techmap/recursive_map.v new file mode 100644 index 000000000..934256552 --- /dev/null +++ b/tests/techmap/recursive_map.v @@ -0,0 +1,4 @@ +module sub; + sub _TECHMAP_REPLACE_ (); + bar f0(); +endmodule diff --git a/tests/techmap/recursive_runtest.sh b/tests/techmap/recursive_runtest.sh new file mode 100644 index 000000000..30c79bf03 --- /dev/null +++ b/tests/techmap/recursive_runtest.sh @@ -0,0 +1,3 @@ +set -ev + +../../yosys -p 'hierarchy -top top; techmap -map recursive_map.v -max_iter 1; select -assert-count 2 t:sub; select -assert-count 2 t:bar' recursive.v -- cgit v1.2.3 From a6776ee35ee5404ca7d5b63fd2daccc46354112c Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Wed, 21 Aug 2019 13:36:01 -0700 Subject: mem2reg to preserve user attributes and src --- tests/various/mem2reg.ys | 13 +++++++++++++ 1 file changed, 13 insertions(+) create mode 100644 tests/various/mem2reg.ys (limited to 'tests') diff --git a/tests/various/mem2reg.ys b/tests/various/mem2reg.ys new file mode 100644 index 000000000..00389c700 --- /dev/null +++ b/tests/various/mem2reg.ys @@ -0,0 +1,13 @@ +read_verilog < Date: Wed, 21 Aug 2019 21:58:20 -0700 Subject: Add test --- tests/opt/opt_expr.ys | 14 ++++++++++++++ 1 file changed, 14 insertions(+) (limited to 'tests') diff --git a/tests/opt/opt_expr.ys b/tests/opt/opt_expr.ys index f0306efa1..4affc1ac8 100644 --- a/tests/opt/opt_expr.ys +++ b/tests/opt/opt_expr.ys @@ -221,3 +221,17 @@ check equiv_opt opt_expr -fine design -load postopt select -assert-count 1 t:$alu r:A_WIDTH=8 r:B_WIDTH=8 r:Y_WIDTH=9 %i %i %i + +########### + +design -reset +read_verilog -icells < Date: Thu, 22 Aug 2019 08:22:23 -0700 Subject: Handle $shift and Y_WIDTH > 1 as per @cliffordwolf --- tests/opt/opt_expr.ys | 44 +++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 43 insertions(+), 1 deletion(-) (limited to 'tests') diff --git a/tests/opt/opt_expr.ys b/tests/opt/opt_expr.ys index 4affc1ac8..02be20a62 100644 --- a/tests/opt/opt_expr.ys +++ b/tests/opt/opt_expr.ys @@ -226,7 +226,7 @@ select -assert-count 1 t:$alu r:A_WIDTH=8 r:B_WIDTH=8 r:Y_WIDTH=9 %i %i %i design -reset read_verilog -icells < Date: Thu, 22 Aug 2019 08:37:27 -0700 Subject: Respect opt_expr -keepdc as per @cliffordwolf --- tests/opt/opt_expr.ys | 14 ++++++++++++++ 1 file changed, 14 insertions(+) (limited to 'tests') diff --git a/tests/opt/opt_expr.ys b/tests/opt/opt_expr.ys index 02be20a62..ecc2c8da8 100644 --- a/tests/opt/opt_expr.ys +++ b/tests/opt/opt_expr.ys @@ -277,3 +277,17 @@ check equiv_opt opt_expr design -load postopt select -assert-count 1 t:$shift r:A_WIDTH=10 %i + +########### + +design -reset +read_verilog -icells < Date: Thu, 22 Aug 2019 16:42:19 -0700 Subject: In sat: 'x' in init attr should not override constant --- tests/sat/initval.v | 4 ++++ tests/sat/initval.ys | 2 +- 2 files changed, 5 insertions(+), 1 deletion(-) (limited to 'tests') diff --git a/tests/sat/initval.v b/tests/sat/initval.v index 5b661f8d6..d46ccae48 100644 --- a/tests/sat/initval.v +++ b/tests/sat/initval.v @@ -1,6 +1,7 @@ module test(input clk, input [3:0] bar, output [3:0] foo); reg [3:0] foo = 0; reg [3:0] last_bar = 0; + reg [3:0] asdf = 4'b1xxx; always @* foo[1:0] <= bar[1:0]; @@ -11,5 +12,8 @@ module test(input clk, input [3:0] bar, output [3:0] foo); always @(posedge clk) last_bar <= bar; + always @* + asdf[2:0] <= 3'b111; + assert property (foo == {last_bar[3:2], bar[1:0]}); endmodule diff --git a/tests/sat/initval.ys b/tests/sat/initval.ys index 2079d2f34..3d88aa971 100644 --- a/tests/sat/initval.ys +++ b/tests/sat/initval.ys @@ -1,4 +1,4 @@ read_verilog -sv initval.v -proc;; +proc; sat -seq 10 -prove-asserts -- cgit v1.2.3 From fe1b2337fd7950e1d563be5b8ccbaa81688261e4 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 22 Aug 2019 16:57:59 -0700 Subject: Do not propagate mem2reg attribute through to result --- tests/various/mem2reg.ys | 1 + 1 file changed, 1 insertion(+) (limited to 'tests') diff --git a/tests/various/mem2reg.ys b/tests/various/mem2reg.ys index 00389c700..85d6267c5 100644 --- a/tests/various/mem2reg.ys +++ b/tests/various/mem2reg.ys @@ -11,3 +11,4 @@ proc cd top select -assert-count 1 m:data1 a:src=< Date: Fri, 23 Aug 2019 09:11:04 -0700 Subject: Blocking assignment --- tests/sat/initval.v | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'tests') diff --git a/tests/sat/initval.v b/tests/sat/initval.v index d46ccae48..fcec9dd8c 100644 --- a/tests/sat/initval.v +++ b/tests/sat/initval.v @@ -13,7 +13,7 @@ module test(input clk, input [3:0] bar, output [3:0] foo); last_bar <= bar; always @* - asdf[2:0] <= 3'b111; + asdf[2:0] = 3'b111; assert property (foo == {last_bar[3:2], bar[1:0]}); endmodule -- cgit v1.2.3 From d62c10d641c5af4b1d395caa042681788df1aae4 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 23 Aug 2019 11:09:50 -0700 Subject: tests/techmap/run-test.sh to cope with *.ys --- tests/techmap/.gitignore | 1 + tests/techmap/run-test.sh | 24 +++++++++++++++++------- 2 files changed, 18 insertions(+), 7 deletions(-) (limited to 'tests') diff --git a/tests/techmap/.gitignore b/tests/techmap/.gitignore index 397b4a762..cfed22fc5 100644 --- a/tests/techmap/.gitignore +++ b/tests/techmap/.gitignore @@ -1 +1,2 @@ *.log +/*.mk diff --git a/tests/techmap/run-test.sh b/tests/techmap/run-test.sh index e2fc11e52..96489ff15 100755 --- a/tests/techmap/run-test.sh +++ b/tests/techmap/run-test.sh @@ -1,10 +1,20 @@ -#!/bin/bash +#!/usr/bin/env bash set -e -for x in *_runtest.sh; do - echo "Running $x.." - if ! bash $x &> ${x%.sh}.log; then - tail ${x%.sh}.log - echo ERROR - exit 1 +{ +echo "all::" +for x in *.ys; do + echo "all:: run-$x" + echo "run-$x:" + echo " @echo 'Running $x..'" + echo " @../../yosys -ql ${x%.ys}.log $x" +done +for s in *.sh; do + if [ "$s" != "run-test.sh" ]; then + echo "all:: run-$s" + echo "run-$s:" + echo " @echo 'Running $s..'" + echo " @bash $s > ${s%.sh}.log 2>&1" fi done +} > run-test.mk +exec ${MAKE:-make} -f run-test.mk -- cgit v1.2.3 From 5628e2ec53c3a1d5f1828b8f522c5c09c9856b0d Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 23 Aug 2019 11:10:02 -0700 Subject: Add simple clkbufmap tests --- tests/techmap/clkbufmap.ys | 52 ++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 52 insertions(+) create mode 100644 tests/techmap/clkbufmap.ys (limited to 'tests') diff --git a/tests/techmap/clkbufmap.ys b/tests/techmap/clkbufmap.ys new file mode 100644 index 000000000..eb8970af4 --- /dev/null +++ b/tests/techmap/clkbufmap.ys @@ -0,0 +1,52 @@ +read_verilog < Date: Fri, 23 Aug 2019 11:15:26 -0700 Subject: Check clkbuf_inhibit=1 is ignored for custom selection --- tests/techmap/clkbufmap.ys | 1 + 1 file changed, 1 insertion(+) (limited to 'tests') diff --git a/tests/techmap/clkbufmap.ys b/tests/techmap/clkbufmap.ys index eb8970af4..46ff4d694 100644 --- a/tests/techmap/clkbufmap.ys +++ b/tests/techmap/clkbufmap.ys @@ -35,6 +35,7 @@ select -assert-count 1 t:clkbuf # ---------------------- design -load ref +setattr -set clkbuf_inhibit 1 w:clk1 setattr -set buffer_type "bufg" w:clk2 clkbufmap -buf clkbuf o:i w:* a:buffer_type=none a:buffer_type=bufr %u %d select -assert-count 1 w:clk1 %a %co t:clkbuf %i -- cgit v1.2.3 From dc87372a97d515563ccccd517ef8f35662870fe6 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Sat, 24 Aug 2019 15:05:44 -0700 Subject: Wire with init on FF part, 1'bx on non-FF part --- tests/sat/initval.v | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) (limited to 'tests') diff --git a/tests/sat/initval.v b/tests/sat/initval.v index fcec9dd8c..81f71b5ba 100644 --- a/tests/sat/initval.v +++ b/tests/sat/initval.v @@ -1,4 +1,4 @@ -module test(input clk, input [3:0] bar, output [3:0] foo); +module test(input clk, input [3:0] bar, output [3:0] foo, asdf); reg [3:0] foo = 0; reg [3:0] last_bar = 0; reg [3:0] asdf = 4'b1xxx; @@ -12,6 +12,8 @@ module test(input clk, input [3:0] bar, output [3:0] foo); always @(posedge clk) last_bar <= bar; + always @(posedge clk) + asdf[3] <= bar[3]; always @* asdf[2:0] = 3'b111; -- cgit v1.2.3 From 528f1c86877d247700bd9445e03c85b3eb437b5c Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Mon, 26 Aug 2019 13:45:16 -0700 Subject: Improve tests to check that clkbuf is connected to expected --- tests/techmap/clkbufmap.ys | 27 +++++++++++++++++++++------ 1 file changed, 21 insertions(+), 6 deletions(-) (limited to 'tests') diff --git a/tests/techmap/clkbufmap.ys b/tests/techmap/clkbufmap.ys index 46ff4d694..5847c3ce5 100644 --- a/tests/techmap/clkbufmap.ys +++ b/tests/techmap/clkbufmap.ys @@ -18,9 +18,15 @@ design -save ref design -load ref clkbufmap -buf clkbuf o:i -select -assert-count 1 w:clk1 %a %co t:clkbuf %i -select -assert-count 1 w:clk2 %a %co t:clkbuf %i select -assert-count 2 t:clkbuf +select -set clk1 w:clk1 %a %co t:clkbuf %i # Find 'clk1' fanouts that are 'clkbuf' +select -assert-count 1 @clk1 # Check there is one such fanout +select -assert-count 1 @clk1 %x:+[o] %co c:s* %i # Check that the 'o' of that clkbuf drives one fanout +select -assert-count 1 @clk1 %x:+[o] %co c:s0 %i # And that one fanout is 's0' +select -set clk2 w:clk2 %a %co t:clkbuf %i +select -assert-count 1 @clk2 +select -assert-count 1 @clk2 %x:+[o] %co c:s* %i +select -assert-count 1 @clk2 %x:+[o] %co c:s1 %i # ---------------------- @@ -28,9 +34,12 @@ design -load ref setattr -set clkbuf_inhibit 0 w:clk1 setattr -set clkbuf_inhibit 1 w:clk2 clkbufmap -buf clkbuf o:i -select -assert-count 1 w:clk1 %a %co t:clkbuf %i -select -assert-count 0 w:clk2 %a %co t:clkbuf %i select -assert-count 1 t:clkbuf +select -set clk1 w:clk1 %a %co t:clkbuf %i # Find 'clk1' fanouts that are 'clkbuf' +select -assert-count 1 @clk1 # Check there is one such fanout +select -assert-count 1 @clk1 %x:+[o] %co c:s* %i # Check that the 'o' of that clkbuf drives one fanout +select -assert-count 1 @clk1 %x:+[o] %co c:s0 %i # And that one fanout is 's0' +select -assert-count 0 w:clk2 %a %co t:clkbuf %i # ---------------------- @@ -38,9 +47,15 @@ design -load ref setattr -set clkbuf_inhibit 1 w:clk1 setattr -set buffer_type "bufg" w:clk2 clkbufmap -buf clkbuf o:i w:* a:buffer_type=none a:buffer_type=bufr %u %d -select -assert-count 1 w:clk1 %a %co t:clkbuf %i -select -assert-count 1 w:clk2 %a %co t:clkbuf %i select -assert-count 2 t:clkbuf +select -set clk1 w:clk1 %a %co t:clkbuf %i # Find 'clk1' fanouts that are 'clkbuf' +select -assert-count 1 @clk1 # Check there is one such fanout +select -assert-count 1 @clk1 %x:+[o] %co c:s* %i # Check that the 'o' of that clkbuf drives one fanout +select -assert-count 1 @clk1 %x:+[o] %co c:s0 %i # And that one fanout is 's0' +select -set clk2 w:clk2 %a %co t:clkbuf %i # Find 'clk1' fanouts that are 'clkbuf' +select -assert-count 1 @clk2 # Check there is one such fanout +select -assert-count 1 @clk2 %x:+[o] %co c:s* %i # Check that the 'o' of that clkbuf drives one fanout +select -assert-count 1 @clk2 %x:+[o] %co c:s1 %i # And that one fanout is 's0' # ---------------------- -- cgit v1.2.3 From 5fb4b12cb50b870b546d76f9c702678d8f0aa60a Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Marcin=20Ko=C5=9Bcielnicki?= Date: Tue, 27 Aug 2019 17:26:47 +0200 Subject: improve clkbuf_inhibit propagation upwards through hierarchy --- tests/techmap/clkbufmap.ys | 38 +++++++++++++++++++++++++++++++++----- 1 file changed, 33 insertions(+), 5 deletions(-) (limited to 'tests') diff --git a/tests/techmap/clkbufmap.ys b/tests/techmap/clkbufmap.ys index 5847c3ce5..f1277864e 100644 --- a/tests/techmap/clkbufmap.ys +++ b/tests/techmap/clkbufmap.ys @@ -3,11 +3,26 @@ module clkbuf (input i, (* clkbuf_driver *) output o); endmodule module dff ((* clkbuf_sink *) input clk, input d, output q); endmodule module dffe ((* clkbuf_sink *) input c, input d, e, output q); endmodule module latch (input e, d, output q); endmodule +module clkgen (output o); endmodule -module top(input clk1, clk2, clk3, d, e, output [2:0] q); +module top(input clk1, clk2, clk3, d, e, output [4:0] q); +wire clk4, clk5, clk6; dff s0 (.clk(clk1), .d(d), .q(q[0])); dffe s1 (.c(clk2), .d(d), .e(e), .q(q[1])); latch s2 (.e(clk3), .d(d), .q(q[2])); +sub s3 (.sclk4(clk4), .sclk5(clk5), .sclk6(clk6), .sd(d), .sq(q[3])); +dff s4 (.clk(clk4), .d(d), .q(q[4])); +dff s5 (.clk(clk5), .d(d), .q(q[4])); +dff s6 (.clk(clk6), .d(d), .q(q[4])); +endmodule + +module sub(output sclk4, output sclk5, output sclk6, input sd, output sq); +wire tmp; +clkgen s7(.o(sclk4)); +clkgen s8(.o(sclk5)); +clkgen s9(.o(tmp)); +clkbuf s10(.i(tmp), .o(sclk6)); +dff s11(.clk(sclk4), .d(sd), .q(sq)); endmodule EOT @@ -18,7 +33,8 @@ design -save ref design -load ref clkbufmap -buf clkbuf o:i -select -assert-count 2 t:clkbuf +select -assert-count 3 top/t:clkbuf +select -assert-count 2 sub/t:clkbuf select -set clk1 w:clk1 %a %co t:clkbuf %i # Find 'clk1' fanouts that are 'clkbuf' select -assert-count 1 @clk1 # Check there is one such fanout select -assert-count 1 @clk1 %x:+[o] %co c:s* %i # Check that the 'o' of that clkbuf drives one fanout @@ -27,6 +43,14 @@ select -set clk2 w:clk2 %a %co t:clkbuf %i select -assert-count 1 @clk2 select -assert-count 1 @clk2 %x:+[o] %co c:s* %i select -assert-count 1 @clk2 %x:+[o] %co c:s1 %i +select -set clk5 w:clk5 %a %ci t:clkbuf %i +select -assert-count 1 @clk5 +select -assert-count 1 @clk5 %x:+[o] %co c:s5 %i +select -assert-count 1 @clk5 %x:+[i] %ci c:s3 %i +select -set sclk4 w:sclk4 %a %ci t:clkbuf %i +select -assert-count 1 @sclk4 +select -assert-count 1 @sclk4 %x:+[o] %co c:s11 %i +select -assert-count 1 @sclk4 %x:+[i] %ci c:s7 %i # ---------------------- @@ -34,7 +58,7 @@ design -load ref setattr -set clkbuf_inhibit 0 w:clk1 setattr -set clkbuf_inhibit 1 w:clk2 clkbufmap -buf clkbuf o:i -select -assert-count 1 t:clkbuf +select -assert-count 2 top/t:clkbuf select -set clk1 w:clk1 %a %co t:clkbuf %i # Find 'clk1' fanouts that are 'clkbuf' select -assert-count 1 @clk1 # Check there is one such fanout select -assert-count 1 @clk1 %x:+[o] %co c:s* %i # Check that the 'o' of that clkbuf drives one fanout @@ -47,7 +71,8 @@ design -load ref setattr -set clkbuf_inhibit 1 w:clk1 setattr -set buffer_type "bufg" w:clk2 clkbufmap -buf clkbuf o:i w:* a:buffer_type=none a:buffer_type=bufr %u %d -select -assert-count 2 t:clkbuf +select -assert-count 3 top/t:clkbuf +select -assert-count 2 sub/t:clkbuf select -set clk1 w:clk1 %a %co t:clkbuf %i # Find 'clk1' fanouts that are 'clkbuf' select -assert-count 1 @clk1 # Check there is one such fanout select -assert-count 1 @clk1 %x:+[o] %co c:s* %i # Check that the 'o' of that clkbuf drives one fanout @@ -62,7 +87,10 @@ select -assert-count 1 @clk2 %x:+[o] %co c:s1 %i # And that one fanout is 's0 design -load ref setattr -set buffer_type "none" w:clk1 setattr -set buffer_type "bufr" w:clk2 +setattr -set buffer_type "bufr" w:sclk4 +setattr -set buffer_type "bufr" w:sclk5 clkbufmap -buf clkbuf o:i w:* a:buffer_type=none a:buffer_type=bufr %u %d select -assert-count 0 w:clk1 %a %co t:clkbuf %i select -assert-count 0 w:clk2 %a %co t:clkbuf %i -select -assert-count 0 t:clkbuf +select -assert-count 0 top/t:clkbuf +select -assert-count 1 sub/t:clkbuf -- cgit v1.2.3 From 00387f39277ab817b3b17e72b59793e6d5dfcde8 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Tue, 27 Aug 2019 09:24:32 -0700 Subject: Revert to using clean --- tests/sat/initval.ys | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'tests') diff --git a/tests/sat/initval.ys b/tests/sat/initval.ys index 3d88aa971..2079d2f34 100644 --- a/tests/sat/initval.ys +++ b/tests/sat/initval.ys @@ -1,4 +1,4 @@ read_verilog -sv initval.v -proc; +proc;; sat -seq 10 -prove-asserts -- cgit v1.2.3 From dd42aa87b9b3bb041cbfe49079c6538f0a6d5646 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Wed, 28 Aug 2019 18:34:32 -0700 Subject: Add ice40_opt test --- tests/ice40/ice40_opt.ys | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) create mode 100644 tests/ice40/ice40_opt.ys (limited to 'tests') diff --git a/tests/ice40/ice40_opt.ys b/tests/ice40/ice40_opt.ys new file mode 100644 index 000000000..18e0d2b8a --- /dev/null +++ b/tests/ice40/ice40_opt.ys @@ -0,0 +1,24 @@ +read_verilog -icells -formal < Date: Wed, 28 Aug 2019 18:44:57 -0700 Subject: Add SB_CARRY to ice40_opt test --- tests/ice40/ice40_opt.ys | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) (limited to 'tests') diff --git a/tests/ice40/ice40_opt.ys b/tests/ice40/ice40_opt.ys index 18e0d2b8a..b17c69c91 100644 --- a/tests/ice40/ice40_opt.ys +++ b/tests/ice40/ice40_opt.ys @@ -1,5 +1,5 @@ read_verilog -icells -formal < Date: Wed, 28 Aug 2019 18:47:48 -0700 Subject: Add run-test.sh too --- tests/ice40/run-test.sh | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) create mode 100755 tests/ice40/run-test.sh (limited to 'tests') diff --git a/tests/ice40/run-test.sh b/tests/ice40/run-test.sh new file mode 100755 index 000000000..ea56b70f0 --- /dev/null +++ b/tests/ice40/run-test.sh @@ -0,0 +1,20 @@ +#!/usr/bin/env bash +set -e +{ +echo "all::" +for x in *.ys; do + echo "all:: run-$x" + echo "run-$x:" + echo " @echo 'Running $x..'" + echo " @../../yosys -ql ${x%.ys}.log $x" +done +for s in *.sh; do + if [ "$s" != "run-test.sh" ]; then + echo "all:: run-$s" + echo "run-$s:" + echo " @echo 'Running $s..'" + echo " @bash $s" + fi +done +} > run-test.mk +exec ${MAKE:-make} -f run-test.mk -- cgit v1.2.3