From ad6c49fff12e27d99c1fc15850857e5129dd76ee Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 17 Jan 2020 15:38:26 -0800
Subject: ice40_dsp: add test

---
 tests/arch/ice40/ice40_dsp.ys | 11 +++++++++++
 1 file changed, 11 insertions(+)
 create mode 100644 tests/arch/ice40/ice40_dsp.ys

(limited to 'tests')

diff --git a/tests/arch/ice40/ice40_dsp.ys b/tests/arch/ice40/ice40_dsp.ys
new file mode 100644
index 000000000..250273859
--- /dev/null
+++ b/tests/arch/ice40/ice40_dsp.ys
@@ -0,0 +1,11 @@
+read_verilog <<EOT
+module top(input [15:0] a, b, output [31:0] o1, o2, o5);
+SB_MAC16 m1 (.A(a), .B(16'd1234), .O(o1));
+assign o2 = a * 16'd0;
+wire [31:0] o3, o4;
+SB_MAC16 m2 (.A(a), .B(b), .O(o3));
+assign o4 = a * b;
+SB_MAC16 m3 (.A(a), .B(b), .O(o5));
+endmodule
+EOT
+ice40_dsp
-- 
cgit v1.2.3


From 5507c328fff7b534abcba4186b2e5b1e26c4ad5e Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 17 Jan 2020 15:57:52 -0800
Subject: Add #1644 testcase

---
 tests/arch/ice40/bug1644.il.gz | Bin 0 -> 25669 bytes
 tests/arch/ice40/bug1644.ys    |   2 ++
 2 files changed, 2 insertions(+)
 create mode 100644 tests/arch/ice40/bug1644.il.gz
 create mode 100644 tests/arch/ice40/bug1644.ys

(limited to 'tests')

diff --git a/tests/arch/ice40/bug1644.il.gz b/tests/arch/ice40/bug1644.il.gz
new file mode 100644
index 000000000..363c510ef
Binary files /dev/null and b/tests/arch/ice40/bug1644.il.gz differ
diff --git a/tests/arch/ice40/bug1644.ys b/tests/arch/ice40/bug1644.ys
new file mode 100644
index 000000000..5950f0e3c
--- /dev/null
+++ b/tests/arch/ice40/bug1644.ys
@@ -0,0 +1,2 @@
+read_ilang bug1644.il.gz
+synth_ice40 -top top -dsp -json adc_dac_pass_through.json -run :map_bram
-- 
cgit v1.2.3


From db68e4c2a7a39eda46863fba8b8c8313a831f606 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 17 Jan 2020 16:08:04 -0800
Subject: ice40_dsp: fix typo

---
 tests/arch/xilinx/xilinx_dsp.ys | 11 +++++++++++
 1 file changed, 11 insertions(+)
 create mode 100644 tests/arch/xilinx/xilinx_dsp.ys

(limited to 'tests')

diff --git a/tests/arch/xilinx/xilinx_dsp.ys b/tests/arch/xilinx/xilinx_dsp.ys
new file mode 100644
index 000000000..3b9f52930
--- /dev/null
+++ b/tests/arch/xilinx/xilinx_dsp.ys
@@ -0,0 +1,11 @@
+read_verilog <<EOT
+module top(input [24:0] a, input [17:0] b, output [42:0] o1, o2, o5);
+DSP48E1 m1 (.A(a), .B(16'd1234), .P(o1));
+assign o2 = a * 16'd0;
+wire [42:0] o3, o4;
+DSP48E1 m2 (.A(a), .B(b), .P(o3));
+assign o4 = a * b;
+DSP48E1 m3 (.A(a), .B(b), .P(o5));
+endmodule
+EOT
+xilinx_dsp
-- 
cgit v1.2.3


From 6a163b5ddd378ba847054ad9226af8ca569c977a Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 17 Jan 2020 17:07:03 -0800
Subject: xilinx_dsp: another typo; move xilinx specific test

---
 tests/arch/xilinx/bug1462.ys | 11 +++++++++++
 tests/various/bug1462.ys     | 11 -----------
 2 files changed, 11 insertions(+), 11 deletions(-)
 create mode 100644 tests/arch/xilinx/bug1462.ys
 delete mode 100644 tests/various/bug1462.ys

(limited to 'tests')

diff --git a/tests/arch/xilinx/bug1462.ys b/tests/arch/xilinx/bug1462.ys
new file mode 100644
index 000000000..15cab5121
--- /dev/null
+++ b/tests/arch/xilinx/bug1462.ys
@@ -0,0 +1,11 @@
+read_verilog << EOF
+module top(...);
+input wire [31:0] A;
+output wire [31:0] P;
+
+assign P = A * 32'h12300000;
+
+endmodule
+EOF
+
+synth_xilinx
diff --git a/tests/various/bug1462.ys b/tests/various/bug1462.ys
deleted file mode 100644
index 15cab5121..000000000
--- a/tests/various/bug1462.ys
+++ /dev/null
@@ -1,11 +0,0 @@
-read_verilog << EOF
-module top(...);
-input wire [31:0] A;
-output wire [31:0] P;
-
-assign P = A * 32'h12300000;
-
-endmodule
-EOF
-
-synth_xilinx
-- 
cgit v1.2.3