From 6378e2cd46711fed551ecf3201cee1f174d7053d Mon Sep 17 00:00:00 2001 From: Udi Finkelstein Date: Sun, 4 Mar 2018 23:35:08 +0200 Subject: First draft of Verilog parser support for specify blocks and parameters. The only functionality of this code at the moment is to accept correct specify syntax and ignore it. No part of the specify block is added to the AST --- tests/simple/specify.v | 31 +++++++++++++++++++++++++++++++ 1 file changed, 31 insertions(+) create mode 100644 tests/simple/specify.v (limited to 'tests') diff --git a/tests/simple/specify.v b/tests/simple/specify.v new file mode 100644 index 000000000..74563509e --- /dev/null +++ b/tests/simple/specify.v @@ -0,0 +1,31 @@ +module test_specify; + +specparam a=1; + +specify +endspecify + +specify +(A => B) = ( 1 ) ; +(A- => B) = ( 1,2 ) ; +(A+ => B) = ( 1,2,3 ) ; +(A => B) = ( + 1.1, 2, 3, + 4, 5.5, 6.6 +) ; +(A => B) = ( + 1.1, 2, 3, + 4, 5.5, 6.6 , + 7.7, 8.8, 9, + 10.1, 11, 12 +) ; +specparam a=1; +specparam [1:2] asasa=1; +endspecify + +specify +specparam a=1:2:3; +endspecify + +endmodule + -- cgit v1.2.3