From b11cf67a8170ee830beedadc7156c4e83e4f1134 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Mon, 11 May 2020 10:30:20 -0700
Subject: Setup tests/verilog properly

---
 tests/verilog/.gitignore  |  3 +++
 tests/verilog/run-test.sh | 20 ++++++++++++++++++++
 2 files changed, 23 insertions(+)
 create mode 100644 tests/verilog/.gitignore
 create mode 100755 tests/verilog/run-test.sh

(limited to 'tests')

diff --git a/tests/verilog/.gitignore b/tests/verilog/.gitignore
new file mode 100644
index 000000000..b48f808a1
--- /dev/null
+++ b/tests/verilog/.gitignore
@@ -0,0 +1,3 @@
+/*.log
+/*.out
+/run-test.mk
diff --git a/tests/verilog/run-test.sh b/tests/verilog/run-test.sh
new file mode 100755
index 000000000..ea56b70f0
--- /dev/null
+++ b/tests/verilog/run-test.sh
@@ -0,0 +1,20 @@
+#!/usr/bin/env bash
+set -e
+{
+echo "all::"
+for x in *.ys; do
+	echo "all:: run-$x"
+	echo "run-$x:"
+	echo "	@echo 'Running $x..'"
+	echo "	@../../yosys -ql ${x%.ys}.log $x"
+done
+for s in *.sh; do
+	if [ "$s" != "run-test.sh" ]; then
+		echo "all:: run-$s"
+		echo "run-$s:"
+		echo "	@echo 'Running $s..'"
+		echo "	@bash $s"
+	fi
+done
+} > run-test.mk
+exec ${MAKE:-make} -f run-test.mk
-- 
cgit v1.2.3


From e5ce5a4fd532f35cf8dd625b97aa426e4661e119 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Mon, 11 May 2020 11:05:19 -0700
Subject: tests: add #2042 testcase

---
 tests/verilog/bug2042.ys | 12 ++++++++++++
 1 file changed, 12 insertions(+)
 create mode 100644 tests/verilog/bug2042.ys

(limited to 'tests')

diff --git a/tests/verilog/bug2042.ys b/tests/verilog/bug2042.ys
new file mode 100644
index 000000000..009e2c20c
--- /dev/null
+++ b/tests/verilog/bug2042.ys
@@ -0,0 +1,12 @@
+logger -expect error "Non-ANSI style task/function arguments not currently supported" 1
+read_verilog <<EOT
+module Task_Test_Top
+(
+);
+
+    task SomeTaskName(a)
+    endtask
+
+endmodule
+EOT
+
-- 
cgit v1.2.3


From 0d2c33f9f4f8ca1bb507e3e688e0c7d372f0247b Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 13 May 2020 10:11:45 -0700
Subject: tests: update/extend task argument tests

---
 tests/verilog/bug2042-sv.ys | 34 ++++++++++++++++++++++++++++++++++
 tests/verilog/bug2042.ys    |  3 +--
 2 files changed, 35 insertions(+), 2 deletions(-)
 create mode 100644 tests/verilog/bug2042-sv.ys

(limited to 'tests')

diff --git a/tests/verilog/bug2042-sv.ys b/tests/verilog/bug2042-sv.ys
new file mode 100644
index 000000000..9a0d419c8
--- /dev/null
+++ b/tests/verilog/bug2042-sv.ys
@@ -0,0 +1,34 @@
+read_verilog -sv <<EOT
+module Task_Test_Top
+(
+input a,
+output b
+);
+
+    task SomeTaskName(a);
+       b = ~a;
+    endtask
+
+    always @*
+        SomeTaskName(a);
+
+    assert property (b == ~a);
+
+endmodule
+EOT
+proc
+sat -verify -prove-asserts
+
+
+design -reset
+logger -expect error "syntax error, unexpected TOK_ENDTASK, expecting ';'" 1
+read_verilog -sv <<EOT
+module Task_Test_Top
+(
+);
+
+    task SomeTaskName(a)
+    endtask
+
+endmodule
+EOT
diff --git a/tests/verilog/bug2042.ys b/tests/verilog/bug2042.ys
index 009e2c20c..f9d8e2837 100644
--- a/tests/verilog/bug2042.ys
+++ b/tests/verilog/bug2042.ys
@@ -1,4 +1,4 @@
-logger -expect error "Non-ANSI style task/function arguments not currently supported" 1
+logger -expect error "task/function argument direction missing" 1
 read_verilog <<EOT
 module Task_Test_Top
 (
@@ -9,4 +9,3 @@ module Task_Test_Top
 
 endmodule
 EOT
-
-- 
cgit v1.2.3


From 56a5b1d2daf1b244990d81f32183034071ebd185 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 14 May 2020 08:36:36 -0700
Subject: test: add another testcase as per @nakengelhardt

---
 tests/verilog/bug2042-sv.ys | 25 +++++++++++++++++++++++++
 1 file changed, 25 insertions(+)

(limited to 'tests')

diff --git a/tests/verilog/bug2042-sv.ys b/tests/verilog/bug2042-sv.ys
index 9a0d419c8..e815d7fc5 100644
--- a/tests/verilog/bug2042-sv.ys
+++ b/tests/verilog/bug2042-sv.ys
@@ -20,6 +20,31 @@ proc
 sat -verify -prove-asserts
 
 
+design -reset
+read_verilog -sv <<EOT
+module Task_Test_Top
+(
+input a,
+output b, c
+);
+
+    task SomeTaskName(x, output y, z);
+       y = ~x;
+       z = x;
+    endtask
+
+    always @*
+        SomeTaskName(a, b, c);
+
+    assert property (b == ~a);
+    assert property (c == a);
+
+endmodule
+EOT
+proc
+sat -verify -prove-asserts
+
+
 design -reset
 logger -expect error "syntax error, unexpected TOK_ENDTASK, expecting ';'" 1
 read_verilog -sv <<EOT
-- 
cgit v1.2.3