From 1ecf6aee9b331efebeca1bd95a3d5125abf8da50 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Wed, 21 Sep 2022 15:46:43 +0200 Subject: Test fixes for latest iverilog --- tests/simple/memory.v | 14 ++++++++++++-- 1 file changed, 12 insertions(+), 2 deletions(-) (limited to 'tests') diff --git a/tests/simple/memory.v b/tests/simple/memory.v index f38bdafd3..b478d9409 100644 --- a/tests/simple/memory.v +++ b/tests/simple/memory.v @@ -137,8 +137,13 @@ endmodule // ---------------------------------------------------------- -module memtest06_sync(input clk, input rst, input [2:0] idx, input [7:0] din, output [7:0] dout); +module memtest06_sync(clk, rst, idx, din, dout); + input clk; + input rst; (* gentb_constant=0 *) wire rst; + input [2:0] idx; + input [7:0] din; + output [7:0] dout; reg [7:0] test [0:7]; integer i; always @(posedge clk) begin @@ -156,8 +161,13 @@ module memtest06_sync(input clk, input rst, input [2:0] idx, input [7:0] din, ou assign dout = test[idx]; endmodule -module memtest06_async(input clk, input rst, input [2:0] idx, input [7:0] din, output [7:0] dout); +module memtest06_async(clk, rst, idx, din, dout); + input clk; + input rst; (* gentb_constant=0 *) wire rst; + input [2:0] idx; + input [7:0] din; + output [7:0] dout; reg [7:0] test [0:7]; integer i; always @(posedge clk or posedge rst) begin -- cgit v1.2.3