From 8b239ee707a2bf4a868728046d7f64c16d74aa2a Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Mon, 30 Sep 2019 15:34:04 -0700
Subject: Add quick test

---
 tests/techmap/aigmap.ys | 10 ++++++++++
 1 file changed, 10 insertions(+)
 create mode 100644 tests/techmap/aigmap.ys

(limited to 'tests')

diff --git a/tests/techmap/aigmap.ys b/tests/techmap/aigmap.ys
new file mode 100644
index 000000000..a40aa39f1
--- /dev/null
+++ b/tests/techmap/aigmap.ys
@@ -0,0 +1,10 @@
+read_verilog <<EOT
+module top(input i, j, s, output o, p);
+assign o = s ? j : i;
+assign p = ~i;
+endmodule
+EOT
+
+select t:$mux
+aigmap -select
+select -assert-any %
-- 
cgit v1.2.3


From 369652d4b99181e2f7b875b6c458c1a5a3b0381e Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Mon, 30 Sep 2019 17:20:39 -0700
Subject: Add test

---
 tests/techmap/techmap_replace.ys | 16 ++++++++++++++++
 1 file changed, 16 insertions(+)
 create mode 100644 tests/techmap/techmap_replace.ys

(limited to 'tests')

diff --git a/tests/techmap/techmap_replace.ys b/tests/techmap/techmap_replace.ys
new file mode 100644
index 000000000..ee5c6bc7e
--- /dev/null
+++ b/tests/techmap/techmap_replace.ys
@@ -0,0 +1,16 @@
+read_verilog <<EOT
+module sub(input i, output o, input j);
+foobar _TECHMAP_REPLACE_(i, o, j);
+wire _TECHMAP_REPLACE_.asdf = i ;
+endmodule
+EOT
+design -stash techmap
+
+read_verilog <<EOT
+module top(input i, output o);
+sub s0(i, o);
+endmodule
+EOT
+
+techmap -map %techmap
+select -assert-any w:s0.asdf
-- 
cgit v1.2.3


From a4f2f7d23cb27f7677236d7a1823f36215c874e9 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 2 Oct 2019 12:43:18 -0700
Subject: Extend test with renaming cells with prefix too

---
 tests/techmap/techmap_replace.ys | 2 ++
 1 file changed, 2 insertions(+)

(limited to 'tests')

diff --git a/tests/techmap/techmap_replace.ys b/tests/techmap/techmap_replace.ys
index ee5c6bc7e..c2f42d50b 100644
--- a/tests/techmap/techmap_replace.ys
+++ b/tests/techmap/techmap_replace.ys
@@ -2,6 +2,7 @@ read_verilog <<EOT
 module sub(input i, output o, input j);
 foobar _TECHMAP_REPLACE_(i, o, j);
 wire _TECHMAP_REPLACE_.asdf = i ;
+barfoo _TECHMAP_REPLACE_.blah (i, o, j);
 endmodule
 EOT
 design -stash techmap
@@ -14,3 +15,4 @@ EOT
 
 techmap -map %techmap
 select -assert-any w:s0.asdf
+select -assert-any c:s0.blah
-- 
cgit v1.2.3