From bfd71e09906096c72039beebb1b3b6a79dd6b36c Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Tue, 23 Apr 2019 16:11:14 -0700
Subject: Fix abc9 with (* keep *) wires

---
 tests/simple_abc9/abc9.v | 38 ++++++++++++++++++++++++++++++++++++++
 1 file changed, 38 insertions(+)

(limited to 'tests')

diff --git a/tests/simple_abc9/abc9.v b/tests/simple_abc9/abc9.v
index eca340693..f37d975ff 100644
--- a/tests/simple_abc9/abc9.v
+++ b/tests/simple_abc9/abc9.v
@@ -104,3 +104,41 @@ always @(io or oe)
 assign io[3:0] = oe ? ~latch[3:0] : 4'bz;
 assign io[7:4] = !oe ? {latch[4], latch[7:3]} : 4'bz;
 endmodule
+
+module abc9_test015(input a, output b, input c);
+assign b = ~a;
+(* keep *) wire d;
+assign d = ~c;
+endmodule
+
+module abc9_test016(input a, output b);
+assign b = ~a;
+(* keep *) reg c;
+always @* c <= ~a;
+endmodule
+
+module abc9_test017(input a, output b);
+assign b = ~a;
+(* keep *) reg c;
+always @* c = b;
+endmodule
+
+module abc9_test018(input a, output b, output c);
+assign b = ~a;
+(* keep *) wire [1:0] d;
+assign c = &d;
+endmodule
+
+module abc9_test019(input a, output b);
+assign b = ~a;
+(* keep *) reg [1:0] c;
+reg d;
+always @* d <= &c;
+endmodule
+
+module abc9_test020(input a, output b);
+assign b = ~a;
+(* keep *) reg [1:0] c;
+(* keep *) reg d;
+always @* d <= &c;
+endmodule
-- 
cgit v1.2.3


From eec314e2621d3d055d7810f4b7e573a99e0239b2 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 24 Apr 2019 21:06:53 -0700
Subject: Remove topo sort no-loop assertion, with test

---
 tests/simple_abc9/abc.box     |  2 ++
 tests/simple_abc9/abc9.v      | 73 +++++++++++++++++++++++++++++++++++++++++++
 tests/simple_abc9/run-test.sh |  2 +-
 3 files changed, 76 insertions(+), 1 deletion(-)
 create mode 100644 tests/simple_abc9/abc.box

(limited to 'tests')

diff --git a/tests/simple_abc9/abc.box b/tests/simple_abc9/abc.box
new file mode 100644
index 000000000..a8801d807
--- /dev/null
+++ b/tests/simple_abc9/abc.box
@@ -0,0 +1,2 @@
+MUXF8 1 0 3 1
+1 1 1
diff --git a/tests/simple_abc9/abc9.v b/tests/simple_abc9/abc9.v
index f37d975ff..fb5b759fb 100644
--- a/tests/simple_abc9/abc9.v
+++ b/tests/simple_abc9/abc9.v
@@ -142,3 +142,76 @@ assign b = ~a;
 (* keep *) reg d;
 always @* d <= &c;
 endmodule
+
+module abc9_test021(clk, rst, s_eth_hdr_valid, s_eth_hdr_ready, s_eth_dest_mac, s_eth_src_mac, s_eth_type, s_eth_payload_axis_tdata, s_eth_payload_axis_tkeep, s_eth_payload_axis_tvalid, s_eth_payload_axis_tready, s_eth_payload_axis_tlast, s_eth_payload_axis_tid, s_eth_payload_axis_tdest, s_eth_payload_axis_tuser, m_eth_hdr_valid, m_eth_hdr_ready, m_eth_dest_mac, m_eth_src_mac, m_eth_type, m_eth_payload_axis_tdata, m_eth_payload_axis_tkeep, m_eth_payload_axis_tvalid, m_eth_payload_axis_tready, m_eth_payload_axis_tlast, m_eth_payload_axis_tid, m_eth_payload_axis_tdest, m_eth_payload_axis_tuser);
+  input clk;
+  output [47:0] m_eth_dest_mac;
+  input m_eth_hdr_ready;
+  output m_eth_hdr_valid;
+  output [7:0] m_eth_payload_axis_tdata;
+  output [7:0] m_eth_payload_axis_tdest;
+  output [7:0] m_eth_payload_axis_tid;
+  output m_eth_payload_axis_tkeep;
+  output m_eth_payload_axis_tlast;
+  input m_eth_payload_axis_tready;
+  output m_eth_payload_axis_tuser;
+  output m_eth_payload_axis_tvalid;
+  output [47:0] m_eth_src_mac;
+  output [15:0] m_eth_type;
+  input rst;
+  input [191:0] s_eth_dest_mac;
+  output [3:0] s_eth_hdr_ready;
+  input [3:0] s_eth_hdr_valid;
+  input [31:0] s_eth_payload_axis_tdata;
+  input [31:0] s_eth_payload_axis_tdest;
+  input [31:0] s_eth_payload_axis_tid;
+  input [3:0] s_eth_payload_axis_tkeep;
+  input [3:0] s_eth_payload_axis_tlast;
+  output [3:0] s_eth_payload_axis_tready;
+  input [3:0] s_eth_payload_axis_tuser;
+  input [3:0] s_eth_payload_axis_tvalid;
+  input [191:0] s_eth_src_mac;
+  input [63:0] s_eth_type;
+  (* keep *)
+  wire [0:0] grant, request;
+  wire a;
+  not u0 (
+    a,
+    grant[0]
+  );
+  and u1  (
+    request[0],
+    s_eth_hdr_valid[0],
+    a
+  );
+  (* keep *)
+  MUXF8 u2  (
+    .I0(1'bx),
+    .I1(1'bx),
+    .O(o),
+    .S(1'bx)
+  );
+  arbiter  arb_inst (
+    .acknowledge(acknowledge),
+    .clk(clk),
+    .grant(grant),
+    .grant_encoded(grant_encoded),
+    .grant_valid(grant_valid),
+    .request(request),
+    .rst(rst)
+  );
+endmodule
+
+module arbiter (clk, rst, request, acknowledge, grant, grant_valid, grant_encoded);
+  input [3:0] acknowledge;
+  input clk;
+  output [3:0] grant;
+  output [1:0] grant_encoded;
+  output grant_valid;
+  input [3:0] request;
+  input rst;
+endmodule
+
+(* abc_box_id=1 *)
+module MUXF8(input I0, I1, S, output O);
+endmodule
diff --git a/tests/simple_abc9/run-test.sh b/tests/simple_abc9/run-test.sh
index 97f284378..4935d41ad 100755
--- a/tests/simple_abc9/run-test.sh
+++ b/tests/simple_abc9/run-test.sh
@@ -19,4 +19,4 @@ fi
 
 cp ../simple/*.v .
 DOLLAR='?'
-exec ${MAKE:-make} -f ../tools/autotest.mk $seed *.v EXTRA_FLAGS="-p 'hierarchy; synth -run coarse; techmap; opt -full; abc9 -lut 4; stat; check -assert; select -assert-none t:${DOLLAR}_NOT_ t:${DOLLAR}_AND_ %%'"
+exec ${MAKE:-make} -f ../tools/autotest.mk $seed *.v EXTRA_FLAGS="-p 'hierarchy; synth -run coarse; opt -full; techmap; abc9 -lut 4 -box ../abc.box; stat; check -assert; select -assert-none t:${DOLLAR}_NOT_ t:${DOLLAR}_AND_ %%'"
-- 
cgit v1.2.3


From 0eb7150a5706e81ff36a6a57d8c0c6a2fda05e07 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 25 Apr 2019 18:08:05 -0700
Subject: Add test

---
 tests/various/split_shiftx.v  | 118 ++++++++++++++++++++++++++++++++++++++++++
 tests/various/split_shiftx.ys |  21 ++++++++
 2 files changed, 139 insertions(+)
 create mode 100644 tests/various/split_shiftx.v
 create mode 100644 tests/various/split_shiftx.ys

(limited to 'tests')

diff --git a/tests/various/split_shiftx.v b/tests/various/split_shiftx.v
new file mode 100644
index 000000000..dfcea3880
--- /dev/null
+++ b/tests/various/split_shiftx.v
@@ -0,0 +1,118 @@
+module split_shiftx_test01(i, s, o);
+  wire [3:0] _0_;
+  input [8:0] i;
+  output [2:0] o;
+  input [1:0] s;
+  \$macc  #(
+    .A_WIDTH(32'd4),
+    .B_WIDTH(32'd0),
+    .CONFIG(10'h282),
+    .CONFIG_WIDTH(32'd10),
+    .Y_WIDTH(32'd4)
+  ) _1_ (
+    .A({ 2'h3, s }),
+    .B(),
+    .Y(_0_)
+  );
+  \$shiftx  #(
+    .A_SIGNED(32'd0),
+    .A_WIDTH(32'd9),
+    .B_SIGNED(32'd1),
+    .B_WIDTH(32'd5),
+    .Y_WIDTH(32'd3)
+  ) _2_ (
+    .A(i),
+    .B({ 1'h0, _0_ }),
+    .Y(o)
+  );
+endmodule
+
+// Sign bit is 1
+module split_shiftx_test02(i, s, o);
+  wire [3:0] _0_;
+  input [8:0] i;
+  output [2:0] o;
+  input [1:0] s;
+  \$macc  #(
+    .A_WIDTH(32'd4),
+    .B_WIDTH(32'd0),
+    .CONFIG(10'h282),
+    .CONFIG_WIDTH(32'd10),
+    .Y_WIDTH(32'd4)
+  ) _1_ (
+    .A({ 2'h3, s }),
+    .B(),
+    .Y(_0_)
+  );
+  \$shiftx  #(
+    .A_SIGNED(32'd0),
+    .A_WIDTH(32'd9),
+    .B_SIGNED(32'd1),
+    .B_WIDTH(32'd5),
+    .Y_WIDTH(32'd3)
+  ) _2_ (
+    .A(i),
+    .B({ 1'h1, _0_ }),
+    .Y(o)
+  );
+endmodule
+
+// Non constant $macc
+module split_shiftx_test03(i, s, o);
+  wire [3:0] _0_;
+  input [8:0] i;
+  output [2:0] o;
+  input [1:0] s;
+  \$macc  #(
+    .A_WIDTH(32'd4),
+    .B_WIDTH(32'd0),
+    .CONFIG(10'h282),
+    .CONFIG_WIDTH(32'd10),
+    .Y_WIDTH(32'd4)
+  ) _1_ (
+    .A({ s, s }),
+    .B(),
+    .Y(_0_)
+  );
+  \$shiftx  #(
+    .A_SIGNED(32'd0),
+    .A_WIDTH(32'd9),
+    .B_SIGNED(32'd1),
+    .B_WIDTH(32'd5),
+    .Y_WIDTH(32'd3)
+  ) _2_ (
+    .A(i),
+    .B({ 1'h0, _0_ }),
+    .Y(o)
+  );
+endmodule
+
+// Wrong constant $macc
+module split_shiftx_test04(i, s, o);
+  wire [3:0] _0_;
+  input [8:0] i;
+  output [2:0] o;
+  input [1:0] s;
+  \$macc  #(
+    .A_WIDTH(32'd4),
+    .B_WIDTH(32'd0),
+    .CONFIG(10'h282),
+    .CONFIG_WIDTH(32'd10),
+    .Y_WIDTH(32'd4)
+  ) _1_ (
+    .A({ 2'h2, s }),
+    .B(),
+    .Y(_0_)
+  );
+  \$shiftx  #(
+    .A_SIGNED(32'd0),
+    .A_WIDTH(32'd9),
+    .B_SIGNED(32'd1),
+    .B_WIDTH(32'd5),
+    .Y_WIDTH(32'd3)
+  ) _2_ (
+    .A(i),
+    .B({ 1'h0, _0_ }),
+    .Y(o)
+  );
+endmodule
diff --git a/tests/various/split_shiftx.ys b/tests/various/split_shiftx.ys
new file mode 100644
index 000000000..810348aa3
--- /dev/null
+++ b/tests/various/split_shiftx.ys
@@ -0,0 +1,21 @@
+read_verilog -icells split_shiftx.v
+split_shiftx
+
+cd split_shiftx_test01
+select -assert-count 3 t:$shiftx
+select -assert-count 0 t: t:$shiftx %n %i
+
+cd split_shiftx_test02
+select -assert-count 1 t:$shiftx
+select -assert-count 1 t:$macc
+select -assert-count 0 t: t:$shiftx t:$macc %u %n %i
+
+cd split_shiftx_test03
+select -assert-count 1 t:$shiftx
+select -assert-count 1 t:$macc
+select -assert-count 0 t: t:$shiftx t:$macc %u %n %i
+
+cd split_shiftx_test04
+select -assert-count 1 t:$shiftx
+select -assert-count 1 t:$macc
+select -assert-count 0 t: t:$shiftx t:$macc %u %n %i
-- 
cgit v1.2.3


From 0f1ba949243aa7ccc7c6b42738a60a09be7a209e Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 26 Apr 2019 19:45:47 -0700
Subject: Remove split_shiftx tests

---
 tests/various/split_shiftx.v  | 118 ------------------------------------------
 tests/various/split_shiftx.ys |  21 --------
 2 files changed, 139 deletions(-)
 delete mode 100644 tests/various/split_shiftx.v
 delete mode 100644 tests/various/split_shiftx.ys

(limited to 'tests')

diff --git a/tests/various/split_shiftx.v b/tests/various/split_shiftx.v
deleted file mode 100644
index dfcea3880..000000000
--- a/tests/various/split_shiftx.v
+++ /dev/null
@@ -1,118 +0,0 @@
-module split_shiftx_test01(i, s, o);
-  wire [3:0] _0_;
-  input [8:0] i;
-  output [2:0] o;
-  input [1:0] s;
-  \$macc  #(
-    .A_WIDTH(32'd4),
-    .B_WIDTH(32'd0),
-    .CONFIG(10'h282),
-    .CONFIG_WIDTH(32'd10),
-    .Y_WIDTH(32'd4)
-  ) _1_ (
-    .A({ 2'h3, s }),
-    .B(),
-    .Y(_0_)
-  );
-  \$shiftx  #(
-    .A_SIGNED(32'd0),
-    .A_WIDTH(32'd9),
-    .B_SIGNED(32'd1),
-    .B_WIDTH(32'd5),
-    .Y_WIDTH(32'd3)
-  ) _2_ (
-    .A(i),
-    .B({ 1'h0, _0_ }),
-    .Y(o)
-  );
-endmodule
-
-// Sign bit is 1
-module split_shiftx_test02(i, s, o);
-  wire [3:0] _0_;
-  input [8:0] i;
-  output [2:0] o;
-  input [1:0] s;
-  \$macc  #(
-    .A_WIDTH(32'd4),
-    .B_WIDTH(32'd0),
-    .CONFIG(10'h282),
-    .CONFIG_WIDTH(32'd10),
-    .Y_WIDTH(32'd4)
-  ) _1_ (
-    .A({ 2'h3, s }),
-    .B(),
-    .Y(_0_)
-  );
-  \$shiftx  #(
-    .A_SIGNED(32'd0),
-    .A_WIDTH(32'd9),
-    .B_SIGNED(32'd1),
-    .B_WIDTH(32'd5),
-    .Y_WIDTH(32'd3)
-  ) _2_ (
-    .A(i),
-    .B({ 1'h1, _0_ }),
-    .Y(o)
-  );
-endmodule
-
-// Non constant $macc
-module split_shiftx_test03(i, s, o);
-  wire [3:0] _0_;
-  input [8:0] i;
-  output [2:0] o;
-  input [1:0] s;
-  \$macc  #(
-    .A_WIDTH(32'd4),
-    .B_WIDTH(32'd0),
-    .CONFIG(10'h282),
-    .CONFIG_WIDTH(32'd10),
-    .Y_WIDTH(32'd4)
-  ) _1_ (
-    .A({ s, s }),
-    .B(),
-    .Y(_0_)
-  );
-  \$shiftx  #(
-    .A_SIGNED(32'd0),
-    .A_WIDTH(32'd9),
-    .B_SIGNED(32'd1),
-    .B_WIDTH(32'd5),
-    .Y_WIDTH(32'd3)
-  ) _2_ (
-    .A(i),
-    .B({ 1'h0, _0_ }),
-    .Y(o)
-  );
-endmodule
-
-// Wrong constant $macc
-module split_shiftx_test04(i, s, o);
-  wire [3:0] _0_;
-  input [8:0] i;
-  output [2:0] o;
-  input [1:0] s;
-  \$macc  #(
-    .A_WIDTH(32'd4),
-    .B_WIDTH(32'd0),
-    .CONFIG(10'h282),
-    .CONFIG_WIDTH(32'd10),
-    .Y_WIDTH(32'd4)
-  ) _1_ (
-    .A({ 2'h2, s }),
-    .B(),
-    .Y(_0_)
-  );
-  \$shiftx  #(
-    .A_SIGNED(32'd0),
-    .A_WIDTH(32'd9),
-    .B_SIGNED(32'd1),
-    .B_WIDTH(32'd5),
-    .Y_WIDTH(32'd3)
-  ) _2_ (
-    .A(i),
-    .B({ 1'h0, _0_ }),
-    .Y(o)
-  );
-endmodule
diff --git a/tests/various/split_shiftx.ys b/tests/various/split_shiftx.ys
deleted file mode 100644
index 810348aa3..000000000
--- a/tests/various/split_shiftx.ys
+++ /dev/null
@@ -1,21 +0,0 @@
-read_verilog -icells split_shiftx.v
-split_shiftx
-
-cd split_shiftx_test01
-select -assert-count 3 t:$shiftx
-select -assert-count 0 t: t:$shiftx %n %i
-
-cd split_shiftx_test02
-select -assert-count 1 t:$shiftx
-select -assert-count 1 t:$macc
-select -assert-count 0 t: t:$shiftx t:$macc %u %n %i
-
-cd split_shiftx_test03
-select -assert-count 1 t:$shiftx
-select -assert-count 1 t:$macc
-select -assert-count 0 t: t:$shiftx t:$macc %u %n %i
-
-cd split_shiftx_test04
-select -assert-count 1 t:$shiftx
-select -assert-count 1 t:$macc
-select -assert-count 0 t: t:$shiftx t:$macc %u %n %i
-- 
cgit v1.2.3


From 5f39c262c278f90f6bbb55d5969b970230876ef5 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Tue, 28 May 2019 09:38:58 -0700
Subject: From master

---
 tests/tools/autotest.sh | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'tests')

diff --git a/tests/tools/autotest.sh b/tests/tools/autotest.sh
index 1825990a9..920474a84 100755
--- a/tests/tools/autotest.sh
+++ b/tests/tools/autotest.sh
@@ -132,13 +132,13 @@ do
 		fn=$(basename $fn)
 		bn=$(basename $bn)
 
+		rm -f ${bn}_ref.fir
 		if [[ "$ext" == "v" ]]; then
 			egrep -v '^\s*`timescale' ../$fn > ${bn}_ref.${ext}
 		else
 			"$toolsdir"/../../yosys -f "$frontend $include_opts" -b "verilog" -o ${bn}_ref.v ../${fn}
 			frontend="verilog -noblackbox"
 		fi
-		rm -f ${bn}_ref.fir
 
 		if [ ! -f ../${bn}_tb.v ]; then
 			"$toolsdir"/../../yosys -f "$frontend $include_opts" -b "test_autotb $autotb_opts" -o ${bn}_tb.v ${bn}_ref.v
-- 
cgit v1.2.3


From 92197326b8fa406e94c952cfcb778611642a3e00 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Tue, 28 May 2019 12:43:07 -0700
Subject: Add abc9_test022

---
 tests/simple_abc9/abc9.v | 22 ++++++++++++++++++++++
 1 file changed, 22 insertions(+)

(limited to 'tests')

diff --git a/tests/simple_abc9/abc9.v b/tests/simple_abc9/abc9.v
index fb5b759fb..e666d1a6a 100644
--- a/tests/simple_abc9/abc9.v
+++ b/tests/simple_abc9/abc9.v
@@ -143,6 +143,7 @@ assign b = ~a;
 always @* d <= &c;
 endmodule
 
+// Citation: https://github.com/alexforencich/verilog-ethernet
 module abc9_test021(clk, rst, s_eth_hdr_valid, s_eth_hdr_ready, s_eth_dest_mac, s_eth_src_mac, s_eth_type, s_eth_payload_axis_tdata, s_eth_payload_axis_tkeep, s_eth_payload_axis_tvalid, s_eth_payload_axis_tready, s_eth_payload_axis_tlast, s_eth_payload_axis_tid, s_eth_payload_axis_tdest, s_eth_payload_axis_tuser, m_eth_hdr_valid, m_eth_hdr_ready, m_eth_dest_mac, m_eth_src_mac, m_eth_type, m_eth_payload_axis_tdata, m_eth_payload_axis_tkeep, m_eth_payload_axis_tvalid, m_eth_payload_axis_tready, m_eth_payload_axis_tlast, m_eth_payload_axis_tid, m_eth_payload_axis_tdest, m_eth_payload_axis_tuser);
   input clk;
   output [47:0] m_eth_dest_mac;
@@ -215,3 +216,24 @@ endmodule
 (* abc_box_id=1 *)
 module MUXF8(input I0, I1, S, output O);
 endmodule
+
+// Citation: https://github.com/alexforencich/verilog-ethernet
+// TODO: yosys -p "synth_xilinx -abc9 -top abc9_test022" abc9.v -q
+// returns before b4321a31
+//   Warning: Wire abc9_test022.\m_eth_payload_axis_tkeep [7] is used but has no
+//   driver.
+//   Warning: Wire abc9_test022.\m_eth_payload_axis_tkeep [3] is used but has no
+//   driver.
+module abc9_test022
+(
+    input  wire        clk,
+    input  wire        i,
+    output wire [7:0]  m_eth_payload_axis_tkeep
+);
+
+reg [7:0]  m_eth_payload_axis_tkeep_reg = 8'd0;
+assign m_eth_payload_axis_tkeep = m_eth_payload_axis_tkeep_reg;
+always @(posedge clk)
+    m_eth_payload_axis_tkeep_reg <= i ? 8'hff : 8'h0f;
+
+endmodule
-- 
cgit v1.2.3


From aa2380c17a7c97d4c3835cd6d78310cf4961c4f8 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 29 May 2019 15:24:38 -0700
Subject: Add abc_test024

---
 tests/simple_abc9/abc9.v | 25 +++++++++++++++++++------
 1 file changed, 19 insertions(+), 6 deletions(-)

(limited to 'tests')

diff --git a/tests/simple_abc9/abc9.v b/tests/simple_abc9/abc9.v
index e666d1a6a..7af2ace01 100644
--- a/tests/simple_abc9/abc9.v
+++ b/tests/simple_abc9/abc9.v
@@ -230,10 +230,23 @@ module abc9_test022
     input  wire        i,
     output wire [7:0]  m_eth_payload_axis_tkeep
 );
-
-reg [7:0]  m_eth_payload_axis_tkeep_reg = 8'd0;
-assign m_eth_payload_axis_tkeep = m_eth_payload_axis_tkeep_reg;
-always @(posedge clk)
-    m_eth_payload_axis_tkeep_reg <= i ? 8'hff : 8'h0f;
-
+    reg [7:0]  m_eth_payload_axis_tkeep_reg = 8'd0;
+    assign m_eth_payload_axis_tkeep = m_eth_payload_axis_tkeep_reg;
+    always @(posedge clk)
+        m_eth_payload_axis_tkeep_reg <= i ? 8'hff : 8'h0f;
+endmodule
+
+// Citation: https://github.com/riscv/riscv-bitmanip
+// TODO: yosys -p "synth_xilinx -abc9 -top abc9_test024" abc9.v -q
+// returns before 14233843
+//   Warning: Wire abc9_test024.\dout [1] is used but has no driver.
+module abc9_test024 #(
+	parameter integer N = 2,
+	parameter integer M = 2
+) (
+	input [7:0] din,
+	output [M-1:0] dout
+);
+	wire [2*M-1:0] mask = {M{1'b1}};
+	assign dout = (mask << din[N-1:0]) >> M;
 endmodule
-- 
cgit v1.2.3


From 25befbf5425458cf8cc5ee89635ad7e5f42d5778 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 29 May 2019 15:26:33 -0700
Subject: Rename to #23

---
 tests/simple_abc9/abc9.v | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

(limited to 'tests')

diff --git a/tests/simple_abc9/abc9.v b/tests/simple_abc9/abc9.v
index 7af2ace01..2752ff8cc 100644
--- a/tests/simple_abc9/abc9.v
+++ b/tests/simple_abc9/abc9.v
@@ -237,10 +237,10 @@ module abc9_test022
 endmodule
 
 // Citation: https://github.com/riscv/riscv-bitmanip
-// TODO: yosys -p "synth_xilinx -abc9 -top abc9_test024" abc9.v -q
+// TODO: yosys -p "synth_xilinx -abc9 -top abc9_test023" abc9.v -q
 // returns before 14233843
-//   Warning: Wire abc9_test024.\dout [1] is used but has no driver.
-module abc9_test024 #(
+//   Warning: Wire abc9_test023.\dout [1] is used but has no driver.
+module abc9_test023 #(
 	parameter integer N = 2,
 	parameter integer M = 2
 ) (
-- 
cgit v1.2.3


From 3e76e3a6fa4355e7223b10bba394f986d6821551 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 6 Jun 2019 11:54:38 -0700
Subject: Add tests, fix for !=

---
 tests/various/muxpack.v  | 36 ++++++++++++++++++++++++++++++++++++
 tests/various/muxpack.ys | 42 ++++++++++++++++++++++++++++++++++++++++++
 2 files changed, 78 insertions(+)
 create mode 100644 tests/various/muxpack.v
 create mode 100644 tests/various/muxpack.ys

(limited to 'tests')

diff --git a/tests/various/muxpack.v b/tests/various/muxpack.v
new file mode 100644
index 000000000..abc87ba44
--- /dev/null
+++ b/tests/various/muxpack.v
@@ -0,0 +1,36 @@
+module mux_if_unbal_4_1 #(parameter N=4, parameter W=1) (input [N*W-1:0] i, input [$clog2(N)-1:0] s, output reg [W-1:0] o);
+always @*
+    if (s == 0) o <= i[0*W+:W];
+    else if (s == 1) o <= i[1*W+:W];
+    else if (s == 2) o <= i[2*W+:W];
+    else if (s == 3) o <= i[3*W+:W];
+    else o <= {W{1'bx}};
+
+endmodule
+
+module mux_if_unbal_5_3 #(parameter N=5, parameter W=3) (input [N*W-1:0] i, input [$clog2(N)-1:0] s, output reg [W-1:0] o);
+always @* begin
+    o <= {W{1'bx}};
+    if (s == 0) o <= i[0*W+:W];
+    if (s == 1) o <= i[1*W+:W];
+    if (s == 2) o <= i[2*W+:W];
+    if (s == 3) o <= i[3*W+:W];
+    if (s == 4) o <= i[4*W+:W];
+end
+
+endmodule
+
+module mux_if_unbal_5_3_invert #(parameter N=5, parameter W=3) (input [N*W-1:0] i, input [$clog2(N)-1:0] s, output reg [W-1:0] o);
+always @*
+    if (s != 0) 
+	   	if (s != 1) 
+			if (s != 2)
+				if (s != 3)
+					if (s != 4) o <= i[4*W+:W];
+					else o <= i[0*W+:W];
+				else o <= i[3*W+:W];
+			else o <= i[2*W+:W];
+		else o <= i[1*W+:W];
+    else o <= {W{1'bx}};
+
+endmodule
diff --git a/tests/various/muxpack.ys b/tests/various/muxpack.ys
new file mode 100644
index 000000000..58c01cf05
--- /dev/null
+++ b/tests/various/muxpack.ys
@@ -0,0 +1,42 @@
+read_verilog muxpack.v
+design -save read
+hierarchy -top mux_if_unbal_4_1
+prep
+design -save gold
+muxpack
+opt
+stat
+select -assert-count 1 t:$pmux
+design -stash gate
+design -import gold -as gold
+design -import gate -as gate
+miter -equiv -flatten -make_assert -make_outputs gold gate miter
+sat -verify -prove-asserts -show-ports miter
+
+design -load read
+hierarchy -top mux_if_unbal_5_3
+prep
+design -save gold
+muxpack
+opt
+stat
+select -assert-count 1 t:$pmux
+design -stash gate
+design -import gold -as gold
+design -import gate -as gate
+miter -equiv -flatten -make_assert -make_outputs gold gate miter
+sat -verify -prove-asserts -show-ports miter
+
+design -load read
+hierarchy -top mux_if_unbal_5_3_invert
+prep
+design -save gold
+muxpack
+opt
+stat
+select -assert-count 1 t:$pmux
+design -stash gate
+design -import gold -as gold
+design -import gate -as gate
+miter -equiv -flatten -make_assert -make_outputs gold gate miter
+sat -verify -prove-asserts -show-ports miter
-- 
cgit v1.2.3


From 5d4eca5a298d2f98de220cfd0efe5452ab4052d8 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 6 Jun 2019 11:59:41 -0700
Subject: Add a few more special case tests

---
 tests/various/muxpack.v  | 23 +++++++++++++++++++++++
 tests/various/muxpack.ys | 28 ++++++++++++++++++++++++++++
 2 files changed, 51 insertions(+)

(limited to 'tests')

diff --git a/tests/various/muxpack.v b/tests/various/muxpack.v
index abc87ba44..333908fcb 100644
--- a/tests/various/muxpack.v
+++ b/tests/various/muxpack.v
@@ -34,3 +34,26 @@ always @*
     else o <= {W{1'bx}};
 
 endmodule
+
+module mux_if_unbal_5_3_width_mismatch #(parameter N=5, parameter W=3) (input [N*W-1:0] i, input [$clog2(N)-1:0] s, output reg [W-1:0] o);
+always @* begin
+    o <= {W{1'bx}};
+    if (s == 0) o <= i[0*W+:W];
+    if (s == 1) o <= i[1*W+:W];
+    if (s == 2) o[W-2:0] <= i[2*W+:W-1];
+    if (s == 3) o <= i[3*W+:W];
+    if (s == 4) o <= i[4*W+:W];
+end
+
+endmodule
+
+module mux_if_unbal_5_3_missing #(parameter N=5, parameter W=3) (input [N*W-1:0] i, input [$clog2(N)-1:0] s, output reg [W-1:0] o);
+always @* begin
+    if (s == 0) o <= i[0*W+:W];
+//    else if (s == 1) o <= i[1*W+:W];
+//    else if (s == 2) o <= i[2*W+:W];
+    else if (s == 3) o <= i[3*W+:W];
+    else o <= {W{1'bx}};
+end
+
+endmodule
diff --git a/tests/various/muxpack.ys b/tests/various/muxpack.ys
index 58c01cf05..174eea74b 100644
--- a/tests/various/muxpack.ys
+++ b/tests/various/muxpack.ys
@@ -40,3 +40,31 @@ design -import gold -as gold
 design -import gate -as gate
 miter -equiv -flatten -make_assert -make_outputs gold gate miter
 sat -verify -prove-asserts -show-ports miter
+
+design -load read
+hierarchy -top mux_if_unbal_5_3_width_mismatch
+prep
+design -save gold
+muxpack
+opt
+stat
+select -assert-count 2 t:$pmux
+design -stash gate
+design -import gold -as gold
+design -import gate -as gate
+miter -equiv -flatten -make_assert -make_outputs gold gate miter
+sat -verify -prove-asserts -show-ports miter
+
+design -load read
+hierarchy -top mux_if_unbal_5_3_missing
+prep
+design -save gold
+muxpack
+opt
+stat
+select -assert-count 1 t:$pmux
+design -stash gate
+design -import gold -as gold
+design -import gate -as gate
+miter -equiv -flatten -make_assert -make_outputs gold gate miter
+sat -verify -prove-asserts -show-ports miter
-- 
cgit v1.2.3


From b8620f7b3dde4460e5a8ed3ea7fd7aef54aa7da1 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 6 Jun 2019 12:03:44 -0700
Subject: One more and tidy up

---
 tests/various/muxpack.v  | 18 +++++++++++++-----
 tests/various/muxpack.ys | 16 +++++++++++++++-
 2 files changed, 28 insertions(+), 6 deletions(-)

(limited to 'tests')

diff --git a/tests/various/muxpack.v b/tests/various/muxpack.v
index 333908fcb..c2c2537a0 100644
--- a/tests/various/muxpack.v
+++ b/tests/various/muxpack.v
@@ -5,7 +5,6 @@ always @*
     else if (s == 2) o <= i[2*W+:W];
     else if (s == 3) o <= i[3*W+:W];
     else o <= {W{1'bx}};
-
 endmodule
 
 module mux_if_unbal_5_3 #(parameter N=5, parameter W=3) (input [N*W-1:0] i, input [$clog2(N)-1:0] s, output reg [W-1:0] o);
@@ -17,7 +16,6 @@ always @* begin
     if (s == 3) o <= i[3*W+:W];
     if (s == 4) o <= i[4*W+:W];
 end
-
 endmodule
 
 module mux_if_unbal_5_3_invert #(parameter N=5, parameter W=3) (input [N*W-1:0] i, input [$clog2(N)-1:0] s, output reg [W-1:0] o);
@@ -32,7 +30,6 @@ always @*
 			else o <= i[2*W+:W];
 		else o <= i[1*W+:W];
     else o <= {W{1'bx}};
-
 endmodule
 
 module mux_if_unbal_5_3_width_mismatch #(parameter N=5, parameter W=3) (input [N*W-1:0] i, input [$clog2(N)-1:0] s, output reg [W-1:0] o);
@@ -44,10 +41,9 @@ always @* begin
     if (s == 3) o <= i[3*W+:W];
     if (s == 4) o <= i[4*W+:W];
 end
-
 endmodule
 
-module mux_if_unbal_5_3_missing #(parameter N=5, parameter W=3) (input [N*W-1:0] i, input [$clog2(N)-1:0] s, output reg [W-1:0] o);
+module mux_if_unbal_4_1_missing #(parameter N=5, parameter W=3) (input [N*W-1:0] i, input [$clog2(N)-1:0] s, output reg [W-1:0] o);
 always @* begin
     if (s == 0) o <= i[0*W+:W];
 //    else if (s == 1) o <= i[1*W+:W];
@@ -55,5 +51,17 @@ always @* begin
     else if (s == 3) o <= i[3*W+:W];
     else o <= {W{1'bx}};
 end
+endmodule
 
+module mux_if_unbal_5_3_order #(parameter N=5, parameter W=3) (input [N*W-1:0] i, input [$clog2(N)-1:0] s, output reg [W-1:0] o);
+always @* begin
+    o <= {W{1'bx}};
+    if (s == 3) o <= i[3*W+:W];
+    if (s == 2) o <= i[2*W+:W];
+    if (s == 1) o <= i[1*W+:W];
+    if (s == 4) o <= i[4*W+:W];
+    if (s == 0) o <= i[0*W+:W];
+end
 endmodule
+
+
diff --git a/tests/various/muxpack.ys b/tests/various/muxpack.ys
index 174eea74b..a967ddfef 100644
--- a/tests/various/muxpack.ys
+++ b/tests/various/muxpack.ys
@@ -56,7 +56,21 @@ miter -equiv -flatten -make_assert -make_outputs gold gate miter
 sat -verify -prove-asserts -show-ports miter
 
 design -load read
-hierarchy -top mux_if_unbal_5_3_missing
+hierarchy -top mux_if_unbal_4_1_missing
+prep
+design -save gold
+muxpack
+opt
+stat
+select -assert-count 1 t:$pmux
+design -stash gate
+design -import gold -as gold
+design -import gate -as gate
+miter -equiv -flatten -make_assert -make_outputs gold gate miter
+sat -verify -prove-asserts -show-ports miter
+
+design -load read
+hierarchy -top mux_if_unbal_5_3_order
 prep
 design -save gold
 muxpack
-- 
cgit v1.2.3


From 705388eb24022d2a310ae72cd81e67a2f0ce7586 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 6 Jun 2019 12:44:06 -0700
Subject: Add non exclusive test

---
 tests/various/muxpack.v  | 20 ++++++++++++++++++++
 tests/various/muxpack.ys | 36 ++++++++++++++++++++++++++++++++++++
 2 files changed, 56 insertions(+)

(limited to 'tests')

diff --git a/tests/various/muxpack.v b/tests/various/muxpack.v
index c2c2537a0..e847fef27 100644
--- a/tests/various/muxpack.v
+++ b/tests/various/muxpack.v
@@ -64,4 +64,24 @@ always @* begin
 end
 endmodule
 
+module mux_if_unbal_4_1_nonexcl #(parameter N=4, parameter W=1) (input [N*W-1:0] i, input [$clog2(N)-1:0] s, output reg [W-1:0] o);
+always @*
+    if (s == 0) o <= i[0*W+:W];
+    else if (s == 1) o <= i[1*W+:W];
+    else if (s == 2) o <= i[2*W+:W];
+    else if (s == 3) o <= i[3*W+:W];
+	else if (s == 0) o <= {W{1'b0}};
+    else o <= {W{1'bx}};
+endmodule
 
+module mux_if_unbal_5_3_nonexcl #(parameter N=4, parameter W=1) (input [N*W-1:0] i, input [$clog2(N)-1:0] s, output reg [W-1:0] o);
+always @* begin
+    o <= {W{1'bx}};
+    if (s == 0) o <= i[0*W+:W];
+    if (s == 1) o <= i[1*W+:W];
+    if (s == 2) o <= i[2*W+:W];
+    if (s == 3) o <= i[3*W+:W];
+    if (s == 4) o <= i[4*W+:W];
+	if (s == 0) o <= i[2*W+:W];
+end
+endmodule
diff --git a/tests/various/muxpack.ys b/tests/various/muxpack.ys
index a967ddfef..178860b88 100644
--- a/tests/various/muxpack.ys
+++ b/tests/various/muxpack.ys
@@ -6,6 +6,7 @@ design -save gold
 muxpack
 opt
 stat
+select -assert-count 0 t:$mux
 select -assert-count 1 t:$pmux
 design -stash gate
 design -import gold -as gold
@@ -20,6 +21,7 @@ design -save gold
 muxpack
 opt
 stat
+select -assert-count 0 t:$mux
 select -assert-count 1 t:$pmux
 design -stash gate
 design -import gold -as gold
@@ -34,6 +36,7 @@ design -save gold
 muxpack
 opt
 stat
+select -assert-count 0 t:$mux
 select -assert-count 1 t:$pmux
 design -stash gate
 design -import gold -as gold
@@ -48,6 +51,7 @@ design -save gold
 muxpack
 opt
 stat
+select -assert-count 0 t:$mux
 select -assert-count 2 t:$pmux
 design -stash gate
 design -import gold -as gold
@@ -62,6 +66,7 @@ design -save gold
 muxpack
 opt
 stat
+select -assert-count 0 t:$mux
 select -assert-count 1 t:$pmux
 design -stash gate
 design -import gold -as gold
@@ -76,6 +81,37 @@ design -save gold
 muxpack
 opt
 stat
+select -assert-count 0 t:$mux
+select -assert-count 1 t:$pmux
+design -stash gate
+design -import gold -as gold
+design -import gate -as gate
+miter -equiv -flatten -make_assert -make_outputs gold gate miter
+sat -verify -prove-asserts -show-ports miter
+
+design -load read
+hierarchy -top mux_if_unbal_4_1_nonexcl
+prep
+design -save gold
+muxpack
+opt
+stat
+select -assert-count 0 t:$mux
+select -assert-count 1 t:$pmux
+design -stash gate
+design -import gold -as gold
+design -import gate -as gate
+miter -equiv -flatten -make_assert -make_outputs gold gate miter
+sat -verify -prove-asserts -show-ports miter
+
+design -load read
+hierarchy -top mux_if_unbal_5_3_nonexcl
+prep
+design -save gold
+muxpack
+opt
+stat
+select -assert-count 0 t:$mux
 select -assert-count 1 t:$pmux
 design -stash gate
 design -import gold -as gold
-- 
cgit v1.2.3


From ccdf989025e57da7dfd5ab609676ebe3cfb2c2d6 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 6 Jun 2019 13:51:22 -0700
Subject: Support cascading $pmux.A with $mux.A and $mux.B

---
 tests/various/muxpack.v  | 25 +++++++++++++++++++++++++
 tests/various/muxpack.ys | 15 +++++++++++++++
 2 files changed, 40 insertions(+)

(limited to 'tests')

diff --git a/tests/various/muxpack.v b/tests/various/muxpack.v
index e847fef27..fe0150532 100644
--- a/tests/various/muxpack.v
+++ b/tests/various/muxpack.v
@@ -85,3 +85,28 @@ always @* begin
 	if (s == 0) o <= i[2*W+:W];
 end
 endmodule
+
+module mux_case_unbal_7_7#(parameter N=7, parameter W=7) (input [N*W-1:0] i, input [$clog2(N)-1:0] s, output reg [W-1:0] o);
+always @* begin
+    o <= {W{1'bx}};
+    case (s)
+    0: o <= i[0*W+:W];
+    default:
+        case (s)
+        1: o <= i[1*W+:W];
+        2: o <= i[2*W+:W];
+        default:
+            case (s)
+            3: o <= i[3*W+:W];
+            4: o <= i[4*W+:W];
+            5: o <= i[5*W+:W];
+            default:
+                case (s)
+                    6: o <= i[6*W+:W];
+                    default: o <= i[7*W+:W];
+                endcase
+            endcase
+        endcase
+    endcase
+end
+endmodule
diff --git a/tests/various/muxpack.ys b/tests/various/muxpack.ys
index 178860b88..4dcb9ed89 100644
--- a/tests/various/muxpack.ys
+++ b/tests/various/muxpack.ys
@@ -118,3 +118,18 @@ design -import gold -as gold
 design -import gate -as gate
 miter -equiv -flatten -make_assert -make_outputs gold gate miter
 sat -verify -prove-asserts -show-ports miter
+
+design -load read
+hierarchy -top mux_case_unbal_7_7
+prep
+design -save gold
+muxpack
+opt
+stat
+select -assert-count 0 t:$mux
+select -assert-count 1 t:$pmux
+design -stash gate
+design -import gold -as gold
+design -import gate -as gate
+miter -equiv -flatten -make_assert -make_outputs gold gate miter
+sat -verify -prove-asserts -show-ports miter
-- 
cgit v1.2.3


From 0a66720f6f67b087fe6342d01d45944506240942 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 6 Jun 2019 14:01:42 -0700
Subject: Fix warnings

---
 tests/various/muxpack.v  | 4 ++--
 tests/various/muxpack.ys | 2 +-
 2 files changed, 3 insertions(+), 3 deletions(-)

(limited to 'tests')

diff --git a/tests/various/muxpack.v b/tests/various/muxpack.v
index fe0150532..7c189fff8 100644
--- a/tests/various/muxpack.v
+++ b/tests/various/muxpack.v
@@ -74,7 +74,7 @@ always @*
     else o <= {W{1'bx}};
 endmodule
 
-module mux_if_unbal_5_3_nonexcl #(parameter N=4, parameter W=1) (input [N*W-1:0] i, input [$clog2(N)-1:0] s, output reg [W-1:0] o);
+module mux_if_unbal_5_3_nonexcl #(parameter N=5, parameter W=3) (input [N*W-1:0] i, input [$clog2(N)-1:0] s, output reg [W-1:0] o);
 always @* begin
     o <= {W{1'bx}};
     if (s == 0) o <= i[0*W+:W];
@@ -86,7 +86,7 @@ always @* begin
 end
 endmodule
 
-module mux_case_unbal_7_7#(parameter N=7, parameter W=7) (input [N*W-1:0] i, input [$clog2(N)-1:0] s, output reg [W-1:0] o);
+module mux_case_unbal_8_7#(parameter N=8, parameter W=7) (input [N*W-1:0] i, input [$clog2(N)-1:0] s, output reg [W-1:0] o);
 always @* begin
     o <= {W{1'bx}};
     case (s)
diff --git a/tests/various/muxpack.ys b/tests/various/muxpack.ys
index 4dcb9ed89..0c5b82818 100644
--- a/tests/various/muxpack.ys
+++ b/tests/various/muxpack.ys
@@ -120,7 +120,7 @@ miter -equiv -flatten -make_assert -make_outputs gold gate miter
 sat -verify -prove-asserts -show-ports miter
 
 design -load read
-hierarchy -top mux_case_unbal_7_7
+hierarchy -top mux_case_unbal_8_7
 prep
 design -save gold
 muxpack
-- 
cgit v1.2.3


From 5c277c6325b78bfe18cf294b63ea69ff272e69c5 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 6 Jun 2019 14:21:34 -0700
Subject: Fix and test for balanced case

---
 tests/various/muxpack.v  | 26 ++++++++++++++++++++++++++
 tests/various/muxpack.ys | 15 +++++++++++++++
 2 files changed, 41 insertions(+)

(limited to 'tests')

diff --git a/tests/various/muxpack.v b/tests/various/muxpack.v
index 7c189fff8..f1bd5ea8e 100644
--- a/tests/various/muxpack.v
+++ b/tests/various/muxpack.v
@@ -110,3 +110,29 @@ always @* begin
     endcase
 end
 endmodule
+
+module mux_if_bal_8_2 #(parameter N=8, parameter W=2) (input [N*W-1:0] i, input [$clog2(N)-1:0] s, output reg [W-1:0] o);
+always @*
+    if (s[0] == 1'b0)
+     if (s[1] == 1'b0)
+      if (s[2] == 1'b0)
+       o <= i[0*W+:W];
+      else
+       o <= i[1*W+:W];
+     else
+      if (s[2] == 1'b0)
+       o <= i[2*W+:W];
+      else
+       o <= i[3*W+:W];
+    else
+     if (s[1] == 1'b0)
+      if (s[2] == 1'b0)
+       o <= i[4*W+:W];
+      else
+       o <= i[5*W+:W];
+     else
+      if (s[2] == 1'b0)
+       o <= i[6*W+:W];
+      else
+       o <= i[7*W+:W];
+endmodule
diff --git a/tests/various/muxpack.ys b/tests/various/muxpack.ys
index 0c5b82818..9ea743b9f 100644
--- a/tests/various/muxpack.ys
+++ b/tests/various/muxpack.ys
@@ -133,3 +133,18 @@ design -import gold -as gold
 design -import gate -as gate
 miter -equiv -flatten -make_assert -make_outputs gold gate miter
 sat -verify -prove-asserts -show-ports miter
+
+design -load read
+hierarchy -top mux_if_bal_8_2
+prep
+design -save gold
+muxpack
+opt
+stat
+select -assert-count 7 t:$mux
+select -assert-count 0 t:$pmux
+design -stash gate
+design -import gold -as gold
+design -import gate -as gate
+miter -equiv -flatten -make_assert -make_outputs gold gate miter
+sat -verify -prove-asserts -show-ports miter
-- 
cgit v1.2.3


From c314ca3c51579a9c5305cbf9a69635e123db0423 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Mon, 10 Jun 2019 16:16:26 -0700
Subject: Add test

---
 tests/various/shregmap.v  | 22 ++++++++++++++++++++++
 tests/various/shregmap.ys | 31 +++++++++++++++++++++++++++++++
 2 files changed, 53 insertions(+)
 create mode 100644 tests/various/shregmap.v
 create mode 100644 tests/various/shregmap.ys

(limited to 'tests')

diff --git a/tests/various/shregmap.v b/tests/various/shregmap.v
new file mode 100644
index 000000000..56e05c2c0
--- /dev/null
+++ b/tests/various/shregmap.v
@@ -0,0 +1,22 @@
+module shregmap_test(input i, clk, output [1:0] q);
+reg head = 1'b0;
+reg [3:0] shift1 = 4'b0000;
+reg [3:0] shift2 = 4'b0000;
+
+always @(posedge clk) begin
+    head <= i;
+    shift1 <= {shift1[2:0], head};
+    shift2 <= {shift2[2:0], head};
+end
+
+assign q = {shift2[3], shift1[3]};
+endmodule
+
+module $__SHREG_DFF_P_(input C, D, output Q);
+parameter DEPTH = 1;
+parameter [DEPTH-1:0] INIT = {DEPTH{1'b0}};
+reg [DEPTH-1:0] r = INIT;
+always @(posedge C) 
+    r <= { r[DEPTH-2:0], D };
+assign Q = r[DEPTH-1];
+endmodule
diff --git a/tests/various/shregmap.ys b/tests/various/shregmap.ys
new file mode 100644
index 000000000..ca7f47015
--- /dev/null
+++ b/tests/various/shregmap.ys
@@ -0,0 +1,31 @@
+read_verilog shregmap.v
+design -copy-to model $__SHREG_DFF_P_
+hierarchy -top shregmap_test
+prep
+design -save gold
+
+techmap
+shregmap -init
+
+opt
+
+stat
+# show -width
+select -assert-count 1 t:$_DFF_P_
+select -assert-count 2 t:$__SHREG_DFF_P_
+
+design -stash gate
+
+design -import gold -as gold
+design -import gate -as gate
+design -copy-from model -as $__SHREG_DFF_P_ \$__SHREG_DFF_P_
+prep
+
+miter -equiv -flatten -make_assert -make_outputs gold gate miter
+sat -verify -prove-asserts -show-ports -seq 5 miter
+
+design -load gold
+stat
+
+design -load gate
+stat
-- 
cgit v1.2.3