From 4fadcc8f25d5ef1e494aa7d5e49d893afdaa1705 Mon Sep 17 00:00:00 2001 From: Zachary Snow Date: Wed, 20 Jan 2021 08:49:32 -0700 Subject: verilog: allow spaces in macro arguments --- tests/simple/macro_arg_spaces.sv | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) create mode 100644 tests/simple/macro_arg_spaces.sv (limited to 'tests') diff --git a/tests/simple/macro_arg_spaces.sv b/tests/simple/macro_arg_spaces.sv new file mode 100644 index 000000000..75c4cd136 --- /dev/null +++ b/tests/simple/macro_arg_spaces.sv @@ -0,0 +1,28 @@ +module top( + input wire [31:0] i, + output wire [31:0] x, y, z +); + +`define BAR(a) a +`define FOO(a = function automatic [31:0] f) a + +`BAR(function automatic [31:0] a); + input [31:0] i; + a = i * 2; +endfunction + +`FOO(); + input [31:0] i; + f = i * 3; +endfunction + +`FOO(function automatic [31:0] b); + input [31:0] i; + b = i * 5; +endfunction + +assign x = a(i); +assign y = f(i); +assign z = b(i); + +endmodule -- cgit v1.2.3