From d738b2c1272b02d8799e9feda83b1eae8ba10c07 Mon Sep 17 00:00:00 2001
From: Zachary Snow <zach@zachjs.com>
Date: Tue, 2 Mar 2021 10:43:53 -0500
Subject: sv: support for parameters without default values

- Modules with a parameter without a default value will be automatically
  deferred until the hierarchy pass
- Allows for parameters without defaults as module items, rather than
  just int the `parameter_port_list`, despite being forbidden in the LRM
- Check for parameters without defaults that haven't been overriden
- Add location info to parameter/localparam declarations
---
 tests/verilog/localparam_no_default_1.ys     | 17 +++++++++
 tests/verilog/localparam_no_default_2.ys     | 15 ++++++++
 tests/verilog/param_no_default.sv            | 52 ++++++++++++++++++++++++++++
 tests/verilog/param_no_default.ys            |  7 ++++
 tests/verilog/param_no_default_not_svmode.ys | 26 ++++++++++++++
 tests/verilog/param_no_default_unbound_1.ys  | 12 +++++++
 tests/verilog/param_no_default_unbound_2.ys  | 12 +++++++
 tests/verilog/param_no_default_unbound_3.ys  | 12 +++++++
 tests/verilog/param_no_default_unbound_4.ys  | 12 +++++++
 tests/verilog/param_no_default_unbound_5.ys  | 12 +++++++
 10 files changed, 177 insertions(+)
 create mode 100644 tests/verilog/localparam_no_default_1.ys
 create mode 100644 tests/verilog/localparam_no_default_2.ys
 create mode 100644 tests/verilog/param_no_default.sv
 create mode 100644 tests/verilog/param_no_default.ys
 create mode 100644 tests/verilog/param_no_default_not_svmode.ys
 create mode 100644 tests/verilog/param_no_default_unbound_1.ys
 create mode 100644 tests/verilog/param_no_default_unbound_2.ys
 create mode 100644 tests/verilog/param_no_default_unbound_3.ys
 create mode 100644 tests/verilog/param_no_default_unbound_4.ys
 create mode 100644 tests/verilog/param_no_default_unbound_5.ys

(limited to 'tests')

diff --git a/tests/verilog/localparam_no_default_1.ys b/tests/verilog/localparam_no_default_1.ys
new file mode 100644
index 000000000..426a48a1c
--- /dev/null
+++ b/tests/verilog/localparam_no_default_1.ys
@@ -0,0 +1,17 @@
+logger -expect-no-warnings
+read_verilog -sv <<EOF
+module Module #(
+    localparam X = 1
+);
+endmodule
+EOF
+
+design -reset
+
+logger -expect error "localparam initialization is missing!" 1
+read_verilog <<EOF
+module Module #(
+    localparam X
+);
+endmodule
+EOF
diff --git a/tests/verilog/localparam_no_default_2.ys b/tests/verilog/localparam_no_default_2.ys
new file mode 100644
index 000000000..b7b2622ad
--- /dev/null
+++ b/tests/verilog/localparam_no_default_2.ys
@@ -0,0 +1,15 @@
+logger -expect-no-warnings
+read_verilog -sv <<EOF
+module Module;
+    localparam X = 1;
+endmodule
+EOF
+
+design -reset
+
+logger -expect error "localparam initialization is missing!" 1
+read_verilog <<EOF
+module Module;
+    localparam X;
+endmodule
+EOF
diff --git a/tests/verilog/param_no_default.sv b/tests/verilog/param_no_default.sv
new file mode 100644
index 000000000..cc35bd2ea
--- /dev/null
+++ b/tests/verilog/param_no_default.sv
@@ -0,0 +1,52 @@
+module example #(
+    parameter w,
+    parameter x = 1,
+    parameter byte y,
+    parameter byte z = 3
+) (
+    output a, b,
+    output byte c, d
+);
+    assign a = w;
+    assign b = x;
+    assign c = y;
+    assign d = z;
+endmodule
+
+module top;
+    wire a1, b1;
+    wire a2, b2;
+    wire a3, b3;
+    wire a4, b4;
+    byte c1, d1;
+    byte c2, d2;
+    byte c3, d3;
+    byte c4, d4;
+
+    example #(0, 1, 2) e1(a1, b1, c1, d1);
+    example #(.w(1), .y(4)) e2(a2, b2, c2, d2);
+    example #(.x(0), .w(1), .y(5)) e3(a3, b3, c3, d3);
+    example #(1, 0, 9, 10) e4(a4, b4, c4, d4);
+
+    always @* begin
+        assert (a1 == 0);
+        assert (b1 == 1);
+        assert (c1 == 2);
+        assert (d1 == 3);
+
+        assert (a2 == 1);
+        assert (b2 == 1);
+        assert (c2 == 4);
+        assert (d3 == 3);
+
+        assert (a3 == 1);
+        assert (b3 == 0);
+        assert (c3 == 5);
+        assert (d3 == 3);
+
+        assert (a4 == 1);
+        assert (b4 == 0);
+        assert (c4 == 9);
+        assert (d4 == 10);
+    end
+endmodule
diff --git a/tests/verilog/param_no_default.ys b/tests/verilog/param_no_default.ys
new file mode 100644
index 000000000..7f161a909
--- /dev/null
+++ b/tests/verilog/param_no_default.ys
@@ -0,0 +1,7 @@
+read_verilog -sv param_no_default.sv
+hierarchy
+proc
+flatten
+opt -full
+select -module top
+sat -verify -seq 1 -tempinduct -prove-asserts -show-all
diff --git a/tests/verilog/param_no_default_not_svmode.ys b/tests/verilog/param_no_default_not_svmode.ys
new file mode 100644
index 000000000..1ded84e9c
--- /dev/null
+++ b/tests/verilog/param_no_default_not_svmode.ys
@@ -0,0 +1,26 @@
+logger -expect-no-warnings
+read_verilog -sv <<EOF
+module Module;
+    parameter X;
+endmodule
+EOF
+
+design -reset
+
+logger -expect-no-warnings
+read_verilog -sv <<EOF
+module Module #(
+    parameter X
+);
+endmodule
+EOF
+
+design -reset
+
+logger -expect error "Parameter defaults can only be omitted in SystemVerilog mode!" 1
+read_verilog <<EOF
+module Module #(
+    parameter X
+);
+endmodule
+EOF
diff --git a/tests/verilog/param_no_default_unbound_1.ys b/tests/verilog/param_no_default_unbound_1.ys
new file mode 100644
index 000000000..4aab85ab5
--- /dev/null
+++ b/tests/verilog/param_no_default_unbound_1.ys
@@ -0,0 +1,12 @@
+read_verilog -sv <<EOF
+module Example #(
+    parameter X
+);
+endmodule
+module top;
+    Example e();
+endmodule
+EOF
+
+logger -expect error "Parameter `\\X' has no default value and has not been overridden!" 1
+hierarchy -top top
diff --git a/tests/verilog/param_no_default_unbound_2.ys b/tests/verilog/param_no_default_unbound_2.ys
new file mode 100644
index 000000000..4b7f3b028
--- /dev/null
+++ b/tests/verilog/param_no_default_unbound_2.ys
@@ -0,0 +1,12 @@
+read_verilog -sv <<EOF
+module Example #(
+    parameter X, Y
+);
+endmodule
+module top;
+    Example e();
+endmodule
+EOF
+
+logger -expect error "Parameter `\\X' has no default value and has not been overridden!" 1
+hierarchy -top top
diff --git a/tests/verilog/param_no_default_unbound_3.ys b/tests/verilog/param_no_default_unbound_3.ys
new file mode 100644
index 000000000..f32b879a5
--- /dev/null
+++ b/tests/verilog/param_no_default_unbound_3.ys
@@ -0,0 +1,12 @@
+read_verilog -sv <<EOF
+module Example #(
+    parameter X, Y
+);
+endmodule
+module top;
+    Example #(1) e();
+endmodule
+EOF
+
+logger -expect error "Parameter `\\Y' has no default value and has not been overridden!" 1
+hierarchy -top top
diff --git a/tests/verilog/param_no_default_unbound_4.ys b/tests/verilog/param_no_default_unbound_4.ys
new file mode 100644
index 000000000..3a8d69d78
--- /dev/null
+++ b/tests/verilog/param_no_default_unbound_4.ys
@@ -0,0 +1,12 @@
+read_verilog -sv <<EOF
+module Example #(
+    parameter X, Y
+);
+endmodule
+module top;
+    Example #(.Y(1)) e();
+endmodule
+EOF
+
+logger -expect error "Parameter `\\X' has no default value and has not been overridden!" 1
+hierarchy -top top
diff --git a/tests/verilog/param_no_default_unbound_5.ys b/tests/verilog/param_no_default_unbound_5.ys
new file mode 100644
index 000000000..30282eba7
--- /dev/null
+++ b/tests/verilog/param_no_default_unbound_5.ys
@@ -0,0 +1,12 @@
+read_verilog -sv <<EOF
+module Example #(
+    parameter X, Y = 2
+);
+endmodule
+module top;
+    Example #(.Y(1)) e();
+endmodule
+EOF
+
+logger -expect error "Parameter `\\X' has no default value and has not been overridden!" 1
+hierarchy -top top
-- 
cgit v1.2.3


From c18ddbcd822410095d28c4be1c3ac3c6358622d2 Mon Sep 17 00:00:00 2001
From: Zachary Snow <zach@zachjs.com>
Date: Thu, 4 Mar 2021 15:08:16 -0500
Subject: verilog: impose limit on maximum expression width

Designs with unreasonably wide expressions would previously get stuck
allocating memory forever.
---
 tests/verilog/absurd_width.ys       | 17 +++++++++++++++++
 tests/verilog/absurd_width_const.ys | 16 ++++++++++++++++
 2 files changed, 33 insertions(+)
 create mode 100644 tests/verilog/absurd_width.ys
 create mode 100644 tests/verilog/absurd_width_const.ys

(limited to 'tests')

diff --git a/tests/verilog/absurd_width.ys b/tests/verilog/absurd_width.ys
new file mode 100644
index 000000000..c0d2af4c2
--- /dev/null
+++ b/tests/verilog/absurd_width.ys
@@ -0,0 +1,17 @@
+logger -expect error "Expression width 1073741824 exceeds implementation limit of 16777216!" 1
+read_verilog <<EOF
+module top(
+    input inp,
+    output out
+);
+    assign out =
+        {1024 {
+        {1024 {
+        {1024 {
+        inp
+        }}
+        }}
+        }}
+        ;
+endmodule
+EOF
diff --git a/tests/verilog/absurd_width_const.ys b/tests/verilog/absurd_width_const.ys
new file mode 100644
index 000000000..b7191fd0d
--- /dev/null
+++ b/tests/verilog/absurd_width_const.ys
@@ -0,0 +1,16 @@
+logger -expect error "Expression width 1073741824 exceeds implementation limit of 16777216!" 1
+read_verilog <<EOF
+module top(
+    output out
+);
+    assign out =
+        {1024 {
+        {1024 {
+        {1024 {
+        1'b1
+        }}
+        }}
+        }}
+        ;
+endmodule
+EOF
-- 
cgit v1.2.3


From b1a8e73a609d3065f1caf7a230529443b54295bc Mon Sep 17 00:00:00 2001
From: Zachary Snow <zach@zachjs.com>
Date: Wed, 3 Mar 2021 14:36:19 -0500
Subject: sv: fix some edge cases for unbased unsized literals

- Fix explicit size cast of unbased unsized literals
- Fix unbased unsized literal bound directly to port
- Output `is_unsized` flag in `dumpAst`
---
 tests/verilog/unbased_unsized.sv | 40 ++++++++++++++++++++++++++++++++++++++++
 tests/verilog/unbased_unsized.ys |  7 +++++++
 2 files changed, 47 insertions(+)
 create mode 100644 tests/verilog/unbased_unsized.sv
 create mode 100644 tests/verilog/unbased_unsized.ys

(limited to 'tests')

diff --git a/tests/verilog/unbased_unsized.sv b/tests/verilog/unbased_unsized.sv
new file mode 100644
index 000000000..1d0c5a72c
--- /dev/null
+++ b/tests/verilog/unbased_unsized.sv
@@ -0,0 +1,40 @@
+module pass_through(
+    input [63:0] inp,
+    output [63:0] out
+);
+    assign out = inp;
+endmodule
+
+module top;
+    logic [63:0]
+        o01, o02, o03, o04,
+        o05, o06, o07, o08,
+        o09, o10, o11, o12,
+        o13, o14, o15, o16;
+    assign o01 = '0;
+    assign o02 = '1;
+    assign o03 = 'x;
+    assign o04 = 'z;
+    assign o05 = 3'('0);
+    assign o06 = 3'('1);
+    assign o07 = 3'('x);
+    assign o08 = 3'('z);
+    pass_through pt09('0, o09);
+    pass_through pt10('1, o10);
+    pass_through pt11('x, o11);
+    pass_through pt12('z, o12);
+    always @* begin
+        assert (o01 === {64 {1'b0}});
+        assert (o02 === {64 {1'b1}});
+        assert (o03 === {64 {1'bx}});
+        assert (o04 === {64 {1'bz}});
+        assert (o05 === {61'b0, 3'b000});
+        assert (o06 === {61'b0, 3'b111});
+        assert (o07 === {61'b0, 3'bxxx});
+        assert (o08 === {61'b0, 3'bzzz});
+        assert (o09 === {64 {1'b0}});
+        assert (o10 === {64 {1'b1}});
+        assert (o11 === {64 {1'bx}});
+        assert (o12 === {64 {1'bz}});
+    end
+endmodule
diff --git a/tests/verilog/unbased_unsized.ys b/tests/verilog/unbased_unsized.ys
new file mode 100644
index 000000000..e1bc99c64
--- /dev/null
+++ b/tests/verilog/unbased_unsized.ys
@@ -0,0 +1,7 @@
+read_verilog -sv unbased_unsized.sv
+hierarchy
+proc
+flatten
+opt -full
+select -module top
+sat -verify -seq 1 -tempinduct -prove-asserts -show-all
-- 
cgit v1.2.3


From d555454969aed080d345b044eefb20a2ce53eae2 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Marcelina=20Ko=C5=9Bcielnicka?= <mwk@0x04.net>
Date: Thu, 4 Mar 2021 17:55:57 +0100
Subject: tests/bram: Do not generate write address collisions.

These have no defined semantics, making the tests non-deterministic.
---
 tests/bram/generate.py | 28 +++++++++++++++++++++++-----
 1 file changed, 23 insertions(+), 5 deletions(-)

(limited to 'tests')

diff --git a/tests/bram/generate.py b/tests/bram/generate.py
index def0b23c1..79dd500a3 100644
--- a/tests/bram/generate.py
+++ b/tests/bram/generate.py
@@ -93,18 +93,22 @@ def create_bram(dsc_f, sim_f, ref_f, tb_f, k1, k2, or_next):
     tb_dout = list()
     tb_addrlist = list()
 
+    addrmask = (1 << abits) - 1
+
     for i in range(10):
-        tb_addrlist.append(random.randrange(1048576))
+        tb_addrlist.append(random.randrange(1048576) & addrmask)
 
     t = random.randrange(1048576)
     for i in range(10):
-        tb_addrlist.append(t ^ (1 << i))
+        tb_addrlist.append((t ^ (1 << i)) & addrmask)
 
     v_stmts.append("(* nomem2reg *) reg [%d:0] memory [0:%d];" % (dbits-1, 2**abits-1))
 
     portindex = 0
     last_always_hdr = (-1, "")
 
+    addr2en = {}
+
     for p1 in range(groups):
         for p2 in range(ports[p1]):
             pf = "%c%d" % (chr(ord("A") + p1), p2 + 1)
@@ -143,6 +147,7 @@ def create_bram(dsc_f, sim_f, ref_f, tb_f, k1, k2, or_next):
                 v_stmts.append("input [%d:0] %sEN;" % (enable[p1]-1, pf))
                 tb_decls.append("reg [%d:0] %sEN;" % (enable[p1]-1, pf))
                 tb_din.append("%sEN" % pf)
+                addr2en["%sADDR" % pf] = "%sEN" % pf
 
             assign_op = "<="
             if clocks[p1] == 0:
@@ -247,10 +252,23 @@ def create_bram(dsc_f, sim_f, ref_f, tb_f, k1, k2, or_next):
         print("    #100;", file=tb_f)
         print("    $display(\"bram_%02d_%02d %3d: %%b %%b %%s\", %s, %s, error ? \"ERROR\" : \"OK\");" %
                 (k1, k2, i, expr_dout, expr_dout_ref), file=tb_f)
-        for p in tb_din:
-            print("    %s <= %d;" % (p, random.randrange(1048576)), file=tb_f)
+        a2e = {}
         for p in tb_addr:
-            print("    %s <= %d;" % (p, random.choice(tb_addrlist)), file=tb_f)
+            addr = random.choice(tb_addrlist)
+            if p in addr2en:
+                if addr not in a2e:
+                    a2e[addr] = []
+                a2e[addr].append(addr2en[p])
+            print("    %s <= %d;" % (p, addr), file=tb_f)
+        enzero = set()
+        for v in a2e.values():
+            x = random.choice(v)
+            for s in v:
+                if s != x:
+                    enzero.add(s)
+        for p in tb_din:
+            val = 0 if p in enzero else random.randrange(1048576)
+            print("    %s <= %d;" % (p, val), file=tb_f)
         print("    #900;", file=tb_f)
 
     print("  end", file=tb_f)
-- 
cgit v1.2.3


From 760284033d6f255790d44bfcda0d1625a0c7bc87 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Marcelina=20Ko=C5=9Bcielnicka?= <mwk@0x04.net>
Date: Sat, 6 Mar 2021 03:59:03 +0100
Subject: proc_dff: Fix emitted FF when a register is not assigned in async
 reset

Fixes #2619.
---
 tests/proc/bug2619.ys | 23 +++++++++++++++++++++++
 1 file changed, 23 insertions(+)
 create mode 100644 tests/proc/bug2619.ys

(limited to 'tests')

diff --git a/tests/proc/bug2619.ys b/tests/proc/bug2619.ys
new file mode 100644
index 000000000..a080b94f5
--- /dev/null
+++ b/tests/proc/bug2619.ys
@@ -0,0 +1,23 @@
+read_verilog << EOT
+
+module top(...);
+
+input D1, D2, R, CLK;
+output reg Q1, Q2;
+
+always @(posedge CLK, posedge R) begin
+	Q1 <= 0;
+	if (!R) begin
+		Q1 <= D1;
+		Q2 <= D2;
+	end
+end
+
+endmodule
+
+EOT
+
+proc
+opt
+select -assert-count 1 t:$adff
+select -assert-count 1 t:$dffe
-- 
cgit v1.2.3


From a3528649c82ed7c6d14850affef8e9368f4fe065 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Marcelina=20Ko=C5=9Bcielnicka?= <mwk@0x04.net>
Date: Tue, 23 Feb 2021 19:42:51 +0100
Subject: memory_dff: Remove now-useless write port handling.

---
 tests/opt/opt_clean_mem.ys | 1 -
 tests/tools/autotest.sh    | 2 +-
 2 files changed, 1 insertion(+), 2 deletions(-)

(limited to 'tests')

diff --git a/tests/opt/opt_clean_mem.ys b/tests/opt/opt_clean_mem.ys
index b35b15871..d08943da4 100644
--- a/tests/opt/opt_clean_mem.ys
+++ b/tests/opt/opt_clean_mem.ys
@@ -22,7 +22,6 @@ endmodule
 EOT
 
 proc
-memory_dff
 
 select -assert-count 2 t:$memrd
 select -assert-count 1 t:$memwr
diff --git a/tests/tools/autotest.sh b/tests/tools/autotest.sh
index 72a3d51eb..e4aef9917 100755
--- a/tests/tools/autotest.sh
+++ b/tests/tools/autotest.sh
@@ -197,7 +197,7 @@ do
 			test_passes -f "$frontend $include_opts" -p "hierarchy; synth -run coarse; techmap; opt; abc -dff" ${bn}_ref.${refext}
 			if [ -n "$firrtl2verilog" ]; then
 			    if test -z "$xfirrtl" || ! grep "$fn" "$xfirrtl" ; then
-				"$toolsdir"/../../yosys -b "firrtl" -o ${bn}_ref.fir -f "$frontend $include_opts" -p "prep -nordff; proc; opt -nodffe -nosdff; fsm; opt; memory; opt -full -fine; pmuxtree" ${bn}_ref.${refext}
+				"$toolsdir"/../../yosys -b "firrtl" -o ${bn}_ref.fir -f "$frontend $include_opts" -p "prep; proc; opt -nodffe -nosdff; fsm; opt; memory; opt -full -fine; pmuxtree" ${bn}_ref.${refext}
 				$firrtl2verilog -i ${bn}_ref.fir -o ${bn}_ref.fir.v
 				test_passes -f "$frontend $include_opts" -p "hierarchy; proc; opt -nodffe -nosdff; fsm; opt; memory; opt -full -fine" ${bn}_ref.fir.v
 			    fi
-- 
cgit v1.2.3


From cb9f3b6abfbc769589e5e5ceb2497955a155065c Mon Sep 17 00:00:00 2001
From: Zachary Snow <zach@zachjs.com>
Date: Thu, 11 Mar 2021 11:49:15 -0500
Subject: verilog: disallow overriding global parameters

It was previously possible to override global parameters on a
per-instance basis. This could be dangerous when using positional
parameter bindings, hiding oversupplied parameters.
---
 tests/verilog/global_parameter.ys | 16 ++++++++++++++++
 1 file changed, 16 insertions(+)
 create mode 100644 tests/verilog/global_parameter.ys

(limited to 'tests')

diff --git a/tests/verilog/global_parameter.ys b/tests/verilog/global_parameter.ys
new file mode 100644
index 000000000..a7a3cddc7
--- /dev/null
+++ b/tests/verilog/global_parameter.ys
@@ -0,0 +1,16 @@
+read_verilog -sv <<EOF
+parameter P = 1;
+module example(
+    output integer out
+);
+    assign out = P;
+endmodule
+module top(
+    output integer out
+);
+    example #(2) e1(out);
+endmodule
+EOF
+
+logger -expect error "Can't find object for defparam" 1
+hierarchy
-- 
cgit v1.2.3


From 640b9927fae23d3127cc9ecb56ccbc8a2c66afbe Mon Sep 17 00:00:00 2001
From: Zachary Snow <zach@zachjs.com>
Date: Thu, 11 Mar 2021 13:05:04 -0500
Subject: sv: allow globals in one file to depend on globals in another

This defers the simplification of globals so that globals in one file
may depend on globals in other files. Adds a simplify() call downstream
because globals are appended at the end.
---
 tests/verilog/parameters_across_files.ys | 20 ++++++++++++++++++++
 1 file changed, 20 insertions(+)
 create mode 100644 tests/verilog/parameters_across_files.ys

(limited to 'tests')

diff --git a/tests/verilog/parameters_across_files.ys b/tests/verilog/parameters_across_files.ys
new file mode 100644
index 000000000..c53e40179
--- /dev/null
+++ b/tests/verilog/parameters_across_files.ys
@@ -0,0 +1,20 @@
+read_verilog -sv <<EOF
+parameter Q = 1;
+EOF
+read_verilog -sv <<EOF
+parameter P = Q;
+module top(
+    output integer out
+);
+    assign out = P;
+    always @*
+        assert (out == 1);
+endmodule
+EOF
+
+hierarchy
+proc
+flatten
+opt -full
+select -module top
+sat -verify -seq 1 -tempinduct -prove-asserts -show-all
-- 
cgit v1.2.3


From f965b3fa54eb38bf7f0246acc874087fc696f7f5 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Marcelina=20Ko=C5=9Bcielnicka?= <mwk@0x04.net>
Date: Tue, 9 Mar 2021 02:54:56 +0100
Subject: rtlil: Disallow 0-width chunks in SigSpec.

Among other problems, this also fixes equality comparisons between
SigSpec by enforcing a canonical form.

Also fix another minor issue with possible non-canonical SigSpec.

Fixes #2623.
---
 tests/opt/bug2623.ys | 14 ++++++++++++++
 1 file changed, 14 insertions(+)
 create mode 100644 tests/opt/bug2623.ys

(limited to 'tests')

diff --git a/tests/opt/bug2623.ys b/tests/opt/bug2623.ys
new file mode 100644
index 000000000..2ff23ea6f
--- /dev/null
+++ b/tests/opt/bug2623.ys
@@ -0,0 +1,14 @@
+read_rtlil << EOT
+
+module \top
+  wire output 1 \a
+  wire width 0 $dummy
+  cell \abc \abc
+    connect \a \a
+    connect \b $dummy
+  end
+end
+
+EOT
+
+opt_clean
-- 
cgit v1.2.3


From 3af871f969f7f5bd5201bac17544559671312a6f Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Marcelina=20Ko=C5=9Bcielnicka?= <mwk@0x04.net>
Date: Tue, 9 Mar 2021 21:32:16 +0100
Subject: opt_clean: Remove init attribute bits together with removed DFFs.

Fixes #2546.
---
 tests/opt/opt_clean_init.ys | 31 ++++++++++++++++++++-----------
 1 file changed, 20 insertions(+), 11 deletions(-)

(limited to 'tests')

diff --git a/tests/opt/opt_clean_init.ys b/tests/opt/opt_clean_init.ys
index 0d567608d..7933f3e17 100644
--- a/tests/opt/opt_clean_init.ys
+++ b/tests/opt/opt_clean_init.ys
@@ -1,13 +1,22 @@
-logger -expect warning "Initial value conflict for \\y resolving to 1'0 but with init 1'1" 1
-logger -expect-no-warnings
-read_verilog <<EOT
-module top;
-(* init=1'b0 *) wire w = 1'b0;
-(* init=1'bx *) wire x = 1'b0;
-(* init=1'b1 *) wire y = 1'b0;
-(* init=1'b0 *) wire z = 1'bx;
+read_verilog << EOT
+module top(...);
+
+input [1:0] D;
+input C;
+output O;
+reg [1:0] Q;
+
+initial Q = 0;
+
+always @(posedge C)
+        Q <= D;
+
+assign O = Q[1];
+
 endmodule
 EOT
-clean
-select -assert-count 1 a:init
-select -assert-count 1 w:y a:init %i
+
+synth
+check -assert -initdrv
+
+select -assert-count 1 a:init=2'b0x
-- 
cgit v1.2.3


From a55bf6375b38a955de4589a66e4d2992ac7dd621 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Marcelina=20Ko=C5=9Bcielnicka?= <mwk@0x04.net>
Date: Fri, 12 Mar 2021 17:05:39 +0100
Subject: proc_arst: Add special-casing of clock signal in conditionals.
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

The already-existing special case for conditionals on clock has been
remade as follows:

- now triggered for the last remaining edge trigger after all others
  have been converted to async reset, not just when there is only one
  sync rule in the first place
- does not require all contained assignments to be constant, as opposed
  to a reset conditional — merely const-folds the condition

In addition, the code has been refactored a bit; as a bonus, the
priority order of async resets found is now preserved in resulting sync
rule ordering (though this is not yet respected by proc_dff).

Fixes #2656.
---
 tests/proc/bug2656.ys | 31 +++++++++++++++++++++++++++++++
 1 file changed, 31 insertions(+)
 create mode 100644 tests/proc/bug2656.ys

(limited to 'tests')

diff --git a/tests/proc/bug2656.ys b/tests/proc/bug2656.ys
new file mode 100644
index 000000000..3fe7cb33b
--- /dev/null
+++ b/tests/proc/bug2656.ys
@@ -0,0 +1,31 @@
+read_verilog <<EOT
+module top (...);
+
+input clk, rst, d1, d2;
+output q1, q2;
+
+always @(posedge clk)
+	if (clk)
+		q1 <= d1;
+
+always @(posedge clk, posedge rst)
+	if (rst)
+		q2 <= 0;
+	else if (clk)
+		q2 <= d2;
+
+endmodule
+EOT
+
+proc
+opt
+
+select -assert-count 1 t:$dff
+select -assert-count 1 w:clk %a %co t:$dff %i
+select -assert-count 1 w:d1 %a %co t:$dff %i
+select -assert-count 1 w:q1 %a %ci t:$dff %i
+select -assert-count 1 t:$adff
+select -assert-count 1 w:clk %a %co t:$adff %i
+select -assert-count 1 w:rst %a %co t:$adff %i
+select -assert-count 1 w:d2 %a %co t:$adff %i
+select -assert-count 1 w:q2 %a %ci t:$adff %i
-- 
cgit v1.2.3


From 4f187d53c5a0580275857ec308b41f57808ec727 Mon Sep 17 00:00:00 2001
From: Zachary Snow <zach@zachjs.com>
Date: Thu, 4 Mar 2021 14:07:56 -0500
Subject: verilog: support module scope identifiers in parametric modules

---
 tests/simple/module_scope.v | 29 +++++++++++++++++++++++++++++
 1 file changed, 29 insertions(+)
 create mode 100644 tests/simple/module_scope.v

(limited to 'tests')

diff --git a/tests/simple/module_scope.v b/tests/simple/module_scope.v
new file mode 100644
index 000000000..3e46b72ef
--- /dev/null
+++ b/tests/simple/module_scope.v
@@ -0,0 +1,29 @@
+`default_nettype none
+
+module Example(o1, o2);
+   parameter [31:0] v1 = 10;
+   parameter [31:0] v2 = 20;
+   output [31:0] o1, o2;
+   assign Example.o1 = Example.v1;
+   assign Example.o2 = Example.v2;
+endmodule
+
+module ExampleLong(o1, o2);
+   parameter [31:0] ThisIsAnExtremelyLongParameterNameToTriggerTheSHA1Checksum1 = 10;
+   parameter [31:0] ThisIsAnExtremelyLongParameterNameToTriggerTheSHA1Checksum2 = 20;
+   output [31:0] o1, o2;
+   assign ExampleLong.o1 = ExampleLong.ThisIsAnExtremelyLongParameterNameToTriggerTheSHA1Checksum1;
+   assign ExampleLong.o2 = ExampleLong.ThisIsAnExtremelyLongParameterNameToTriggerTheSHA1Checksum2;
+endmodule
+
+module top(
+   output [31:0] a1, a2, b1, b2, c1, c2,
+   output [31:0] d1, d2, e1, e2, f1, f2
+);
+   Example a(a1, a2);
+   Example #(1) b(b1, b2);
+   Example #(1, 2) c(c1, c2);
+   ExampleLong d(d1, d2);
+   ExampleLong #(1) e(e1, e2);
+   ExampleLong #(1, 2) f(f1, f2);
+endmodule
-- 
cgit v1.2.3


From dd6d34f461910a120ac95c485fe34cca6485b95e Mon Sep 17 00:00:00 2001
From: gatecat <gatecat@ds0.me>
Date: Wed, 17 Mar 2021 12:06:09 +0000
Subject: blackbox: Include whiteboxed modules

Signed-off-by: gatecat <gatecat@ds0.me>
---
 tests/various/blackbox_wb.ys | 14 ++++++++++++++
 1 file changed, 14 insertions(+)
 create mode 100644 tests/various/blackbox_wb.ys

(limited to 'tests')

diff --git a/tests/various/blackbox_wb.ys b/tests/various/blackbox_wb.ys
new file mode 100644
index 000000000..f9c9bec06
--- /dev/null
+++ b/tests/various/blackbox_wb.ys
@@ -0,0 +1,14 @@
+read_verilog <<EOT
+(* whitebox *)
+module box(input a, output q);
+assign q = ~a;
+endmodule
+
+module top(input a, output q);
+box box_i(.a(a), .q(q));
+endmodule
+EOT
+select -assert-count 1 =box/t:$not
+blackbox =box
+select -assert-count 0 =A:whitebox
+select -assert-count 0 =box/t:$not
-- 
cgit v1.2.3


From 092e923330ce23adffa7843a27bdba8a0b139e58 Mon Sep 17 00:00:00 2001
From: Xiretza <xiretza@xiretza.xyz>
Date: Wed, 17 Mar 2021 00:18:36 +0100
Subject: verilog: fix buf/not primitives with multiple outputs

From IEEE1364-2005, section 7.3 buf and not gates:

> These two logic gates shall have one input and one or more outputs.
> The last terminal in the terminal list shall connect to the input of the
> logic gate, and the other terminals shall connect to the outputs of
> the logic gate.

yosys does not follow this and instead interprets the first argument as
the output, the second as the input and ignores the rest.
---
 tests/simple/verilog_primitives.v | 15 +++++++++++++++
 1 file changed, 15 insertions(+)
 create mode 100644 tests/simple/verilog_primitives.v

(limited to 'tests')

diff --git a/tests/simple/verilog_primitives.v b/tests/simple/verilog_primitives.v
new file mode 100644
index 000000000..0ee07393b
--- /dev/null
+++ b/tests/simple/verilog_primitives.v
@@ -0,0 +1,15 @@
+module verilog_primitives (
+	input wire in1, in2, in3,
+	output wire out_buf0, out_buf1, out_buf2, out_buf3, out_buf4,
+	output wire out_not0, out_not1, out_not2,
+	output wire out_xnor
+);
+
+buf u_buf0 (out_buf0, in1);
+buf u_buf1 (out_buf1, out_buf2, out_buf3, out_buf4, in2);
+
+not u_not0 (out_not0, out_not1, out_not2, in1);
+
+xnor u_xnor0 (out_xnor, in1, in2, in3);
+
+endmodule
-- 
cgit v1.2.3


From f71c2dcca6b63ad3cbd3d5b6f51f67f9cd85f03e Mon Sep 17 00:00:00 2001
From: Zachary Snow <zach@zachjs.com>
Date: Tue, 16 Mar 2021 11:06:40 -0400
Subject: sv: carry over global typedefs from previous files

This breaks the ability to use a global typename as a standard
identifier in a subsequent input file. This is otherwise backwards
compatible, including for sources which previously included conflicting
typedefs in each input file.
---
 tests/verilog/typedef_across_files.ys    | 23 ++++++++++++++++++++
 tests/verilog/typedef_legacy_conflict.ys | 37 ++++++++++++++++++++++++++++++++
 2 files changed, 60 insertions(+)
 create mode 100644 tests/verilog/typedef_across_files.ys
 create mode 100644 tests/verilog/typedef_legacy_conflict.ys

(limited to 'tests')

diff --git a/tests/verilog/typedef_across_files.ys b/tests/verilog/typedef_across_files.ys
new file mode 100644
index 000000000..ca9bba736
--- /dev/null
+++ b/tests/verilog/typedef_across_files.ys
@@ -0,0 +1,23 @@
+read_verilog -sv <<EOF
+typedef logic T;
+EOF
+
+read_verilog -sv <<EOF
+typedef T [3:0] S;
+EOF
+
+read_verilog -sv <<EOF
+module top;
+    T t;
+    S s;
+    always @* begin
+        assert ($bits(t) == 1);
+        assert ($bits(s) == 4);
+    end
+endmodule
+EOF
+
+proc
+opt -full
+select -module top
+sat -verify -seq 1 -tempinduct -prove-asserts -show-all
diff --git a/tests/verilog/typedef_legacy_conflict.ys b/tests/verilog/typedef_legacy_conflict.ys
new file mode 100644
index 000000000..8dff4ec5f
--- /dev/null
+++ b/tests/verilog/typedef_legacy_conflict.ys
@@ -0,0 +1,37 @@
+read_verilog -sv <<EOF
+typedef logic T;
+typedef T [3:0] S;
+EOF
+
+read_verilog -sv <<EOF
+module example;
+    // S and T refer to the definitions from the first file
+    T t;
+    S s;
+    always @* begin
+        assert ($bits(t) == 1);
+        assert ($bits(s) == 4);
+    end
+endmodule
+
+typedef byte T;
+typedef T S;
+
+module top;
+    // S and T refer to the most recent overrides
+    T t;
+    S s;
+    always @* begin
+        assert ($bits(t) == 8);
+        assert ($bits(s) == 8);
+    end
+    example e();
+endmodule
+EOF
+
+hierarchy
+proc
+flatten
+opt -full
+select -module top
+sat -verify -seq 1 -tempinduct -prove-asserts -show-all
-- 
cgit v1.2.3


From cae905f55128a77e8d2eecc75d861292d79baa79 Mon Sep 17 00:00:00 2001
From: gatecat <gatecat@ds0.me>
Date: Wed, 17 Mar 2021 12:16:53 +0000
Subject: Blackbox all whiteboxes after synthesis

This prevents issues like processes in whiteboxes triggering an error in
the JSON backend.

Signed-off-by: gatecat <gatecat@ds0.me>
---
 tests/arch/ecp5/mux.ys | 18 +++++++++---------
 1 file changed, 9 insertions(+), 9 deletions(-)

(limited to 'tests')

diff --git a/tests/arch/ecp5/mux.ys b/tests/arch/ecp5/mux.ys
index 92463aa32..db63dda5f 100644
--- a/tests/arch/ecp5/mux.ys
+++ b/tests/arch/ecp5/mux.ys
@@ -15,9 +15,9 @@ proc
 equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd mux4 # Constrain all select calls below inside the top module
-select -assert-count 1 t:L6MUX21
-select -assert-count 4 t:LUT4
-select -assert-count 2 t:PFUMX
+select -assert-max 1 t:L6MUX21
+select -assert-max 4 t:LUT4
+select -assert-max 2 t:PFUMX
 
 select -assert-none t:LUT4 t:L6MUX21 t:PFUMX %% t:* %D
 
@@ -27,9 +27,9 @@ proc
 equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd mux8 # Constrain all select calls below inside the top module
-select -assert-count 1 t:L6MUX21
-select -assert-count 7 t:LUT4
-select -assert-count 2 t:PFUMX
+select -assert-max 1 t:L6MUX21
+select -assert-max 7 t:LUT4
+select -assert-max 2 t:PFUMX
 
 select -assert-none t:LUT4 t:L6MUX21 t:PFUMX %% t:* %D
 
@@ -39,8 +39,8 @@ proc
 equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd mux16 # Constrain all select calls below inside the top module
-select -assert-count 8 t:L6MUX21
-select -assert-count 26 t:LUT4
-select -assert-count 12 t:PFUMX
+select -assert-max 12 t:L6MUX21
+select -assert-max 34 t:LUT4
+select -assert-max 17 t:PFUMX
 
 select -assert-none t:LUT4 t:L6MUX21 t:PFUMX %% t:* %D
-- 
cgit v1.2.3


From 8740fdf1d799fd8a3196bac28fe4e418e74f2acc Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Marcelina=20Ko=C5=9Bcielnicka?= <mwk@0x04.net>
Date: Wed, 17 Mar 2021 18:30:49 +0100
Subject: ast: Use better parameter serialization for paramod names.

Calling log_signal is problematic for several reasons:

- with recent changes, empty string is serialized as { }, which violates
  the "no spaces in IdString" rule
- the type (plain / real / signed / string) is dropped, wrongly conflating
  functionally different values and potentially introducing a subtle
  elaboration bug

Instead, use a custom simple serialization scheme.
---
 tests/arch/xilinx/abc9_dff.ys | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

(limited to 'tests')

diff --git a/tests/arch/xilinx/abc9_dff.ys b/tests/arch/xilinx/abc9_dff.ys
index 210e87477..0ba3901f7 100644
--- a/tests/arch/xilinx/abc9_dff.ys
+++ b/tests/arch/xilinx/abc9_dff.ys
@@ -50,10 +50,10 @@ FDCE_1 /*#(.INIT(1))*/ fd7(.C(C), .CE(1'b0), .D(D), .CLR(1'b0), .Q(Q[6]));
 FDPE_1 #(.INIT(1)) fd8(.C(C), .CE(1'b0), .D(D), .PRE(1'b0), .Q(Q[7]));
 endmodule
 EOT
-logger -expect warning "Whitebox '\$paramod\\FDRE\\INIT=1' with \(\* abc9_flop \*\) contains a \$dff cell with non-zero initial state -- this is not supported for ABC9 sequential synthesis. Treating as a blackbox\." 1
-logger -expect warning "Whitebox '\$paramod\\FDRE_1\\INIT=1' with \(\* abc9_flop \*\) contains a \$dff cell with non-zero initial state -- this is not supported for ABC9 sequential synthesis. Treating as a blackbox\." 1
+logger -expect warning "Whitebox '\$paramod\\FDRE\\INIT=.*1' with \(\* abc9_flop \*\) contains a \$dff cell with non-zero initial state -- this is not supported for ABC9 sequential synthesis. Treating as a blackbox\." 1
+logger -expect warning "Whitebox '\$paramod\\FDRE_1\\INIT=.*1' with \(\* abc9_flop \*\) contains a \$dff cell with non-zero initial state -- this is not supported for ABC9 sequential synthesis. Treating as a blackbox\." 1
 logger -expect warning "Whitebox 'FDSE' with \(\* abc9_flop \*\) contains a \$dff cell with non-zero initial state -- this is not supported for ABC9 sequential synthesis. Treating as a blackbox\." 1
-logger -expect warning "Whitebox '\$paramod\\FDSE_1\\INIT=1' with \(\* abc9_flop \*\) contains a \$dff cell with non-zero initial state -- this is not supported for ABC9 sequential synthesis. Treating as a blackbox\." 1
+logger -expect warning "Whitebox '\$paramod\\FDSE_1\\INIT=.*1' with \(\* abc9_flop \*\) contains a \$dff cell with non-zero initial state -- this is not supported for ABC9 sequential synthesis. Treating as a blackbox\." 1
 equiv_opt -assert -multiclock -map +/xilinx/cells_sim.v synth_xilinx -abc9 -dff -noiopad -noclkbuf
 design -load postopt
 select -assert-count 8 t:FD*
-- 
cgit v1.2.3


From f4298b057ae0939b83283c8c7431097e71a32b62 Mon Sep 17 00:00:00 2001
From: Lofty <dan.ravensloft@gmail.com>
Date: Wed, 17 Mar 2021 02:34:30 +0000
Subject: quicklogic: PolarPro 3 support
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Co-authored-by: Grzegorz Latosiński <glatosinski@antmicro.com>
Co-authored-by: Maciej Kurc <mkurc@antmicro.com>
Co-authored-by: Tarachand Pagarani <tpagarani@quicklogic.com>
Co-authored-by: Lalit Sharma <lsharma@quicklogic.com>
Co-authored-by: kkumar23 <kkumar@quicklogic.com>
---
 tests/arch/quicklogic/add_sub.ys  | 11 +++++++
 tests/arch/quicklogic/adffs.ys    | 67 +++++++++++++++++++++++++++++++++++++++
 tests/arch/quicklogic/counter.ys  | 18 +++++++++++
 tests/arch/quicklogic/dffs.ys     | 20 ++++++++++++
 tests/arch/quicklogic/fsm.ys      | 24 ++++++++++++++
 tests/arch/quicklogic/latches.ys  | 39 +++++++++++++++++++++++
 tests/arch/quicklogic/logic.ys    | 14 ++++++++
 tests/arch/quicklogic/mux.ys      | 52 ++++++++++++++++++++++++++++++
 tests/arch/quicklogic/run-test.sh |  4 +++
 tests/arch/quicklogic/tribuf.ys   | 13 ++++++++
 10 files changed, 262 insertions(+)
 create mode 100644 tests/arch/quicklogic/add_sub.ys
 create mode 100644 tests/arch/quicklogic/adffs.ys
 create mode 100644 tests/arch/quicklogic/counter.ys
 create mode 100644 tests/arch/quicklogic/dffs.ys
 create mode 100644 tests/arch/quicklogic/fsm.ys
 create mode 100644 tests/arch/quicklogic/latches.ys
 create mode 100644 tests/arch/quicklogic/logic.ys
 create mode 100644 tests/arch/quicklogic/mux.ys
 create mode 100755 tests/arch/quicklogic/run-test.sh
 create mode 100644 tests/arch/quicklogic/tribuf.ys

(limited to 'tests')

diff --git a/tests/arch/quicklogic/add_sub.ys b/tests/arch/quicklogic/add_sub.ys
new file mode 100644
index 000000000..168b3f8b3
--- /dev/null
+++ b/tests/arch/quicklogic/add_sub.ys
@@ -0,0 +1,11 @@
+read_verilog ../common/add_sub.v
+hierarchy -top top
+equiv_opt -assert -map +/quicklogic/lut_sim.v -map +/quicklogic/pp3_cells_sim.v synth_quicklogic -family pp3 # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd top # Constrain all select calls below inside the top module
+select -assert-count 3 t:LUT2
+select -assert-count 4 t:LUT3
+select -assert-count 4 t:LUT4
+select -assert-count 8 t:inpad
+select -assert-count 8 t:outpad
+select -assert-none t:LUT2 t:LUT3 t:LUT4 t:inpad t:outpad %% t:* %D
diff --git a/tests/arch/quicklogic/adffs.ys b/tests/arch/quicklogic/adffs.ys
new file mode 100644
index 000000000..41a175844
--- /dev/null
+++ b/tests/arch/quicklogic/adffs.ys
@@ -0,0 +1,67 @@
+read_verilog ../common/adffs.v
+design -save read
+
+hierarchy -top adff
+proc
+equiv_opt -async2sync -assert -map +/quicklogic/pp3_cells_sim.v -map +/quicklogic/cells_sim.v synth_quicklogic # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd adff # Constrain all select calls below inside the top module
+select -assert-count 1 t:dffepc
+select -assert-count 1 t:logic_0
+select -assert-count 1 t:logic_1
+select -assert-count 1 t:inpad
+select -assert-count 1 t:outpad
+select -assert-count 2 t:ckpad
+
+select -assert-none t:dffepc t:logic_0 t:logic_1 t:inpad t:outpad t:ckpad %% t:* %D
+
+
+design -load read
+hierarchy -top adffn
+proc
+equiv_opt -async2sync -assert -map +/quicklogic/pp3_cells_sim.v -map +/quicklogic/cells_sim.v -map +/quicklogic/lut_sim.v synth_quicklogic # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd adffn # Constrain all select calls below inside the top module
+select -assert-count 1 t:LUT1
+select -assert-count 1 t:dffepc
+select -assert-count 1 t:logic_0
+select -assert-count 1 t:logic_1
+select -assert-count 2 t:inpad
+select -assert-count 1 t:outpad
+select -assert-count 1 t:ckpad
+
+select -assert-none t:LUT1 t:dffepc t:logic_0 t:logic_1 t:inpad t:outpad t:ckpad %% t:* %D
+
+
+design -load read
+hierarchy -top dffs
+proc
+equiv_opt -async2sync -assert -map +/quicklogic/pp3_cells_sim.v -map +/quicklogic/cells_sim.v -map +/quicklogic/lut_sim.v synth_quicklogic # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd dffs # Constrain all select calls below inside the top module
+select -assert-count 1 t:LUT2
+select -assert-count 1 t:dffepc
+select -assert-count 1 t:logic_0
+select -assert-count 1 t:logic_1
+select -assert-count 3 t:inpad
+select -assert-count 1 t:outpad
+select -assert-count 1 t:ckpad
+
+select -assert-none t:LUT2 t:dffepc t:logic_0 t:logic_1 t:inpad t:outpad t:ckpad %% t:* %D
+
+
+design -load read
+hierarchy -top ndffnr
+proc
+equiv_opt -async2sync -assert -map +/quicklogic/pp3_cells_sim.v -map +/quicklogic/cells_sim.v -map +/quicklogic/lut_sim.v synth_quicklogic # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd ndffnr # Constrain all select calls below inside the top module
+select -assert-count 1 t:LUT1
+select -assert-count 1 t:LUT2
+select -assert-count 1 t:dffepc
+select -assert-count 1 t:logic_0
+select -assert-count 1 t:logic_1
+select -assert-count 4 t:inpad
+select -assert-count 1 t:outpad
+
+select -assert-none t:LUT1 t:LUT2 t:dffepc t:logic_0 t:logic_1 t:inpad t:outpad %% t:* %D
diff --git a/tests/arch/quicklogic/counter.ys b/tests/arch/quicklogic/counter.ys
new file mode 100644
index 000000000..0c04b5742
--- /dev/null
+++ b/tests/arch/quicklogic/counter.ys
@@ -0,0 +1,18 @@
+read_verilog ../common/counter.v
+hierarchy -top top
+proc
+flatten
+equiv_opt -assert -multiclock -map +/quicklogic/pp3_cells_sim.v -map +/quicklogic/cells_sim.v -map +/quicklogic/lut_sim.v synth_quicklogic # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd top # Constrain all select calls below inside the top module
+select -assert-count 1 t:LUT1
+select -assert-count 5 t:LUT2
+select -assert-count 2 t:LUT3
+select -assert-count 3 t:LUT4
+select -assert-count 8 t:dffepc
+select -assert-count 1 t:logic_0
+select -assert-count 1 t:logic_1
+select -assert-count 8 t:outpad
+select -assert-count 2 t:ckpad
+
+select -assert-none t:LUT1 t:LUT2 t:LUT3 t:LUT4 t:dffepc t:logic_0 t:logic_1 t:outpad t:ckpad %% t:* %D
diff --git a/tests/arch/quicklogic/dffs.ys b/tests/arch/quicklogic/dffs.ys
new file mode 100644
index 000000000..2e0a34540
--- /dev/null
+++ b/tests/arch/quicklogic/dffs.ys
@@ -0,0 +1,20 @@
+read_verilog ../common/dffs.v
+rename dff my_dff # Work around conflicting module names between test and vendor cells
+rename dffe my_dffe
+design -save read
+
+hierarchy -top my_dff
+proc
+equiv_opt -async2sync -assert -map +/quicklogic/pp3_cells_sim.v -map +/quicklogic/cells_sim.v synth_quicklogic # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd dff # Constrain all select calls below inside the top module
+select -assert-none t:*
+
+design -load read
+hierarchy -top my_dffe
+proc
+equiv_opt -async2sync -assert -map +/quicklogic/pp3_cells_sim.v -map +/quicklogic/cells_sim.v synth_quicklogic # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd dffe # Constrain all select calls below inside the top module
+
+select -assert-none t:*
\ No newline at end of file
diff --git a/tests/arch/quicklogic/fsm.ys b/tests/arch/quicklogic/fsm.ys
new file mode 100644
index 000000000..7ed36b9e4
--- /dev/null
+++ b/tests/arch/quicklogic/fsm.ys
@@ -0,0 +1,24 @@
+read_verilog ../common/fsm.v
+hierarchy -top fsm
+proc
+flatten
+
+equiv_opt -run :prove -map +/quicklogic/pp3_cells_sim.v -map +/quicklogic/cells_sim.v -map +/quicklogic/lut_sim.v synth_quicklogic
+async2sync
+miter -equiv -make_assert -flatten gold gate miter
+sat -verify -prove-asserts -show-public -set-at 1 in_reset 1 -seq 20 -prove-skip 1 miter
+
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd fsm # Constrain all select calls below inside the top module
+
+select -assert-count 3 t:LUT2
+select -assert-count 6 t:LUT3
+select -assert-count 7 t:LUT4
+select -assert-count 6 t:dffepc
+select -assert-count 1 t:logic_0
+select -assert-count 1 t:logic_1
+select -assert-count 3 t:inpad
+select -assert-count 2 t:outpad
+select -assert-count 1 t:ckpad
+
+select -assert-none t:LUT2 t:LUT3 t:LUT4 t:dffepc t:logic_0 t:logic_1 t:inpad t:outpad t:ckpad %% t:* %D
diff --git a/tests/arch/quicklogic/latches.ys b/tests/arch/quicklogic/latches.ys
new file mode 100644
index 000000000..d7652f749
--- /dev/null
+++ b/tests/arch/quicklogic/latches.ys
@@ -0,0 +1,39 @@
+read_verilog ../common/latches.v
+design -save read
+
+hierarchy -top latchp
+proc
+# Can't run any sort of equivalence check because latches are blown to LUTs
+synth_quicklogic
+cd latchp # Constrain all select calls below inside the top module
+select -assert-count 1 t:LUT3
+select -assert-count 3 t:inpad
+select -assert-count 1 t:outpad
+
+select -assert-none t:LUT3 t:inpad t:outpad %% t:* %D
+
+
+design -load read
+hierarchy -top latchn
+proc
+# Can't run any sort of equivalence check because latches are blown to LUTs
+synth_quicklogic
+cd latchn # Constrain all select calls below inside the top module
+select -assert-count 1 t:LUT3
+select -assert-count 3 t:inpad
+select -assert-count 1 t:outpad
+
+select -assert-none t:LUT3 t:inpad t:outpad %% t:* %D
+
+
+design -load read
+hierarchy -top latchsr
+proc
+# Can't run any sort of equivalence check because latches are blown to LUTs
+synth_quicklogic
+cd latchsr # Constrain all select calls below inside the top module
+select -assert-count 2 t:LUT3
+select -assert-count 5 t:inpad
+select -assert-count 1 t:outpad
+
+select -assert-none t:LUT3 t:inpad t:outpad %% t:* %D
diff --git a/tests/arch/quicklogic/logic.ys b/tests/arch/quicklogic/logic.ys
new file mode 100644
index 000000000..65f48a42b
--- /dev/null
+++ b/tests/arch/quicklogic/logic.ys
@@ -0,0 +1,14 @@
+read_verilog ../common/logic.v
+hierarchy -top top
+proc
+equiv_opt -assert -map +/quicklogic/pp3_cells_sim.v -map +/quicklogic/cells_sim.v -map +/quicklogic/lut_sim.v synth_quicklogic # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd top # Constrain all select calls below inside the top module
+
+select -assert-count 1 t:LUT1
+select -assert-count 6 t:LUT2
+select -assert-count 2 t:LUT4
+select -assert-count 8 t:inpad
+select -assert-count 10 t:outpad
+
+select -assert-none t:LUT1 t:LUT2 t:LUT4 t:inpad t:outpad %% t:* %D
diff --git a/tests/arch/quicklogic/mux.ys b/tests/arch/quicklogic/mux.ys
new file mode 100644
index 000000000..632d14687
--- /dev/null
+++ b/tests/arch/quicklogic/mux.ys
@@ -0,0 +1,52 @@
+read_verilog ../common/mux.v
+design -save read
+
+hierarchy -top mux2
+proc
+equiv_opt -assert -map +/quicklogic/pp3_cells_sim.v -map +/quicklogic/cells_sim.v -map +/quicklogic/lut_sim.v synth_quicklogic # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd mux2 # Constrain all select calls below inside the top module
+select -assert-count 1 t:LUT3
+select -assert-count 3 t:inpad
+select -assert-count 1 t:outpad
+
+select -assert-none t:LUT3 t:inpad t:outpad %% t:* %D
+
+design -load read
+hierarchy -top mux4
+proc
+equiv_opt -assert -map +/quicklogic/pp3_cells_sim.v -map +/quicklogic/cells_sim.v -map +/quicklogic/lut_sim.v synth_quicklogic # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd mux4 # Constrain all select calls below inside the top module
+select -assert-count 3 t:LUT3
+select -assert-count 6 t:inpad
+select -assert-count 1 t:outpad
+
+select -assert-none t:LUT3 t:inpad t:outpad %% t:* %D
+
+design -load read
+hierarchy -top mux8
+proc
+equiv_opt -assert -map +/quicklogic/pp3_cells_sim.v -map +/quicklogic/cells_sim.v -map +/quicklogic/lut_sim.v synth_quicklogic # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd mux8 # Constrain all select calls below inside the top module
+select -assert-count 4 t:LUT2
+select -assert-count 1 t:LUT3
+select -assert-count 2 t:mux4x0
+select -assert-count 11 t:inpad
+select -assert-count 1 t:outpad
+
+select -assert-none t:LUT2 t:LUT3 t:mux4x0 t:inpad t:outpad %% t:* %D
+
+design -load read
+hierarchy -top mux16
+proc
+equiv_opt -assert -map +/quicklogic/pp3_cells_sim.v -map +/quicklogic/cells_sim.v -map +/quicklogic/lut_sim.v synth_quicklogic # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd mux16 # Constrain all select calls below inside the top module
+select -assert-count 1 t:LUT3
+select -assert-count 2 t:mux8x0
+select -assert-count 20 t:inpad
+select -assert-count 1 t:outpad
+
+select -assert-none t:LUT3 t:mux8x0 t:inpad t:outpad %% t:* %D
diff --git a/tests/arch/quicklogic/run-test.sh b/tests/arch/quicklogic/run-test.sh
new file mode 100755
index 000000000..4be4b70ae
--- /dev/null
+++ b/tests/arch/quicklogic/run-test.sh
@@ -0,0 +1,4 @@
+#!/usr/bin/env bash
+set -eu
+source ../../gen-tests-makefile.sh
+run_tests --yosys-scripts --bash --yosys-args "-w 'Yosys has only limited support for tri-state logic at the moment.'"
diff --git a/tests/arch/quicklogic/tribuf.ys b/tests/arch/quicklogic/tribuf.ys
new file mode 100644
index 000000000..de763009e
--- /dev/null
+++ b/tests/arch/quicklogic/tribuf.ys
@@ -0,0 +1,13 @@
+read_verilog ../common/tribuf.v
+hierarchy -top tristate
+proc
+tribuf
+flatten
+synth
+equiv_opt -assert -map +/quicklogic/pp3_cells_sim.v -map +/quicklogic/cells_sim.v -map +/simcells.v synth_quicklogic # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd tristate # Constrain all select calls below inside the top module
+select -assert-count 2 t:inpad
+select -assert-count 1 t:outpad
+select -assert-count 1 t:$_TBUF_
+select -assert-none t:inpad t:outpad t:$_TBUF_ %% t:* %D
-- 
cgit v1.2.3


From 4f4e70876f06738fa7dda24e01ac296fe318264a Mon Sep 17 00:00:00 2001
From: Zachary Snow <zach@zachjs.com>
Date: Thu, 18 Mar 2021 13:38:25 -0400
Subject: sv: allow typenames as function return types

---
 tests/verilog/func_typename_ret.sv | 35 +++++++++++++++++++++++++++++++++++
 tests/verilog/func_typename_ret.ys |  5 +++++
 2 files changed, 40 insertions(+)
 create mode 100644 tests/verilog/func_typename_ret.sv
 create mode 100644 tests/verilog/func_typename_ret.ys

(limited to 'tests')

diff --git a/tests/verilog/func_typename_ret.sv b/tests/verilog/func_typename_ret.sv
new file mode 100644
index 000000000..423975f97
--- /dev/null
+++ b/tests/verilog/func_typename_ret.sv
@@ -0,0 +1,35 @@
+typedef logic [1:0] T;
+
+package P;
+    typedef logic [3:0] S;
+endpackage
+
+module gate(
+    output wire [31:0] out1, out2
+);
+    function automatic T func1;
+        input reg signed inp;
+        func1 = inp;
+    endfunction
+    assign out1 = func1(1);
+    function automatic P::S func2;
+        input reg signed inp;
+        func2 = inp;
+    endfunction
+    assign out2 = func2(1);
+endmodule
+
+module gold(
+    output wire [31:0] out1, out2
+);
+    function automatic [1:0] func1;
+        input reg signed inp;
+        func1 = inp;
+    endfunction
+    assign out1 = func1(1);
+    function automatic [3:0] func2;
+        input reg signed inp;
+        func2 = inp;
+    endfunction
+    assign out2 = func2(1);
+endmodule
diff --git a/tests/verilog/func_typename_ret.ys b/tests/verilog/func_typename_ret.ys
new file mode 100644
index 000000000..7f6049961
--- /dev/null
+++ b/tests/verilog/func_typename_ret.ys
@@ -0,0 +1,5 @@
+read_verilog -sv func_typename_ret.sv
+proc
+equiv_make gold gate equiv
+equiv_simple
+equiv_status -assert
-- 
cgit v1.2.3


From 92d5550a90558a0292c8ac63cecabb2de30eb6aa Mon Sep 17 00:00:00 2001
From: Xiretza <xiretza@xiretza.xyz>
Date: Thu, 18 Mar 2021 21:53:02 +0100
Subject: verilog: check entire user type stack for type definition

---
 tests/svtypes/typedef_scopes.sv | 10 ++++++++++
 1 file changed, 10 insertions(+)

(limited to 'tests')

diff --git a/tests/svtypes/typedef_scopes.sv b/tests/svtypes/typedef_scopes.sv
index 5507d84f2..9a898fac8 100644
--- a/tests/svtypes/typedef_scopes.sv
+++ b/tests/svtypes/typedef_scopes.sv
@@ -4,6 +4,7 @@ typedef enum logic {s0, s1} outer_enum_t;
 
 module top;
 
+	// globals are inherited
 	outer_uint4_t u4_i = 8'hA5;
 	outer_enum_t enum4_i = s0;
 	always @(*) assert(u4_i == 4'h5);
@@ -17,13 +18,22 @@ module top;
 	always @(*) assert(inner_enum1 == 3'h3);
 
 	if (1) begin: genblock
+		// type declarations in child scopes shadow their parents
 		typedef logic [7:0] inner_type;
 		parameter inner_type inner_const = 8'hA5;
  		typedef enum logic [2:0] {s5=5, s6, s7} inner_enum_t;
+
 		inner_type inner_gb_i = inner_const; //8'hA5;
  		inner_enum_t inner_gb_enum1 = s7;
 		always @(*) assert(inner_gb_i == 8'hA5);
  		always @(*) assert(inner_gb_enum1 == 3'h7);
+
+		// check that copying of struct member types works over multiple type scopes
+		typedef struct packed {
+			outer_uint4_t x;
+		} mystruct_t;
+		mystruct_t mystruct;
+		always @(*) assert($bits(mystruct) == 4);
 	end
 
 	inner_type inner_i2 = 8'h42;
-- 
cgit v1.2.3


From 4a35f244aa6ac187610cae0014d261e38cbab550 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Marcelina=20Ko=C5=9Bcielnicka?= <mwk@0x04.net>
Date: Tue, 23 Mar 2021 14:51:37 +0100
Subject: quicklogic: Add .gitignore file for test outputs.

---
 tests/arch/quicklogic/.gitignore | 4 ++++
 1 file changed, 4 insertions(+)
 create mode 100644 tests/arch/quicklogic/.gitignore

(limited to 'tests')

diff --git a/tests/arch/quicklogic/.gitignore b/tests/arch/quicklogic/.gitignore
new file mode 100644
index 000000000..9a71dca69
--- /dev/null
+++ b/tests/arch/quicklogic/.gitignore
@@ -0,0 +1,4 @@
+*.log
+/run-test.mk
++*_synth.v
++*_testbench
-- 
cgit v1.2.3


From 55dc5a4e4f7335741d2155dc0183ed4e26e8ddf8 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Mon, 29 Mar 2021 22:01:57 -0700
Subject: abc9: fix SCC issues (#2694)

* xilinx: add SCC test for DSP48E1

* xilinx: Gate DSP48E1 being a whitebox behind ALLOW_WHITEBOX_DSP48E1

Have a test that checks it works through ABC9 when enabled

* abc9 to break SCCs using $__ABC9_SCC_BREAKER module

* Add test

* abc9_ops: remove refs to (* abc9_keep *) on wires

* abc9_ops: do not bypass cells in an SCC

* Add myself to CODEOWNERS for abc9*

* Fix compile

* abc9_ops: run -prep_hier before scc

* Fix tests

* Remove bug reference pending fix

* abc9: fix for -prep_hier -dff

* xaiger: restore PI handling

* abc9_ops: -prep_xaiger sigmap

* abc9_ops: -mark_scc -> -break_scc

* abc9: eliminate hard-coded abc9.box from tests

Also tidy up

* Address review
---
 tests/simple_abc9/abc9.box    |  3 ---
 tests/simple_abc9/abc9.v      | 24 +++++++++++++++++++-----
 tests/simple_abc9/run-test.sh | 12 ++++++++----
 3 files changed, 27 insertions(+), 12 deletions(-)
 delete mode 100644 tests/simple_abc9/abc9.box

(limited to 'tests')

diff --git a/tests/simple_abc9/abc9.box b/tests/simple_abc9/abc9.box
deleted file mode 100644
index b3c88437c..000000000
--- a/tests/simple_abc9/abc9.box
+++ /dev/null
@@ -1,3 +0,0 @@
-MUXF8 1 0 3 1
-#I0 I1 S
-0 0 0 # O
diff --git a/tests/simple_abc9/abc9.v b/tests/simple_abc9/abc9.v
index 5e969c614..fba089b1f 100644
--- a/tests/simple_abc9/abc9.v
+++ b/tests/simple_abc9/abc9.v
@@ -213,7 +213,7 @@ module arbiter (clk, rst, request, acknowledge, grant, grant_valid, grant_encode
   input rst;
 endmodule
 
-(* abc9_box_id=1, blackbox *)
+(* abc9_box, blackbox *)
 module MUXF8(input I0, I1, S, output O);
 specify
     (I0 => O) = 0;
@@ -300,15 +300,29 @@ endmodule
 module abc9_test036(input A, B, S, output [1:0] O);
   (* keep *)
   MUXF8 m  (
-    .I0(I0),
-    .I1(I1),
+    .I0(A),
+    .I1(B),
     .O(O[0]),
     .S(S)
   );
   MUXF8 m2  (
-    .I0(I0),
-    .I1(I1),
+    .I0(A),
+    .I1(B),
     .O(O[1]),
     .S(S)
   );
 endmodule
+
+(* abc9_box, whitebox *)
+module MUXF7(input I0, I1, S, output O);
+assign O = S ? I1 : I0;
+specify
+    (I0 => O) = 0;
+    (I1 => O) = 0;
+    (S => O) = 0;
+endspecify
+endmodule
+
+module abc9_test037(output o);
+MUXF7 m(.I0(1'b1), .I1(1'b0), .S(o), .O(o));
+endmodule
diff --git a/tests/simple_abc9/run-test.sh b/tests/simple_abc9/run-test.sh
index b48505e29..4a5bf01a3 100755
--- a/tests/simple_abc9/run-test.sh
+++ b/tests/simple_abc9/run-test.sh
@@ -37,14 +37,18 @@ done
 
 cp ../simple/*.v .
 cp ../simple/*.sv .
+rm specify.v # bug 2675
 DOLLAR='?'
-exec ${MAKE:-make} -f ../tools/autotest.mk $seed *.v *.sv EXTRA_FLAGS="-n 300 -p '\
+exec ${MAKE:-make} -f ../tools/autotest.mk $seed *.v *.sv EXTRA_FLAGS="-f \"verilog -noblackbox -specify\" -n 300 -p '\
+    read_verilog -icells -lib +/abc9_model.v; \
     hierarchy; \
     synth -run coarse; \
     opt -full; \
     techmap; \
-    abc9 -lut 4 -box ../abc9.box; \
+    abc9 -lut 4; \
     clean; \
-    check -assert; \
+    check -assert * abc9_test037 %d; \
     select -assert-none t:${DOLLAR}_NOT_ t:${DOLLAR}_AND_ %%; \
-    setattr -mod -unset blackbox'"
+    setattr -mod -unset blackbox -unset whitebox'"
+
+# NOTE: Skip 'check -assert' on abc9_test037 because it intentionally has a combinatorial loop
-- 
cgit v1.2.3


From 8c5f379435a1140a4320cdd4152b60338e45a362 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Mon, 29 Mar 2021 22:02:06 -0700
Subject: abc9: uniquify blackboxes like whiteboxes (#2695)

* abc9_ops: uniquify blackboxes too

* abc9_ops: update comment

* abc9_ops: allow bypass for param-less blackboxes

* Add tests
---
 tests/various/abc9.ys | 57 ++++++++++++++++++++++++++++++++++++++++++++++++++-
 1 file changed, 56 insertions(+), 1 deletion(-)

(limited to 'tests')

diff --git a/tests/various/abc9.ys b/tests/various/abc9.ys
index a9880c722..e0add714b 100644
--- a/tests/various/abc9.ys
+++ b/tests/various/abc9.ys
@@ -90,7 +90,7 @@ $_DFF_N_ ff4(.C(clk), .D(1'b1), .Q(z));
 endmodule
 EOT
 simplemap
-equiv_opt abc9 -lut 4 -dff
+equiv_opt -assert abc9 -lut 4 -dff
 design -load postopt
 cd abc9_test038
 select -assert-count 3 t:$_DFF_N_
@@ -99,3 +99,58 @@ clean
 select -assert-count 2 a:init
 select -assert-count 1 w:w a:init %i
 select -assert-count 1 c:ff4 %co c:ff4 %d %a a:init %i
+
+
+# Check that non-dangling ABC9 black-boxes are preserved
+design -reset
+read_verilog -specify <<EOT
+(* abc9_box, blackbox *)
+module mux_with_param(input I0, I1, S, output O);
+parameter P = 0;
+specify
+    (I0 => O) = P;
+    (I1 => O) = P;
+    (S => O) = P;
+endspecify
+endmodule
+
+module abc9_test039(output O);
+  mux_with_param #(.P(1)) m (
+    .I0(1'b1),
+    .I1(1'b1),
+    .O(O),
+    .S(1'b0)
+  );
+endmodule
+EOT
+abc9 -lut 4
+cd abc9_test039
+select -assert-count 1 t:mux_with_param
+
+
+# Check that dangling ABC9 black-boxes are swept away
+design -reset
+read_verilog -specify <<EOT
+(* abc9_box, blackbox *)
+module mux_with_param(input I0, I1, S, output O);
+parameter P = 0;
+specify
+    (I0 => O) = P;
+    (I1 => O) = P;
+    (S => O) = P;
+endspecify
+endmodule
+
+module abc9_test040(output O);
+  wire w;
+  mux_with_param #(.P(1)) m (
+    .I0(1'b1),
+    .I1(1'b1),
+    .O(w),
+    .S(1'b0)
+  );
+endmodule
+EOT
+abc9 -lut 4
+cd abc9_test040
+select -assert-count 0 t:mux_with_param
-- 
cgit v1.2.3


From 0ccc7229c02449618209a20d66b9fa07e3ea79f2 Mon Sep 17 00:00:00 2001
From: Zachary Snow <zach@zachjs.com>
Date: Tue, 30 Mar 2021 09:38:00 -0400
Subject: preproc: test coverage for #2712

---
 tests/verilog/ifdef_nest.ys         | 7 +++++++
 tests/verilog/ifdef_unterminated.ys | 4 ++++
 tests/verilog/unmatched_endif_2.ys  | 7 +++++++
 3 files changed, 18 insertions(+)
 create mode 100644 tests/verilog/ifdef_nest.ys
 create mode 100644 tests/verilog/ifdef_unterminated.ys
 create mode 100644 tests/verilog/unmatched_endif_2.ys

(limited to 'tests')

diff --git a/tests/verilog/ifdef_nest.ys b/tests/verilog/ifdef_nest.ys
new file mode 100644
index 000000000..2202109aa
--- /dev/null
+++ b/tests/verilog/ifdef_nest.ys
@@ -0,0 +1,7 @@
+read_verilog <<EOF
+`ifndef a
+`ifdef b
+`endif
+`else
+`endif
+EOF
diff --git a/tests/verilog/ifdef_unterminated.ys b/tests/verilog/ifdef_unterminated.ys
new file mode 100644
index 000000000..ce511fa8f
--- /dev/null
+++ b/tests/verilog/ifdef_unterminated.ys
@@ -0,0 +1,4 @@
+logger -expect error "Unterminated preprocessor conditional!" 1
+read_verilog <<EOF
+`ifndef a
+EOF
diff --git a/tests/verilog/unmatched_endif_2.ys b/tests/verilog/unmatched_endif_2.ys
new file mode 100644
index 000000000..2ee084170
--- /dev/null
+++ b/tests/verilog/unmatched_endif_2.ys
@@ -0,0 +1,7 @@
+logger -expect error "Found `endif outside of macro conditional branch!" 1
+read_verilog <<EOF
+`ifndef a
+`else
+`endif
+`endif
+EOF
-- 
cgit v1.2.3


From dce037a62c5bda9a8256d271d39b06be366120e8 Mon Sep 17 00:00:00 2001
From: Lofty <dan.ravensloft@gmail.com>
Date: Mon, 12 Apr 2021 10:33:40 +0100
Subject: quicklogic: ABC9 synthesis

---
 tests/arch/quicklogic/add_sub.ys | 6 +++---
 tests/arch/quicklogic/counter.ys | 6 +++---
 tests/arch/quicklogic/fsm.ys     | 9 ++++-----
 tests/arch/quicklogic/latches.ys | 5 +++--
 tests/arch/quicklogic/logic.ys   | 4 ++--
 tests/arch/quicklogic/mux.ys     | 4 ++--
 6 files changed, 17 insertions(+), 17 deletions(-)

(limited to 'tests')

diff --git a/tests/arch/quicklogic/add_sub.ys b/tests/arch/quicklogic/add_sub.ys
index 168b3f8b3..73ee5cb44 100644
--- a/tests/arch/quicklogic/add_sub.ys
+++ b/tests/arch/quicklogic/add_sub.ys
@@ -3,9 +3,9 @@ hierarchy -top top
 equiv_opt -assert -map +/quicklogic/lut_sim.v -map +/quicklogic/pp3_cells_sim.v synth_quicklogic -family pp3 # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd top # Constrain all select calls below inside the top module
-select -assert-count 3 t:LUT2
-select -assert-count 4 t:LUT3
-select -assert-count 4 t:LUT4
+select -assert-count 2 t:LUT2
+select -assert-count 8 t:LUT3
+select -assert-count 2 t:LUT4
 select -assert-count 8 t:inpad
 select -assert-count 8 t:outpad
 select -assert-none t:LUT2 t:LUT3 t:LUT4 t:inpad t:outpad %% t:* %D
diff --git a/tests/arch/quicklogic/counter.ys b/tests/arch/quicklogic/counter.ys
index 0c04b5742..2e266417c 100644
--- a/tests/arch/quicklogic/counter.ys
+++ b/tests/arch/quicklogic/counter.ys
@@ -6,9 +6,9 @@ equiv_opt -assert -multiclock -map +/quicklogic/pp3_cells_sim.v -map +/quicklogi
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd top # Constrain all select calls below inside the top module
 select -assert-count 1 t:LUT1
-select -assert-count 5 t:LUT2
-select -assert-count 2 t:LUT3
-select -assert-count 3 t:LUT4
+select -assert-count 3 t:LUT2
+select -assert-count 5 t:LUT3
+select -assert-count 1 t:LUT4
 select -assert-count 8 t:dffepc
 select -assert-count 1 t:logic_0
 select -assert-count 1 t:logic_1
diff --git a/tests/arch/quicklogic/fsm.ys b/tests/arch/quicklogic/fsm.ys
index 7ed36b9e4..130dacf42 100644
--- a/tests/arch/quicklogic/fsm.ys
+++ b/tests/arch/quicklogic/fsm.ys
@@ -11,14 +11,13 @@ sat -verify -prove-asserts -show-public -set-at 1 in_reset 1 -seq 20 -prove-skip
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd fsm # Constrain all select calls below inside the top module
 
-select -assert-count 3 t:LUT2
-select -assert-count 6 t:LUT3
-select -assert-count 7 t:LUT4
-select -assert-count 6 t:dffepc
+select -assert-count 1 t:LUT2
+select -assert-count 9 t:LUT3
+select -assert-count 4 t:dffepc
 select -assert-count 1 t:logic_0
 select -assert-count 1 t:logic_1
 select -assert-count 3 t:inpad
 select -assert-count 2 t:outpad
 select -assert-count 1 t:ckpad
 
-select -assert-none t:LUT2 t:LUT3 t:LUT4 t:dffepc t:logic_0 t:logic_1 t:inpad t:outpad t:ckpad %% t:* %D
+select -assert-none t:LUT2 t:LUT3 t:dffepc t:logic_0 t:logic_1 t:inpad t:outpad t:ckpad %% t:* %D
diff --git a/tests/arch/quicklogic/latches.ys b/tests/arch/quicklogic/latches.ys
index d7652f749..bcef42990 100644
--- a/tests/arch/quicklogic/latches.ys
+++ b/tests/arch/quicklogic/latches.ys
@@ -32,8 +32,9 @@ proc
 # Can't run any sort of equivalence check because latches are blown to LUTs
 synth_quicklogic
 cd latchsr # Constrain all select calls below inside the top module
-select -assert-count 2 t:LUT3
+select -assert-count 1 t:LUT2
+select -assert-count 1 t:LUT4
 select -assert-count 5 t:inpad
 select -assert-count 1 t:outpad
 
-select -assert-none t:LUT3 t:inpad t:outpad %% t:* %D
+select -assert-none t:LUT2 t:LUT4 t:inpad t:outpad %% t:* %D
diff --git a/tests/arch/quicklogic/logic.ys b/tests/arch/quicklogic/logic.ys
index 65f48a42b..4b327c00a 100644
--- a/tests/arch/quicklogic/logic.ys
+++ b/tests/arch/quicklogic/logic.ys
@@ -7,8 +7,8 @@ cd top # Constrain all select calls below inside the top module
 
 select -assert-count 1 t:LUT1
 select -assert-count 6 t:LUT2
-select -assert-count 2 t:LUT4
+select -assert-count 2 t:LUT3
 select -assert-count 8 t:inpad
 select -assert-count 10 t:outpad
 
-select -assert-none t:LUT1 t:LUT2 t:LUT4 t:inpad t:outpad %% t:* %D
+select -assert-none t:LUT1 t:LUT2 t:LUT3 t:inpad t:outpad %% t:* %D
diff --git a/tests/arch/quicklogic/mux.ys b/tests/arch/quicklogic/mux.ys
index 632d14687..ea17fa99b 100644
--- a/tests/arch/quicklogic/mux.ys
+++ b/tests/arch/quicklogic/mux.ys
@@ -30,13 +30,13 @@ proc
 equiv_opt -assert -map +/quicklogic/pp3_cells_sim.v -map +/quicklogic/cells_sim.v -map +/quicklogic/lut_sim.v synth_quicklogic # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd mux8 # Constrain all select calls below inside the top module
-select -assert-count 4 t:LUT2
+select -assert-count 1 t:LUT1
 select -assert-count 1 t:LUT3
 select -assert-count 2 t:mux4x0
 select -assert-count 11 t:inpad
 select -assert-count 1 t:outpad
 
-select -assert-none t:LUT2 t:LUT3 t:mux4x0 t:inpad t:outpad %% t:* %D
+select -assert-none t:LUT1 t:LUT3 t:mux4x0 t:inpad t:outpad %% t:* %D
 
 design -load read
 hierarchy -top mux16
-- 
cgit v1.2.3


From 8aee80040de0b0812f2aec7ba4059c14407a0567 Mon Sep 17 00:00:00 2001
From: Claire Xenia Wolf <claire@clairexen.net>
Date: Mon, 15 Mar 2021 23:27:55 +0100
Subject: Add default assignments to SB_LUT4

Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
---
 tests/arch/run-test.sh | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'tests')

diff --git a/tests/arch/run-test.sh b/tests/arch/run-test.sh
index 170078a7f..5d923db56 100755
--- a/tests/arch/run-test.sh
+++ b/tests/arch/run-test.sh
@@ -11,7 +11,7 @@ for arch in ../../techlibs/*; do
 		if [ "${defines[$arch_name]}" ]; then
 			for def in ${defines[$arch_name]}; do
 				echo -n "Test $path -D$def ->"
-				iverilog -t null -I$arch -D$def $path
+				iverilog -t null -I$arch -D$def -DNO_ICE40_DEFAULT_ASSIGNMENTS $path
 				echo " ok"
 			done
 		else
-- 
cgit v1.2.3


From 5c1e6a0e201f1bb623c3fc7d2c8ee13c783c9c07 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Marcelina=20Ko=C5=9Bcielnicka?= <mwk@0x04.net>
Date: Tue, 4 May 2021 19:14:24 +0200
Subject: opt_dff: Fix NOT gates wired in reverse.

---
 tests/opt/opt_dff_sr.ys | 21 +++++++++++++--------
 1 file changed, 13 insertions(+), 8 deletions(-)

(limited to 'tests')

diff --git a/tests/opt/opt_dff_sr.ys b/tests/opt/opt_dff_sr.ys
index daedb115c..0961cb11e 100644
--- a/tests/opt/opt_dff_sr.ys
+++ b/tests/opt/opt_dff_sr.ys
@@ -22,8 +22,10 @@ EOT
 
 design -save orig
 
-equiv_opt -undef -assert -multiclock opt_dff
-design -load postopt
+# Equivalence check will fail for unmapped adlatch and dlatchsr due to negative hold hack.
+#equiv_opt -undef -assert -multiclock opt_dff
+#design -load postopt
+opt_dff
 select -assert-count 1 t:$dffsr
 select -assert-count 1 t:$dffsr r:WIDTH=2 %i
 select -assert-count 1 t:$dffsre
@@ -34,8 +36,9 @@ select -assert-none t:$sr
 
 design -load orig
 
-equiv_opt -undef -assert -multiclock opt_dff -keepdc
-design -load postopt
+#equiv_opt -undef -assert -multiclock opt_dff -keepdc
+#design -load postopt
+opt_dff -keepdc
 select -assert-count 1 t:$dffsr
 select -assert-count 1 t:$dffsr r:WIDTH=4 %i
 select -assert-count 1 t:$dffsre
@@ -48,8 +51,9 @@ select -assert-count 1 t:$sr r:WIDTH=4 %i
 design -load orig
 simplemap
 
-equiv_opt -undef -assert -multiclock opt_dff
-design -load postopt
+#equiv_opt -undef -assert -multiclock opt_dff
+#design -load postopt
+opt_dff
 select -assert-count 1 t:$_DFF_PP0_
 select -assert-count 1 t:$_DFF_PP1_
 select -assert-count 1 t:$_DFFE_PN0P_
@@ -61,8 +65,9 @@ select -assert-none t:$_DFF_PP0_ t:$_DFF_PP1_ t:$_DFFE_PN0P_ t:$_DFFE_PN1P_ t:$_
 design -load orig
 simplemap
 
-equiv_opt -undef -assert -multiclock opt_dff -keepdc
-design -load postopt
+#equiv_opt -undef -assert -multiclock opt_dff -keepdc
+#design -load postopt
+opt_dff -keepdc
 select -assert-count 1 t:$_DFF_PP0_
 select -assert-count 1 t:$_DFF_PP1_
 select -assert-count 2 t:$_DFFSR_PPP_
-- 
cgit v1.2.3


From 32a0ce9d6809d073abcbf19fe3eaf7a0cf936963 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Marcelina=20Ko=C5=9Bcielnicka?= <mwk@0x04.net>
Date: Wed, 5 May 2021 20:31:27 +0200
Subject: blif: Use library cells' start_offset and upto for wideports.

Fixes #2729.
---
 tests/blif/bug2729.ys  | 20 ++++++++++++++++++++
 tests/blif/run-test.sh |  6 ++++++
 2 files changed, 26 insertions(+)
 create mode 100644 tests/blif/bug2729.ys
 create mode 100755 tests/blif/run-test.sh

(limited to 'tests')

diff --git a/tests/blif/bug2729.ys b/tests/blif/bug2729.ys
new file mode 100644
index 000000000..0cbc21aa0
--- /dev/null
+++ b/tests/blif/bug2729.ys
@@ -0,0 +1,20 @@
+read_verilog <<EOF
+
+module cell (input [2:12] I, output [5:-5] O);
+endmodule
+
+module top(input [10:0] A, output [10:0] B);
+cell my_cell(.I(A), .O(B));
+endmodule
+
+EOF
+
+write_blif tmp-bug2729.blif
+delete top
+read_blif -wideports tmp-bug2729.blif
+!rm tmp-bug2729.blif
+rename -enumerate t:cell
+dump
+cd top
+connect -assert -port _0_ I A
+connect -assert -port _0_ O B
diff --git a/tests/blif/run-test.sh b/tests/blif/run-test.sh
new file mode 100755
index 000000000..44ce7e674
--- /dev/null
+++ b/tests/blif/run-test.sh
@@ -0,0 +1,6 @@
+#!/bin/bash
+set -e
+for x in *.ys; do
+  echo "Running $x.."
+  ../../yosys -ql ${x%.ys}.log $x
+done
-- 
cgit v1.2.3


From 445208086121ea343bdb80a9998637361c841bea Mon Sep 17 00:00:00 2001
From: Zachary Snow <zach@zachjs.com>
Date: Mon, 10 May 2021 11:06:02 -0400
Subject: sv: check validity of package end label

---
 tests/verilog/package_end_label.ys | 15 +++++++++++++++
 1 file changed, 15 insertions(+)
 create mode 100644 tests/verilog/package_end_label.ys

(limited to 'tests')

diff --git a/tests/verilog/package_end_label.ys b/tests/verilog/package_end_label.ys
new file mode 100644
index 000000000..ccc5c96e9
--- /dev/null
+++ b/tests/verilog/package_end_label.ys
@@ -0,0 +1,15 @@
+logger -expect-no-warnings
+read_verilog -sv <<EOF
+package correct_name;
+localparam X = 1;
+endpackage : correct_name
+EOF
+
+design -reset
+
+logger -expect error "Package name \(correct_name\) and end label \(incorrect_name\) don't match\." 1
+read_verilog -sv <<EOF
+package correct_name;
+localparam X = 1;
+endpackage : incorrect_name
+EOF
-- 
cgit v1.2.3


From 5dba138c87762d4b5bb7b9348da372a92fab1cc0 Mon Sep 17 00:00:00 2001
From: gatecat <gatecat@ds0.me>
Date: Sat, 15 May 2021 14:23:22 +0100
Subject: intel_alm: Add IO buffer insertion

Signed-off-by: gatecat <gatecat@ds0.me>
---
 tests/arch/intel_alm/add_sub.ys     |  4 ++--
 tests/arch/intel_alm/adffs.ys       | 16 ++++++++--------
 tests/arch/intel_alm/blockram.ys    |  2 +-
 tests/arch/intel_alm/counter.ys     |  4 ++--
 tests/arch/intel_alm/dffs.ys        |  8 ++++----
 tests/arch/intel_alm/fsm.ys         |  4 ++--
 tests/arch/intel_alm/logic.ys       |  4 ++--
 tests/arch/intel_alm/lutram.ys      |  4 ++--
 tests/arch/intel_alm/mul.ys         | 10 +++++-----
 tests/arch/intel_alm/mux.ys         | 12 ++++++------
 tests/arch/intel_alm/quartus_ice.ys |  2 +-
 tests/arch/intel_alm/shifter.ys     |  4 ++--
 tests/arch/intel_alm/tribuf.ys      |  4 ++--
 13 files changed, 39 insertions(+), 39 deletions(-)

(limited to 'tests')

diff --git a/tests/arch/intel_alm/add_sub.ys b/tests/arch/intel_alm/add_sub.ys
index 0f552a27c..a189ada1b 100644
--- a/tests/arch/intel_alm/add_sub.ys
+++ b/tests/arch/intel_alm/add_sub.ys
@@ -1,6 +1,6 @@
 read_verilog ../common/add_sub.v
 hierarchy -top top
-equiv_opt -assert -map +/intel_alm/common/alm_sim.v synth_intel_alm -family cyclonev # equivalency check
+equiv_opt -assert -map +/intel_alm/common/alm_sim.v synth_intel_alm -family cyclonev -noiopad # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd top # Constrain all select calls below inside the top module
 stat
@@ -10,7 +10,7 @@ select -assert-none t:MISTRAL_ALUT_ARITH %% t:* %D
 design -reset
 read_verilog ../common/add_sub.v
 hierarchy -top top
-equiv_opt -assert -map +/intel_alm/common/alm_sim.v synth_intel_alm -family cyclone10gx # equivalency check
+equiv_opt -assert -map +/intel_alm/common/alm_sim.v synth_intel_alm -family cyclone10gx -noiopad # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd top # Constrain all select calls below inside the top module
 stat
diff --git a/tests/arch/intel_alm/adffs.ys b/tests/arch/intel_alm/adffs.ys
index 4565dcc64..7013ebb73 100644
--- a/tests/arch/intel_alm/adffs.ys
+++ b/tests/arch/intel_alm/adffs.ys
@@ -3,7 +3,7 @@ design -save read
 
 hierarchy -top adff
 proc
-equiv_opt -async2sync -assert -map +/intel_alm/common/alm_sim.v -map +/intel_alm/common/dff_sim.v synth_intel_alm -family cyclonev # equivalency check
+equiv_opt -async2sync -assert -map +/intel_alm/common/alm_sim.v -map +/intel_alm/common/dff_sim.v synth_intel_alm  -family cyclonev -noiopad # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd adff # Constrain all select calls below inside the top module
 select -assert-count 1 t:MISTRAL_FF
@@ -15,7 +15,7 @@ select -assert-none t:MISTRAL_FF t:MISTRAL_NOT %% t:* %D
 design -load read
 hierarchy -top adff
 proc
-equiv_opt -async2sync -assert -map +/intel_alm/common/alm_sim.v -map +/intel_alm/common/dff_sim.v synth_intel_alm -family cyclone10gx # equivalency check
+equiv_opt -async2sync -assert -map +/intel_alm/common/alm_sim.v -map +/intel_alm/common/dff_sim.v synth_intel_alm -family cyclone10gx -noiopad # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd adff # Constrain all select calls below inside the top module
 select -assert-count 1 t:MISTRAL_FF
@@ -27,7 +27,7 @@ select -assert-none t:MISTRAL_FF t:MISTRAL_NOT %% t:* %D
 design -load read
 hierarchy -top adffn
 proc
-equiv_opt -async2sync -assert -map +/intel_alm/common/alm_sim.v -map +/intel_alm/common/dff_sim.v synth_intel_alm -family cyclonev # equivalency check
+equiv_opt -async2sync -assert -map +/intel_alm/common/alm_sim.v -map +/intel_alm/common/dff_sim.v synth_intel_alm -family cyclonev -noiopad # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd adffn # Constrain all select calls below inside the top module
 select -assert-count 1 t:MISTRAL_FF
@@ -38,7 +38,7 @@ select -assert-none t:MISTRAL_FF %% t:* %D
 design -load read
 hierarchy -top adffn
 proc
-equiv_opt -async2sync -assert -map +/intel_alm/common/alm_sim.v -map +/intel_alm/common/dff_sim.v synth_intel_alm -family cyclone10gx # equivalency check
+equiv_opt -async2sync -assert -map +/intel_alm/common/alm_sim.v -map +/intel_alm/common/dff_sim.v synth_intel_alm -family cyclone10gx -noiopad # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd adffn # Constrain all select calls below inside the top module
 select -assert-count 1 t:MISTRAL_FF
@@ -49,7 +49,7 @@ select -assert-none t:MISTRAL_FF %% t:* %D
 design -load read
 hierarchy -top dffs
 proc
-equiv_opt -async2sync -assert -map +/intel_alm/common/alm_sim.v -map +/intel_alm/common/dff_sim.v synth_intel_alm -family cyclonev # equivalency check
+equiv_opt -async2sync -assert -map +/intel_alm/common/alm_sim.v -map +/intel_alm/common/dff_sim.v synth_intel_alm -family cyclonev -noiopad # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd dffs # Constrain all select calls below inside the top module
 select -assert-count 1 t:MISTRAL_FF
@@ -61,7 +61,7 @@ select -assert-none t:MISTRAL_FF t:MISTRAL_ALUT2 %% t:* %D
 design -load read
 hierarchy -top dffs
 proc
-equiv_opt -async2sync -assert -map +/intel_alm/common/alm_sim.v -map +/intel_alm/common/dff_sim.v synth_intel_alm -family cyclone10gx # equivalency check
+equiv_opt -async2sync -assert -map +/intel_alm/common/alm_sim.v -map +/intel_alm/common/dff_sim.v synth_intel_alm -family cyclone10gx -noiopad # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd dffs # Constrain all select calls below inside the top module
 select -assert-count 1 t:MISTRAL_FF
@@ -73,7 +73,7 @@ select -assert-none t:MISTRAL_FF t:MISTRAL_ALUT2 %% t:* %D
 design -load read
 hierarchy -top ndffnr
 proc
-equiv_opt -async2sync -assert -map +/intel_alm/common/alm_sim.v -map +/intel_alm/common/dff_sim.v synth_intel_alm -family cyclonev # equivalency check
+equiv_opt -async2sync -assert -map +/intel_alm/common/alm_sim.v -map +/intel_alm/common/dff_sim.v synth_intel_alm -family cyclonev -noiopad # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd ndffnr # Constrain all select calls below inside the top module
 select -assert-count 1 t:MISTRAL_FF
@@ -85,7 +85,7 @@ select -assert-none t:MISTRAL_FF t:MISTRAL_NOT %% t:* %D
 design -load read
 hierarchy -top ndffnr
 proc
-equiv_opt -async2sync -assert -map +/intel_alm/common/alm_sim.v -map +/intel_alm/common/dff_sim.v synth_intel_alm -family cyclone10gx # equivalency check
+equiv_opt -async2sync -assert -map +/intel_alm/common/alm_sim.v -map +/intel_alm/common/dff_sim.v synth_intel_alm -family cyclone10gx -noiopad # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd ndffnr # Constrain all select calls below inside the top module
 select -assert-count 1 t:MISTRAL_FF
diff --git a/tests/arch/intel_alm/blockram.ys b/tests/arch/intel_alm/blockram.ys
index 610ae1ffd..b7c0e9564 100644
--- a/tests/arch/intel_alm/blockram.ys
+++ b/tests/arch/intel_alm/blockram.ys
@@ -1,6 +1,6 @@
 read_verilog ../common/blockram.v
 chparam -set ADDRESS_WIDTH 10 -set DATA_WIDTH 10 sync_ram_sdp
-synth_intel_alm -family cyclonev
+synth_intel_alm -family cyclonev -noiopad
 cd sync_ram_sdp
 select -assert-count 1 t:MISTRAL_M10K
 select -assert-none t:MISTRAL_M10K %% t:* %D
diff --git a/tests/arch/intel_alm/counter.ys b/tests/arch/intel_alm/counter.ys
index 50103fefc..98a9e360a 100644
--- a/tests/arch/intel_alm/counter.ys
+++ b/tests/arch/intel_alm/counter.ys
@@ -2,7 +2,7 @@ read_verilog ../common/counter.v
 hierarchy -top top
 proc
 flatten
-equiv_opt -async2sync -map +/intel_alm/common/alm_sim.v -map +/intel_alm/common/dff_sim.v synth_intel_alm -family cyclonev # equivalency check
+equiv_opt -async2sync -map +/intel_alm/common/alm_sim.v -map +/intel_alm/common/dff_sim.v synth_intel_alm -family cyclonev -noiopad # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd top # Constrain all select calls below inside the top module
 
@@ -17,7 +17,7 @@ read_verilog ../common/counter.v
 hierarchy -top top
 proc
 flatten
-equiv_opt -async2sync -map +/intel_alm/common/alm_sim.v -map +/intel_alm/common/dff_sim.v synth_intel_alm -family cyclone10gx # equivalency check
+equiv_opt -async2sync -map +/intel_alm/common/alm_sim.v -map +/intel_alm/common/dff_sim.v synth_intel_alm -family cyclone10gx -noiopad # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd top # Constrain all select calls below inside the top module
 
diff --git a/tests/arch/intel_alm/dffs.ys b/tests/arch/intel_alm/dffs.ys
index 9ae6c637a..811a5d82f 100644
--- a/tests/arch/intel_alm/dffs.ys
+++ b/tests/arch/intel_alm/dffs.ys
@@ -3,7 +3,7 @@ design -save read
 
 hierarchy -top dff
 proc
-equiv_opt -async2sync -assert -map +/intel_alm/common/alm_sim.v -map +/intel_alm/common/dff_sim.v synth_intel_alm -family cyclonev # equivalency check
+equiv_opt -async2sync -assert -map +/intel_alm/common/alm_sim.v -map +/intel_alm/common/dff_sim.v synth_intel_alm -family cyclonev -noiopad # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd dff # Constrain all select calls below inside the top module
 select -assert-count 1 t:MISTRAL_FF
@@ -13,7 +13,7 @@ select -assert-none t:MISTRAL_FF %% t:* %D
 design -load read
 hierarchy -top dff
 proc
-equiv_opt -async2sync -assert -map +/intel_alm/common/alm_sim.v -map +/intel_alm/common/dff_sim.v synth_intel_alm -family cyclone10gx # equivalency check
+equiv_opt -async2sync -assert -map +/intel_alm/common/alm_sim.v -map +/intel_alm/common/dff_sim.v synth_intel_alm -family cyclone10gx -noiopad # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd dff # Constrain all select calls below inside the top module
 select -assert-count 1 t:MISTRAL_FF
@@ -24,7 +24,7 @@ select -assert-none t:MISTRAL_FF %% t:* %D
 design -load read
 hierarchy -top dffe
 proc
-equiv_opt -async2sync -assert -map +/intel_alm/common/alm_sim.v -map +/intel_alm/common/dff_sim.v synth_intel_alm -family cyclonev # equivalency check
+equiv_opt -async2sync -assert -map +/intel_alm/common/alm_sim.v -map +/intel_alm/common/dff_sim.v synth_intel_alm -family cyclonev -noiopad # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd dffe # Constrain all select calls below inside the top module
 select -assert-count 1 t:MISTRAL_FF
@@ -35,7 +35,7 @@ select -assert-none t:MISTRAL_FF %% t:* %D
 design -load read
 hierarchy -top dffe
 proc
-equiv_opt -async2sync -assert -map +/intel_alm/common/alm_sim.v -map +/intel_alm/common/dff_sim.v synth_intel_alm -family cyclone10gx # equivalency check
+equiv_opt -async2sync -assert -map +/intel_alm/common/alm_sim.v -map +/intel_alm/common/dff_sim.v synth_intel_alm -family cyclone10gx -noiopad # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd dffe # Constrain all select calls below inside the top module
 select -assert-count 1 t:MISTRAL_FF
diff --git a/tests/arch/intel_alm/fsm.ys b/tests/arch/intel_alm/fsm.ys
index e54b5c21e..96c050bad 100644
--- a/tests/arch/intel_alm/fsm.ys
+++ b/tests/arch/intel_alm/fsm.ys
@@ -3,7 +3,7 @@ hierarchy -top fsm
 proc
 flatten
 
-equiv_opt -run :prove -map +/intel_alm/common/alm_sim.v -map +/intel_alm/common/dff_sim.v synth_intel_alm -family cyclonev
+equiv_opt -run :prove -map +/intel_alm/common/alm_sim.v -map +/intel_alm/common/dff_sim.v synth_intel_alm -family cyclonev -noiopad
 async2sync
 miter -equiv -make_assert -flatten gold gate miter
 sat -verify -prove-asserts -show-public -set-at 1 in_reset 1 -seq 20 -prove-skip 1 miter
@@ -26,7 +26,7 @@ hierarchy -top fsm
 proc
 flatten
 
-equiv_opt -run :prove -map +/intel_alm/common/alm_sim.v -map +/intel_alm/common/dff_sim.v synth_intel_alm -family cyclone10gx
+equiv_opt -run :prove -map +/intel_alm/common/alm_sim.v -map +/intel_alm/common/dff_sim.v synth_intel_alm -family cyclone10gx -noiopad
 async2sync
 miter -equiv -make_assert -flatten gold gate miter
 sat -verify -prove-asserts -show-public -set-at 1 in_reset 1 -seq 20 -prove-skip 1 miter
diff --git a/tests/arch/intel_alm/logic.ys b/tests/arch/intel_alm/logic.ys
index e8b26a524..916c1161c 100644
--- a/tests/arch/intel_alm/logic.ys
+++ b/tests/arch/intel_alm/logic.ys
@@ -1,7 +1,7 @@
 read_verilog ../common/logic.v
 hierarchy -top top
 proc
-equiv_opt -assert -map +/intel_alm/common/alm_sim.v synth_intel_alm -family cyclonev # equivalency check
+equiv_opt -assert -map +/intel_alm/common/alm_sim.v synth_intel_alm -family cyclonev -noiopad # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd top # Constrain all select calls below inside the top module
 
@@ -15,7 +15,7 @@ design -reset
 read_verilog ../common/logic.v
 hierarchy -top top
 proc
-equiv_opt -assert -map +/intel_alm/common/alm_sim.v synth_intel_alm -family cyclone10gx # equivalency check
+equiv_opt -assert -map +/intel_alm/common/alm_sim.v synth_intel_alm -family cyclone10gx -noiopad # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd top # Constrain all select calls below inside the top module
 
diff --git a/tests/arch/intel_alm/lutram.ys b/tests/arch/intel_alm/lutram.ys
index 66f8a1536..c21c9103b 100644
--- a/tests/arch/intel_alm/lutram.ys
+++ b/tests/arch/intel_alm/lutram.ys
@@ -2,7 +2,7 @@ read_verilog ../common/lutram.v
 hierarchy -top lutram_1w1r
 proc
 memory -nomap
-equiv_opt -run :prove -map +/intel_alm/common/alm_sim.v -map +/intel_alm/common/dff_sim.v -map +/intel_alm/common/mem_sim.v synth_intel_alm -family cyclonev -nobram
+equiv_opt -run :prove -map +/intel_alm/common/alm_sim.v -map +/intel_alm/common/dff_sim.v -map +/intel_alm/common/mem_sim.v synth_intel_alm -family cyclonev -nobram -noiopad
 memory
 opt -full
 
@@ -24,7 +24,7 @@ read_verilog ../common/lutram.v
 hierarchy -top lutram_1w1r
 proc
 memory -nomap
-equiv_opt -run :prove -map +/intel_alm/common/alm_sim.v -map +/intel_alm/common/dff_sim.v -map +/intel_alm/common/mem_sim.v synth_intel_alm -family cyclonev -nobram
+equiv_opt -run :prove -map +/intel_alm/common/alm_sim.v -map +/intel_alm/common/dff_sim.v -map +/intel_alm/common/mem_sim.v synth_intel_alm -family cyclonev -nobram -noiopad
 memory
 opt -full
 
diff --git a/tests/arch/intel_alm/mul.ys b/tests/arch/intel_alm/mul.ys
index 49934740f..10f3f7bf4 100644
--- a/tests/arch/intel_alm/mul.ys
+++ b/tests/arch/intel_alm/mul.ys
@@ -2,7 +2,7 @@ read_verilog ../common/mul.v
 chparam -set X_WIDTH 8 -set Y_WIDTH 8 -set A_WIDTH 16
 hierarchy -top top
 proc
-equiv_opt -assert -map +/intel_alm/common/dsp_sim.v synth_intel_alm -family cyclonev # equivalency check
+equiv_opt -assert -map +/intel_alm/common/dsp_sim.v synth_intel_alm -family cyclonev -noiopad # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd top # Constrain all select calls below inside the top module
 
@@ -16,7 +16,7 @@ read_verilog ../common/mul.v
 chparam -set X_WIDTH 17 -set Y_WIDTH 17 -set A_WIDTH 34
 hierarchy -top top
 proc
-equiv_opt -assert -map +/intel_alm/common/dsp_sim.v synth_intel_alm -family cyclonev # equivalency check
+equiv_opt -assert -map +/intel_alm/common/dsp_sim.v synth_intel_alm -family cyclonev -noiopad # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd top # Constrain all select calls below inside the top module
 
@@ -28,7 +28,7 @@ read_verilog ../common/mul.v
 chparam -set X_WIDTH 17 -set Y_WIDTH 17 -set A_WIDTH 34
 hierarchy -top top
 proc
-equiv_opt -assert -map +/intel_alm/common/dsp_sim.v synth_intel_alm -family cyclone10gx # equivalency check
+equiv_opt -assert -map +/intel_alm/common/dsp_sim.v synth_intel_alm -family cyclone10gx -noiopad # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd top # Constrain all select calls below inside the top module
 
@@ -40,7 +40,7 @@ read_verilog ../common/mul.v
 chparam -set X_WIDTH 26 -set Y_WIDTH 26 -set A_WIDTH 52
 hierarchy -top top
 proc
-equiv_opt -assert -map +/intel_alm/common/dsp_sim.v synth_intel_alm -family cyclonev # equivalency check
+equiv_opt -assert -map +/intel_alm/common/dsp_sim.v synth_intel_alm -family cyclonev -noiopad # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd top # Constrain all select calls below inside the top module
 
@@ -52,7 +52,7 @@ read_verilog ../common/mul.v
 chparam -set X_WIDTH 26 -set Y_WIDTH 26 -set A_WIDTH 52
 hierarchy -top top
 proc
-equiv_opt -assert -map +/intel_alm/common/dsp_sim.v synth_intel_alm -family cyclone10gx # equivalency check
+equiv_opt -assert -map +/intel_alm/common/dsp_sim.v synth_intel_alm -family cyclone10gx -noiopad # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd top # Constrain all select calls below inside the top module
 
diff --git a/tests/arch/intel_alm/mux.ys b/tests/arch/intel_alm/mux.ys
index ac3b9b08f..c386542c4 100644
--- a/tests/arch/intel_alm/mux.ys
+++ b/tests/arch/intel_alm/mux.ys
@@ -4,7 +4,7 @@ design -save read
 
 hierarchy -top mux2
 proc
-equiv_opt -assert -map +/intel_alm/common/alm_sim.v synth_intel_alm -family cyclonev # equivalency check
+equiv_opt -assert -map +/intel_alm/common/alm_sim.v synth_intel_alm -family cyclonev -noiopad # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd mux2 # Constrain all select calls below inside the top module
 select -assert-count 1 t:MISTRAL_ALUT3
@@ -14,7 +14,7 @@ select -assert-none t:MISTRAL_ALUT3 %% t:* %D
 design -load read
 hierarchy -top mux2
 proc
-equiv_opt -assert -map +/intel_alm/common/alm_sim.v synth_intel_alm -family cyclone10gx # equivalency check
+equiv_opt -assert -map +/intel_alm/common/alm_sim.v synth_intel_alm -family cyclone10gx -noiopad # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd mux2 # Constrain all select calls below inside the top module
 select -assert-count 1 t:MISTRAL_ALUT3
@@ -24,7 +24,7 @@ select -assert-none t:MISTRAL_ALUT3 %% t:* %D
 design -load read
 hierarchy -top mux4
 proc
-equiv_opt -assert -map +/intel_alm/common/alm_sim.v synth_intel_alm -family cyclonev # equivalency check
+equiv_opt -assert -map +/intel_alm/common/alm_sim.v synth_intel_alm -family cyclonev -noiopad # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd mux4 # Constrain all select calls below inside the top module
 select -assert-count 1 t:MISTRAL_ALUT6
@@ -34,7 +34,7 @@ select -assert-none t:MISTRAL_ALUT6 %% t:* %D
 design -load read
 hierarchy -top mux4
 proc
-equiv_opt -assert -map +/intel_alm/common/alm_sim.v synth_intel_alm -family cyclone10gx # equivalency check
+equiv_opt -assert -map +/intel_alm/common/alm_sim.v synth_intel_alm -family cyclone10gx -noiopad # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd mux4 # Constrain all select calls below inside the top module
 select -assert-count 1 t:MISTRAL_ALUT6
@@ -44,7 +44,7 @@ select -assert-none t:MISTRAL_ALUT6 %% t:* %D
 design -load read
 hierarchy -top mux8
 proc
-equiv_opt -assert -map +/intel_alm/common/alm_sim.v synth_intel_alm -family cyclonev # equivalency check
+equiv_opt -assert -map +/intel_alm/common/alm_sim.v synth_intel_alm -family cyclonev -noiopad # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd mux8 # Constrain all select calls below inside the top module
 select -assert-count 1 t:MISTRAL_ALUT3
@@ -55,7 +55,7 @@ select -assert-none t:MISTRAL_ALUT3 t:MISTRAL_ALUT6 %% t:* %D
 design -load read
 hierarchy -top mux8
 proc
-equiv_opt -assert -map +/intel_alm/common/alm_sim.v synth_intel_alm -family cyclone10gx # equivalency check
+equiv_opt -assert -map +/intel_alm/common/alm_sim.v synth_intel_alm -family cyclone10gx -noiopad # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd mux8 # Constrain all select calls below inside the top module
 select -assert-count 1 t:MISTRAL_ALUT3
diff --git a/tests/arch/intel_alm/quartus_ice.ys b/tests/arch/intel_alm/quartus_ice.ys
index a88226e13..286e6653c 100644
--- a/tests/arch/intel_alm/quartus_ice.ys
+++ b/tests/arch/intel_alm/quartus_ice.ys
@@ -22,5 +22,5 @@ module top();
 endmodule
 EOT
 
-synth_intel_alm -family cyclone10gx -quartus
+synth_intel_alm -family cyclone10gx -quartus -noiopad
 select -assert-none w:*[* w:*]*
diff --git a/tests/arch/intel_alm/shifter.ys b/tests/arch/intel_alm/shifter.ys
index e307b5486..bf19beef1 100644
--- a/tests/arch/intel_alm/shifter.ys
+++ b/tests/arch/intel_alm/shifter.ys
@@ -2,7 +2,7 @@ read_verilog ../common/shifter.v
 hierarchy -top top
 proc
 flatten
-equiv_opt -async2sync -assert -map +/intel_alm/common/alm_sim.v -map +/intel_alm/common/dff_sim.v synth_intel_alm -family cyclonev # equivalency check
+equiv_opt -async2sync -assert -map +/intel_alm/common/alm_sim.v -map +/intel_alm/common/dff_sim.v synth_intel_alm -family cyclonev -noiopad # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd top # Constrain all select calls below inside the top module
 select -assert-count 8 t:MISTRAL_FF
@@ -14,7 +14,7 @@ read_verilog ../common/shifter.v
 hierarchy -top top
 proc
 flatten
-equiv_opt -async2sync -assert -map +/intel_alm/common/alm_sim.v -map +/intel_alm/common/dff_sim.v synth_intel_alm -family cyclone10gx # equivalency check
+equiv_opt -async2sync -assert -map +/intel_alm/common/alm_sim.v -map +/intel_alm/common/dff_sim.v synth_intel_alm -family cyclone10gx -noiopad # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd top # Constrain all select calls below inside the top module
 select -assert-count 8 t:MISTRAL_FF
diff --git a/tests/arch/intel_alm/tribuf.ys b/tests/arch/intel_alm/tribuf.ys
index 7f3b38493..8b81c4cd4 100644
--- a/tests/arch/intel_alm/tribuf.ys
+++ b/tests/arch/intel_alm/tribuf.ys
@@ -4,7 +4,7 @@ proc
 tribuf
 flatten
 synth
-equiv_opt -assert -map +/simcells.v synth_intel_alm -family cyclonev # equivalency check
+equiv_opt -assert -map +/simcells.v synth_intel_alm -family cyclonev -noiopad # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd tristate # Constrain all select calls below inside the top module
 #Internal cell type used. Need support it.
@@ -19,7 +19,7 @@ proc
 tribuf
 flatten
 synth
-equiv_opt -assert -map +/simcells.v synth_intel_alm -family cyclone10gx # equivalency check
+equiv_opt -assert -map +/simcells.v synth_intel_alm -family cyclone10gx -noiopad # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd tristate # Constrain all select calls below inside the top module
 #Internal cell type used. Need support it.
-- 
cgit v1.2.3


From eb106732d94322fb5b48fbff0420ce5a6fc83eb9 Mon Sep 17 00:00:00 2001
From: gatecat <gatecat@ds0.me>
Date: Sat, 15 May 2021 14:34:48 +0100
Subject: intel_alm: Add global buffer insertion

Signed-off-by: gatecat <gatecat@ds0.me>
---
 tests/arch/intel_alm/add_sub.ys     |  4 ++--
 tests/arch/intel_alm/adffs.ys       | 16 ++++++++--------
 tests/arch/intel_alm/blockram.ys    |  2 +-
 tests/arch/intel_alm/counter.ys     |  4 ++--
 tests/arch/intel_alm/dffs.ys        |  8 ++++----
 tests/arch/intel_alm/fsm.ys         |  4 ++--
 tests/arch/intel_alm/logic.ys       |  4 ++--
 tests/arch/intel_alm/lutram.ys      |  4 ++--
 tests/arch/intel_alm/mul.ys         | 10 +++++-----
 tests/arch/intel_alm/mux.ys         | 16 ++++++++--------
 tests/arch/intel_alm/quartus_ice.ys |  2 +-
 tests/arch/intel_alm/shifter.ys     |  4 ++--
 tests/arch/intel_alm/tribuf.ys      |  4 ++--
 13 files changed, 41 insertions(+), 41 deletions(-)

(limited to 'tests')

diff --git a/tests/arch/intel_alm/add_sub.ys b/tests/arch/intel_alm/add_sub.ys
index a189ada1b..2d464788b 100644
--- a/tests/arch/intel_alm/add_sub.ys
+++ b/tests/arch/intel_alm/add_sub.ys
@@ -1,6 +1,6 @@
 read_verilog ../common/add_sub.v
 hierarchy -top top
-equiv_opt -assert -map +/intel_alm/common/alm_sim.v synth_intel_alm -family cyclonev -noiopad # equivalency check
+equiv_opt -assert -map +/intel_alm/common/alm_sim.v synth_intel_alm -family cyclonev -noiopad -noclkbuf # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd top # Constrain all select calls below inside the top module
 stat
@@ -10,7 +10,7 @@ select -assert-none t:MISTRAL_ALUT_ARITH %% t:* %D
 design -reset
 read_verilog ../common/add_sub.v
 hierarchy -top top
-equiv_opt -assert -map +/intel_alm/common/alm_sim.v synth_intel_alm -family cyclone10gx -noiopad # equivalency check
+equiv_opt -assert -map +/intel_alm/common/alm_sim.v synth_intel_alm -family cyclone10gx -noiopad -noclkbuf # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd top # Constrain all select calls below inside the top module
 stat
diff --git a/tests/arch/intel_alm/adffs.ys b/tests/arch/intel_alm/adffs.ys
index 7013ebb73..d7487c40b 100644
--- a/tests/arch/intel_alm/adffs.ys
+++ b/tests/arch/intel_alm/adffs.ys
@@ -3,7 +3,7 @@ design -save read
 
 hierarchy -top adff
 proc
-equiv_opt -async2sync -assert -map +/intel_alm/common/alm_sim.v -map +/intel_alm/common/dff_sim.v synth_intel_alm  -family cyclonev -noiopad # equivalency check
+equiv_opt -async2sync -assert -map +/intel_alm/common/alm_sim.v -map +/intel_alm/common/dff_sim.v synth_intel_alm  -family cyclonev -noiopad -noclkbuf # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd adff # Constrain all select calls below inside the top module
 select -assert-count 1 t:MISTRAL_FF
@@ -15,7 +15,7 @@ select -assert-none t:MISTRAL_FF t:MISTRAL_NOT %% t:* %D
 design -load read
 hierarchy -top adff
 proc
-equiv_opt -async2sync -assert -map +/intel_alm/common/alm_sim.v -map +/intel_alm/common/dff_sim.v synth_intel_alm -family cyclone10gx -noiopad # equivalency check
+equiv_opt -async2sync -assert -map +/intel_alm/common/alm_sim.v -map +/intel_alm/common/dff_sim.v synth_intel_alm -family cyclone10gx -noiopad -noclkbuf # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd adff # Constrain all select calls below inside the top module
 select -assert-count 1 t:MISTRAL_FF
@@ -27,7 +27,7 @@ select -assert-none t:MISTRAL_FF t:MISTRAL_NOT %% t:* %D
 design -load read
 hierarchy -top adffn
 proc
-equiv_opt -async2sync -assert -map +/intel_alm/common/alm_sim.v -map +/intel_alm/common/dff_sim.v synth_intel_alm -family cyclonev -noiopad # equivalency check
+equiv_opt -async2sync -assert -map +/intel_alm/common/alm_sim.v -map +/intel_alm/common/dff_sim.v synth_intel_alm -family cyclonev -noiopad -noclkbuf # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd adffn # Constrain all select calls below inside the top module
 select -assert-count 1 t:MISTRAL_FF
@@ -38,7 +38,7 @@ select -assert-none t:MISTRAL_FF %% t:* %D
 design -load read
 hierarchy -top adffn
 proc
-equiv_opt -async2sync -assert -map +/intel_alm/common/alm_sim.v -map +/intel_alm/common/dff_sim.v synth_intel_alm -family cyclone10gx -noiopad # equivalency check
+equiv_opt -async2sync -assert -map +/intel_alm/common/alm_sim.v -map +/intel_alm/common/dff_sim.v synth_intel_alm -family cyclone10gx -noiopad -noclkbuf # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd adffn # Constrain all select calls below inside the top module
 select -assert-count 1 t:MISTRAL_FF
@@ -49,7 +49,7 @@ select -assert-none t:MISTRAL_FF %% t:* %D
 design -load read
 hierarchy -top dffs
 proc
-equiv_opt -async2sync -assert -map +/intel_alm/common/alm_sim.v -map +/intel_alm/common/dff_sim.v synth_intel_alm -family cyclonev -noiopad # equivalency check
+equiv_opt -async2sync -assert -map +/intel_alm/common/alm_sim.v -map +/intel_alm/common/dff_sim.v synth_intel_alm -family cyclonev -noiopad -noclkbuf # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd dffs # Constrain all select calls below inside the top module
 select -assert-count 1 t:MISTRAL_FF
@@ -61,7 +61,7 @@ select -assert-none t:MISTRAL_FF t:MISTRAL_ALUT2 %% t:* %D
 design -load read
 hierarchy -top dffs
 proc
-equiv_opt -async2sync -assert -map +/intel_alm/common/alm_sim.v -map +/intel_alm/common/dff_sim.v synth_intel_alm -family cyclone10gx -noiopad # equivalency check
+equiv_opt -async2sync -assert -map +/intel_alm/common/alm_sim.v -map +/intel_alm/common/dff_sim.v synth_intel_alm -family cyclone10gx -noiopad -noclkbuf # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd dffs # Constrain all select calls below inside the top module
 select -assert-count 1 t:MISTRAL_FF
@@ -73,7 +73,7 @@ select -assert-none t:MISTRAL_FF t:MISTRAL_ALUT2 %% t:* %D
 design -load read
 hierarchy -top ndffnr
 proc
-equiv_opt -async2sync -assert -map +/intel_alm/common/alm_sim.v -map +/intel_alm/common/dff_sim.v synth_intel_alm -family cyclonev -noiopad # equivalency check
+equiv_opt -async2sync -assert -map +/intel_alm/common/alm_sim.v -map +/intel_alm/common/dff_sim.v synth_intel_alm -family cyclonev -noiopad -noclkbuf # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd ndffnr # Constrain all select calls below inside the top module
 select -assert-count 1 t:MISTRAL_FF
@@ -85,7 +85,7 @@ select -assert-none t:MISTRAL_FF t:MISTRAL_NOT %% t:* %D
 design -load read
 hierarchy -top ndffnr
 proc
-equiv_opt -async2sync -assert -map +/intel_alm/common/alm_sim.v -map +/intel_alm/common/dff_sim.v synth_intel_alm -family cyclone10gx -noiopad # equivalency check
+equiv_opt -async2sync -assert -map +/intel_alm/common/alm_sim.v -map +/intel_alm/common/dff_sim.v synth_intel_alm -family cyclone10gx -noiopad -noclkbuf # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd ndffnr # Constrain all select calls below inside the top module
 select -assert-count 1 t:MISTRAL_FF
diff --git a/tests/arch/intel_alm/blockram.ys b/tests/arch/intel_alm/blockram.ys
index b7c0e9564..c157c3165 100644
--- a/tests/arch/intel_alm/blockram.ys
+++ b/tests/arch/intel_alm/blockram.ys
@@ -1,6 +1,6 @@
 read_verilog ../common/blockram.v
 chparam -set ADDRESS_WIDTH 10 -set DATA_WIDTH 10 sync_ram_sdp
-synth_intel_alm -family cyclonev -noiopad
+synth_intel_alm -family cyclonev -noiopad -noclkbuf
 cd sync_ram_sdp
 select -assert-count 1 t:MISTRAL_M10K
 select -assert-none t:MISTRAL_M10K %% t:* %D
diff --git a/tests/arch/intel_alm/counter.ys b/tests/arch/intel_alm/counter.ys
index 98a9e360a..f2f3f14f7 100644
--- a/tests/arch/intel_alm/counter.ys
+++ b/tests/arch/intel_alm/counter.ys
@@ -2,7 +2,7 @@ read_verilog ../common/counter.v
 hierarchy -top top
 proc
 flatten
-equiv_opt -async2sync -map +/intel_alm/common/alm_sim.v -map +/intel_alm/common/dff_sim.v synth_intel_alm -family cyclonev -noiopad # equivalency check
+equiv_opt -async2sync -map +/intel_alm/common/alm_sim.v -map +/intel_alm/common/dff_sim.v synth_intel_alm -family cyclonev -noiopad -noclkbuf # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd top # Constrain all select calls below inside the top module
 
@@ -17,7 +17,7 @@ read_verilog ../common/counter.v
 hierarchy -top top
 proc
 flatten
-equiv_opt -async2sync -map +/intel_alm/common/alm_sim.v -map +/intel_alm/common/dff_sim.v synth_intel_alm -family cyclone10gx -noiopad # equivalency check
+equiv_opt -async2sync -map +/intel_alm/common/alm_sim.v -map +/intel_alm/common/dff_sim.v synth_intel_alm -family cyclone10gx -noiopad -noclkbuf # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd top # Constrain all select calls below inside the top module
 
diff --git a/tests/arch/intel_alm/dffs.ys b/tests/arch/intel_alm/dffs.ys
index 811a5d82f..34b99f04c 100644
--- a/tests/arch/intel_alm/dffs.ys
+++ b/tests/arch/intel_alm/dffs.ys
@@ -3,7 +3,7 @@ design -save read
 
 hierarchy -top dff
 proc
-equiv_opt -async2sync -assert -map +/intel_alm/common/alm_sim.v -map +/intel_alm/common/dff_sim.v synth_intel_alm -family cyclonev -noiopad # equivalency check
+equiv_opt -async2sync -assert -map +/intel_alm/common/alm_sim.v -map +/intel_alm/common/dff_sim.v synth_intel_alm -family cyclonev -noiopad -noclkbuf # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd dff # Constrain all select calls below inside the top module
 select -assert-count 1 t:MISTRAL_FF
@@ -13,7 +13,7 @@ select -assert-none t:MISTRAL_FF %% t:* %D
 design -load read
 hierarchy -top dff
 proc
-equiv_opt -async2sync -assert -map +/intel_alm/common/alm_sim.v -map +/intel_alm/common/dff_sim.v synth_intel_alm -family cyclone10gx -noiopad # equivalency check
+equiv_opt -async2sync -assert -map +/intel_alm/common/alm_sim.v -map +/intel_alm/common/dff_sim.v synth_intel_alm -family cyclone10gx -noiopad -noclkbuf # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd dff # Constrain all select calls below inside the top module
 select -assert-count 1 t:MISTRAL_FF
@@ -24,7 +24,7 @@ select -assert-none t:MISTRAL_FF %% t:* %D
 design -load read
 hierarchy -top dffe
 proc
-equiv_opt -async2sync -assert -map +/intel_alm/common/alm_sim.v -map +/intel_alm/common/dff_sim.v synth_intel_alm -family cyclonev -noiopad # equivalency check
+equiv_opt -async2sync -assert -map +/intel_alm/common/alm_sim.v -map +/intel_alm/common/dff_sim.v synth_intel_alm -family cyclonev -noiopad -noclkbuf # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd dffe # Constrain all select calls below inside the top module
 select -assert-count 1 t:MISTRAL_FF
@@ -35,7 +35,7 @@ select -assert-none t:MISTRAL_FF %% t:* %D
 design -load read
 hierarchy -top dffe
 proc
-equiv_opt -async2sync -assert -map +/intel_alm/common/alm_sim.v -map +/intel_alm/common/dff_sim.v synth_intel_alm -family cyclone10gx -noiopad # equivalency check
+equiv_opt -async2sync -assert -map +/intel_alm/common/alm_sim.v -map +/intel_alm/common/dff_sim.v synth_intel_alm -family cyclone10gx -noiopad -noclkbuf # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd dffe # Constrain all select calls below inside the top module
 select -assert-count 1 t:MISTRAL_FF
diff --git a/tests/arch/intel_alm/fsm.ys b/tests/arch/intel_alm/fsm.ys
index 96c050bad..0aeea450a 100644
--- a/tests/arch/intel_alm/fsm.ys
+++ b/tests/arch/intel_alm/fsm.ys
@@ -3,7 +3,7 @@ hierarchy -top fsm
 proc
 flatten
 
-equiv_opt -run :prove -map +/intel_alm/common/alm_sim.v -map +/intel_alm/common/dff_sim.v synth_intel_alm -family cyclonev -noiopad
+equiv_opt -run :prove -map +/intel_alm/common/alm_sim.v -map +/intel_alm/common/dff_sim.v synth_intel_alm -family cyclonev -noiopad -noclkbuf
 async2sync
 miter -equiv -make_assert -flatten gold gate miter
 sat -verify -prove-asserts -show-public -set-at 1 in_reset 1 -seq 20 -prove-skip 1 miter
@@ -26,7 +26,7 @@ hierarchy -top fsm
 proc
 flatten
 
-equiv_opt -run :prove -map +/intel_alm/common/alm_sim.v -map +/intel_alm/common/dff_sim.v synth_intel_alm -family cyclone10gx -noiopad
+equiv_opt -run :prove -map +/intel_alm/common/alm_sim.v -map +/intel_alm/common/dff_sim.v synth_intel_alm -family cyclone10gx -noiopad -noclkbuf
 async2sync
 miter -equiv -make_assert -flatten gold gate miter
 sat -verify -prove-asserts -show-public -set-at 1 in_reset 1 -seq 20 -prove-skip 1 miter
diff --git a/tests/arch/intel_alm/logic.ys b/tests/arch/intel_alm/logic.ys
index 916c1161c..d34d1bc65 100644
--- a/tests/arch/intel_alm/logic.ys
+++ b/tests/arch/intel_alm/logic.ys
@@ -1,7 +1,7 @@
 read_verilog ../common/logic.v
 hierarchy -top top
 proc
-equiv_opt -assert -map +/intel_alm/common/alm_sim.v synth_intel_alm -family cyclonev -noiopad # equivalency check
+equiv_opt -assert -map +/intel_alm/common/alm_sim.v synth_intel_alm -family cyclonev -noiopad -noclkbuf # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd top # Constrain all select calls below inside the top module
 
@@ -15,7 +15,7 @@ design -reset
 read_verilog ../common/logic.v
 hierarchy -top top
 proc
-equiv_opt -assert -map +/intel_alm/common/alm_sim.v synth_intel_alm -family cyclone10gx -noiopad # equivalency check
+equiv_opt -assert -map +/intel_alm/common/alm_sim.v synth_intel_alm -family cyclone10gx -noiopad -noclkbuf # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd top # Constrain all select calls below inside the top module
 
diff --git a/tests/arch/intel_alm/lutram.ys b/tests/arch/intel_alm/lutram.ys
index c21c9103b..5d33b8e12 100644
--- a/tests/arch/intel_alm/lutram.ys
+++ b/tests/arch/intel_alm/lutram.ys
@@ -2,7 +2,7 @@ read_verilog ../common/lutram.v
 hierarchy -top lutram_1w1r
 proc
 memory -nomap
-equiv_opt -run :prove -map +/intel_alm/common/alm_sim.v -map +/intel_alm/common/dff_sim.v -map +/intel_alm/common/mem_sim.v synth_intel_alm -family cyclonev -nobram -noiopad
+equiv_opt -run :prove -map +/intel_alm/common/alm_sim.v -map +/intel_alm/common/dff_sim.v -map +/intel_alm/common/mem_sim.v synth_intel_alm -family cyclonev -nobram -noiopad -noclkbuf
 memory
 opt -full
 
@@ -24,7 +24,7 @@ read_verilog ../common/lutram.v
 hierarchy -top lutram_1w1r
 proc
 memory -nomap
-equiv_opt -run :prove -map +/intel_alm/common/alm_sim.v -map +/intel_alm/common/dff_sim.v -map +/intel_alm/common/mem_sim.v synth_intel_alm -family cyclonev -nobram -noiopad
+equiv_opt -run :prove -map +/intel_alm/common/alm_sim.v -map +/intel_alm/common/dff_sim.v -map +/intel_alm/common/mem_sim.v synth_intel_alm -family cyclonev -nobram -noiopad -noclkbuf
 memory
 opt -full
 
diff --git a/tests/arch/intel_alm/mul.ys b/tests/arch/intel_alm/mul.ys
index 10f3f7bf4..e147d93ac 100644
--- a/tests/arch/intel_alm/mul.ys
+++ b/tests/arch/intel_alm/mul.ys
@@ -2,7 +2,7 @@ read_verilog ../common/mul.v
 chparam -set X_WIDTH 8 -set Y_WIDTH 8 -set A_WIDTH 16
 hierarchy -top top
 proc
-equiv_opt -assert -map +/intel_alm/common/dsp_sim.v synth_intel_alm -family cyclonev -noiopad # equivalency check
+equiv_opt -assert -map +/intel_alm/common/dsp_sim.v synth_intel_alm -family cyclonev -noiopad -noclkbuf # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd top # Constrain all select calls below inside the top module
 
@@ -16,7 +16,7 @@ read_verilog ../common/mul.v
 chparam -set X_WIDTH 17 -set Y_WIDTH 17 -set A_WIDTH 34
 hierarchy -top top
 proc
-equiv_opt -assert -map +/intel_alm/common/dsp_sim.v synth_intel_alm -family cyclonev -noiopad # equivalency check
+equiv_opt -assert -map +/intel_alm/common/dsp_sim.v synth_intel_alm -family cyclonev -noiopad -noclkbuf # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd top # Constrain all select calls below inside the top module
 
@@ -28,7 +28,7 @@ read_verilog ../common/mul.v
 chparam -set X_WIDTH 17 -set Y_WIDTH 17 -set A_WIDTH 34
 hierarchy -top top
 proc
-equiv_opt -assert -map +/intel_alm/common/dsp_sim.v synth_intel_alm -family cyclone10gx -noiopad # equivalency check
+equiv_opt -assert -map +/intel_alm/common/dsp_sim.v synth_intel_alm -family cyclone10gx -noiopad -noclkbuf # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd top # Constrain all select calls below inside the top module
 
@@ -40,7 +40,7 @@ read_verilog ../common/mul.v
 chparam -set X_WIDTH 26 -set Y_WIDTH 26 -set A_WIDTH 52
 hierarchy -top top
 proc
-equiv_opt -assert -map +/intel_alm/common/dsp_sim.v synth_intel_alm -family cyclonev -noiopad # equivalency check
+equiv_opt -assert -map +/intel_alm/common/dsp_sim.v synth_intel_alm -family cyclonev -noiopad -noclkbuf # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd top # Constrain all select calls below inside the top module
 
@@ -52,7 +52,7 @@ read_verilog ../common/mul.v
 chparam -set X_WIDTH 26 -set Y_WIDTH 26 -set A_WIDTH 52
 hierarchy -top top
 proc
-equiv_opt -assert -map +/intel_alm/common/dsp_sim.v synth_intel_alm -family cyclone10gx -noiopad # equivalency check
+equiv_opt -assert -map +/intel_alm/common/dsp_sim.v synth_intel_alm -family cyclone10gx -noiopad -noclkbuf # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd top # Constrain all select calls below inside the top module
 
diff --git a/tests/arch/intel_alm/mux.ys b/tests/arch/intel_alm/mux.ys
index c386542c4..6fb6ae80a 100644
--- a/tests/arch/intel_alm/mux.ys
+++ b/tests/arch/intel_alm/mux.ys
@@ -4,7 +4,7 @@ design -save read
 
 hierarchy -top mux2
 proc
-equiv_opt -assert -map +/intel_alm/common/alm_sim.v synth_intel_alm -family cyclonev -noiopad # equivalency check
+equiv_opt -assert -map +/intel_alm/common/alm_sim.v synth_intel_alm -family cyclonev -noiopad -noclkbuf # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd mux2 # Constrain all select calls below inside the top module
 select -assert-count 1 t:MISTRAL_ALUT3
@@ -14,7 +14,7 @@ select -assert-none t:MISTRAL_ALUT3 %% t:* %D
 design -load read
 hierarchy -top mux2
 proc
-equiv_opt -assert -map +/intel_alm/common/alm_sim.v synth_intel_alm -family cyclone10gx -noiopad # equivalency check
+equiv_opt -assert -map +/intel_alm/common/alm_sim.v synth_intel_alm -family cyclone10gx -noiopad -noclkbuf # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd mux2 # Constrain all select calls below inside the top module
 select -assert-count 1 t:MISTRAL_ALUT3
@@ -24,7 +24,7 @@ select -assert-none t:MISTRAL_ALUT3 %% t:* %D
 design -load read
 hierarchy -top mux4
 proc
-equiv_opt -assert -map +/intel_alm/common/alm_sim.v synth_intel_alm -family cyclonev -noiopad # equivalency check
+equiv_opt -assert -map +/intel_alm/common/alm_sim.v synth_intel_alm -family cyclonev -noiopad -noclkbuf # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd mux4 # Constrain all select calls below inside the top module
 select -assert-count 1 t:MISTRAL_ALUT6
@@ -34,7 +34,7 @@ select -assert-none t:MISTRAL_ALUT6 %% t:* %D
 design -load read
 hierarchy -top mux4
 proc
-equiv_opt -assert -map +/intel_alm/common/alm_sim.v synth_intel_alm -family cyclone10gx -noiopad # equivalency check
+equiv_opt -assert -map +/intel_alm/common/alm_sim.v synth_intel_alm -family cyclone10gx -noiopad -noclkbuf # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd mux4 # Constrain all select calls below inside the top module
 select -assert-count 1 t:MISTRAL_ALUT6
@@ -44,7 +44,7 @@ select -assert-none t:MISTRAL_ALUT6 %% t:* %D
 design -load read
 hierarchy -top mux8
 proc
-equiv_opt -assert -map +/intel_alm/common/alm_sim.v synth_intel_alm -family cyclonev -noiopad # equivalency check
+equiv_opt -assert -map +/intel_alm/common/alm_sim.v synth_intel_alm -family cyclonev -noiopad -noclkbuf # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd mux8 # Constrain all select calls below inside the top module
 select -assert-count 1 t:MISTRAL_ALUT3
@@ -55,7 +55,7 @@ select -assert-none t:MISTRAL_ALUT3 t:MISTRAL_ALUT6 %% t:* %D
 design -load read
 hierarchy -top mux8
 proc
-equiv_opt -assert -map +/intel_alm/common/alm_sim.v synth_intel_alm -family cyclone10gx -noiopad # equivalency check
+equiv_opt -assert -map +/intel_alm/common/alm_sim.v synth_intel_alm -family cyclone10gx -noiopad -noclkbuf # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd mux8 # Constrain all select calls below inside the top module
 select -assert-count 1 t:MISTRAL_ALUT3
@@ -66,7 +66,7 @@ select -assert-none t:MISTRAL_ALUT3 t:MISTRAL_ALUT6 %% t:* %D
 design -load read
 hierarchy -top mux16
 proc
-equiv_opt -assert -map +/intel_alm/common/alm_sim.v synth_intel_alm -family cyclonev # equivalency check
+equiv_opt -assert -map +/intel_alm/common/alm_sim.v synth_intel_alm -family cyclonev -noiopad -noclkbuf # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd mux16 # Constrain all select calls below inside the top module
 select -assert-count 1 t:MISTRAL_ALUT3
@@ -78,7 +78,7 @@ select -assert-none t:MISTRAL_ALUT3 t:MISTRAL_ALUT5 t:MISTRAL_ALUT6 %% t:* %D
 design -load read
 hierarchy -top mux16
 proc
-equiv_opt -assert -map +/intel_alm/common/alm_sim.v synth_intel_alm -family cyclone10gx # equivalency check
+equiv_opt -assert -map +/intel_alm/common/alm_sim.v synth_intel_alm -family cyclone10gx -noiopad -noclkbuf # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd mux16 # Constrain all select calls below inside the top module
 select -assert-count 1 t:MISTRAL_ALUT3
diff --git a/tests/arch/intel_alm/quartus_ice.ys b/tests/arch/intel_alm/quartus_ice.ys
index 286e6653c..4e1896b82 100644
--- a/tests/arch/intel_alm/quartus_ice.ys
+++ b/tests/arch/intel_alm/quartus_ice.ys
@@ -22,5 +22,5 @@ module top();
 endmodule
 EOT
 
-synth_intel_alm -family cyclone10gx -quartus -noiopad
+synth_intel_alm -family cyclone10gx -quartus -noiopad -noclkbuf
 select -assert-none w:*[* w:*]*
diff --git a/tests/arch/intel_alm/shifter.ys b/tests/arch/intel_alm/shifter.ys
index bf19beef1..77ff98896 100644
--- a/tests/arch/intel_alm/shifter.ys
+++ b/tests/arch/intel_alm/shifter.ys
@@ -2,7 +2,7 @@ read_verilog ../common/shifter.v
 hierarchy -top top
 proc
 flatten
-equiv_opt -async2sync -assert -map +/intel_alm/common/alm_sim.v -map +/intel_alm/common/dff_sim.v synth_intel_alm -family cyclonev -noiopad # equivalency check
+equiv_opt -async2sync -assert -map +/intel_alm/common/alm_sim.v -map +/intel_alm/common/dff_sim.v synth_intel_alm -family cyclonev -noiopad -noclkbuf # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd top # Constrain all select calls below inside the top module
 select -assert-count 8 t:MISTRAL_FF
@@ -14,7 +14,7 @@ read_verilog ../common/shifter.v
 hierarchy -top top
 proc
 flatten
-equiv_opt -async2sync -assert -map +/intel_alm/common/alm_sim.v -map +/intel_alm/common/dff_sim.v synth_intel_alm -family cyclone10gx -noiopad # equivalency check
+equiv_opt -async2sync -assert -map +/intel_alm/common/alm_sim.v -map +/intel_alm/common/dff_sim.v synth_intel_alm -family cyclone10gx -noiopad -noclkbuf # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd top # Constrain all select calls below inside the top module
 select -assert-count 8 t:MISTRAL_FF
diff --git a/tests/arch/intel_alm/tribuf.ys b/tests/arch/intel_alm/tribuf.ys
index 8b81c4cd4..fb5fecb78 100644
--- a/tests/arch/intel_alm/tribuf.ys
+++ b/tests/arch/intel_alm/tribuf.ys
@@ -4,7 +4,7 @@ proc
 tribuf
 flatten
 synth
-equiv_opt -assert -map +/simcells.v synth_intel_alm -family cyclonev -noiopad # equivalency check
+equiv_opt -assert -map +/simcells.v synth_intel_alm -family cyclonev -noiopad -noclkbuf # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd tristate # Constrain all select calls below inside the top module
 #Internal cell type used. Need support it.
@@ -19,7 +19,7 @@ proc
 tribuf
 flatten
 synth
-equiv_opt -assert -map +/simcells.v synth_intel_alm -family cyclone10gx -noiopad # equivalency check
+equiv_opt -assert -map +/simcells.v synth_intel_alm -family cyclone10gx -noiopad -noclkbuf # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd tristate # Constrain all select calls below inside the top module
 #Internal cell type used. Need support it.
-- 
cgit v1.2.3


From 34a08750fa1a490be09411b07f64f4236eff234e Mon Sep 17 00:00:00 2001
From: gatecat <gatecat@ds0.me>
Date: Sat, 15 May 2021 14:40:37 +0100
Subject: intel_alm: Fix illegal carry chains

Signed-off-by: gatecat <gatecat@ds0.me>
---
 tests/arch/intel_alm/add_sub.ys | 4 ++--
 tests/arch/intel_alm/counter.ys | 4 ++--
 2 files changed, 4 insertions(+), 4 deletions(-)

(limited to 'tests')

diff --git a/tests/arch/intel_alm/add_sub.ys b/tests/arch/intel_alm/add_sub.ys
index 2d464788b..8f87adf27 100644
--- a/tests/arch/intel_alm/add_sub.ys
+++ b/tests/arch/intel_alm/add_sub.ys
@@ -4,7 +4,7 @@ equiv_opt -assert -map +/intel_alm/common/alm_sim.v synth_intel_alm -family cycl
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd top # Constrain all select calls below inside the top module
 stat
-select -assert-count 8 t:MISTRAL_ALUT_ARITH
+select -assert-count 9 t:MISTRAL_ALUT_ARITH
 select -assert-none t:MISTRAL_ALUT_ARITH %% t:* %D
 
 design -reset
@@ -14,5 +14,5 @@ equiv_opt -assert -map +/intel_alm/common/alm_sim.v synth_intel_alm -family cycl
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd top # Constrain all select calls below inside the top module
 stat
-select -assert-count 8 t:MISTRAL_ALUT_ARITH
+select -assert-count 9 t:MISTRAL_ALUT_ARITH
 select -assert-none t:MISTRAL_ALUT_ARITH %% t:* %D
diff --git a/tests/arch/intel_alm/counter.ys b/tests/arch/intel_alm/counter.ys
index f2f3f14f7..56c9cabb3 100644
--- a/tests/arch/intel_alm/counter.ys
+++ b/tests/arch/intel_alm/counter.ys
@@ -6,7 +6,7 @@ equiv_opt -async2sync -map +/intel_alm/common/alm_sim.v -map +/intel_alm/common/
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd top # Constrain all select calls below inside the top module
 
-select -assert-count 2 t:MISTRAL_NOT
+select -assert-count 1 t:MISTRAL_NOT
 select -assert-count 8 t:MISTRAL_ALUT_ARITH
 select -assert-count 8 t:MISTRAL_FF
 select -assert-none t:MISTRAL_NOT t:MISTRAL_ALUT_ARITH t:MISTRAL_FF %% t:* %D
@@ -21,7 +21,7 @@ equiv_opt -async2sync -map +/intel_alm/common/alm_sim.v -map +/intel_alm/common/
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd top # Constrain all select calls below inside the top module
 
-select -assert-count 2 t:MISTRAL_NOT
+select -assert-count 1 t:MISTRAL_NOT
 select -assert-count 8 t:MISTRAL_ALUT_ARITH
 select -assert-count 8 t:MISTRAL_FF
 select -assert-none t:MISTRAL_NOT t:MISTRAL_ALUT_ARITH t:MISTRAL_FF %% t:* %D
-- 
cgit v1.2.3


From 4240498f71e61dbb57668ef31be67ef5ad7e574a Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Marcelina=20Ko=C5=9Bcielnicka?= <mwk@0x04.net>
Date: Thu, 20 May 2021 12:49:51 +0200
Subject: tests/blif: Add missing gitignore

---
 tests/blif/.gitignore | 1 +
 1 file changed, 1 insertion(+)
 create mode 100644 tests/blif/.gitignore

(limited to 'tests')

diff --git a/tests/blif/.gitignore b/tests/blif/.gitignore
new file mode 100644
index 000000000..397b4a762
--- /dev/null
+++ b/tests/blif/.gitignore
@@ -0,0 +1 @@
+*.log
-- 
cgit v1.2.3


From a23d9409e7d04fcfa31a139d0cf6169be4c46fca Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Marcelina=20Ko=C5=9Bcielnicka?= <mwk@0x04.net>
Date: Sat, 22 May 2021 20:27:51 +0200
Subject: opt_mem: Remove write ports with const-0 EN.

Fixes #2765.
---
 tests/opt/bug2765.ys | 34 ++++++++++++++++++++++++++++++++++
 1 file changed, 34 insertions(+)
 create mode 100644 tests/opt/bug2765.ys

(limited to 'tests')

diff --git a/tests/opt/bug2765.ys b/tests/opt/bug2765.ys
new file mode 100644
index 000000000..de670c2d1
--- /dev/null
+++ b/tests/opt/bug2765.ys
@@ -0,0 +1,34 @@
+read_verilog << EOT
+
+module top(...);
+
+input clk;
+input [3:0] wa;
+input [15:0] wd;
+input [3:0] ra;
+output [15:0] rd;
+
+reg [15:0] mem[0:15];
+
+integer i;
+reg x;
+
+always @(posedge clk) begin
+        for (i = 0; i < 2; i = i + 1) begin
+                x = i == 1;
+                if (x)
+                        mem[wa] <= wd;
+        end
+end
+
+assign rd = mem[ra];
+
+endmodule
+
+EOT
+
+proc
+opt
+select -assert-count 2 t:$memwr
+opt_mem
+select -assert-count 1 t:$memwr
-- 
cgit v1.2.3


From 1eea06bcc0750de02a460f3e949df2f68f800382 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Marcelina=20Ko=C5=9Bcielnicka?= <mwk@0x04.net>
Date: Mon, 15 Mar 2021 15:38:45 +0100
Subject: Add new helper class for merging FFs into cells, use for memory_dff.

Fixes #1854.
---
 tests/opt/bug1854.ys | 17 +++++++++++++++++
 1 file changed, 17 insertions(+)
 create mode 100644 tests/opt/bug1854.ys

(limited to 'tests')

diff --git a/tests/opt/bug1854.ys b/tests/opt/bug1854.ys
new file mode 100644
index 000000000..00a36ae94
--- /dev/null
+++ b/tests/opt/bug1854.ys
@@ -0,0 +1,17 @@
+read_verilog << EOT
+module top(input clk, input [3:0] addr, output reg [0:0] dout);
+	reg [1:0] mem[0:15];
+	initial begin
+		mem[0] = 2'b00;
+		mem[1] = 2'b01;
+		mem[2] = 2'b10;
+		mem[3] = 2'b11;
+	end
+	always @(posedge clk)
+		dout <= mem[addr];
+endmodule
+EOT
+
+prep -rdff
+
+select -assert-none t:$dff
-- 
cgit v1.2.3


From 835688bf80eb9db7241c1aa767b7e97dad1c0eeb Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Marcelina=20Ko=C5=9Bcielnicka?= <mwk@0x04.net>
Date: Mon, 24 May 2021 21:21:51 +0200
Subject: opt_mem_feedback: Rewrite feedback path finding logic.

Fixes #2766.
---
 tests/opt/bug2766.ys          | 101 ++++++++++++++++++++++++++++++
 tests/opt/opt_mem_feedback.ys | 142 ++++++++++++++++++++++++++++++++++++++++++
 2 files changed, 243 insertions(+)
 create mode 100644 tests/opt/bug2766.ys
 create mode 100644 tests/opt/opt_mem_feedback.ys

(limited to 'tests')

diff --git a/tests/opt/bug2766.ys b/tests/opt/bug2766.ys
new file mode 100644
index 000000000..c7aa916f4
--- /dev/null
+++ b/tests/opt/bug2766.ys
@@ -0,0 +1,101 @@
+# Case 1.
+
+read_verilog << EOT
+
+module top(...);
+
+input clk;
+input sel;
+input [3:0] ra;
+input [3:0] wa;
+input wd;
+output [3:0] rd;
+
+reg [3:0] mem[0:15];
+
+integer i;
+initial begin
+        for (i = 0; i < 16; i = i + 1)
+                mem[i] <= i;
+end
+
+assign rd = mem[ra];
+
+always @(posedge clk) begin
+        mem[wa] <= {4{sel ? wd : mem[wa][0]}};
+end
+
+endmodule
+
+EOT
+
+hierarchy -auto-top
+proc
+opt_clean
+
+design -save start
+memory_map
+design -save preopt
+
+design -load start
+opt_mem_feedback
+memory_map
+design -save postopt
+
+equiv_opt -assert -run prepare: :
+
+
+
+design -reset
+
+# Case 2.
+
+read_verilog << EOT
+
+module top(...);
+
+input clk;
+input s1;
+input s2;
+input s3;
+input [3:0] ra;
+input [3:0] wa;
+input wd;
+output rd;
+
+reg mem[0:15];
+
+integer i;
+initial begin
+        for (i = 0; i < 16; i = i + 1)
+                mem[i] <= ^i;
+end
+
+assign rd = mem[ra];
+
+wire ta = s1 ? wd : mem[wa];
+wire tb = s2 ? wd : ta;
+wire tc = s3 ? tb : ta;
+
+always @(posedge clk) begin
+        mem[wa] <= tc;
+end
+
+endmodule
+
+EOT
+
+hierarchy -auto-top
+proc
+opt_clean
+
+design -save start
+memory_map
+design -save preopt
+
+design -load start
+opt_mem_feedback
+memory_map
+design -save postopt
+
+equiv_opt -assert -run prepare: :
diff --git a/tests/opt/opt_mem_feedback.ys b/tests/opt/opt_mem_feedback.ys
new file mode 100644
index 000000000..6a68921c3
--- /dev/null
+++ b/tests/opt/opt_mem_feedback.ys
@@ -0,0 +1,142 @@
+# Good case: proper feedback port.
+
+read_verilog << EOT
+
+module top(...);
+
+input clk;
+input en;
+input s;
+
+input [3:0] ra;
+output [15:0] rd;
+input [3:0] wa;
+input [15:0] wd;
+
+reg [15:0] mem[0:15];
+
+assign rd = mem[ra];
+
+always @(posedge clk) begin
+	if (en) begin
+		mem[wa] <= {mem[wa][15:8], s ? wd[7:0] : mem[wa][7:0]};
+	end
+end
+
+endmodule
+
+EOT
+
+hierarchy -auto-top
+proc
+opt_clean
+
+design -save start
+memory_map
+design -save preopt
+
+design -load start
+opt_mem_feedback
+select -assert-count 1 t:$memrd
+memory_map
+design -save postopt
+
+equiv_opt -assert -run prepare: :
+
+
+
+design -reset
+
+# Bad case: read port also used for other things.
+
+read_verilog << EOT
+
+module top(...);
+
+input clk;
+input en;
+input s;
+
+output [15:0] rd;
+input [3:0] wa;
+input [15:0] wd;
+
+reg [15:0] mem[0:15];
+
+assign rd = mem[wa];
+
+always @(posedge clk) begin
+	if (en) begin
+		mem[wa] <= {s ? rd : wd[15:8], s ? wd[7:0] : rd};
+	end
+end
+
+endmodule
+
+EOT
+
+hierarchy -auto-top
+proc
+opt_clean
+
+design -save start
+memory_map
+design -save preopt
+
+design -load start
+select -assert-count 1 t:$memrd
+opt_mem_feedback
+select -assert-count 1 t:$memrd
+memory_map
+design -save postopt
+
+equiv_opt -assert -run prepare: :
+
+
+
+design -reset
+
+# Bad case: another user of the mux out.
+
+read_verilog << EOT
+
+module top(...);
+
+input clk;
+input en;
+input s;
+
+output [15:0] rd;
+input [3:0] wa;
+input [15:0] wd;
+
+reg [15:0] mem[0:15];
+
+assign rd = s ? wd : mem[wa];
+
+always @(posedge clk) begin
+	if (en) begin
+		mem[wa] <= rd;
+	end
+end
+
+endmodule
+
+EOT
+
+hierarchy -auto-top
+proc
+opt_clean
+
+design -save start
+memory_map
+design -save preopt
+
+design -load start
+select -assert-count 1 t:$memrd
+opt_mem_feedback
+select -assert-count 1 t:$memrd
+memory_map
+design -save postopt
+
+equiv_opt -assert -run prepare: :
-- 
cgit v1.2.3


From 5628f5a88fa49c126af0149e302a8292229ab9df Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Marcelina=20Ko=C5=9Bcielnicka?= <mwk@0x04.net>
Date: Tue, 25 May 2021 15:17:29 +0200
Subject: opt_mem_feedback: Respect write port priority.

---
 tests/opt/opt_mem_feedback.ys | 47 +++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 47 insertions(+)

(limited to 'tests')

diff --git a/tests/opt/opt_mem_feedback.ys b/tests/opt/opt_mem_feedback.ys
index 6a68921c3..56078ec27 100644
--- a/tests/opt/opt_mem_feedback.ys
+++ b/tests/opt/opt_mem_feedback.ys
@@ -140,3 +140,50 @@ memory_map
 design -save postopt
 
 equiv_opt -assert -run prepare: :
+
+
+
+design -reset
+
+# Tricky case: legit feedback path, but priority needs to be preserved.
+
+read_verilog << EOT
+
+module top(...);
+
+input clk;
+input sel;
+input [3:0] wa1;
+input [3:0] wa2;
+input [15:0] wd1;
+input [3:0] ra;
+output [15:0] rd;
+
+reg [15:0] mem [0:15];
+
+always @(posedge clk) begin
+	mem[wa1] <= sel ? wd1 : mem[wa1];
+	mem[wa2] <= mem[wa2];
+end
+
+assign rd = mem[ra];
+
+endmodule
+
+EOT
+
+hierarchy -auto-top
+proc
+opt_clean
+
+design -save start
+memory_map
+design -save preopt
+
+design -load start
+opt_mem_feedback
+select -assert-count 1 t:$memrd
+memory_map
+design -save postopt
+
+equiv_opt -assert -run prepare: :
-- 
cgit v1.2.3


From 15f35d6754af619accdf63030e0a5ad3085cec16 Mon Sep 17 00:00:00 2001
From: Zachary Snow <zach@zachjs.com>
Date: Sat, 27 Mar 2021 15:59:48 -0400
Subject: sv: support remaining assignment operators

- Add support for: *=, /=, %=, <<=, >>=, <<<=, >>>=
- Unify existing support for: +=, -=, &=, |=, ^=
---
 tests/simple/asgn_binop.sv | 23 +++++++++++++++++++++++
 1 file changed, 23 insertions(+)
 create mode 100644 tests/simple/asgn_binop.sv

(limited to 'tests')

diff --git a/tests/simple/asgn_binop.sv b/tests/simple/asgn_binop.sv
new file mode 100644
index 000000000..b134e5697
--- /dev/null
+++ b/tests/simple/asgn_binop.sv
@@ -0,0 +1,23 @@
+`define TEST(name, asgnop)\
+	module test_``name ( \
+		input logic [3:0] a, b, \
+		output logic [3:0] c \
+	); \
+		always @* begin \
+			c = a; \
+			c asgnop b; \
+		end \
+	endmodule
+
+`TEST(add, +=)
+`TEST(sub, -=)
+`TEST(mul, *=)
+`TEST(div, /=)
+`TEST(mod, %=)
+`TEST(bit_and, &=)
+`TEST(bit_or , |=)
+`TEST(bit_xor, ^=)
+`TEST(shl, <<=)
+`TEST(shr, >>=)
+`TEST(sshl, <<<=)
+`TEST(sshr, >>>=)
-- 
cgit v1.2.3


From 0795b3ec076d8d2c0aa0d954b707271bd2f064bf Mon Sep 17 00:00:00 2001
From: Zachary Snow <zach@zachjs.com>
Date: Thu, 25 Mar 2021 14:06:05 -0400
Subject: verilog: fix case expression sign and width handling

- The case expression and case item expressions are extended to the
  maximum width among them, and are only interpreted as signed if all of
  them are signed
- Add overall width and sign detection for AST_CASE
- Add sign argument to genWidthRTLIL helper
- Coverage for both const and non-const case statements
---
 tests/simple/case_expr_const.v     | 49 +++++++++++++++++++++++++++++++
 tests/simple/case_expr_non_const.v | 59 ++++++++++++++++++++++++++++++++++++++
 2 files changed, 108 insertions(+)
 create mode 100644 tests/simple/case_expr_const.v
 create mode 100644 tests/simple/case_expr_non_const.v

(limited to 'tests')

diff --git a/tests/simple/case_expr_const.v b/tests/simple/case_expr_const.v
new file mode 100644
index 000000000..58267b965
--- /dev/null
+++ b/tests/simple/case_expr_const.v
@@ -0,0 +1,49 @@
+// Note: case_expr_{,non_}const.v should be modified in tandem to ensure both
+// the constant and non-constant case evaluation logic is covered
+module top(
+	// expected to output all 1s
+    output reg a, b, c, d, e, f, g, h
+);
+    initial begin
+        case (2'b0)
+            1'b0:    a = 1;
+            default: a = 0;
+        endcase
+        case (2'sb11)
+            2'sb01:  b = 0;
+            1'sb1:   b = 1;
+        endcase
+        case (2'sb11)
+            1'sb0:   c = 0;
+            1'sb1:   c = 1;
+        endcase
+        case (2'sb11)
+            1'b0:    d = 0;
+            1'sb1:   d = 0;
+            default: d = 1;
+        endcase
+        case (2'b11)
+            1'sb0:   e = 0;
+            1'sb1:   e = 0;
+            default: e = 1;
+        endcase
+        case (1'sb1)
+            1'sb0:   f = 0;
+            2'sb11:  f = 1;
+            default: f = 0;
+        endcase
+        case (1'sb1)
+            1'sb0:   g = 0;
+            3'b0:    g = 0;
+            2'sb11:  g = 0;
+            default: g = 1;
+        endcase
+        case (1'sb1)
+            1'sb0:   h = 0;
+            1'b1:    h = 1;
+            3'b0:    h = 0;
+            2'sb11:  h = 0;
+            default: h = 0;
+        endcase
+    end
+endmodule
diff --git a/tests/simple/case_expr_non_const.v b/tests/simple/case_expr_non_const.v
new file mode 100644
index 000000000..7856e781c
--- /dev/null
+++ b/tests/simple/case_expr_non_const.v
@@ -0,0 +1,59 @@
+// Note: case_expr_{,non_}const.v should be modified in tandem to ensure both
+// the constant and non-constant case evaluation logic is covered
+module top(
+	// expected to output all 1s
+    output reg a, b, c, d, e, f, g, h
+);
+    reg x_1b0 = 1'b0;
+    reg x_1b1 = 1'b1;
+    reg signed x_1sb0 = 1'sb0;
+    reg signed x_1sb1 = 1'sb1;
+    reg [1:0] x_2b0 = 2'b0;
+    reg [1:0] x_2b11 = 2'b11;
+    reg signed [1:0] x_2sb01 = 2'sb01;
+    reg signed [1:0] x_2sb11 = 2'sb11;
+    reg [2:0] x_3b0 = 3'b0;
+
+    initial begin
+        case (x_2b0)
+            x_1b0:   a = 1;
+            default: a = 0;
+        endcase
+        case (x_2sb11)
+            x_2sb01: b = 0;
+            x_1sb1:  b = 1;
+        endcase
+        case (x_2sb11)
+            x_1sb0:  c = 0;
+            x_1sb1:  c = 1;
+        endcase
+        case (x_2sb11)
+            x_1b0:   d = 0;
+            x_1sb1:  d = 0;
+            default: d = 1;
+        endcase
+        case (x_2b11)
+            x_1sb0:  e = 0;
+            x_1sb1:  e = 0;
+            default: e = 1;
+        endcase
+        case (x_1sb1)
+            x_1sb0:  f = 0;
+            x_2sb11: f = 1;
+            default: f = 0;
+        endcase
+        case (x_1sb1)
+            x_1sb0:  g = 0;
+            x_3b0:   g = 0;
+            x_2sb11: g = 0;
+            default: g = 1;
+        endcase
+        case (x_1sb1)
+            x_1sb0:  h = 0;
+            x_1b1:   h = 1;
+            x_3b0:   h = 0;
+            x_2sb11: h = 0;
+            default: h = 0;
+        endcase
+    end
+endmodule
-- 
cgit v1.2.3


From 18806f1ef653f29654533ee47fd8a1b0cf1d645a Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Marcelina=20Ko=C5=9Bcielnicka?= <mwk@0x04.net>
Date: Tue, 25 May 2021 19:31:53 +0200
Subject: memory_bram: Reuse extract_rdff helper for make_outreg.

Also properly skip read ports with init value or reset when not making
use of make_outreg.  Proper support for matching those will land later.
---
 tests/arch/anlogic/lutram.ys   |  9 ++++-----
 tests/arch/ecp5/lutram.ys      |  8 ++++----
 tests/arch/intel_alm/lutram.ys | 10 ++++------
 tests/arch/nexus/lutram.ys     |  4 ++--
 4 files changed, 14 insertions(+), 17 deletions(-)

(limited to 'tests')

diff --git a/tests/arch/anlogic/lutram.ys b/tests/arch/anlogic/lutram.ys
index 9ebb75443..6dbdbdac3 100644
--- a/tests/arch/anlogic/lutram.ys
+++ b/tests/arch/anlogic/lutram.ys
@@ -13,9 +13,8 @@ miter -equiv -flatten -make_assert -make_outputs gold gate miter
 design -load postopt
 cd lutram_1w1r
 
-select -assert-count 8  t:AL_MAP_LUT2
-select -assert-count 8  t:AL_MAP_LUT4
-select -assert-count 8   t:AL_MAP_LUT5
-select -assert-count 36 t:AL_MAP_SEQ
+select -assert-count 4 t:AL_MAP_LUT3
+select -assert-count 8 t:AL_MAP_LUT6
+select -assert-count 8 t:AL_MAP_SEQ
 select -assert-count 8  t:EG_LOGIC_DRAM16X4 #Why not AL_LOGIC_BRAM?
-select -assert-none t:AL_MAP_LUT2 t:AL_MAP_LUT4 t:AL_MAP_LUT5 t:AL_MAP_SEQ t:EG_LOGIC_DRAM16X4 %% t:* %D
+select -assert-none t:AL_MAP_LUT3 t:AL_MAP_LUT6 t:AL_MAP_SEQ t:EG_LOGIC_DRAM16X4 %% t:* %D
diff --git a/tests/arch/ecp5/lutram.ys b/tests/arch/ecp5/lutram.ys
index e1ae7abd5..9bef37c68 100644
--- a/tests/arch/ecp5/lutram.ys
+++ b/tests/arch/ecp5/lutram.ys
@@ -11,9 +11,9 @@ sat -verify -prove-asserts -seq 5 -set-init-zero -show-inputs -show-outputs mite
 
 design -load postopt
 cd lutram_1w1r
-select -assert-count 24 t:L6MUX21
-select -assert-count 71 t:LUT4
-select -assert-count 32 t:PFUMX
+select -assert-count 8 t:L6MUX21
+select -assert-count 36 t:LUT4
+select -assert-count 16 t:PFUMX
 select -assert-count 8 t:TRELLIS_DPR16X4
-select -assert-count 35 t:TRELLIS_FF
+select -assert-count 8 t:TRELLIS_FF
 select -assert-none t:L6MUX21 t:LUT4 t:PFUMX t:TRELLIS_DPR16X4 t:TRELLIS_FF %% t:* %D
diff --git a/tests/arch/intel_alm/lutram.ys b/tests/arch/intel_alm/lutram.ys
index 5d33b8e12..9ddb1ec87 100644
--- a/tests/arch/intel_alm/lutram.ys
+++ b/tests/arch/intel_alm/lutram.ys
@@ -12,11 +12,10 @@ sat -verify -prove-asserts -seq 3 -set-init-zero -show-inputs -show-outputs mite
 design -load postopt
 cd lutram_1w1r
 select -assert-count 16 t:MISTRAL_MLAB
-select -assert-count 1 t:MISTRAL_NOT
 select -assert-count 2 t:MISTRAL_ALUT2
 select -assert-count 8 t:MISTRAL_ALUT3
-select -assert-count 17 t:MISTRAL_FF
-select -assert-none t:MISTRAL_NOT t:MISTRAL_ALUT2 t:MISTRAL_ALUT3 t:MISTRAL_FF t:MISTRAL_MLAB %% t:* %D
+select -assert-count 8 t:MISTRAL_FF
+select -assert-none t:MISTRAL_ALUT2 t:MISTRAL_ALUT3 t:MISTRAL_FF t:MISTRAL_MLAB %% t:* %D
 
 
 design -reset
@@ -34,8 +33,7 @@ sat -verify -prove-asserts -seq 3 -set-init-zero -show-inputs -show-outputs mite
 design -load postopt
 cd lutram_1w1r
 select -assert-count 16 t:MISTRAL_MLAB
-select -assert-count 1 t:MISTRAL_NOT
 select -assert-count 2 t:MISTRAL_ALUT2
 select -assert-count 8 t:MISTRAL_ALUT3
-select -assert-count 17 t:MISTRAL_FF
-select -assert-none t:MISTRAL_NOT t:MISTRAL_ALUT2 t:MISTRAL_ALUT3 t:MISTRAL_FF t:MISTRAL_MLAB %% t:* %D
+select -assert-count 8 t:MISTRAL_FF
+select -assert-none t:MISTRAL_ALUT2 t:MISTRAL_ALUT3 t:MISTRAL_FF t:MISTRAL_MLAB %% t:* %D
diff --git a/tests/arch/nexus/lutram.ys b/tests/arch/nexus/lutram.ys
index cd645f717..6e33431b6 100644
--- a/tests/arch/nexus/lutram.ys
+++ b/tests/arch/nexus/lutram.ys
@@ -13,7 +13,7 @@ design -load postopt
 cd lutram_1w1r
 stat
 select -assert-count 8 t:WIDEFN9
-select -assert-count 16 t:LUT4
+select -assert-count 12 t:LUT4
 select -assert-count 8 t:DPR16X4
-select -assert-count 36 t:FD1P3IX
+select -assert-count 8 t:FD1P3IX
 select -assert-none t:DPR16X4 t:FD1P3IX t:WIDEFN9 t:LUT4 t:INV t:IB t:OB t:VLO t:VHI %% t:* %D
-- 
cgit v1.2.3


From 13b901bf1c5ac7d25ea061fc129d944ea0317150 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Marcelina=20Ko=C5=9Bcielnicka?= <mwk@0x04.net>
Date: Mon, 31 May 2021 15:53:18 +0200
Subject: memory_map: Improve start_offset handling.

Fixes #2775.
---
 tests/opt/memory_map_offset.ys | 100 +++++++++++++++++++++++++++++++++++++++++
 1 file changed, 100 insertions(+)
 create mode 100644 tests/opt/memory_map_offset.ys

(limited to 'tests')

diff --git a/tests/opt/memory_map_offset.ys b/tests/opt/memory_map_offset.ys
new file mode 100644
index 000000000..06969922d
--- /dev/null
+++ b/tests/opt/memory_map_offset.ys
@@ -0,0 +1,100 @@
+read_verilog << EOT
+
+module top(...);
+
+input [3:0] ra;
+input [3:0] wa;
+
+input [15:0] wd;
+output [15:0] rd;
+input en, clk;
+
+reg [15:0] mem[3:9];
+
+always @(posedge clk)
+	if (en)
+		mem[wa] <= wd;
+
+assign rd = mem[ra];
+
+endmodule
+
+EOT
+
+hierarchy -auto-top
+proc
+opt_clean
+memory_map
+
+design -stash gate
+
+read_verilog << EOT
+
+module top(...);
+
+input [3:0] ra;
+input [3:0] wa;
+
+input [15:0] wd;
+output reg [15:0] rd;
+input en, clk;
+
+reg [15:0] \mem[3] ;
+reg [15:0] \mem[4] ;
+reg [15:0] \mem[5] ;
+reg [15:0] \mem[6] ;
+reg [15:0] \mem[7] ;
+reg [15:0] \mem[8] ;
+reg [15:0] \mem[9] ;
+
+always @(posedge clk) begin
+	if (en && wa == 3)
+		\mem[3] <= wd;
+	if (en && wa == 4)
+		\mem[4] <= wd;
+	if (en && wa == 5)
+		\mem[5] <= wd;
+	if (en && wa == 6)
+		\mem[6] <= wd;
+	if (en && wa == 7)
+		\mem[7] <= wd;
+	if (en && wa == 8)
+		\mem[8] <= wd;
+	if (en && wa == 9)
+		\mem[9] <= wd;
+end
+
+always @* begin
+	rd = 16'bx;
+	if (ra == 3)
+		rd = \mem[3] ;
+	if (ra == 4)
+		rd = \mem[4] ;
+	if (ra == 5)
+		rd = \mem[5] ;
+	if (ra == 6)
+		rd = \mem[6] ;
+	if (ra == 7)
+		rd = \mem[7] ;
+	if (ra == 8)
+		rd = \mem[8] ;
+	if (ra == 9)
+		rd = \mem[9] ;
+end
+
+endmodule
+
+EOT
+
+hierarchy -auto-top
+proc
+opt_clean
+
+design -stash gold
+
+design -copy-from gold -as gold A:top
+design -copy-from gate -as gate A:top
+
+equiv_make gold gate equiv
+equiv_induct -undef equiv
+equiv_status -assert equiv
-- 
cgit v1.2.3


From 8cfed1a97957e4c096d1e0a0304d978bcb27e116 Mon Sep 17 00:00:00 2001
From: Zachary Snow <zach@zachjs.com>
Date: Thu, 27 May 2021 16:47:02 -0400
Subject: sv: support tasks and functions within packages

---
 tests/verilog/package_task_func.sv | 30 ++++++++++++++++++++++++++++++
 tests/verilog/package_task_func.ys |  4 ++++
 2 files changed, 34 insertions(+)
 create mode 100644 tests/verilog/package_task_func.sv
 create mode 100644 tests/verilog/package_task_func.ys

(limited to 'tests')

diff --git a/tests/verilog/package_task_func.sv b/tests/verilog/package_task_func.sv
new file mode 100644
index 000000000..2df7a5205
--- /dev/null
+++ b/tests/verilog/package_task_func.sv
@@ -0,0 +1,30 @@
+package P;
+    localparam Y = 2;
+    localparam X = Y + 1;
+    task t;
+        output integer x;
+        x = Y;
+    endtask
+    function automatic integer f;
+        input integer i;
+        f = i * X;
+    endfunction
+    function automatic integer g;
+        input integer i;
+        g = i == 0 ? 1 : Y * g(i - 1);
+    endfunction
+    localparam Z = g(4);
+endpackage
+
+module top;
+    integer a;
+    initial P::t(a);
+    integer b = P::f(3);
+    integer c = P::g(3);
+    integer d = P::Z;
+
+    assert property (a == 2);
+    assert property (b == 9);
+    assert property (c == 8);
+    assert property (d == 16);
+endmodule
diff --git a/tests/verilog/package_task_func.ys b/tests/verilog/package_task_func.ys
new file mode 100644
index 000000000..c94cc2acb
--- /dev/null
+++ b/tests/verilog/package_task_func.ys
@@ -0,0 +1,4 @@
+read_verilog -sv package_task_func.sv
+proc
+opt -full
+sat -verify -seq 1 -prove-asserts -show-all
-- 
cgit v1.2.3


From 72787f52fc31954e4b7dc3dc34d86705fc4e9dd1 Mon Sep 17 00:00:00 2001
From: Claire Xenia Wolf <claire@clairexen.net>
Date: Tue, 8 Jun 2021 00:39:36 +0200
Subject: Fixing old e-mail addresses and deadnames

s/((Claire|Xen|Xenia|Clifford)\s+)+(Wolf|Xen)\s+<(claire|clifford)@(symbioticeda.com|clifford.at|yosyshq.com)>/Claire Xenia Wolf <claire@yosyshq.com>/gi;
s/((Nina|Nak|N\.)\s+)+Engelhardt\s+<nak@(symbioticeda.com|yosyshq.com)>/N. Engelhardt <nak@yosyshq.com>/gi;
s/((David)\s+)+Shah\s+<(dave|david)@(symbioticeda.com|yosyshq.com|ds0.me)>/David Shah <dave@ds0.me>/gi;
s/((Miodrag)\s+)+Milanovic\s+<(miodrag|micko)@(symbioticeda.com|yosyshq.com)>/Miodrag Milanovic <micko@yosyshq.com>/gi;
s,https?://www.clifford.at/yosys/,http://yosyshq.net/yosys/,g;
---
 tests/vloghtb/run-test.sh | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'tests')

diff --git a/tests/vloghtb/run-test.sh b/tests/vloghtb/run-test.sh
index ad99226e7..9e22d1b74 100755
--- a/tests/vloghtb/run-test.sh
+++ b/tests/vloghtb/run-test.sh
@@ -3,7 +3,7 @@
 set -ex
 
 rm -rf Makefile refdat rtl scripts spec
-wget -N http://www.clifford.at/yosys/nogit/vloghammer_tb.tar.bz2
+wget -N http://yosyshq.net/yosys/nogit/vloghammer_tb.tar.bz2
 tar --strip=1 -xjf vloghammer_tb.tar.bz2
 
 make clean
-- 
cgit v1.2.3


From c79fbfe0a130f1a2979413174c3e5688433bafe3 Mon Sep 17 00:00:00 2001
From: Zachary Snow <zach@zachjs.com>
Date: Wed, 26 May 2021 18:22:31 -0400
Subject: mem2reg: tolerate out of bounds constant accesses

This brings the mem2reg behavior in line with the nomem2reg behavior.
---
 tests/simple/mem2reg_bounds_tern.v | 19 +++++++++++++++++++
 tests/verilog/mem_bounds.sv        | 27 +++++++++++++++++++++++++++
 tests/verilog/mem_bounds.ys        |  6 ++++++
 3 files changed, 52 insertions(+)
 create mode 100644 tests/simple/mem2reg_bounds_tern.v
 create mode 100644 tests/verilog/mem_bounds.sv
 create mode 100644 tests/verilog/mem_bounds.ys

(limited to 'tests')

diff --git a/tests/simple/mem2reg_bounds_tern.v b/tests/simple/mem2reg_bounds_tern.v
new file mode 100644
index 000000000..89d6dd3e8
--- /dev/null
+++ b/tests/simple/mem2reg_bounds_tern.v
@@ -0,0 +1,19 @@
+module top(
+    input clk,
+    input wire [1:0] sel,
+    input wire [7:0] base,
+    output reg [7:0] line
+);
+    reg [0:7] mem [0:2];
+
+    generate
+        genvar i;
+        for (i = 0; i < 4; i = i + 1) begin : gen
+            always @(posedge clk)
+                mem[i] <= i == 0 ? base : mem[i - 1] + 1;
+        end
+    endgenerate
+
+    always @(posedge clk)
+        line = mem[sel];
+endmodule
diff --git a/tests/verilog/mem_bounds.sv b/tests/verilog/mem_bounds.sv
new file mode 100644
index 000000000..7fb2fb042
--- /dev/null
+++ b/tests/verilog/mem_bounds.sv
@@ -0,0 +1,27 @@
+module top;
+    reg [0:7] mem [0:2];
+
+    initial mem[1] = '1;
+    wire [31:0] a, b, c, d;
+    assign a = mem[1];
+    assign b = mem[-1];
+    assign c = mem[-1][0];
+    assign d = mem[-1][0:1];
+
+    always @* begin
+
+    	assert ($countbits(a, '0) == 24);
+    	assert ($countbits(a, '1) == 8);
+    	assert ($countbits(a, 'x) == 0);
+
+    	assert ($countbits(b, '0) == 24);
+    	assert ($countbits(b, 'x) == 8);
+
+    	assert ($countbits(c, '0) == 31);
+    	assert ($countbits(c, 'x) == 1);
+
+    	assert ($countbits(d, '0) == 30);
+    	assert ($countbits(d, 'x) == 2);
+
+    end
+endmodule
diff --git a/tests/verilog/mem_bounds.ys b/tests/verilog/mem_bounds.ys
new file mode 100644
index 000000000..42623ad09
--- /dev/null
+++ b/tests/verilog/mem_bounds.ys
@@ -0,0 +1,6 @@
+read_verilog -sv -mem2reg mem_bounds.sv
+proc
+flatten
+opt -full
+select -module top
+sat -verify -seq 1 -tempinduct -prove-asserts -show-all -enable_undef
-- 
cgit v1.2.3


From 2e697f5655455fd8ce5fec40b94683a11ade24e8 Mon Sep 17 00:00:00 2001
From: Zachary Snow <zach@zachjs.com>
Date: Sat, 5 Jun 2021 16:21:09 -0400
Subject: verilog: check for module scope identifiers during width detection

The recent fix for case expression width detection causes the width of
the expressions to be queried before they are simplified. Because the
logic supporting module scope identifiers only existed in simplify,
looking them up would fail during width detection. This moves the logic
to a common helper used in both simplify() and detectSignWidthWorker().
---
 tests/simple/module_scope_case.v | 11 +++++++++++
 1 file changed, 11 insertions(+)
 create mode 100644 tests/simple/module_scope_case.v

(limited to 'tests')

diff --git a/tests/simple/module_scope_case.v b/tests/simple/module_scope_case.v
new file mode 100644
index 000000000..1472b6912
--- /dev/null
+++ b/tests/simple/module_scope_case.v
@@ -0,0 +1,11 @@
+module top(
+	input wire x,
+	output reg y
+);
+	always @* begin
+		case (top.x)
+			1: top.y = 0;
+			0: top.y = 1;
+		endcase
+	end
+endmodule
-- 
cgit v1.2.3


From 92e705cb51d8c8f6d9f1550ed103b677a2447c93 Mon Sep 17 00:00:00 2001
From: Claire Xenia Wolf <claire@clairexen.net>
Date: Wed, 9 Jun 2021 12:16:33 +0200
Subject: Fix files with CRLF line endings

---
 tests/arch/common/counter.v |  22 +++++-----
 tests/arch/common/fsm.v     | 102 ++++++++++++++++++++++----------------------
 tests/arch/common/shifter.v |  22 +++++-----
 3 files changed, 73 insertions(+), 73 deletions(-)

(limited to 'tests')

diff --git a/tests/arch/common/counter.v b/tests/arch/common/counter.v
index 9746fd701..1e0a13dc9 100644
--- a/tests/arch/common/counter.v
+++ b/tests/arch/common/counter.v
@@ -1,11 +1,11 @@
-module top ( out, clk, reset );
-    output [7:0] out;
-    input clk, reset;
-    reg [7:0] out;
-
-    always @(posedge clk, posedge reset)
-      if (reset)
-          out <= 8'b0;
-      else
-          out <= out + 1;
-endmodule
+module top ( out, clk, reset );
+    output [7:0] out;
+    input clk, reset;
+    reg [7:0] out;
+
+    always @(posedge clk, posedge reset)
+      if (reset)
+          out <= 8'b0;
+      else
+          out <= out + 1;
+endmodule
diff --git a/tests/arch/common/fsm.v b/tests/arch/common/fsm.v
index 9d3fbb64a..cf1c21a58 100644
--- a/tests/arch/common/fsm.v
+++ b/tests/arch/common/fsm.v
@@ -1,51 +1,51 @@
- module fsm ( clock, reset, req_0, req_1, gnt_0, gnt_1 );
-    input   clock,reset,req_0,req_1;
-    output  gnt_0,gnt_1;
-    wire    clock,reset,req_0,req_1;
-    reg     gnt_0,gnt_1;
-
-    parameter SIZE = 3;
-    parameter IDLE = 3'b001;
-    parameter GNT0 = 3'b010;
-    parameter GNT1 = 3'b100;
-    parameter GNT2 = 3'b101;
-
-    reg [SIZE-1:0] state;
-    reg [SIZE-1:0] next_state;
-
-    always @ (posedge clock)
-        begin : FSM
-          if (reset == 1'b1) begin
-            state <=  #1  IDLE;
-            gnt_0 <= 0;
-            gnt_1 <= 0;
-          end 
-          else
-            case(state)
-              IDLE :  if (req_0 == 1'b1) begin
-                          state <=  #1  GNT0;
-                          gnt_0 <= 1;
-                      end else if (req_1 == 1'b1) begin
-                          gnt_1 <= 1;
-                          state <=  #1  GNT0;
-                      end else begin
-                          state <=  #1  IDLE;
-                      end
-              GNT0 :  if (req_0 == 1'b1) begin
-                          state <=  #1  GNT0;
-                      end else begin
-                          gnt_0 <= 0;
-                          state <=  #1  IDLE;
-                      end
-              GNT1 :  if (req_1 == 1'b1) begin
-                          state <=  #1  GNT2;
-                          gnt_1 <= req_0;
-                      end
-              GNT2 :  if (req_0 == 1'b1) begin
-                          state <=  #1  GNT1;
-                          gnt_1 <= req_1;
-                      end
-              default : state <=  #1  IDLE;
-            endcase
-        end
-endmodule
+ module fsm ( clock, reset, req_0, req_1, gnt_0, gnt_1 );
+    input   clock,reset,req_0,req_1;
+    output  gnt_0,gnt_1;
+    wire    clock,reset,req_0,req_1;
+    reg     gnt_0,gnt_1;
+
+    parameter SIZE = 3;
+    parameter IDLE = 3'b001;
+    parameter GNT0 = 3'b010;
+    parameter GNT1 = 3'b100;
+    parameter GNT2 = 3'b101;
+
+    reg [SIZE-1:0] state;
+    reg [SIZE-1:0] next_state;
+
+    always @ (posedge clock)
+        begin : FSM
+          if (reset == 1'b1) begin
+            state <=  #1  IDLE;
+            gnt_0 <= 0;
+            gnt_1 <= 0;
+          end 
+          else
+            case(state)
+              IDLE :  if (req_0 == 1'b1) begin
+                          state <=  #1  GNT0;
+                          gnt_0 <= 1;
+                      end else if (req_1 == 1'b1) begin
+                          gnt_1 <= 1;
+                          state <=  #1  GNT0;
+                      end else begin
+                          state <=  #1  IDLE;
+                      end
+              GNT0 :  if (req_0 == 1'b1) begin
+                          state <=  #1  GNT0;
+                      end else begin
+                          gnt_0 <= 0;
+                          state <=  #1  IDLE;
+                      end
+              GNT1 :  if (req_1 == 1'b1) begin
+                          state <=  #1  GNT2;
+                          gnt_1 <= req_0;
+                      end
+              GNT2 :  if (req_0 == 1'b1) begin
+                          state <=  #1  GNT1;
+                          gnt_1 <= req_1;
+                      end
+              default : state <=  #1  IDLE;
+            endcase
+        end
+endmodule
diff --git a/tests/arch/common/shifter.v b/tests/arch/common/shifter.v
index cace3b588..3030608ab 100644
--- a/tests/arch/common/shifter.v
+++ b/tests/arch/common/shifter.v
@@ -1,11 +1,11 @@
-module top(out, clk, in);
-    output [7:0] out;
-    input signed clk, in;
-    reg signed [7:0] out = 0;
-
-    always @(posedge clk)
-	begin
-		out    <= out >> 1;
-		out[7] <= in;
-	end    
-endmodule
+module top(out, clk, in);
+    output [7:0] out;
+    input signed clk, in;
+    reg signed [7:0] out = 0;
+
+    always @(posedge clk)
+	begin
+		out    <= out >> 1;
+		out[7] <= in;
+	end    
+endmodule
-- 
cgit v1.2.3


From 0ada13cbe2f8e3c8568bc7e6731be9edb4c46e47 Mon Sep 17 00:00:00 2001
From: Claire Xenia Wolf <claire@clairexen.net>
Date: Wed, 9 Jun 2021 12:16:56 +0200
Subject: Use HTTPS for website links, gatecat email

git ls-tree -r --name-only HEAD | xargs sed -i -rf ~/fixemails.sed

s/((Claire|Xen|Xenia|Clifford)\s+)+(Wolf|Xen)\s+<(claire|clifford)@(symbioticeda.com|clifford.at|yosyshq.com)>/Claire Xenia Wolf <claire@yosyshq.com>/gi;
s/((Nina|Nak|N\.)\s+)+Engelhardt\s+<nak@(symbioticeda.com|yosyshq.com)>/N. Engelhardt <nak@yosyshq.com>/gi;
s/((David)\s+)+(Shah|gatecat)\s+<(dave|david|gatecat)@(symbioticeda.com|yosyshq.com|ds0.me)>/gatecat <gatecat@ds0.me>/gi;
s/((Miodrag)\s+)+Milanovic\s+<(miodrag|micko)@(symbioticeda.com|yosyshq.com)>/Miodrag Milanovic <micko@yosyshq.com>/gi;
s,https?://www.clifford.at/yosys/|http://yosyshq.net/yosys/,https://yosyshq.net/yosys/,g;
---
 tests/vloghtb/run-test.sh | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'tests')

diff --git a/tests/vloghtb/run-test.sh b/tests/vloghtb/run-test.sh
index 9e22d1b74..3c0689619 100755
--- a/tests/vloghtb/run-test.sh
+++ b/tests/vloghtb/run-test.sh
@@ -3,7 +3,7 @@
 set -ex
 
 rm -rf Makefile refdat rtl scripts spec
-wget -N http://yosyshq.net/yosys/nogit/vloghammer_tb.tar.bz2
+wget -N https://yosyshq.net/yosys/nogit/vloghammer_tb.tar.bz2
 tar --strip=1 -xjf vloghammer_tb.tar.bz2
 
 make clean
-- 
cgit v1.2.3


From a734face3a200a6704342e61466ca85fc0c732b0 Mon Sep 17 00:00:00 2001
From: Claire Xenia Wolf <claire@clairexen.net>
Date: Wed, 9 Jun 2021 12:33:41 +0200
Subject: More deadname stuff

---
 tests/simple/vloghammer.v | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'tests')

diff --git a/tests/simple/vloghammer.v b/tests/simple/vloghammer.v
index 3bb3cf992..5fcedbff1 100644
--- a/tests/simple/vloghammer.v
+++ b/tests/simple/vloghammer.v
@@ -1,6 +1,6 @@
 
 // test cases found using vloghammer
-// https://github.com/cliffordwolf/VlogHammer
+// https://github.com/YosysHQ/VlogHammer
 
 module test01(a, y);
   input [7:0] a;
-- 
cgit v1.2.3


From 0ff4fb1eb35bfba5b7a936401b58deb21776c81a Mon Sep 17 00:00:00 2001
From: Claire Xenia Wolf <claire@clairexen.net>
Date: Wed, 9 Jun 2021 12:40:33 +0200
Subject: More deadname stuff

Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
---
 tests/various/muxpack.v  | 4 ++--
 tests/various/muxpack.ys | 4 ++--
 2 files changed, 4 insertions(+), 4 deletions(-)

(limited to 'tests')

diff --git a/tests/various/muxpack.v b/tests/various/muxpack.v
index 33ece1f16..752f9ba48 100644
--- a/tests/various/muxpack.v
+++ b/tests/various/muxpack.v
@@ -154,7 +154,7 @@ always @*
      o <= i[4*W+:W];
 endmodule
 
-module cliffordwolf_nonexclusive_select (
+module clairexen_nonexclusive_select (
         input wire x, y, z,
         input wire a, b, c, d,
         output reg o
@@ -167,7 +167,7 @@ module cliffordwolf_nonexclusive_select (
         end
 endmodule
 
-module cliffordwolf_freduce (
+module clairexen_freduce (
         input wire [1:0] s,
         input wire a, b, c, d,
         output reg [3:0] o
diff --git a/tests/various/muxpack.ys b/tests/various/muxpack.ys
index 3e90419af..d73fc44b4 100644
--- a/tests/various/muxpack.ys
+++ b/tests/various/muxpack.ys
@@ -167,7 +167,7 @@ miter -equiv -flatten -make_assert -make_outputs gold gate miter
 sat -verify -prove-asserts -show-ports miter
 
 design -load read
-hierarchy -top cliffordwolf_nonexclusive_select
+hierarchy -top clairexen_nonexclusive_select
 prep
 design -save gold
 muxpack
@@ -182,7 +182,7 @@ miter -equiv -flatten -make_assert -make_outputs gold gate miter
 sat -verify -prove-asserts -show-ports miter
 
 #design -load read
-#hierarchy -top cliffordwolf_freduce
+#hierarchy -top clairexen_freduce
 #prep
 #design -save gold
 #proc; opt; freduce; opt
-- 
cgit v1.2.3


From 438bcc68c0859057e4d3f521d1c865d2a9d90e15 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Marcelina=20Ko=C5=9Bcielnicka?= <mwk@0x04.net>
Date: Fri, 11 Jun 2021 12:19:21 +0200
Subject: Add regression test for #2824.

---
 tests/opt/bug2824.ys | 7 +++++++
 1 file changed, 7 insertions(+)
 create mode 100644 tests/opt/bug2824.ys

(limited to 'tests')

diff --git a/tests/opt/bug2824.ys b/tests/opt/bug2824.ys
new file mode 100644
index 000000000..9d0d1e9e5
--- /dev/null
+++ b/tests/opt/bug2824.ys
@@ -0,0 +1,7 @@
+read_verilog -icells << EOT
+module top(input I, output O);
+$pmux #(.WIDTH(1), .S_WIDTH(2)) m (.S({I, 1'b0}), .A(1'b0), .B({I, 1'b0}), .Y(O));
+endmodule
+EOT
+
+equiv_opt -assert opt_muxtree
-- 
cgit v1.2.3


From f2c2d73f36d7aaef90ded549143d1ee0c4d4a9f5 Mon Sep 17 00:00:00 2001
From: Zachary Snow <zach@zachjs.com>
Date: Mon, 14 Jun 2021 15:32:01 -0400
Subject: sv: fix up end label checking

- disallow [gen]blocks with an end label but not begin label
- check validity of module end label
- fix memory leak of package name and end label
- fix memory leak of module end label
---
 tests/simple/matching_end_labels.sv        | 29 +++++++++++++++++++++++++++++
 tests/verilog/block_end_label_only.ys      |  9 +++++++++
 tests/verilog/block_end_label_wrong.ys     |  9 +++++++++
 tests/verilog/gen_block_end_label_only.ys  |  9 +++++++++
 tests/verilog/gen_block_end_label_wrong.ys |  9 +++++++++
 tests/verilog/module_end_label.ys          | 15 +++++++++++++++
 6 files changed, 80 insertions(+)
 create mode 100644 tests/simple/matching_end_labels.sv
 create mode 100644 tests/verilog/block_end_label_only.ys
 create mode 100644 tests/verilog/block_end_label_wrong.ys
 create mode 100644 tests/verilog/gen_block_end_label_only.ys
 create mode 100644 tests/verilog/gen_block_end_label_wrong.ys
 create mode 100644 tests/verilog/module_end_label.ys

(limited to 'tests')

diff --git a/tests/simple/matching_end_labels.sv b/tests/simple/matching_end_labels.sv
new file mode 100644
index 000000000..09182ebcf
--- /dev/null
+++ b/tests/simple/matching_end_labels.sv
@@ -0,0 +1,29 @@
+module top(
+    output reg [7:0]
+    out1, out2, out3, out4
+);
+    initial begin
+        begin : blk1
+            reg x;
+            x = 1;
+        end
+        out1 = blk1.x;
+        begin : blk2
+            reg x;
+            x = 2;
+        end : blk2
+        out2 = blk2.x;
+    end
+    if (1) begin
+        if (1) begin : blk3
+            reg x;
+            assign x = 3;
+        end
+        assign out3 = blk3.x;
+        if (1) begin : blk4
+            reg x;
+            assign x = 4;
+        end : blk4
+        assign out4 = blk4.x;
+    end
+endmodule
diff --git a/tests/verilog/block_end_label_only.ys b/tests/verilog/block_end_label_only.ys
new file mode 100644
index 000000000..5db1c7879
--- /dev/null
+++ b/tests/verilog/block_end_label_only.ys
@@ -0,0 +1,9 @@
+logger -expect error "Begin label missing where end label \(incorrect_name\) was given\." 1
+read_verilog -sv <<EOF
+module top;
+initial
+    begin
+        $display("HI");
+    end : incorrect_name
+endmodule
+EOF
diff --git a/tests/verilog/block_end_label_wrong.ys b/tests/verilog/block_end_label_wrong.ys
new file mode 100644
index 000000000..47dbbe32f
--- /dev/null
+++ b/tests/verilog/block_end_label_wrong.ys
@@ -0,0 +1,9 @@
+logger -expect error "Begin label \(correct_name\) and end label \(incorrect_name\) don't match\." 1
+read_verilog -sv <<EOF
+module top;
+initial
+    begin : correct_name
+        $display("HI");
+    end : incorrect_name
+endmodule
+EOF
diff --git a/tests/verilog/gen_block_end_label_only.ys b/tests/verilog/gen_block_end_label_only.ys
new file mode 100644
index 000000000..60dc0476a
--- /dev/null
+++ b/tests/verilog/gen_block_end_label_only.ys
@@ -0,0 +1,9 @@
+logger -expect error "Begin label missing where end label \(incorrect_name\) was given\." 1
+read_verilog -sv <<EOF
+module top;
+if (1)
+    begin
+        initial $display("HI");
+    end : incorrect_name
+endmodule
+EOF
diff --git a/tests/verilog/gen_block_end_label_wrong.ys b/tests/verilog/gen_block_end_label_wrong.ys
new file mode 100644
index 000000000..43cfc8773
--- /dev/null
+++ b/tests/verilog/gen_block_end_label_wrong.ys
@@ -0,0 +1,9 @@
+logger -expect error "Begin label \(correct_name\) and end label \(incorrect_name\) don't match\." 1
+read_verilog -sv <<EOF
+module top;
+if (1)
+    begin : correct_name
+        initial $display("HI");
+    end : incorrect_name
+endmodule
+EOF
diff --git a/tests/verilog/module_end_label.ys b/tests/verilog/module_end_label.ys
new file mode 100644
index 000000000..c9e5a13a2
--- /dev/null
+++ b/tests/verilog/module_end_label.ys
@@ -0,0 +1,15 @@
+logger -expect-no-warnings
+read_verilog -sv <<EOF
+module correct_name;
+localparam X = 1;
+endmodule : correct_name
+EOF
+
+design -reset
+
+logger -expect error "Module name \(correct_name\) and end label \(incorrect_name\) don't match\." 1
+read_verilog -sv <<EOF
+module correct_name;
+localparam X = 1;
+endmodule : incorrect_name
+EOF
-- 
cgit v1.2.3


From 1aab608cffa19332dc5cf722def7413b16f5ee54 Mon Sep 17 00:00:00 2001
From: Rupert Swarbrick <rswarbrick@gmail.com>
Date: Wed, 14 Jul 2021 17:27:13 +0100
Subject: Add a test for interfaces on modules loaded on-demand

---
 tests/svinterfaces/load_and_derive.sv | 20 ++++++++++++++++++++
 tests/svinterfaces/load_and_derive.ys |  6 ++++++
 tests/svinterfaces/ondemand.sv        |  5 +++++
 tests/svinterfaces/run-test.sh        |  4 ++--
 tests/svinterfaces/run_simple.sh      | 15 +++++++++++++++
 5 files changed, 48 insertions(+), 2 deletions(-)
 create mode 100644 tests/svinterfaces/load_and_derive.sv
 create mode 100644 tests/svinterfaces/load_and_derive.ys
 create mode 100644 tests/svinterfaces/ondemand.sv
 create mode 100755 tests/svinterfaces/run_simple.sh

(limited to 'tests')

diff --git a/tests/svinterfaces/load_and_derive.sv b/tests/svinterfaces/load_and_derive.sv
new file mode 100644
index 000000000..0de0de3b3
--- /dev/null
+++ b/tests/svinterfaces/load_and_derive.sv
@@ -0,0 +1,20 @@
+// This test checks that we correctly elaborate interfaces in modules, even if they are loaded on
+// demand. The "ondemand" module is defined in ondemand.sv in this directory and will be read as
+// part of the hierarchy pass.
+
+interface iface;
+  logic [7:0] x;
+  logic [7:0] y;
+endinterface
+
+module dut (input logic [7:0] x, output logic [7:0] y);
+  iface intf();
+  assign intf.x = x;
+  assign y = intf.y;
+
+  ondemand u(.intf);
+endmodule
+
+module ref (input logic [7:0] x, output logic [7:0] y);
+  assign y = ~x;
+endmodule
diff --git a/tests/svinterfaces/load_and_derive.ys b/tests/svinterfaces/load_and_derive.ys
new file mode 100644
index 000000000..067235ec2
--- /dev/null
+++ b/tests/svinterfaces/load_and_derive.ys
@@ -0,0 +1,6 @@
+read_verilog -sv load_and_derive.sv
+hierarchy -libdir . -check
+flatten
+equiv_make ref dut equiv
+equiv_simple
+equiv_status -assert
diff --git a/tests/svinterfaces/ondemand.sv b/tests/svinterfaces/ondemand.sv
new file mode 100644
index 000000000..70d6048f8
--- /dev/null
+++ b/tests/svinterfaces/ondemand.sv
@@ -0,0 +1,5 @@
+// This is used by the load_and_derive test.
+
+module ondemand (iface intf);
+  assign intf.y = ~intf.x;
+endmodule
diff --git a/tests/svinterfaces/run-test.sh b/tests/svinterfaces/run-test.sh
index 86567d1c1..9ef53926c 100755
--- a/tests/svinterfaces/run-test.sh
+++ b/tests/svinterfaces/run-test.sh
@@ -1,6 +1,6 @@
 #/bin/bash -e
 
-
-
 ./runone.sh  svinterface1
 ./runone.sh  svinterface_at_top
+
+./run_simple.sh load_and_derive
diff --git a/tests/svinterfaces/run_simple.sh b/tests/svinterfaces/run_simple.sh
new file mode 100755
index 000000000..bce994443
--- /dev/null
+++ b/tests/svinterfaces/run_simple.sh
@@ -0,0 +1,15 @@
+#!/bin/bash
+
+# Run a simple test with a .ys file
+
+if [ $# != 1 ]; then
+    echo >&2 "Expected 1 argument"
+    exit 1
+fi
+
+echo -n "Test: $1 ->"
+../../yosys $1.ys >$1.log_stdout 2>$1.log_stderr || {
+    echo "ERROR!"
+    exit 1
+}
+echo "ok"
-- 
cgit v1.2.3


From a9c8ca21d583c58a38931389f90bbaae0caec0d6 Mon Sep 17 00:00:00 2001
From: Zachary Snow <zach@zachjs.com>
Date: Tue, 22 Jun 2021 10:39:57 -0400
Subject: sv: fix two struct access bugs

- preserve signedness of struct members
- fix initial width detection of struct members (e.g., in case expressions)
---
 tests/verilog/struct_access.sv | 88 ++++++++++++++++++++++++++++++++++++++++++
 tests/verilog/struct_access.ys |  4 ++
 2 files changed, 92 insertions(+)
 create mode 100644 tests/verilog/struct_access.sv
 create mode 100644 tests/verilog/struct_access.ys

(limited to 'tests')

diff --git a/tests/verilog/struct_access.sv b/tests/verilog/struct_access.sv
new file mode 100644
index 000000000..f13b8dd51
--- /dev/null
+++ b/tests/verilog/struct_access.sv
@@ -0,0 +1,88 @@
+module top;
+
+    typedef struct packed {
+        logic a;
+        logic signed b;
+        byte c;
+        byte unsigned d;
+        reg [3:0] e;
+        reg signed [3:0] f;
+        struct packed {
+            logic a;
+            logic signed b;
+        } x;
+        struct packed signed {
+            logic a;
+            logic signed b;
+        } y;
+    } S;
+    S s;
+
+    initial begin
+        // test codegen for LHS
+        s.a = '1;
+        s.b = '1;
+        s.c = '1;
+        s.d = '1;
+        s.e = '1;
+        s.f = '1;
+        s.x.a = '1;
+        s.x.b = '1;
+        s.y.a = '1;
+        s.y.b = '1;
+    end
+
+`define CHECK(expr, width, signedness) \
+    case (expr) \
+        1'sb1: \
+            case (expr) \
+                2'sb11: if (!(signedness)) fail = 1; \
+                default: if (signedness) fail = 1; \
+            endcase \
+        default: if (signedness) fail = 1; \
+    endcase \
+    case (expr) \
+        1'b1: if ((width) != 1) fail = 1; \
+        2'b11: if ((width) != 2) fail = 1; \
+        3'b111: if ((width) != 3) fail = 1; \
+        4'b1111: if ((width) != 4) fail = 1; \
+        5'b1111_1: if ((width) != 5) fail = 1; \
+        6'b1111_11: if ((width) != 6) fail = 1; \
+        7'b1111_11: if ((width) != 7) fail = 1; \
+        8'b1111_1111: if ((width) != 8) fail = 1; \
+        9'b1111_1111_1: if ((width) != 9) fail = 1; \
+        default: fail = 1; \
+    endcase \
+    begin \
+        reg [9:0] indirect; \
+        indirect = (expr); \
+        if ((indirect != (expr)) != (signedness)) fail = 1; \
+        indirect = $unsigned(expr); \
+        if ($countones(indirect) != (width)) fail = 1; \
+    end
+
+    initial begin
+        reg fail;
+        fail = 0;
+
+        `CHECK(s.a, 1, 0)
+        `CHECK(s.b, 1, 1)
+        `CHECK(s.c, 8, 1)
+        `CHECK(s.d, 8, 0)
+        `CHECK(s.e, 4, 0)
+        `CHECK(s.f, 4, 1)
+
+        `CHECK(s.x.a, 1, 0)
+        `CHECK(s.x.b, 1, 1)
+        `CHECK(s.y.a, 1, 0)
+        `CHECK(s.y.b, 1, 1)
+
+        // TODO(zachjs): support access to whole sub-structs and unions
+        // `CHECK(s.x, 2, 0)
+        // `CHECK(s.y, 2, 1)
+
+        assert (fail === 0);
+    end
+
+
+endmodule
diff --git a/tests/verilog/struct_access.ys b/tests/verilog/struct_access.ys
new file mode 100644
index 000000000..29d569c01
--- /dev/null
+++ b/tests/verilog/struct_access.ys
@@ -0,0 +1,4 @@
+read_verilog -formal -sv struct_access.sv
+proc
+opt -full
+sat -verify -seq 1 -prove-asserts -show-all
-- 
cgit v1.2.3


From 414154dd275b8cf9f0ffa071d12fc20fd6fee503 Mon Sep 17 00:00:00 2001
From: Rupert Swarbrick <rswarbrick@gmail.com>
Date: Thu, 21 May 2020 17:36:29 +0100
Subject: Add support for parsing the SystemVerilog 'bind' construct

This doesn't do anything useful yet: the patch just adds support for
the syntax to the lexer and parser and adds some tests to check the
syntax parses properly. This generates AST nodes, but doesn't yet
generate RTLIL.

Since our existing hierarchical_identifier parser doesn't allow bit
selects (so you can't do something like foo[1].bar[2].baz), I've also
not added support for a trailing bit select (the "constant_bit_select"
non-terminal in "bind_target_instance" in the spec). If we turn out to
need this in future, we'll want to augment hierarchical_identifier and
its other users too.

Note that you can't easily use the BNF from the spec:

    bind_directive ::=
        "bind" bind_target_scope [ : bind_target_instance_list]
               bind_instantiation ;
      | "bind" bind_target_instance bind_instantiation ;

even if you fix the lookahead problem, because code like this matches
both branches in the BNF:

    bind a b b_i (.*);

The problem is that 'a' could either be a module name or a degenerate
hierarchical reference. This seems to be a genuine syntactic
ambiguity, which the spec resolves (p739) by saying that we have to
wait until resolution time (the hierarchy pass) and take whatever is
defined, treating 'a' as an instance name if it names both an instance
and a module.

To keep the parser simple, it currently accepts this invalid syntax:

    bind a.b : c d e (.*);

This is invalid because we're in the first branch of the BNF above, so
the "a.b" term should match bind_target_scope: a module or interface
identifier, not an arbitrary hierarchical identifier.

This will fail in the hierarchy pass (when it's implemented in a
future patch).
---
 tests/bind/.gitignore   |  2 ++
 tests/bind/basic.sv     | 20 ++++++++++++++++++++
 tests/bind/basic.ys     |  1 +
 tests/bind/cell_list.sv | 26 ++++++++++++++++++++++++++
 tests/bind/cell_list.ys |  1 +
 tests/bind/hier.sv      | 20 ++++++++++++++++++++
 tests/bind/hier.ys      |  1 +
 tests/bind/inst_list.sv | 24 ++++++++++++++++++++++++
 tests/bind/inst_list.ys |  1 +
 tests/bind/param.sv     | 26 ++++++++++++++++++++++++++
 tests/bind/param.ys     |  1 +
 tests/bind/run-test.sh  | 20 ++++++++++++++++++++
 tests/bind/toplevel.sv  | 20 ++++++++++++++++++++
 tests/bind/toplevel.ys  |  1 +
 14 files changed, 164 insertions(+)
 create mode 100644 tests/bind/.gitignore
 create mode 100644 tests/bind/basic.sv
 create mode 100644 tests/bind/basic.ys
 create mode 100644 tests/bind/cell_list.sv
 create mode 100644 tests/bind/cell_list.ys
 create mode 100644 tests/bind/hier.sv
 create mode 100644 tests/bind/hier.ys
 create mode 100644 tests/bind/inst_list.sv
 create mode 100644 tests/bind/inst_list.ys
 create mode 100644 tests/bind/param.sv
 create mode 100644 tests/bind/param.ys
 create mode 100755 tests/bind/run-test.sh
 create mode 100644 tests/bind/toplevel.sv
 create mode 100644 tests/bind/toplevel.ys

(limited to 'tests')

diff --git a/tests/bind/.gitignore b/tests/bind/.gitignore
new file mode 100644
index 000000000..8355de9dc
--- /dev/null
+++ b/tests/bind/.gitignore
@@ -0,0 +1,2 @@
+*.log
+run-test.mk
diff --git a/tests/bind/basic.sv b/tests/bind/basic.sv
new file mode 100644
index 000000000..ce0d04c48
--- /dev/null
+++ b/tests/bind/basic.sv
@@ -0,0 +1,20 @@
+// A basic example of the bind construct
+
+module foo (input logic a, input logic b, output logic c);
+  // Magic happens here...
+endmodule
+
+module bar (input a, input b, output c);
+  assign c = a ^ b;
+endmodule
+
+module top ();
+  logic u, v, w;
+  foo foo_i (.a (u), .b (v), .c (w));
+
+  bind foo bar bound_i (.*);
+
+  always_comb begin
+    assert(w == u ^ v);
+  end
+endmodule
diff --git a/tests/bind/basic.ys b/tests/bind/basic.ys
new file mode 100644
index 000000000..266fa4e48
--- /dev/null
+++ b/tests/bind/basic.ys
@@ -0,0 +1 @@
+read_verilog -sv basic.sv
diff --git a/tests/bind/cell_list.sv b/tests/bind/cell_list.sv
new file mode 100644
index 000000000..c0da13d29
--- /dev/null
+++ b/tests/bind/cell_list.sv
@@ -0,0 +1,26 @@
+// An example of specifying multiple bind instances in a single directive. This
+// also uses explicit bound names.
+
+module foo (input logic a0, input logic b0, output logic c0,
+            input logic a1, input logic b1, output logic c1);
+  // Magic happens here...
+endmodule
+
+module bar (input a, input b, output c);
+  assign c = a ^ b;
+endmodule
+
+module top ();
+  logic u0, v0, w0;
+  logic u1, v1, w1;
+
+  foo foo0 (.a0 (u0), .b0 (v0), .c0 (w0),
+            .a1 (u1), .b1 (v1), .c1 (w1));
+
+  bind foo bar bar0 (.a(a0), .b(b0), .c(c0)), bar1 (.a(a1), .b(b1), .c(c1));
+
+  always_comb begin
+    assert(w0 == u0 ^ v0);
+    assert(w1 == u1 ^ v1);
+  end
+endmodule
diff --git a/tests/bind/cell_list.ys b/tests/bind/cell_list.ys
new file mode 100644
index 000000000..9afd9a941
--- /dev/null
+++ b/tests/bind/cell_list.ys
@@ -0,0 +1 @@
+read_verilog -sv cell_list.sv
diff --git a/tests/bind/hier.sv b/tests/bind/hier.sv
new file mode 100644
index 000000000..fd3bc62b8
--- /dev/null
+++ b/tests/bind/hier.sv
@@ -0,0 +1,20 @@
+// An example of the bind construct using a hierarchical reference starting with $root
+
+module foo (input logic a, input logic b, output logic c);
+  // Magic happens here...
+endmodule
+
+module bar (input a, input b, output c);
+  assign c = a ^ b;
+endmodule
+
+module top ();
+  logic u, v, w;
+  foo foo_i (.a (u), .b (v), .c (w));
+
+  always_comb begin
+    assert(w == u ^ v);
+  end
+endmodule
+
+bind $root.top.foo_i bar bound_i (.*);
diff --git a/tests/bind/hier.ys b/tests/bind/hier.ys
new file mode 100644
index 000000000..c19fba100
--- /dev/null
+++ b/tests/bind/hier.ys
@@ -0,0 +1 @@
+read_verilog -sv hier.sv
diff --git a/tests/bind/inst_list.sv b/tests/bind/inst_list.sv
new file mode 100644
index 000000000..e0077caec
--- /dev/null
+++ b/tests/bind/inst_list.sv
@@ -0,0 +1,24 @@
+// An example of specifying multiple bind targets with an instance list
+
+module foo (input logic a, input logic b, output logic c);
+  // Magic happens here...
+endmodule
+
+module bar (input a, input b, output c);
+  assign c = a ^ b;
+endmodule
+
+module top ();
+  logic u0, v0, w0;
+  logic u1, v1, w1;
+
+  foo foo0 (.a (u0), .b (v0), .c (w0));
+  foo foo1 (.a (u1), .b (v1), .c (w1));
+
+  bind foo : foo0, foo1 bar bound_i (.*);
+
+  always_comb begin
+    assert(w0 == u0 ^ v0);
+    assert(w1 == u1 ^ v1);
+  end
+endmodule
diff --git a/tests/bind/inst_list.ys b/tests/bind/inst_list.ys
new file mode 100644
index 000000000..ac1385b83
--- /dev/null
+++ b/tests/bind/inst_list.ys
@@ -0,0 +1 @@
+read_verilog -sv inst_list.sv
diff --git a/tests/bind/param.sv b/tests/bind/param.sv
new file mode 100644
index 000000000..c7793527a
--- /dev/null
+++ b/tests/bind/param.sv
@@ -0,0 +1,26 @@
+// An example showing how parameters get inferred when binding
+
+module foo (input logic a, input logic b, output logic c);
+  parameter doit = 1;
+
+  // Magic happens here...
+endmodule
+
+module bar (input a, input b, output c);
+  parameter doit = 1;
+
+  assign c = doit ? a ^ b : 0;
+endmodule
+
+module top (input u0, input v0, output w0,
+            input u1, input v1, output w1);
+  foo #(.doit (0)) foo0 (.a (u0), .b (v0), .c (w0));
+  foo #(.doit (1)) foo1 (.a (u1), .b (v1), .c (w1));
+
+  bind foo bar #(.doit (doit)) bound_i (.*);
+
+  always_comb begin
+    assert (w0 == '0);
+    assert (w1 == u1 ^ v1);
+  end
+endmodule
diff --git a/tests/bind/param.ys b/tests/bind/param.ys
new file mode 100644
index 000000000..a43d05759
--- /dev/null
+++ b/tests/bind/param.ys
@@ -0,0 +1 @@
+read_verilog -sv param.sv
diff --git a/tests/bind/run-test.sh b/tests/bind/run-test.sh
new file mode 100755
index 000000000..ea56b70f0
--- /dev/null
+++ b/tests/bind/run-test.sh
@@ -0,0 +1,20 @@
+#!/usr/bin/env bash
+set -e
+{
+echo "all::"
+for x in *.ys; do
+	echo "all:: run-$x"
+	echo "run-$x:"
+	echo "	@echo 'Running $x..'"
+	echo "	@../../yosys -ql ${x%.ys}.log $x"
+done
+for s in *.sh; do
+	if [ "$s" != "run-test.sh" ]; then
+		echo "all:: run-$s"
+		echo "run-$s:"
+		echo "	@echo 'Running $s..'"
+		echo "	@bash $s"
+	fi
+done
+} > run-test.mk
+exec ${MAKE:-make} -f run-test.mk
diff --git a/tests/bind/toplevel.sv b/tests/bind/toplevel.sv
new file mode 100644
index 000000000..328edcf67
--- /dev/null
+++ b/tests/bind/toplevel.sv
@@ -0,0 +1,20 @@
+// The bind construct occurring at top-level in the script
+
+module foo (input logic a, input logic b, output logic c);
+  // Magic happens here...
+endmodule
+
+module bar (input a, input b, output c);
+  assign c = a ^ b;
+endmodule
+
+module top ();
+  logic u, v, w;
+  foo foo_i (.a (u), .b (v), .c (w));
+
+  always_comb begin
+    assert(w == u ^ v);
+  end
+endmodule
+
+bind top.foo_i bar bound_i (.*);
diff --git a/tests/bind/toplevel.ys b/tests/bind/toplevel.ys
new file mode 100644
index 000000000..11c0ada19
--- /dev/null
+++ b/tests/bind/toplevel.ys
@@ -0,0 +1 @@
+read_verilog -sv toplevel.sv
-- 
cgit v1.2.3


From 436d42c00c2bf1b2eaf84ada388d8aaab65da086 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Marcelina=20Ko=C5=9Bcielnicka?= <mwk@0x04.net>
Date: Tue, 27 Jul 2021 15:24:48 +0200
Subject: opt_expr: Propagate constants to port connections.

This adds one simple piece of functionality to opt_expr: when a cell
port is connected to a fully-constant signal (as determined by sigmap),
the port is reconnected directly to the constant value.  This is just
enough optimization to fix the "non-constant $meminit input" problem
without requiring a full opt_clean or a separate pass.
---
 tests/opt/opt_expr_constconn.v  | 8 ++++++++
 tests/opt/opt_expr_constconn.ys | 7 +++++++
 2 files changed, 15 insertions(+)
 create mode 100644 tests/opt/opt_expr_constconn.v
 create mode 100644 tests/opt/opt_expr_constconn.ys

(limited to 'tests')

diff --git a/tests/opt/opt_expr_constconn.v b/tests/opt/opt_expr_constconn.v
new file mode 100644
index 000000000..d18b120e3
--- /dev/null
+++ b/tests/opt/opt_expr_constconn.v
@@ -0,0 +1,8 @@
+module top(...);
+
+input [7:0] A;
+output [7:0] B;
+wire [7:0] C = 3;
+assign B = A + C;
+
+endmodule
diff --git a/tests/opt/opt_expr_constconn.ys b/tests/opt/opt_expr_constconn.ys
new file mode 100644
index 000000000..9dd848a4b
--- /dev/null
+++ b/tests/opt/opt_expr_constconn.ys
@@ -0,0 +1,7 @@
+read_verilog opt_expr_constconn.v
+select -assert-count 1 t:$add
+select -assert-count 1 t:$add %ci w:C %i
+equiv_opt -assert opt_expr
+design -load postopt
+select -assert-count 1 t:$add
+select -assert-count 0 t:$add %ci w:C %i
-- 
cgit v1.2.3


From 8bdc019730c665f678fc1f3bdd8ed96cf2f513d3 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Marcelina=20Ko=C5=9Bcielnicka?= <mwk@0x04.net>
Date: Fri, 21 May 2021 02:27:06 +0200
Subject: verilog: Emit $meminit_v2 cell.

Fixes #2447.
---
 tests/opt/opt_clean_mem.ys | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

(limited to 'tests')

diff --git a/tests/opt/opt_clean_mem.ys b/tests/opt/opt_clean_mem.ys
index d08943da4..5e85df6c8 100644
--- a/tests/opt/opt_clean_mem.ys
+++ b/tests/opt/opt_clean_mem.ys
@@ -25,24 +25,24 @@ proc
 
 select -assert-count 2 t:$memrd
 select -assert-count 1 t:$memwr
-select -assert-count 1 t:$meminit
+select -assert-count 1 t:$meminit_v2
 design -save orig
 
 opt_clean
 select -assert-none t:$memrd
 select -assert-none t:$memwr
-select -assert-none t:$meminit
+select -assert-none t:$meminit_v2
 
 design -load orig
 expose top/rd1
 opt_clean
 select -assert-count 1 t:$memrd
 select -assert-count 1 t:$memwr
-select -assert-count 1 t:$meminit
+select -assert-count 1 t:$meminit_v2
 
 design -load orig
 expose top/rd1 top/rd2
 opt_clean
 select -assert-count 2 t:$memrd
 select -assert-count 1 t:$memwr
-select -assert-count 1 t:$meminit
+select -assert-count 1 t:$meminit_v2
-- 
cgit v1.2.3


From 3156226233133f5da9dba15c63ca560b4794b831 Mon Sep 17 00:00:00 2001
From: Zachary Snow <zach@zachjs.com>
Date: Thu, 15 Jul 2021 10:36:50 -0400
Subject: verilog: save and restore overwritten macro arguments

---
 tests/verilog/macro_arg_tromp.sv | 21 +++++++++++++++++++++
 tests/verilog/macro_arg_tromp.ys |  2 ++
 2 files changed, 23 insertions(+)
 create mode 100644 tests/verilog/macro_arg_tromp.sv
 create mode 100644 tests/verilog/macro_arg_tromp.ys

(limited to 'tests')

diff --git a/tests/verilog/macro_arg_tromp.sv b/tests/verilog/macro_arg_tromp.sv
new file mode 100644
index 000000000..a9c68a417
--- /dev/null
+++ b/tests/verilog/macro_arg_tromp.sv
@@ -0,0 +1,21 @@
+// Taken from: https://github.com/YosysHQ/yosys/issues/2867
+
+`define MIN(x, y) ((x) < (y) ? (x) : (y))
+`define CEIL_DIV(x, y) (((x) / (y)) + `MIN((x) % (y), 1))
+
+module pad_msg1 (input logic [`MIN(512*`CEIL_DIV(64, 512), 64)-1:0] x,
+                output logic [`MIN(512*`CEIL_DIV(64, 512), 64)-1:0] y);
+   assign y[63:0] = x;
+endmodule
+
+module pad_msg2 (input logic [((512*`CEIL_DIV(64, 512)) < (64) ? (512*`CEIL_DIV(64,512)) : (64))-1:0] x,
+                output logic [((512*`CEIL_DIV(64, 512)) < (64) ? (512*`CEIL_DIV(64,512)) : (64))-1:0] y);
+   assign y[63:0] = x;
+endmodule
+
+module top(...);
+`define add(x) x +
+input [3:0] A;
+output [3:0] B;
+assign B = `add(`add(3)A)A;
+endmodule
diff --git a/tests/verilog/macro_arg_tromp.ys b/tests/verilog/macro_arg_tromp.ys
new file mode 100644
index 000000000..e8bd58e9b
--- /dev/null
+++ b/tests/verilog/macro_arg_tromp.ys
@@ -0,0 +1,2 @@
+logger -expect-no-warnings
+read_verilog -sv macro_arg_tromp.sv
-- 
cgit v1.2.3


From 54e75129e57f29df1099f5cd45cec633d80e3841 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Marcelina=20Ko=C5=9Bcielnicka?= <mwk@0x04.net>
Date: Thu, 29 Jul 2021 16:55:15 +0200
Subject: opt_lut: Allow more than one -dlogic per cell type.

Fixes #2061.
---
 tests/arch/ice40/bug2061.ys | 24 ++++++++++++++++++++++++
 1 file changed, 24 insertions(+)
 create mode 100644 tests/arch/ice40/bug2061.ys

(limited to 'tests')

diff --git a/tests/arch/ice40/bug2061.ys b/tests/arch/ice40/bug2061.ys
new file mode 100644
index 000000000..7dd7ee6a3
--- /dev/null
+++ b/tests/arch/ice40/bug2061.ys
@@ -0,0 +1,24 @@
+read_verilog <<EOT
+module top #(
+    parameter integer WIDTH = 12
+)(
+    output reg  [WIDTH:0] cnt,
+    input  wire clk,
+    input  wire rst
+);
+    wire last_n;
+
+    assign last_n = cnt[WIDTH];
+
+    always @(posedge clk or posedge rst)
+        if (rst)
+            cnt <= 0;
+        else
+            cnt <= last_n ? ( cnt + { (WIDTH+1){last_n} } ) : 13'h1aaa;
+
+endmodule
+EOT
+
+synth_ice40
+splitnets
+select -assert-count 12 t:SB_CARRY %co:+[CO] t:SB_LUT4 %ci:+[I3] %i
-- 
cgit v1.2.3


From 4fec3a85cd7d0fcd35f958bfc89090df25f7de3c Mon Sep 17 00:00:00 2001
From: Zachary Snow <zach@zachjs.com>
Date: Thu, 29 Jul 2021 12:35:22 -0400
Subject: genrtlil: add width detection for AST_PREFIX nodes

---
 tests/simple/loop_prefix_case.v | 18 ++++++++++++++++++
 1 file changed, 18 insertions(+)
 create mode 100644 tests/simple/loop_prefix_case.v

(limited to 'tests')

diff --git a/tests/simple/loop_prefix_case.v b/tests/simple/loop_prefix_case.v
new file mode 100644
index 000000000..7ee28ed70
--- /dev/null
+++ b/tests/simple/loop_prefix_case.v
@@ -0,0 +1,18 @@
+module top(
+	input wire x,
+	output reg y
+);
+	localparam I = 1;
+	genvar i;
+	generate
+		for (i = 0; i < 1; i = i + 1) begin : blk
+			wire [i:i] z = x;
+		end
+	endgenerate
+	always @* begin
+		case (blk[I - 1].z)
+			1: y = 0;
+			0: y = 1;
+		endcase
+	end
+endmodule
-- 
cgit v1.2.3


From c016f6a4236fb970196f35c2afb0f2c7c237a77f Mon Sep 17 00:00:00 2001
From: Zachary Snow <zach@zachjs.com>
Date: Wed, 28 Jul 2021 17:34:24 -0400
Subject: proc_rmdead: use explicit pattern set when there are no wildcards

If width of a case expression was large, explicit patterns could cause
the existing logic to take an extremely long time, or exhaust the
maximum size of the underlying set. For cases where all of the patterns
are fully defined and there are no constants in the case expression,
this change uses a simple set to track which patterns have been seen.
---
 tests/proc/rmdead.v       |  46 ++++++++
 tests/proc/rmdead.ys      |   4 +
 tests/simple/case_large.v | 273 ++++++++++++++++++++++++++++++++++++++++++++++
 3 files changed, 323 insertions(+)
 create mode 100644 tests/proc/rmdead.v
 create mode 100644 tests/proc/rmdead.ys
 create mode 100644 tests/simple/case_large.v

(limited to 'tests')

diff --git a/tests/proc/rmdead.v b/tests/proc/rmdead.v
new file mode 100644
index 000000000..2be89e533
--- /dev/null
+++ b/tests/proc/rmdead.v
@@ -0,0 +1,46 @@
+module top (
+    input wire signed x,
+    output reg [31:0] y
+);
+    wire signed fail = ~x;
+
+    always @*
+        case (x)
+            1'b0: y = 0;
+            1'b1: y = 1;
+            default: y = fail;
+        endcase
+
+    always @*
+        case (x)
+            2'sb00: y = 0;
+            2'sb00: y = fail;
+        endcase
+
+    always @*
+        case (x)
+            2'sb00: y = 0;
+            default: y = fail;
+            2'sb01: y = 1;
+            2'sb10: y = 2;
+            2'sb11: y = 3;
+            2'sb00: y = fail;
+            2'sb01: y = fail;
+            2'sb10: y = fail;
+            2'sb11: y = fail;
+        endcase
+
+
+    always @*
+        case ({x, x})
+            2'b00: y = 0;
+            2'b01: y = 1;
+            2'b10: y = 2;
+            2'b11: y = 3;
+            default: y = fail;
+            2'b00: y = fail;
+            2'b01: y = fail;
+            2'b10: y = fail;
+            2'b11: y = fail;
+        endcase
+endmodule
diff --git a/tests/proc/rmdead.ys b/tests/proc/rmdead.ys
new file mode 100644
index 000000000..697d899e3
--- /dev/null
+++ b/tests/proc/rmdead.ys
@@ -0,0 +1,4 @@
+read_verilog rmdead.v
+proc
+opt_clean
+select -assert-count 0 w:fail
diff --git a/tests/simple/case_large.v b/tests/simple/case_large.v
new file mode 100644
index 000000000..a96ce86fe
--- /dev/null
+++ b/tests/simple/case_large.v
@@ -0,0 +1,273 @@
+module top (
+    input wire [127:0] x,
+    output reg [31:0] y
+);
+    localparam A = 32'hDEAD_BEEF;
+    localparam B = 32'h0BAD_0B01;
+    localparam C = 32'hC001_D00D;
+    localparam D = 32'h1234_5678;
+
+    always @*
+        case (x)
+
+            {C,A,D,B}: y = 142;
+            {C,A,D,A}: y = 141;
+            {D,D,A,A}: y = 241;
+            {A,C,C,D}: y = 44;
+            {A,A,A,C}: y = 3;
+            {A,B,A,C}: y = 19;
+            {A,D,C,C}: y = 59;
+            {A,A,C,C}: y = 11;
+            {D,C,B,B}: y = 230;
+            {A,A,D,D}: y = 16;
+            {A,C,A,A}: y = 33;
+            {A,D,D,D}: y = 64;
+            {D,B,C,B}: y = 218;
+            {A,C,B,D}: y = 40;
+            {C,A,B,B}: y = 134;
+            {A,C,C,C}: y = 43;
+            {D,A,D,D}: y = 208;
+            {A,B,C,A}: y = 25;
+            {B,A,B,B}: y = 70;
+            {A,C,B,B}: y = 38;
+            {C,C,C,B}: y = 170;
+            {C,D,A,C}: y = 179;
+            {B,C,D,B}: y = 110;
+            {A,D,A,C}: y = 51;
+            {C,C,B,B}: y = 166;
+            {D,D,D,B}: y = 254;
+            {C,A,D,C}: y = 143;
+            {C,D,D,B}: y = 190;
+            {C,B,A,A}: y = 145;
+            {C,B,A,C}: y = 147;
+            {B,C,C,B}: y = 106;
+            {C,D,C,A}: y = 185;
+            {C,D,B,D}: y = 184;
+            {D,D,D,D}: y = 256;
+            {D,C,C,C}: y = 235;
+            {D,C,D,B}: y = 238;
+            {A,B,D,C}: y = 31;
+            {A,C,A,D}: y = 36;
+            {C,B,C,B}: y = 154;
+            {A,B,A,A}: y = 17;
+            {C,B,B,A}: y = 149;
+            {B,B,D,C}: y = 95;
+            {B,D,C,B}: y = 122;
+            {D,B,A,A}: y = 209;
+            {B,A,B,A}: y = 69;
+            {B,A,D,A}: y = 77;
+            {A,B,B,B}: y = 22;
+            {C,C,C,C}: y = 171;
+            {C,A,C,B}: y = 138;
+            {B,A,D,D}: y = 80;
+            {C,D,D,C}: y = 191;
+            {B,A,A,C}: y = 67;
+            {D,C,D,C}: y = 239;
+            {C,D,D,D}: y = 192;
+            {C,D,B,B}: y = 182;
+            {B,B,A,C}: y = 83;
+            {D,A,A,D}: y = 196;
+            {A,C,C,B}: y = 42;
+            {B,C,A,A}: y = 97;
+            {A,D,B,A}: y = 53;
+            {D,D,B,C}: y = 247;
+            {A,A,C,A}: y = 9;
+            {D,A,C,B}: y = 202;
+            {A,C,B,C}: y = 39;
+            {B,C,B,A}: y = 101;
+            {B,B,B,C}: y = 87;
+            {C,B,A,B}: y = 146;
+            {B,D,A,D}: y = 116;
+            {A,B,D,D}: y = 32;
+            {B,A,B,C}: y = 71;
+            {C,A,A,A}: y = 129;
+            {B,A,D,C}: y = 79;
+            {B,A,C,B}: y = 74;
+            {B,B,D,B}: y = 94;
+            {B,B,C,C}: y = 91;
+            {D,C,C,A}: y = 233;
+            {C,A,B,A}: y = 133;
+            {D,A,B,A}: y = 197;
+            {D,B,B,D}: y = 216;
+            {C,C,A,C}: y = 163;
+            {D,D,B,A}: y = 245;
+            {B,A,D,B}: y = 78;
+            {A,B,C,D}: y = 28;
+            {C,C,C,D}: y = 172;
+            {D,C,A,D}: y = 228;
+            {A,C,D,A}: y = 45;
+            {B,D,C,C}: y = 123;
+            {C,B,A,D}: y = 148;
+            {B,D,B,B}: y = 118;
+            {A,D,A,B}: y = 50;
+            {C,B,B,C}: y = 151;
+            {A,A,A,A}: y = 1;
+            {A,A,B,B}: y = 6;
+            {B,B,B,B}: y = 86;
+            {A,D,A,A}: y = 49;
+            {A,A,A,B}: y = 2;
+            {B,D,D,A}: y = 125;
+            {C,C,D,B}: y = 174;
+            {D,A,D,B}: y = 206;
+            {D,D,B,D}: y = 248;
+            {A,A,A,D}: y = 4;
+            {B,A,A,B}: y = 66;
+            {B,C,C,A}: y = 105;
+            {B,C,C,C}: y = 107;
+            {D,D,D,C}: y = 255;
+            {B,C,D,D}: y = 112;
+            {A,D,B,C}: y = 55;
+            {C,C,C,A}: y = 169;
+            {C,D,B,C}: y = 183;
+            {A,A,B,D}: y = 8;
+            {D,C,B,A}: y = 229;
+            {C,B,D,A}: y = 157;
+            {A,D,D,C}: y = 63;
+            {D,A,D,A}: y = 205;
+            {A,A,B,C}: y = 7;
+            {A,C,A,B}: y = 34;
+            {C,B,D,C}: y = 159;
+            {C,C,D,D}: y = 176;
+            {D,D,D,A}: y = 253;
+            {A,B,B,D}: y = 24;
+            {B,B,C,A}: y = 89;
+            {B,D,C,A}: y = 121;
+            {A,B,C,C}: y = 27;
+            {A,A,D,C}: y = 15;
+            {A,B,B,A}: y = 21;
+            {A,D,A,D}: y = 52;
+            {D,D,C,C}: y = 251;
+            {C,D,A,B}: y = 178;
+            {A,A,D,B}: y = 14;
+            {D,B,D,B}: y = 222;
+            {A,C,C,A}: y = 41;
+            {D,D,A,C}: y = 243;
+            {A,C,D,B}: y = 46;
+            {B,B,B,D}: y = 88;
+            {D,B,B,B}: y = 214;
+            {C,C,B,D}: y = 168;
+            {A,D,D,A}: y = 61;
+            {D,A,C,C}: y = 203;
+            {D,C,A,C}: y = 227;
+            {C,D,C,D}: y = 188;
+            {D,B,D,D}: y = 224;
+            {A,C,D,C}: y = 47;
+            {B,A,B,D}: y = 72;
+            {A,B,B,C}: y = 23;
+            {C,C,D,A}: y = 173;
+            {D,B,C,C}: y = 219;
+            {D,B,C,A}: y = 217;
+            {A,D,C,D}: y = 60;
+            {B,B,D,A}: y = 93;
+            {A,D,C,A}: y = 57;
+            {C,C,A,A}: y = 161;
+            {C,B,B,D}: y = 152;
+            {B,B,B,A}: y = 85;
+            {B,D,A,A}: y = 113;
+            {D,C,D,A}: y = 237;
+            {B,C,B,C}: y = 103;
+            {A,B,C,B}: y = 26;
+            {C,D,A,D}: y = 180;
+            {A,D,B,D}: y = 56;
+            {D,C,A,B}: y = 226;
+            {D,B,B,C}: y = 215;
+            {D,A,B,C}: y = 199;
+            {B,D,A,C}: y = 115;
+            {C,B,C,D}: y = 156;
+            {B,D,D,B}: y = 126;
+            {D,D,C,B}: y = 250;
+            {D,C,C,D}: y = 236;
+            {B,C,B,D}: y = 104;
+            {C,B,C,A}: y = 153;
+            {C,B,B,B}: y = 150;
+            {C,D,C,B}: y = 186;
+            {C,D,C,C}: y = 187;
+            {A,D,B,B}: y = 54;
+            {D,C,C,B}: y = 234;
+            {C,B,D,D}: y = 160;
+            {A,B,A,D}: y = 20;
+            {C,C,B,A}: y = 165;
+            {C,D,D,A}: y = 189;
+            {C,C,D,C}: y = 175;
+            {D,B,D,C}: y = 223;
+            {B,C,A,B}: y = 98;
+            {C,C,A,B}: y = 162;
+            {B,C,D,A}: y = 109;
+            {D,A,B,D}: y = 200;
+            {B,D,C,D}: y = 124;
+            {D,D,C,A}: y = 249;
+            {B,A,C,C}: y = 75;
+            {A,A,C,B}: y = 10;
+            {C,A,B,D}: y = 136;
+            {B,B,C,D}: y = 92;
+            {D,D,C,D}: y = 252;
+            {B,C,A,D}: y = 100;
+            {C,A,C,C}: y = 139;
+            {C,A,C,D}: y = 140;
+            {D,C,A,A}: y = 225;
+            {A,D,C,B}: y = 58;
+            {D,B,C,D}: y = 220;
+            {D,C,B,D}: y = 232;
+            {B,A,C,D}: y = 76;
+            {B,B,D,D}: y = 96;
+            {D,D,B,B}: y = 246;
+            {C,D,A,A}: y = 177;
+            {D,D,A,B}: y = 242;
+            {A,A,D,A}: y = 13;
+            {B,B,A,D}: y = 84;
+            {B,C,D,C}: y = 111;
+            {D,A,A,B}: y = 194;
+            {C,A,B,C}: y = 135;
+            {D,A,A,C}: y = 195;
+            {B,B,A,B}: y = 82;
+            {D,C,D,D}: y = 240;
+            {B,C,C,D}: y = 108;
+            {D,B,A,C}: y = 211;
+            {A,C,D,D}: y = 48;
+            {D,A,A,A}: y = 193;
+            {C,A,A,B}: y = 130;
+            {D,B,A,D}: y = 212;
+            {D,A,B,B}: y = 198;
+            {A,C,B,A}: y = 37;
+            {B,D,B,D}: y = 120;
+            {C,C,B,C}: y = 167;
+            {D,B,A,B}: y = 210;
+            {A,B,A,B}: y = 18;
+            {B,C,B,B}: y = 102;
+            {B,B,A,A}: y = 81;
+            {D,D,A,D}: y = 244;
+            {A,B,D,B}: y = 30;
+            {A,C,A,C}: y = 35;
+            {A,A,C,D}: y = 12;
+            {B,D,B,C}: y = 119;
+            {B,C,A,C}: y = 99;
+            {D,A,C,A}: y = 201;
+            {B,A,A,D}: y = 68;
+            {C,A,A,D}: y = 132;
+            {B,A,C,A}: y = 73;
+            {C,C,A,D}: y = 164;
+            {B,D,B,A}: y = 117;
+            {A,D,D,B}: y = 62;
+            {B,D,D,C}: y = 127;
+            {A,B,D,A}: y = 29;
+            {C,D,B,A}: y = 181;
+            {B,B,C,B}: y = 90;
+            {B,D,A,B}: y = 114;
+            {B,D,D,D}: y = 128;
+            {C,A,C,A}: y = 137;
+            {A,A,B,A}: y = 5;
+            {C,A,D,D}: y = 144;
+            {D,C,B,C}: y = 231;
+            {D,A,C,D}: y = 204;
+            {C,A,A,C}: y = 131;
+            {C,B,D,B}: y = 158;
+            {B,A,A,A}: y = 65;
+            {D,A,D,C}: y = 207;
+            {D,B,B,A}: y = 213;
+            {D,B,D,A}: y = 221;
+            {C,B,C,C}: y = 155;
+
+            default: y = 0;
+
+        endcase
+endmodule
-- 
cgit v1.2.3


From 98003430d672af05cff7d950e08a42526e766f74 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Marcelina=20Ko=C5=9Bcielnicka?= <mwk@0x04.net>
Date: Sun, 8 Aug 2021 00:33:31 +0200
Subject: opt_merge: Use FfInitVals.

Partial #2920 fix.
---
 tests/opt/bug2920.ys        | 42 ++++++++++++++++++++++++++++++++++++++++++
 tests/opt/opt_merge_init.ys |  2 +-
 2 files changed, 43 insertions(+), 1 deletion(-)
 create mode 100644 tests/opt/bug2920.ys

(limited to 'tests')

diff --git a/tests/opt/bug2920.ys b/tests/opt/bug2920.ys
new file mode 100644
index 000000000..a8281a73a
--- /dev/null
+++ b/tests/opt/bug2920.ys
@@ -0,0 +1,42 @@
+read_ilang <<EOT
+
+module \mod
+  wire input 1 \clk
+  attribute \init 2'00
+  wire width 2 $q1
+  attribute \init 2'00
+  wire width 2 $q2
+  wire output 2 width 4 \q
+  cell $dff $ff1
+    parameter \CLK_POLARITY 1'1
+    parameter \WIDTH 1
+    connect \CLK \clk
+    connect \D 1'0
+    connect \Q $q1 [0]
+  end
+  cell $dff $ff2
+    parameter \CLK_POLARITY 1'1
+    parameter \WIDTH 1
+    connect \CLK \clk
+    connect \D 1'0
+    connect \Q $q2 [0]
+  end
+  cell $dff $ff3
+    parameter \CLK_POLARITY 1'1
+    parameter \WIDTH 2
+    connect \CLK \clk
+    connect \D 2'00
+    connect \Q { $q1 [1] $q2 [1] }
+  end
+  connect \q [0] $q1 [0]
+  connect \q [1] $q2 [0]
+  connect \q [2] $q1 [1]
+  connect \q [3] $q2 [1]
+end
+
+EOT
+
+opt_clean
+opt_merge
+opt_dff
+opt_clean
diff --git a/tests/opt/opt_merge_init.ys b/tests/opt/opt_merge_init.ys
index 0176f09c7..20b6cabee 100644
--- a/tests/opt/opt_merge_init.ys
+++ b/tests/opt/opt_merge_init.ys
@@ -48,7 +48,7 @@ EOT
 
 opt_merge
 select -assert-count 1 t:$dff
-select -assert-count 1 a:init=2'bx1
+select -assert-count 1 a:init=2'bx1 a:init=2'b1x
 
 
 design -reset
-- 
cgit v1.2.3


From fd7921776387a05edadcc90d1300670d49a73d68 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Marcelina=20Ko=C5=9Bcielnicka?= <mwk@0x04.net>
Date: Thu, 27 May 2021 20:54:29 +0200
Subject: Add v2 memory cells.

---
 tests/arch/ecp5/memories.ys       | 34 +++++++++++++++++-----------------
 tests/arch/ice40/memories.ys      | 16 ++++++++--------
 tests/memories/run-test.sh        |  2 +-
 tests/opt/bug2765.ys              |  2 +-
 tests/opt/opt_mem_feedback.ys     |  4 ++--
 tests/svtypes/logic_rom.ys        |  2 +-
 tests/svtypes/typedef_memory.ys   |  2 +-
 tests/svtypes/typedef_memory_2.ys |  2 +-
 8 files changed, 32 insertions(+), 32 deletions(-)

(limited to 'tests')

diff --git a/tests/arch/ecp5/memories.ys b/tests/arch/ecp5/memories.ys
index f55bf01d2..03de49cc0 100644
--- a/tests/arch/ecp5/memories.ys
+++ b/tests/arch/ecp5/memories.ys
@@ -50,25 +50,25 @@ design -reset; read_verilog ../common/blockram.v
 chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 36 sync_ram_sdp
 setattr -set syn_romstyle "ebr" m:memory
 synth_ecp5 -top sync_ram_sdp; cd sync_ram_sdp
-select -assert-count 1 t:$mem # requested BROM but this is a RAM
+select -assert-count 1 t:$mem_v2 # requested BROM but this is a RAM
 
 design -reset; read_verilog ../common/blockram.v
 chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 36 sync_ram_sdp
 setattr -set rom_block 1 m:memory
 synth_ecp5 -top sync_ram_sdp; cd sync_ram_sdp
-select -assert-count 1 t:$mem # requested BROM but this is a RAM
+select -assert-count 1 t:$mem_v2 # requested BROM but this is a RAM
 
 design -reset; read_verilog ../common/blockram.v
 chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 36 sync_ram_sdp
 setattr -set syn_ramstyle "block_ram" m:memory
 synth_ecp5 -top sync_ram_sdp -nobram; cd sync_ram_sdp
-select -assert-count 1 t:$mem # requested BRAM but BRAM is disabled
+select -assert-count 1 t:$mem_v2 # requested BRAM but BRAM is disabled
 
 design -reset; read_verilog ../common/blockram.v
 chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 36 sync_ram_sdp
 setattr -set ram_block 1 m:memory
 synth_ecp5 -top sync_ram_sdp -nobram; cd sync_ram_sdp
-select -assert-count 1 t:$mem # requested BRAM but BRAM is disabled
+select -assert-count 1 t:$mem_v2 # requested BRAM but BRAM is disabled
 
 # RAM bits <= 18K; Data width <= 18; Address width <= 10: -> DP16KD
 
@@ -141,25 +141,25 @@ design -reset; read_verilog ../common/blockram.v
 chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 18 sync_ram_sdp
 setattr -set syn_romstyle "ebr" m:memory
 synth_ecp5 -top sync_ram_sdp; cd sync_ram_sdp
-select -assert-count 1 t:$mem # requested BROM but this is a RAM
+select -assert-count 1 t:$mem_v2 # requested BROM but this is a RAM
 
 design -reset; read_verilog ../common/blockram.v
 chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 18 sync_ram_sdp
 setattr -set rom_block 1 m:memory
 synth_ecp5 -top sync_ram_sdp; cd sync_ram_sdp
-select -assert-count 1 t:$mem # requested BROM but this is a RAM
+select -assert-count 1 t:$mem_v2 # requested BROM but this is a RAM
 
 design -reset; read_verilog ../common/blockram.v
 chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 18 sync_ram_sdp
 setattr -set syn_ramstyle "block_ram" m:memory
 synth_ecp5 -top sync_ram_sdp -nobram; cd sync_ram_sdp
-select -assert-count 1 t:$mem # requested BRAM but BRAM is disabled
+select -assert-count 1 t:$mem_v2 # requested BRAM but BRAM is disabled
 
 design -reset; read_verilog ../common/blockram.v
 chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 18 sync_ram_sdp
 setattr -set ram_block 1 m:memory
 synth_ecp5 -top sync_ram_sdp -nobram; cd sync_ram_sdp
-select -assert-count 1 t:$mem # requested BRAM but BRAM is disabled
+select -assert-count 1 t:$mem_v2 # requested BRAM but BRAM is disabled
 
 # RAM bits <= 64; Data width <= 4; Address width <= 4: -> DPR16X4
 
@@ -194,7 +194,7 @@ design -reset; read_verilog ../common/blockram.v
 chparam -set ADDRESS_WIDTH 4 -set DATA_WIDTH 4 sync_ram_sdp
 setattr -set syn_ramstyle "distributed" m:memory
 synth_ecp5 -top sync_ram_sdp -nolutram; cd sync_ram_sdp
-select -assert-count 1 t:$mem # requested LUTRAM but LUTRAM is disabled
+select -assert-count 1 t:$mem_v2 # requested LUTRAM but LUTRAM is disabled
 
 # ================================ ROM ================================
 # ROM bits <= 18K; Data width <= 36; Address width <= 9: -> PDPW16KD
@@ -242,25 +242,25 @@ design -reset; read_verilog ../common/blockrom.v
 chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 36 sync_rom
 setattr -set syn_ramstyle "block_ram" m:memory
 synth_ecp5 -top sync_rom; cd sync_rom
-select -assert-count 1 t:$mem # requested BRAM but this is a ROM
+select -assert-count 1 t:$mem_v2 # requested BRAM but this is a ROM
 
 design -reset; read_verilog ../common/blockrom.v
 chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 36 sync_rom
 setattr -set ram_block 1 m:memory
 synth_ecp5 -top sync_rom; cd sync_rom
-select -assert-count 1 t:$mem # requested BRAM but this is a ROM
+select -assert-count 1 t:$mem_v2 # requested BRAM but this is a ROM
 
 design -reset; read_verilog ../common/blockrom.v
 chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 36 sync_rom
 setattr -set syn_ramstyle "block_rom" m:memory
 synth_ecp5 -top sync_rom -nobram; cd sync_rom
-select -assert-count 1 t:$mem # requested BROM but BRAM is disabled
+select -assert-count 1 t:$mem_v2 # requested BROM but BRAM is disabled
 
 design -reset; read_verilog ../common/blockrom.v
 chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 36 sync_rom
 setattr -set rom_block 1 m:memory
 synth_ecp5 -top sync_rom -nobram; cd sync_rom
-select -assert-count 1 t:$mem # requested BROM but BRAM is disabled
+select -assert-count 1 t:$mem_v2 # requested BROM but BRAM is disabled
 
 # ROM bits <= 18K; Data width <= 18; Address width <= 10: -> DP16KD
 
@@ -307,22 +307,22 @@ design -reset; read_verilog ../common/blockrom.v
 chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 18 sync_rom
 setattr -set syn_ramstyle "block_ram" m:memory
 synth_ecp5 -top sync_rom; cd sync_rom
-select -assert-count 1 t:$mem # requested BRAM but this is a ROM
+select -assert-count 1 t:$mem_v2 # requested BRAM but this is a ROM
 
 design -reset; read_verilog ../common/blockrom.v
 chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 18 sync_rom
 setattr -set ram_block 1 m:memory
 synth_ecp5 -top sync_rom; cd sync_rom
-select -assert-count 1 t:$mem # requested BRAM but this is a ROM
+select -assert-count 1 t:$mem_v2 # requested BRAM but this is a ROM
 
 design -reset; read_verilog ../common/blockrom.v
 chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 18 sync_rom
 setattr -set syn_ramstyle "block_rom" m:memory
 synth_ecp5 -top sync_rom -nobram; cd sync_rom
-select -assert-count 1 t:$mem # requested BROM but BRAM is disabled
+select -assert-count 1 t:$mem_v2 # requested BROM but BRAM is disabled
 
 design -reset; read_verilog ../common/blockrom.v
 chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 18 sync_rom
 setattr -set rom_block 1 m:memory
 synth_ecp5 -top sync_rom -nobram; cd sync_rom
-select -assert-count 1 t:$mem # requested BROM but BRAM is disabled
+select -assert-count 1 t:$mem_v2 # requested BROM but BRAM is disabled
diff --git a/tests/arch/ice40/memories.ys b/tests/arch/ice40/memories.ys
index c32f12315..a0b0f95b2 100644
--- a/tests/arch/ice40/memories.ys
+++ b/tests/arch/ice40/memories.ys
@@ -65,25 +65,25 @@ design -reset; read_verilog ../common/blockram.v
 chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 8 sync_ram_sdp
 setattr -set syn_romstyle "ebr" m:memory
 synth_ice40 -top sync_ram_sdp; cd sync_ram_sdp
-select -assert-count 1 t:$mem # requested BROM but this is a RAM
+select -assert-count 1 t:$mem_v2 # requested BROM but this is a RAM
 
 design -reset; read_verilog ../common/blockram.v
 chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 8 sync_ram_sdp
 setattr -set rom_block 1 m:memory
 synth_ice40 -top sync_ram_sdp; cd sync_ram_sdp
-select -assert-count 1 t:$mem # requested BROM but this is a RAM
+select -assert-count 1 t:$mem_v2 # requested BROM but this is a RAM
 
 design -reset; read_verilog ../common/blockram.v
 chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 8 sync_ram_sdp
 setattr -set syn_ramstyle "block_ram" m:memory
 synth_ice40 -top sync_ram_sdp -nobram; cd sync_ram_sdp
-select -assert-count 1 t:$mem # requested BRAM but BRAM is disabled
+select -assert-count 1 t:$mem_v2 # requested BRAM but BRAM is disabled
 
 design -reset; read_verilog ../common/blockram.v
 chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 8 sync_ram_sdp
 setattr -set ram_block 1 m:memory
 synth_ice40 -top sync_ram_sdp -nobram; cd sync_ram_sdp
-select -assert-count 1 t:$mem # requested BRAM but BRAM is disabled
+select -assert-count 1 t:$mem_v2 # requested BRAM but BRAM is disabled
 
 # ================================ ROM ================================
 # ROM bits <= 4K; Data width <= 16; Address width <= 11: -> SB_RAM40_4K
@@ -146,22 +146,22 @@ design -reset; read_verilog ../common/blockrom.v
 chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 8 sync_rom
 setattr -set syn_ramstyle "block_ram" m:memory
 synth_ice40 -top sync_rom; cd sync_rom
-select -assert-count 1 t:$mem # requested BRAM but this is a ROM
+select -assert-count 1 t:$mem_v2 # requested BRAM but this is a ROM
 
 design -reset; read_verilog ../common/blockrom.v
 chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 8 sync_rom
 setattr -set ram_block 1 m:memory
 synth_ice40 -top sync_rom; cd sync_rom
-select -assert-count 1 t:$mem # requested BRAM but this is a ROM
+select -assert-count 1 t:$mem_v2 # requested BRAM but this is a ROM
 
 design -reset; read_verilog ../common/blockrom.v
 chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 8 sync_rom
 setattr -set syn_romstyle "ebr" m:memory
 synth_ice40 -top sync_rom -nobram; cd sync_rom
-select -assert-count 1 t:$mem # requested BROM but BRAM is disabled
+select -assert-count 1 t:$mem_v2 # requested BROM but BRAM is disabled
 
 design -reset; read_verilog ../common/blockrom.v
 chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 8 sync_rom
 setattr -set rom_block 1 m:memory
 synth_ice40 -top sync_rom -nobram; cd sync_rom
-select -assert-count 1 t:$mem # requested BROM but BRAM is disabled
+select -assert-count 1 t:$mem_v2 # requested BROM but BRAM is disabled
diff --git a/tests/memories/run-test.sh b/tests/memories/run-test.sh
index 376f5bf79..cded3eb40 100755
--- a/tests/memories/run-test.sh
+++ b/tests/memories/run-test.sh
@@ -18,7 +18,7 @@ ${MAKE:-make} -f ../tools/autotest.mk SEED="$seed" EXTRA_FLAGS="$abcopt" *.v
 
 for f in `egrep -l 'expect-(wr-ports|rd-ports|rd-clk)' *.v`; do
 	echo -n "Testing expectations for $f .."
-	../../yosys -qp "proc; opt; memory -nomap;; dump -outfile ${f%.v}.dmp t:\$mem" $f
+	../../yosys -qp "proc; opt; memory -nomap;; dump -outfile ${f%.v}.dmp t:\$mem_v2" $f
 	if grep -q expect-wr-ports $f; then
 		grep -q "parameter \\\\WR_PORTS $(gawk '/expect-wr-ports/ { print $3; }' $f)\$" ${f%.v}.dmp ||
 				{ echo " ERROR: Unexpected number of write ports."; false; }
diff --git a/tests/opt/bug2765.ys b/tests/opt/bug2765.ys
index de670c2d1..fef9abb02 100644
--- a/tests/opt/bug2765.ys
+++ b/tests/opt/bug2765.ys
@@ -31,4 +31,4 @@ proc
 opt
 select -assert-count 2 t:$memwr
 opt_mem
-select -assert-count 1 t:$memwr
+select -assert-count 1 t:$memwr_v2
diff --git a/tests/opt/opt_mem_feedback.ys b/tests/opt/opt_mem_feedback.ys
index 56078ec27..06d6e7e77 100644
--- a/tests/opt/opt_mem_feedback.ys
+++ b/tests/opt/opt_mem_feedback.ys
@@ -37,7 +37,7 @@ design -save preopt
 
 design -load start
 opt_mem_feedback
-select -assert-count 1 t:$memrd
+select -assert-count 1 t:$memrd_v2
 memory_map
 design -save postopt
 
@@ -182,7 +182,7 @@ design -save preopt
 
 design -load start
 opt_mem_feedback
-select -assert-count 1 t:$memrd
+select -assert-count 1 t:$memrd_v2
 memory_map
 design -save postopt
 
diff --git a/tests/svtypes/logic_rom.ys b/tests/svtypes/logic_rom.ys
index 7b079c136..776d2e985 100644
--- a/tests/svtypes/logic_rom.ys
+++ b/tests/svtypes/logic_rom.ys
@@ -1,3 +1,3 @@
 read_verilog -sv logic_rom.sv
 prep -top top
-select -assert-count 1 t:$mem r:SIZE=16 %i r:WIDTH=8 %i
+select -assert-count 1 t:$mem_v2 r:SIZE=16 %i r:WIDTH=8 %i
diff --git a/tests/svtypes/typedef_memory.ys b/tests/svtypes/typedef_memory.ys
index 93cf47bbe..d47ee9929 100644
--- a/tests/svtypes/typedef_memory.ys
+++ b/tests/svtypes/typedef_memory.ys
@@ -1,3 +1,3 @@
 read_verilog -sv typedef_memory.sv
 prep -top top
-select -assert-count 1 t:$mem r:SIZE=16 %i r:WIDTH=4 %i
+select -assert-count 1 t:$mem_v2 r:SIZE=16 %i r:WIDTH=4 %i
diff --git a/tests/svtypes/typedef_memory_2.ys b/tests/svtypes/typedef_memory_2.ys
index 854e554f3..bfebd05fc 100644
--- a/tests/svtypes/typedef_memory_2.ys
+++ b/tests/svtypes/typedef_memory_2.ys
@@ -1,4 +1,4 @@
 read_verilog -sv typedef_memory_2.sv
 prep -top top
 dump
-select -assert-count 1 t:$mem r:SIZE=16 %i r:WIDTH=4 %i
+select -assert-count 1 t:$mem_v2 r:SIZE=16 %i r:WIDTH=4 %i
-- 
cgit v1.2.3


From 24027b5446ffa9d47e00e2ab8bc773fdebc246bd Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Marcelina=20Ko=C5=9Bcielnicka?= <mwk@0x04.net>
Date: Thu, 27 May 2021 20:55:09 +0200
Subject: proc_memwr: Use the v2 memwr cell.

---
 tests/opt/bug2765.ys       | 2 +-
 tests/opt/opt_clean_mem.ys | 8 ++++----
 2 files changed, 5 insertions(+), 5 deletions(-)

(limited to 'tests')

diff --git a/tests/opt/bug2765.ys b/tests/opt/bug2765.ys
index fef9abb02..7cb790bd7 100644
--- a/tests/opt/bug2765.ys
+++ b/tests/opt/bug2765.ys
@@ -29,6 +29,6 @@ EOT
 
 proc
 opt
-select -assert-count 2 t:$memwr
+select -assert-count 2 t:$memwr_v2
 opt_mem
 select -assert-count 1 t:$memwr_v2
diff --git a/tests/opt/opt_clean_mem.ys b/tests/opt/opt_clean_mem.ys
index 5e85df6c8..71f9e0d7b 100644
--- a/tests/opt/opt_clean_mem.ys
+++ b/tests/opt/opt_clean_mem.ys
@@ -24,25 +24,25 @@ EOT
 proc
 
 select -assert-count 2 t:$memrd
-select -assert-count 1 t:$memwr
+select -assert-count 1 t:$memwr_v2
 select -assert-count 1 t:$meminit_v2
 design -save orig
 
 opt_clean
 select -assert-none t:$memrd
-select -assert-none t:$memwr
+select -assert-none t:$memwr_v2
 select -assert-none t:$meminit_v2
 
 design -load orig
 expose top/rd1
 opt_clean
 select -assert-count 1 t:$memrd
-select -assert-count 1 t:$memwr
+select -assert-count 1 t:$memwr_v2
 select -assert-count 1 t:$meminit_v2
 
 design -load orig
 expose top/rd1 top/rd2
 opt_clean
 select -assert-count 2 t:$memrd
-select -assert-count 1 t:$memwr
+select -assert-count 1 t:$memwr_v2
 select -assert-count 1 t:$meminit_v2
-- 
cgit v1.2.3


From 72d86c327e203a097f15e502e6a90f1e6d345d7e Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Marcelina=20Ko=C5=9Bcielnicka?= <mwk@0x04.net>
Date: Thu, 27 May 2021 21:08:11 +0200
Subject: memory_dff: Recognize read ports with reset / initial value.

---
 tests/memories/read_arst.v    | 27 +++++++++++++++++++++++++++
 tests/memories/read_two_mux.v |  5 ++++-
 tests/memories/run-test.sh    | 24 ++++++++++++++++++++++++
 3 files changed, 55 insertions(+), 1 deletion(-)
 create mode 100644 tests/memories/read_arst.v

(limited to 'tests')

diff --git a/tests/memories/read_arst.v b/tests/memories/read_arst.v
new file mode 100644
index 000000000..6100cc4a7
--- /dev/null
+++ b/tests/memories/read_arst.v
@@ -0,0 +1,27 @@
+// expect-wr-ports 1
+// expect-rd-ports 1
+// expect-rd-clk \clk
+// expect-rd-en \re
+// expect-rd-arst-sig \reset
+// expect-rd-arst-val 8'01011010
+// expect-rd-init-val 8'00111100
+
+module top(input clk, input we, re, reset, input [7:0] addr, wdata, output reg [7:0] rdata);
+
+reg [7:0] bram[0:255];
+initial rdata = 8'h3c;
+
+always @(posedge clk) begin
+	if (we)
+		bram[addr] <= wdata;
+end
+
+always @(posedge clk, posedge reset) begin
+	if (reset)
+		rdata <= 8'h5a;
+	else if (re)
+		rdata <= bram[addr];
+end
+
+endmodule
+
diff --git a/tests/memories/read_two_mux.v b/tests/memories/read_two_mux.v
index 4f2e7e1cd..8b609c552 100644
--- a/tests/memories/read_two_mux.v
+++ b/tests/memories/read_two_mux.v
@@ -1,6 +1,9 @@
 // expect-wr-ports 1
 // expect-rd-ports 1
-// expect-no-rd-clk
+// expect-rd-clk \clk
+// expect-rd-en \re
+// expect-rd-srst-sig \reset
+// expect-rd-srst-val 8'00000000
 
 module top(input clk, input we, re, reset, input [7:0] addr, wdata, output reg [7:0] rdata);
 
diff --git a/tests/memories/run-test.sh b/tests/memories/run-test.sh
index cded3eb40..49922e3da 100755
--- a/tests/memories/run-test.sh
+++ b/tests/memories/run-test.sh
@@ -31,6 +31,30 @@ for f in `egrep -l 'expect-(wr-ports|rd-ports|rd-clk)' *.v`; do
 		grep -q "connect \\\\RD_CLK \\$(gawk '/expect-rd-clk/ { print $3; }' $f)\$" ${f%.v}.dmp ||
 				{ echo " ERROR: Unexpected read clock."; false; }
 	fi
+	if grep -q expect-rd-en $f; then
+		grep -q "connect \\\\RD_EN \\$(gawk '/expect-rd-en/ { print $3; }' $f)\$" ${f%.v}.dmp ||
+				{ echo " ERROR: Unexpected read enable."; false; }
+	fi
+	if grep -q expect-rd-srst-sig $f; then
+		grep -q "connect \\\\RD_SRST \\$(gawk '/expect-rd-srst-sig/ { print $3; }' $f)\$" ${f%.v}.dmp ||
+				{ echo " ERROR: Unexpected read sync reset."; false; }
+	fi
+	if grep -q expect-rd-srst-val $f; then
+		grep -q "parameter \\\\RD_SRST_VALUE $(gawk '/expect-rd-srst-val/ { print $3; }' $f)\$" ${f%.v}.dmp ||
+				{ echo " ERROR: Unexpected read sync reset value."; false; }
+	fi
+	if grep -q expect-rd-arst-sig $f; then
+		grep -q "connect \\\\RD_ARST \\$(gawk '/expect-rd-arst-sig/ { print $3; }' $f)\$" ${f%.v}.dmp ||
+				{ echo " ERROR: Unexpected read async reset."; false; }
+	fi
+	if grep -q expect-rd-arst-val $f; then
+		grep -q "parameter \\\\RD_ARST_VALUE $(gawk '/expect-rd-arst-val/ { print $3; }' $f)\$" ${f%.v}.dmp ||
+				{ echo " ERROR: Unexpected read async reset value."; false; }
+	fi
+	if grep -q expect-rd-init-val $f; then
+		grep -q "parameter \\\\RD_INIT_VALUE $(gawk '/expect-rd-init-val/ { print $3; }' $f)\$" ${f%.v}.dmp ||
+				{ echo " ERROR: Unexpected read init value."; false; }
+	fi
 	if grep -q expect-no-rd-clk $f; then
 		grep -q "connect \\\\RD_CLK 1'x\$" ${f%.v}.dmp ||
 				{ echo " ERROR: Expected no read clock."; false; }
-- 
cgit v1.2.3


From b98376884e559330a0de191fadb098eadfe3fe0c Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Marcelina=20Ko=C5=9Bcielnicka?= <mwk@0x04.net>
Date: Wed, 11 Aug 2021 14:14:45 +0200
Subject: test/arch/{ecp5,ice40}/memories.ys: Use read_verilog -defer.

These parts keep rereading a Verilog module, then using chparam
to test it with various parameter combinations.  Since the default
parameters are on the large side, this spends a lot of time
needlessly elaborating the default parametrization that will then
be discarded.  Fix it with -deref and manual hierarchy call.

Shaves 30s off the test time on my machine.
---
 tests/arch/ecp5/memories.ys  | 153 ++++++++++++++++++++++++++++---------------
 tests/arch/ice40/memories.ys |  81 +++++++++++++++--------
 2 files changed, 156 insertions(+), 78 deletions(-)

(limited to 'tests')

diff --git a/tests/arch/ecp5/memories.ys b/tests/arch/ecp5/memories.ys
index 03de49cc0..44651ba25 100644
--- a/tests/arch/ecp5/memories.ys
+++ b/tests/arch/ecp5/memories.ys
@@ -1,197 +1,228 @@
 # ================================ RAM ================================
 # RAM bits <= 18K; Data width <= 36; Address width <= 9: -> PDPW16KD
 
-design -reset; read_verilog ../common/blockram.v
+design -reset; read_verilog -defer ../common/blockram.v
 chparam -set ADDRESS_WIDTH 9 -set DATA_WIDTH 36 sync_ram_sdp
+hierarchy -top sync_ram_sdp
 synth_ecp5 -top sync_ram_sdp; cd sync_ram_sdp
 select -assert-count 1 t:PDPW16KD
 
 ## With parameters
 
-design -reset; read_verilog ../common/blockram.v
+design -reset; read_verilog -defer ../common/blockram.v
 chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 36 sync_ram_sdp
+hierarchy -top sync_ram_sdp
 synth_ecp5 -top sync_ram_sdp; cd sync_ram_sdp
 select -assert-count 0 t:PDPW16KD # too inefficient
 select -assert-count 9 t:TRELLIS_DPR16X4
 
-design -reset; read_verilog ../common/blockram.v
+design -reset; read_verilog -defer ../common/blockram.v
 chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 36 sync_ram_sdp
+hierarchy -top sync_ram_sdp
 setattr -set syn_ramstyle "block_ram" m:memory
 synth_ecp5 -top sync_ram_sdp; cd sync_ram_sdp
 select -assert-count 1 t:PDPW16KD
 
-design -reset; read_verilog ../common/blockram.v
+design -reset; read_verilog -defer ../common/blockram.v
 chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 36 sync_ram_sdp
+hierarchy -top sync_ram_sdp
 setattr -set syn_ramstyle "Block_RAM" m:memory
 synth_ecp5 -top sync_ram_sdp; cd sync_ram_sdp
 select -assert-count 1 t:PDPW16KD # any case works
 
-design -reset; read_verilog ../common/blockram.v
+design -reset; read_verilog -defer ../common/blockram.v
 chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 36 sync_ram_sdp
+hierarchy -top sync_ram_sdp
 setattr -set ram_block 1 m:memory
 synth_ecp5 -top sync_ram_sdp; cd sync_ram_sdp
 select -assert-count 1 t:PDPW16KD
 
-design -reset; read_verilog ../common/blockram.v
+design -reset; read_verilog -defer ../common/blockram.v
 chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 36 sync_ram_sdp
+hierarchy -top sync_ram_sdp
 setattr -set syn_ramstyle "registers" m:memory
 synth_ecp5 -top sync_ram_sdp; cd sync_ram_sdp
 select -assert-count 0 t:PDPW16KD # requested FFRAM explicitly
 select -assert-count 180 t:TRELLIS_FF
 
-design -reset; read_verilog ../common/blockram.v
+design -reset; read_verilog -defer ../common/blockram.v
 chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 36 sync_ram_sdp
+hierarchy -top sync_ram_sdp
 setattr -set logic_block 1 m:memory
 synth_ecp5 -top sync_ram_sdp; cd sync_ram_sdp
 select -assert-count 0 t:PDPW16KD # requested FFRAM explicitly
 select -assert-count 180 t:TRELLIS_FF
 
-design -reset; read_verilog ../common/blockram.v
+design -reset; read_verilog -defer ../common/blockram.v
 chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 36 sync_ram_sdp
+hierarchy -top sync_ram_sdp
 setattr -set syn_romstyle "ebr" m:memory
 synth_ecp5 -top sync_ram_sdp; cd sync_ram_sdp
 select -assert-count 1 t:$mem_v2 # requested BROM but this is a RAM
 
-design -reset; read_verilog ../common/blockram.v
+design -reset; read_verilog -defer ../common/blockram.v
 chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 36 sync_ram_sdp
+hierarchy -top sync_ram_sdp
 setattr -set rom_block 1 m:memory
 synth_ecp5 -top sync_ram_sdp; cd sync_ram_sdp
 select -assert-count 1 t:$mem_v2 # requested BROM but this is a RAM
 
-design -reset; read_verilog ../common/blockram.v
+design -reset; read_verilog -defer ../common/blockram.v
 chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 36 sync_ram_sdp
+hierarchy -top sync_ram_sdp
 setattr -set syn_ramstyle "block_ram" m:memory
 synth_ecp5 -top sync_ram_sdp -nobram; cd sync_ram_sdp
 select -assert-count 1 t:$mem_v2 # requested BRAM but BRAM is disabled
 
-design -reset; read_verilog ../common/blockram.v
+design -reset; read_verilog -defer ../common/blockram.v
 chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 36 sync_ram_sdp
+hierarchy -top sync_ram_sdp
 setattr -set ram_block 1 m:memory
 synth_ecp5 -top sync_ram_sdp -nobram; cd sync_ram_sdp
 select -assert-count 1 t:$mem_v2 # requested BRAM but BRAM is disabled
 
 # RAM bits <= 18K; Data width <= 18; Address width <= 10: -> DP16KD
 
-design -reset; read_verilog ../common/blockram.v
+design -reset; read_verilog -defer ../common/blockram.v
 chparam -set ADDRESS_WIDTH 10 -set DATA_WIDTH 18 sync_ram_sdp
+hierarchy -top sync_ram_sdp
 synth_ecp5 -top sync_ram_sdp; cd sync_ram_sdp
 select -assert-count 1 t:DP16KD
 
-design -reset; read_verilog ../common/blockram.v
+design -reset; read_verilog -defer ../common/blockram.v
 chparam -set ADDRESS_WIDTH 11 -set DATA_WIDTH 9 sync_ram_sdp
+hierarchy -top sync_ram_sdp
 synth_ecp5 -top sync_ram_sdp; cd sync_ram_sdp
 select -assert-count 1 t:DP16KD
 
-design -reset; read_verilog ../common/blockram.v
+design -reset; read_verilog -defer ../common/blockram.v
 chparam -set ADDRESS_WIDTH 12 -set DATA_WIDTH 4 sync_ram_sdp
+hierarchy -top sync_ram_sdp
 synth_ecp5 -top sync_ram_sdp; cd sync_ram_sdp
 select -assert-count 1 t:DP16KD
 
-design -reset; read_verilog ../common/blockram.v
+design -reset; read_verilog -defer ../common/blockram.v
 chparam -set ADDRESS_WIDTH 13 -set DATA_WIDTH 2 sync_ram_sdp
+hierarchy -top sync_ram_sdp
 synth_ecp5 -top sync_ram_sdp; cd sync_ram_sdp
 select -assert-count 1 t:DP16KD
 
-design -reset; read_verilog ../common/blockram.v
+design -reset; read_verilog -defer ../common/blockram.v
 chparam -set ADDRESS_WIDTH 14 -set DATA_WIDTH 1 sync_ram_sdp
+hierarchy -top sync_ram_sdp
 synth_ecp5 -top sync_ram_sdp; cd sync_ram_sdp
 select -assert-count 1 t:DP16KD
 
 ## With parameters
 
-design -reset; read_verilog ../common/blockram.v
+design -reset; read_verilog -defer ../common/blockram.v
 chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 18 sync_ram_sdp
+hierarchy -top sync_ram_sdp
 synth_ecp5 -top sync_ram_sdp; cd sync_ram_sdp
 select -assert-count 0 t:DP16KD # too inefficient
 select -assert-count 5 t:TRELLIS_DPR16X4
 
-design -reset; read_verilog ../common/blockram.v
+design -reset; read_verilog -defer ../common/blockram.v
 chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 18 sync_ram_sdp
+hierarchy -top sync_ram_sdp
 setattr -set syn_ramstyle "block_ram" m:memory
 synth_ecp5 -top sync_ram_sdp; cd sync_ram_sdp
 select -assert-count 1 t:DP16KD
 
-design -reset; read_verilog ../common/blockram.v
+design -reset; read_verilog -defer ../common/blockram.v
 chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 18 sync_ram_sdp
+hierarchy -top sync_ram_sdp
 setattr -set syn_ramstyle "Block_RAM" m:memory
 synth_ecp5 -top sync_ram_sdp; cd sync_ram_sdp
 select -assert-count 1 t:DP16KD # any case works
 
-design -reset; read_verilog ../common/blockram.v
+design -reset; read_verilog -defer ../common/blockram.v
 chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 18 sync_ram_sdp
+hierarchy -top sync_ram_sdp
 setattr -set ram_block 1 m:memory
 synth_ecp5 -top sync_ram_sdp; cd sync_ram_sdp
 select -assert-count 1 t:DP16KD
 
-design -reset; read_verilog ../common/blockram.v
+design -reset; read_verilog -defer ../common/blockram.v
 chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 18 sync_ram_sdp
+hierarchy -top sync_ram_sdp
 setattr -set syn_ramstyle "registers" m:memory
 synth_ecp5 -top sync_ram_sdp; cd sync_ram_sdp
 select -assert-count 0 t:DP16KD # requested FFRAM explicitly
 select -assert-count 90 t:TRELLIS_FF
 
-design -reset; read_verilog ../common/blockram.v
+design -reset; read_verilog -defer ../common/blockram.v
 chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 18 sync_ram_sdp
+hierarchy -top sync_ram_sdp
 setattr -set logic_block 1 m:memory
 synth_ecp5 -top sync_ram_sdp; cd sync_ram_sdp
 select -assert-count 0 t:DP16KD # requested FFRAM explicitly
 select -assert-count 90 t:TRELLIS_FF
 
-design -reset; read_verilog ../common/blockram.v
+design -reset; read_verilog -defer ../common/blockram.v
 chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 18 sync_ram_sdp
+hierarchy -top sync_ram_sdp
 setattr -set syn_romstyle "ebr" m:memory
 synth_ecp5 -top sync_ram_sdp; cd sync_ram_sdp
 select -assert-count 1 t:$mem_v2 # requested BROM but this is a RAM
 
-design -reset; read_verilog ../common/blockram.v
+design -reset; read_verilog -defer ../common/blockram.v
 chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 18 sync_ram_sdp
+hierarchy -top sync_ram_sdp
 setattr -set rom_block 1 m:memory
 synth_ecp5 -top sync_ram_sdp; cd sync_ram_sdp
 select -assert-count 1 t:$mem_v2 # requested BROM but this is a RAM
 
-design -reset; read_verilog ../common/blockram.v
+design -reset; read_verilog -defer ../common/blockram.v
 chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 18 sync_ram_sdp
+hierarchy -top sync_ram_sdp
 setattr -set syn_ramstyle "block_ram" m:memory
 synth_ecp5 -top sync_ram_sdp -nobram; cd sync_ram_sdp
 select -assert-count 1 t:$mem_v2 # requested BRAM but BRAM is disabled
 
-design -reset; read_verilog ../common/blockram.v
+design -reset; read_verilog -defer ../common/blockram.v
 chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 18 sync_ram_sdp
+hierarchy -top sync_ram_sdp
 setattr -set ram_block 1 m:memory
 synth_ecp5 -top sync_ram_sdp -nobram; cd sync_ram_sdp
 select -assert-count 1 t:$mem_v2 # requested BRAM but BRAM is disabled
 
 # RAM bits <= 64; Data width <= 4; Address width <= 4: -> DPR16X4
 
-design -reset; read_verilog ../common/blockram.v
+design -reset; read_verilog -defer ../common/blockram.v
 chparam -set ADDRESS_WIDTH 4 -set DATA_WIDTH 4 sync_ram_sdp
+hierarchy -top sync_ram_sdp
 synth_ecp5 -top sync_ram_sdp; cd sync_ram_sdp
 select -assert-count 1 t:TRELLIS_DPR16X4
 
 ## With parameters
 
-design -reset; read_verilog ../common/blockram.v
+design -reset; read_verilog -defer ../common/blockram.v
 chparam -set ADDRESS_WIDTH 4 -set DATA_WIDTH 4 sync_ram_sdp
+hierarchy -top sync_ram_sdp
 setattr -set syn_ramstyle "distributed" m:memory
 synth_ecp5 -top sync_ram_sdp; cd sync_ram_sdp
 select -assert-count 1 t:TRELLIS_DPR16X4
 
-design -reset; read_verilog ../common/blockram.v
+design -reset; read_verilog -defer ../common/blockram.v
 chparam -set ADDRESS_WIDTH 4 -set DATA_WIDTH 4 sync_ram_sdp
+hierarchy -top sync_ram_sdp
 setattr -set syn_ramstyle "registers" m:memory
 synth_ecp5 -top sync_ram_sdp; cd sync_ram_sdp
 select -assert-count 0 t:TRELLIS_DPR16X4 # requested FFRAM explicitly
 select -assert-count 68 t:TRELLIS_FF
 
-design -reset; read_verilog ../common/blockram.v
+design -reset; read_verilog -defer ../common/blockram.v
 chparam -set ADDRESS_WIDTH 4 -set DATA_WIDTH 4 sync_ram_sdp
+hierarchy -top sync_ram_sdp
 setattr -set logic_block 1 m:memory
 synth_ecp5 -top sync_ram_sdp; cd sync_ram_sdp
 select -assert-count 0 t:TRELLIS_DPR16X4 # requested FFRAM explicitly
 select -assert-count 68 t:TRELLIS_FF
 
-design -reset; read_verilog ../common/blockram.v
+design -reset; read_verilog -defer ../common/blockram.v
 chparam -set ADDRESS_WIDTH 4 -set DATA_WIDTH 4 sync_ram_sdp
+hierarchy -top sync_ram_sdp
 setattr -set syn_ramstyle "distributed" m:memory
 synth_ecp5 -top sync_ram_sdp -nolutram; cd sync_ram_sdp
 select -assert-count 1 t:$mem_v2 # requested LUTRAM but LUTRAM is disabled
@@ -199,130 +230,150 @@ select -assert-count 1 t:$mem_v2 # requested LUTRAM but LUTRAM is disabled
 # ================================ ROM ================================
 # ROM bits <= 18K; Data width <= 36; Address width <= 9: -> PDPW16KD
 
-design -reset; read_verilog ../common/blockrom.v
+design -reset; read_verilog -defer ../common/blockrom.v
 chparam -set ADDRESS_WIDTH 9 -set DATA_WIDTH 36 sync_rom
+hierarchy -top sync_rom
 synth_ecp5 -top sync_rom; cd sync_rom
 select -assert-count 1 t:PDPW16KD
 
 ## With parameters
 
-design -reset; read_verilog ../common/blockrom.v
+design -reset; read_verilog -defer ../common/blockrom.v
 chparam -set ADDRESS_WIDTH 3 -set DATA_WIDTH 36 sync_rom
+hierarchy -top sync_rom
 synth_ecp5 -top sync_rom; cd sync_rom
 select -assert-count 0 t:PDPW16KD # too inefficient
 select -assert-min 18 t:LUT4
 
-design -reset; read_verilog ../common/blockrom.v
+design -reset; read_verilog -defer ../common/blockrom.v
 chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 36 sync_rom
+hierarchy -top sync_rom
 setattr -set syn_romstyle "ebr" m:memory
 synth_ecp5 -top sync_rom; cd sync_rom
 select -assert-count 1 t:PDPW16KD
 
-design -reset; read_verilog ../common/blockrom.v
+design -reset; read_verilog -defer ../common/blockrom.v
 chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 36 sync_rom
+hierarchy -top sync_rom
 setattr -set rom_block 1 m:memory
 synth_ecp5 -top sync_rom; cd sync_rom
 select -assert-count 1 t:PDPW16KD
 
-design -reset; read_verilog ../common/blockrom.v
+design -reset; read_verilog -defer ../common/blockrom.v
 chparam -set ADDRESS_WIDTH 3 -set DATA_WIDTH 36 sync_rom
+hierarchy -top sync_rom
 setattr -set syn_romstyle "logic" m:memory
 synth_ecp5 -top sync_rom; cd sync_rom
 select -assert-count 0 t:PDPW16KD # requested LUTROM explicitly
 select -assert-min 18 t:LUT4
 
-design -reset; read_verilog ../common/blockrom.v
+design -reset; read_verilog -defer ../common/blockrom.v
 chparam -set ADDRESS_WIDTH 3 -set DATA_WIDTH 36 sync_rom
+hierarchy -top sync_rom
 setattr -set logic_block 1 m:memory
 synth_ecp5 -top sync_rom; cd sync_rom
 select -assert-count 0 t:PDPW16KD # requested LUTROM explicitly
 select -assert-min 18 t:LUT4
 
-design -reset; read_verilog ../common/blockrom.v
+design -reset; read_verilog -defer ../common/blockrom.v
 chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 36 sync_rom
+hierarchy -top sync_rom
 setattr -set syn_ramstyle "block_ram" m:memory
 synth_ecp5 -top sync_rom; cd sync_rom
 select -assert-count 1 t:$mem_v2 # requested BRAM but this is a ROM
 
-design -reset; read_verilog ../common/blockrom.v
+design -reset; read_verilog -defer ../common/blockrom.v
 chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 36 sync_rom
+hierarchy -top sync_rom
 setattr -set ram_block 1 m:memory
 synth_ecp5 -top sync_rom; cd sync_rom
 select -assert-count 1 t:$mem_v2 # requested BRAM but this is a ROM
 
-design -reset; read_verilog ../common/blockrom.v
+design -reset; read_verilog -defer ../common/blockrom.v
 chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 36 sync_rom
+hierarchy -top sync_rom
 setattr -set syn_ramstyle "block_rom" m:memory
 synth_ecp5 -top sync_rom -nobram; cd sync_rom
 select -assert-count 1 t:$mem_v2 # requested BROM but BRAM is disabled
 
-design -reset; read_verilog ../common/blockrom.v
+design -reset; read_verilog -defer ../common/blockrom.v
 chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 36 sync_rom
+hierarchy -top sync_rom
 setattr -set rom_block 1 m:memory
 synth_ecp5 -top sync_rom -nobram; cd sync_rom
 select -assert-count 1 t:$mem_v2 # requested BROM but BRAM is disabled
 
 # ROM bits <= 18K; Data width <= 18; Address width <= 10: -> DP16KD
 
-design -reset; read_verilog ../common/blockrom.v
+design -reset; read_verilog -defer ../common/blockrom.v
 chparam -set ADDRESS_WIDTH 10 -set DATA_WIDTH 18 sync_rom
+hierarchy -top sync_rom
 synth_ecp5 -top sync_rom; cd sync_rom
 select -assert-count 1 t:DP16KD
 
 ## With parameters
 
-design -reset; read_verilog ../common/blockrom.v
+design -reset; read_verilog -defer ../common/blockrom.v
 chparam -set ADDRESS_WIDTH 3 -set DATA_WIDTH 18 sync_rom
+hierarchy -top sync_rom
 synth_ecp5 -top sync_rom; cd sync_rom
 select -assert-count 0 t:DP16KD # too inefficient
 select -assert-min 9 t:LUT4
 
-design -reset; read_verilog ../common/blockrom.v
+design -reset; read_verilog -defer ../common/blockrom.v
 chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 18 sync_rom
+hierarchy -top sync_rom
 setattr -set syn_romstyle "ebr" m:memory
 synth_ecp5 -top sync_rom; cd sync_rom
 select -assert-count 1 t:DP16KD
 
-design -reset; read_verilog ../common/blockrom.v
+design -reset; read_verilog -defer ../common/blockrom.v
 chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 18 sync_rom
+hierarchy -top sync_rom
 setattr -set rom_block 1 m:memory
 synth_ecp5 -top sync_rom; cd sync_rom
 select -assert-count 1 t:DP16KD
 
-design -reset; read_verilog ../common/blockrom.v
+design -reset; read_verilog -defer ../common/blockrom.v
 chparam -set ADDRESS_WIDTH 3 -set DATA_WIDTH 18 sync_rom
+hierarchy -top sync_rom
 setattr -set syn_romstyle "logic" m:memory
 synth_ecp5 -top sync_rom; cd sync_rom
 select -assert-count 0 t:DP16KD # requested LUTROM explicitly
 select -assert-min 9 t:LUT4
 
-design -reset; read_verilog ../common/blockrom.v
+design -reset; read_verilog -defer ../common/blockrom.v
 chparam -set ADDRESS_WIDTH 3 -set DATA_WIDTH 18 sync_rom
+hierarchy -top sync_rom
 setattr -set logic_block 1 m:memory
 synth_ecp5 -top sync_rom; cd sync_rom
 select -assert-count 0 t:DP16KD # requested LUTROM explicitly
 select -assert-min 9 t:LUT4
 
-design -reset; read_verilog ../common/blockrom.v
+design -reset; read_verilog -defer ../common/blockrom.v
 chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 18 sync_rom
+hierarchy -top sync_rom
 setattr -set syn_ramstyle "block_ram" m:memory
 synth_ecp5 -top sync_rom; cd sync_rom
 select -assert-count 1 t:$mem_v2 # requested BRAM but this is a ROM
 
-design -reset; read_verilog ../common/blockrom.v
+design -reset; read_verilog -defer ../common/blockrom.v
 chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 18 sync_rom
+hierarchy -top sync_rom
 setattr -set ram_block 1 m:memory
 synth_ecp5 -top sync_rom; cd sync_rom
 select -assert-count 1 t:$mem_v2 # requested BRAM but this is a ROM
 
-design -reset; read_verilog ../common/blockrom.v
+design -reset; read_verilog -defer ../common/blockrom.v
 chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 18 sync_rom
+hierarchy -top sync_rom
 setattr -set syn_ramstyle "block_rom" m:memory
 synth_ecp5 -top sync_rom -nobram; cd sync_rom
 select -assert-count 1 t:$mem_v2 # requested BROM but BRAM is disabled
 
-design -reset; read_verilog ../common/blockrom.v
+design -reset; read_verilog -defer ../common/blockrom.v
 chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 18 sync_rom
+hierarchy -top sync_rom
 setattr -set rom_block 1 m:memory
 synth_ecp5 -top sync_rom -nobram; cd sync_rom
 select -assert-count 1 t:$mem_v2 # requested BROM but BRAM is disabled
diff --git a/tests/arch/ice40/memories.ys b/tests/arch/ice40/memories.ys
index a0b0f95b2..4920a45e3 100644
--- a/tests/arch/ice40/memories.ys
+++ b/tests/arch/ice40/memories.ys
@@ -1,86 +1,100 @@
 # ================================ RAM ================================
 # RAM bits <= 4K; Data width <= 16; Address width <= 11: -> SB_RAM40_4K
 
-design -reset; read_verilog ../common/blockram.v
+design -reset; read_verilog -defer ../common/blockram.v
 chparam -set ADDRESS_WIDTH 11 -set DATA_WIDTH 2 sync_ram_sdp
+hierarchy -top sync_ram_sdp
 synth_ice40 -top sync_ram_sdp; cd sync_ram_sdp
 select -assert-count 1 t:SB_RAM40_4K
 
-design -reset; read_verilog ../common/blockram.v
+design -reset; read_verilog -defer ../common/blockram.v
 chparam -set ADDRESS_WIDTH 10 -set DATA_WIDTH 4 sync_ram_sdp
+hierarchy -top sync_ram_sdp
 synth_ice40 -top sync_ram_sdp; cd sync_ram_sdp
 select -assert-count 1 t:SB_RAM40_4K
 
-design -reset; read_verilog ../common/blockram.v
+design -reset; read_verilog -defer ../common/blockram.v
 chparam -set ADDRESS_WIDTH 9 -set DATA_WIDTH 8 sync_ram_sdp
+hierarchy -top sync_ram_sdp
 synth_ice40 -top sync_ram_sdp; cd sync_ram_sdp
 select -assert-count 1 t:SB_RAM40_4K
 
-design -reset; read_verilog ../common/blockram.v
+design -reset; read_verilog -defer ../common/blockram.v
 chparam -set ADDRESS_WIDTH 8 -set DATA_WIDTH 16 sync_ram_sdp
+hierarchy -top sync_ram_sdp
 synth_ice40 -top sync_ram_sdp; cd sync_ram_sdp
 select -assert-count 1 t:SB_RAM40_4K
 
 ## With parameters
 
-design -reset; read_verilog ../common/blockram.v
+design -reset; read_verilog -defer ../common/blockram.v
 chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 8 sync_ram_sdp
+hierarchy -top sync_ram_sdp
 synth_ice40 -top sync_ram_sdp; cd sync_ram_sdp
 select -assert-count 0 t:SB_RAM40_4K # too inefficient
 select -assert-min 1 t:SB_DFFE
 
-design -reset; read_verilog ../common/blockram.v
+design -reset; read_verilog -defer ../common/blockram.v
 chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 8 sync_ram_sdp
+hierarchy -top sync_ram_sdp
 setattr -set syn_ramstyle "block_ram" m:memory
 synth_ice40 -top sync_ram_sdp; cd sync_ram_sdp
 select -assert-count 1 t:SB_RAM40_4K
 
-design -reset; read_verilog ../common/blockram.v
+design -reset; read_verilog -defer ../common/blockram.v
 chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 8 sync_ram_sdp
+hierarchy -top sync_ram_sdp
 setattr -set syn_ramstyle "Block_RAM" m:memory
 synth_ice40 -top sync_ram_sdp; cd sync_ram_sdp
 select -assert-count 1 t:SB_RAM40_4K # any case works
 
-design -reset; read_verilog ../common/blockram.v
+design -reset; read_verilog -defer ../common/blockram.v
 chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 8 sync_ram_sdp
+hierarchy -top sync_ram_sdp
 setattr -set ram_block 1 m:memory
 synth_ice40 -top sync_ram_sdp; cd sync_ram_sdp
 select -assert-count 1 t:SB_RAM40_4K
 
-design -reset; read_verilog ../common/blockram.v
+design -reset; read_verilog -defer ../common/blockram.v
 chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 8 sync_ram_sdp
+hierarchy -top sync_ram_sdp
 setattr -set syn_ramstyle "registers" m:memory
 synth_ice40 -top sync_ram_sdp; cd sync_ram_sdp
 select -assert-count 0 t:SB_RAM40_4K # requested FFRAM explicitly
 select -assert-min 1 t:SB_DFFE
 
-design -reset; read_verilog ../common/blockram.v
+design -reset; read_verilog -defer ../common/blockram.v
 chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 8 sync_ram_sdp
+hierarchy -top sync_ram_sdp
 setattr -set logic_block 1 m:memory
 synth_ice40 -top sync_ram_sdp; cd sync_ram_sdp
 select -assert-count 0 t:SB_RAM40_4K # requested FFRAM explicitly
 select -assert-min 1 t:SB_DFFE
 
-design -reset; read_verilog ../common/blockram.v
+design -reset; read_verilog -defer ../common/blockram.v
 chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 8 sync_ram_sdp
+hierarchy -top sync_ram_sdp
 setattr -set syn_romstyle "ebr" m:memory
 synth_ice40 -top sync_ram_sdp; cd sync_ram_sdp
 select -assert-count 1 t:$mem_v2 # requested BROM but this is a RAM
 
-design -reset; read_verilog ../common/blockram.v
+design -reset; read_verilog -defer ../common/blockram.v
 chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 8 sync_ram_sdp
+hierarchy -top sync_ram_sdp
 setattr -set rom_block 1 m:memory
 synth_ice40 -top sync_ram_sdp; cd sync_ram_sdp
 select -assert-count 1 t:$mem_v2 # requested BROM but this is a RAM
 
-design -reset; read_verilog ../common/blockram.v
+design -reset; read_verilog -defer ../common/blockram.v
 chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 8 sync_ram_sdp
+hierarchy -top sync_ram_sdp
 setattr -set syn_ramstyle "block_ram" m:memory
 synth_ice40 -top sync_ram_sdp -nobram; cd sync_ram_sdp
 select -assert-count 1 t:$mem_v2 # requested BRAM but BRAM is disabled
 
-design -reset; read_verilog ../common/blockram.v
+design -reset; read_verilog -defer ../common/blockram.v
 chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 8 sync_ram_sdp
+hierarchy -top sync_ram_sdp
 setattr -set ram_block 1 m:memory
 synth_ice40 -top sync_ram_sdp -nobram; cd sync_ram_sdp
 select -assert-count 1 t:$mem_v2 # requested BRAM but BRAM is disabled
@@ -88,80 +102,93 @@ select -assert-count 1 t:$mem_v2 # requested BRAM but BRAM is disabled
 # ================================ ROM ================================
 # ROM bits <= 4K; Data width <= 16; Address width <= 11: -> SB_RAM40_4K
 
-design -reset; read_verilog ../common/blockrom.v
+design -reset; read_verilog -defer ../common/blockrom.v
 chparam -set ADDRESS_WIDTH 11 -set DATA_WIDTH 2 sync_rom
+hierarchy -top sync_rom
 synth_ice40 -top sync_rom; cd sync_rom
 select -assert-count 1 t:SB_RAM40_4K
 
-design -reset; read_verilog ../common/blockrom.v
+design -reset; read_verilog -defer ../common/blockrom.v
 chparam -set ADDRESS_WIDTH 10 -set DATA_WIDTH 4 sync_rom
+hierarchy -top sync_rom
 synth_ice40 -top sync_rom; cd sync_rom
 select -assert-count 1 t:SB_RAM40_4K
 
-design -reset; read_verilog ../common/blockrom.v
+design -reset; read_verilog -defer ../common/blockrom.v
 chparam -set ADDRESS_WIDTH 9 -set DATA_WIDTH 8 sync_rom
+hierarchy -top sync_rom
 synth_ice40 -top sync_rom; cd sync_rom
 select -assert-count 1 t:SB_RAM40_4K
 
-design -reset; read_verilog ../common/blockrom.v
+design -reset; read_verilog -defer ../common/blockrom.v
 chparam -set ADDRESS_WIDTH 8 -set DATA_WIDTH 16 sync_rom
+hierarchy -top sync_rom
 synth_ice40 -top sync_rom; cd sync_rom
 select -assert-count 1 t:SB_RAM40_4K
 
 ## With parameters
 
-design -reset; read_verilog ../common/blockrom.v
+design -reset; read_verilog -defer ../common/blockrom.v
 chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 8 sync_rom
+hierarchy -top sync_rom
 synth_ice40 -top sync_rom; cd sync_rom
 select -assert-count 0 t:SB_RAM40_4K # too inefficient
 select -assert-min 1 t:SB_LUT4
 
-design -reset; read_verilog ../common/blockrom.v
+design -reset; read_verilog -defer ../common/blockrom.v
 chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 8 sync_rom
+hierarchy -top sync_rom
 setattr -set syn_romstyle "ebr" m:memory
 synth_ice40 -top sync_rom; cd sync_rom
 select -assert-count 1 t:SB_RAM40_4K
 
-design -reset; read_verilog ../common/blockrom.v
+design -reset; read_verilog -defer ../common/blockrom.v
 chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 8 sync_rom
+hierarchy -top sync_rom
 setattr -set rom_block 1 m:memory
 synth_ice40 -top sync_rom; cd sync_rom
 select -assert-count 1 t:SB_RAM40_4K
 
-design -reset; read_verilog ../common/blockrom.v
+design -reset; read_verilog -defer ../common/blockrom.v
 chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 8 sync_rom
+hierarchy -top sync_rom
 setattr -set syn_romstyle "logic" m:memory
 synth_ice40 -top sync_rom; cd sync_rom
 select -assert-count 0 t:SB_RAM40_4K # requested LUTROM explicitly
 select -assert-min 1 t:SB_LUT4
 
-design -reset; read_verilog ../common/blockrom.v
+design -reset; read_verilog -defer ../common/blockrom.v
 chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 8 sync_rom
+hierarchy -top sync_rom
 setattr -set logic_block 1 m:memory
 synth_ice40 -top sync_rom; cd sync_rom
 select -assert-count 0 t:SB_RAM40_4K # requested LUTROM explicitly
 select -assert-min 1 t:SB_LUT4
 
-design -reset; read_verilog ../common/blockrom.v
+design -reset; read_verilog -defer ../common/blockrom.v
 chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 8 sync_rom
+hierarchy -top sync_rom
 setattr -set syn_ramstyle "block_ram" m:memory
 synth_ice40 -top sync_rom; cd sync_rom
 select -assert-count 1 t:$mem_v2 # requested BRAM but this is a ROM
 
-design -reset; read_verilog ../common/blockrom.v
+design -reset; read_verilog -defer ../common/blockrom.v
 chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 8 sync_rom
+hierarchy -top sync_rom
 setattr -set ram_block 1 m:memory
 synth_ice40 -top sync_rom; cd sync_rom
 select -assert-count 1 t:$mem_v2 # requested BRAM but this is a ROM
 
-design -reset; read_verilog ../common/blockrom.v
+design -reset; read_verilog -defer ../common/blockrom.v
 chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 8 sync_rom
+hierarchy -top sync_rom
 setattr -set syn_romstyle "ebr" m:memory
 synth_ice40 -top sync_rom -nobram; cd sync_rom
 select -assert-count 1 t:$mem_v2 # requested BROM but BRAM is disabled
 
-design -reset; read_verilog ../common/blockrom.v
+design -reset; read_verilog -defer ../common/blockrom.v
 chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 8 sync_rom
+hierarchy -top sync_rom
 setattr -set rom_block 1 m:memory
 synth_ice40 -top sync_rom -nobram; cd sync_rom
 select -assert-count 1 t:$mem_v2 # requested BROM but BRAM is disabled
-- 
cgit v1.2.3


From 979053855c85b72c6344bf6350fb9a8360f3d092 Mon Sep 17 00:00:00 2001
From: Brett Witherspoon <brett@witherspoondesign.com>
Date: Tue, 22 Jun 2021 09:51:41 -0500
Subject: sv: improve support for wire and var with user-defined types

- User-defined types must be data types. Using a net type (e.g. wire) is
  a syntax error.
- User-defined types without a net type are always variables (i.e.
  logic).
- Nets and variables can now be explicitly declared using user-defined
  types:

    typedef logic [1:0] W;
    wire W w;

    typedef logic [1:0] V;
    var V v;

Fixes #2846
---
 tests/svtypes/typedef_initial_and_assign.sv | 94 +++++++++++++++++++++++++++++
 tests/svtypes/typedef_initial_and_assign.ys | 14 +++++
 2 files changed, 108 insertions(+)
 create mode 100644 tests/svtypes/typedef_initial_and_assign.sv
 create mode 100644 tests/svtypes/typedef_initial_and_assign.ys

(limited to 'tests')

diff --git a/tests/svtypes/typedef_initial_and_assign.sv b/tests/svtypes/typedef_initial_and_assign.sv
new file mode 100644
index 000000000..05579947d
--- /dev/null
+++ b/tests/svtypes/typedef_initial_and_assign.sv
@@ -0,0 +1,94 @@
+package pkg;
+	typedef logic pkg_user_t;
+endpackage
+
+module top;
+	typedef logic user_t;
+
+	// Continuous assignment to a variable is legal
+	user_t var_1;
+	assign var_1 = 0;
+	assert property (var_1 == 0);
+
+	var user_t var_2;
+	assign var_2 = 0;
+	assert property (var_2 == 0);
+
+	var pkg::pkg_user_t var_3;
+	assign var_3 = 0;
+	assert property (var_3 == 0);
+
+	// Procedural assignment to a variable is legal
+	user_t var_4 = 0;
+	assert property (var_4 == 0);
+
+	user_t var_5;
+	initial var_5 = 0;
+	assert property (var_5 == 0);
+
+	var user_t var_6 = 0;
+	assert property (var_6 == 0);
+
+	var user_t var_7;
+	initial var_7 = 0;
+	assert property (var_7 == 0);
+
+	pkg::pkg_user_t var_8 = 0;
+	assert property (var_8 == 0);
+
+	pkg::pkg_user_t var_9;
+	initial var_9 = 0;
+	assert property (var_9 == 0);
+
+	var pkg::pkg_user_t var_10 = 0;
+	assert property (var_10 == 0);
+
+	var pkg::pkg_user_t var_11;
+	initial var_11 = 0;
+	assert property (var_11 == 0);
+
+	// Continuous assignment to a net is legal
+	wire user_t wire_1 = 0;
+	assert property (wire_3 == 0);
+
+	wire user_t wire_2;
+	assign wire_2 = 0;
+	assert property (wire_2 == 0);
+
+	wire pkg::pkg_user_t wire_3 = 0;
+	assert property (wire_3 == 0);
+
+	wire pkg::pkg_user_t wire_4;
+	assign wire_4 = 0;
+	assert property (wire_4 == 0);
+
+	// Mixing continuous and procedural assignments is illegal
+	user_t var_12 = 0;
+	assign var_12 = 1; // warning: reg assigned in a continuous assignment
+
+	user_t var_13;
+	initial var_13 = 0;
+	assign var_13 = 1; // warning: reg assigned in a continuous assignment
+
+	var user_t var_14 = 0;
+	assign var_14 = 1; // warning: reg assigned in a continuous assignment
+
+	var user_t var_15;
+	initial var_15 = 0;
+	assign var_15 = 1; // warning: reg assigned in a continuous assignment
+
+	pkg::pkg_user_t var_16 = 0;
+	assign var_16 = 1; // warning: reg assigned in a continuous assignment
+
+	pkg::pkg_user_t var_17;
+	initial var_17 = 0;
+	assign var_17 = 1; // warning: reg assigned in a continuous assignment
+
+	var pkg::pkg_user_t var_18 = 0;
+	assign var_18 = 1; // warning: reg assigned in a continuous assignment
+
+	var pkg::pkg_user_t var_19;
+	initial var_19 = 0;
+	assign var_19 = 1; // warning: reg assigned in a continuous assignment
+
+endmodule
diff --git a/tests/svtypes/typedef_initial_and_assign.ys b/tests/svtypes/typedef_initial_and_assign.ys
new file mode 100644
index 000000000..de456bb82
--- /dev/null
+++ b/tests/svtypes/typedef_initial_and_assign.ys
@@ -0,0 +1,14 @@
+logger -expect-no-warnings
+logger -expect warning "reg '\\var_12' is assigned in a continuous assignment" 1
+logger -expect warning "reg '\\var_13' is assigned in a continuous assignment" 1
+logger -expect warning "reg '\\var_14' is assigned in a continuous assignment" 1
+logger -expect warning "reg '\\var_15' is assigned in a continuous assignment" 1
+logger -expect warning "reg '\\var_16' is assigned in a continuous assignment" 1
+logger -expect warning "reg '\\var_17' is assigned in a continuous assignment" 1
+logger -expect warning "reg '\\var_18' is assigned in a continuous assignment" 1
+logger -expect warning "reg '\\var_19' is assigned in a continuous assignment" 1
+
+read_verilog -sv typedef_initial_and_assign.sv
+hierarchy; proc; opt
+select -module top
+sat -verify -seq 1 -tempinduct -prove-asserts -show-all
\ No newline at end of file
-- 
cgit v1.2.3


From 616ace2d9299eee2006650ed3f13e9241664ad20 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Marcelina=20Ko=C5=9Bcielnicka?= <mwk@0x04.net>
Date: Thu, 12 Aug 2021 03:31:56 +0200
Subject: Add new opt_mem_priority pass.

---
 tests/opt/opt_mem_priority.ys | 205 ++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 205 insertions(+)
 create mode 100644 tests/opt/opt_mem_priority.ys

(limited to 'tests')

diff --git a/tests/opt/opt_mem_priority.ys b/tests/opt/opt_mem_priority.ys
new file mode 100644
index 000000000..c1261ddf7
--- /dev/null
+++ b/tests/opt/opt_mem_priority.ys
@@ -0,0 +1,205 @@
+# Bad case: independent write ports.
+
+read_verilog << EOT
+
+module top(
+	input [3:0] wa1, wa2, ra, wd1, wd2,
+	input clk, we1, we2,
+	output [3:0] rd);
+
+reg [3:0] mem[0:15];
+assign rd = mem[ra];
+
+always @(posedge clk) begin
+	if (we1)
+		mem[wa1] <= wd1;
+	if (we2)
+		mem[wa2] <= wd2;
+end
+
+endmodule
+
+EOT
+
+hierarchy -auto-top
+proc
+opt
+memory -nomap
+select -assert-count 1 t:$mem_v2
+select -assert-count 1 t:$mem_v2 r:WR_PRIORITY_MASK=4'b0100 %i
+
+
+design -reset
+
+# Good case: write ports with definitely different addresses.
+
+read_verilog << EOT
+
+module top(
+	input [3:0] wa, ra, wd1, wd2,
+	input clk, we1, we2,
+	output [3:0] rd);
+
+reg [3:0] mem[0:15];
+assign rd = mem[ra];
+
+always @(posedge clk) begin
+	if (we1)
+		mem[wa] <= wd1;
+	if (we2)
+		mem[wa ^ 1] <= wd2;
+end
+
+endmodule
+
+EOT
+
+hierarchy -auto-top
+proc
+opt
+memory -nomap
+select -assert-count 1 t:$mem_v2
+select -assert-count 1 t:$mem_v2 r:WR_PRIORITY_MASK=4'b0000 %i
+
+
+design -reset
+
+# Bad case 2: the above, but broken.
+
+read_verilog << EOT
+
+module top(
+	input [3:0] wa, ra, wd1, wd2,
+	input clk, we1, we2,
+	output [3:0] rd);
+
+reg [3:0] mem[0:15];
+assign rd = mem[ra];
+
+always @(posedge clk) begin
+	if (we1)
+		mem[wa] <= wd1;
+	if (we2)
+		mem[wa | 1] <= wd2;
+end
+
+endmodule
+
+EOT
+
+hierarchy -auto-top
+proc
+opt
+memory -nomap
+select -assert-count 1 t:$mem_v2
+select -assert-count 1 t:$mem_v2 r:WR_PRIORITY_MASK=4'b0100 %i
+
+
+design -reset
+
+# Good case 2: write ports with disjoint bit enables.
+
+read_verilog << EOT
+
+module top(
+	input [3:0] wa1, wa2, ra,
+	input [1:0] wd1, wd2,
+	input clk, we1, we2,
+	output [3:0] rd);
+
+reg [3:0] mem[0:15];
+assign rd = mem[ra];
+
+always @(posedge clk) begin
+	if (we1)
+		mem[wa1][1:0] <= wd1;
+	if (we2)
+		mem[wa2][3:2] <= wd2;
+end
+
+endmodule
+
+EOT
+
+hierarchy -auto-top
+proc
+opt
+memory -nomap
+select -assert-count 1 t:$mem_v2
+select -assert-count 1 t:$mem_v2 r:WR_PRIORITY_MASK=4'b0000 %i
+
+
+design -reset
+
+# Good case 3: write ports with soft priority logic already
+
+read_verilog << EOT
+
+module top(
+	input [3:0] wa1, wa2, ra, wd1, wd2,
+	input clk, we1, we2,
+	output [3:0] rd);
+
+reg [3:0] mem[0:15];
+assign rd = mem[ra];
+
+always @(posedge clk) begin
+	if (we1)
+		mem[wa1] <= wd1;
+	if (we2 && wa1 != wa2)
+		mem[wa2] <= wd2;
+end
+
+endmodule
+
+EOT
+
+hierarchy -auto-top
+proc
+opt
+memory -nomap
+select -assert-count 1 t:$mem_v2
+select -assert-count 1 t:$mem_v2 r:WR_PRIORITY_MASK=4'b0000 %i
+
+
+design -reset
+
+# Good case 4: two wide write ports
+
+read_verilog << EOT
+
+module top(
+	input [5:0] wa1, wa2,
+	input [7:0] ra,
+	input [31:0] wd1, wd2,
+	input clk, we1, we2,
+	output [7:0] rd);
+
+reg [7:0] mem[0:255];
+assign rd = mem[ra];
+
+always @(posedge clk) begin
+	if (we1) begin
+		mem[{wa1, 2'b00}] <= wd1[7:0];
+		mem[{wa1, 2'b01}] <= wd1[15:8];
+		mem[{wa1, 2'b10}] <= wd1[23:16];
+		mem[{wa1, 2'b11}] <= wd1[31:24];
+	end
+	if (we2) begin
+		mem[{wa2, 2'b00}] <= wd2[7:0];
+		mem[{wa2, 2'b01}] <= wd2[15:8];
+		mem[{wa2, 2'b10}] <= wd2[23:16];
+		mem[{wa2, 2'b11}] <= wd2[31:24];
+	end
+end
+
+endmodule
+
+EOT
+
+hierarchy -auto-top
+proc
+opt
+memory -nomap
+select -assert-count 1 t:$mem_v2
+select -assert-count 1 t:$mem_v2 r:WR_PRIORITY_MASK=64'h0804020100000000 %i
-- 
cgit v1.2.3


From 9fdedf4d1c5b1715f98ad107d322966eaee91f20 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Marcelina=20Ko=C5=9Bcielnicka?= <mwk@0x04.net>
Date: Tue, 10 Aug 2021 19:42:10 +0200
Subject: memory_dff: Recognize soft transparency logic.

---
 tests/memories/trans_sdp.v    |  21 +
 tests/memories/trans_sp.v     |  21 +
 tests/opt/memory_dff_trans.ys | 862 ++++++++++++++++++++++++++++++++++++++++++
 3 files changed, 904 insertions(+)
 create mode 100644 tests/memories/trans_sdp.v
 create mode 100644 tests/memories/trans_sp.v
 create mode 100644 tests/opt/memory_dff_trans.ys

(limited to 'tests')

diff --git a/tests/memories/trans_sdp.v b/tests/memories/trans_sdp.v
new file mode 100644
index 000000000..b89f2ccf0
--- /dev/null
+++ b/tests/memories/trans_sdp.v
@@ -0,0 +1,21 @@
+// expect-wr-ports 1
+// expect-rd-ports 1
+// expect-rd-clk \clk
+// expect-rd-en \re
+
+module top(input clk, we, re, input [7:0] ra, wa, wd, output reg [7:0] rd);
+
+reg [7:0] mem[0:255];
+
+always @(posedge clk) begin
+	if (we)
+		mem[wa] <= wd;
+
+	if (re) begin
+		rd <= mem[ra];
+		if (we && ra == wa)
+			rd <= wd;
+	end
+end
+
+endmodule
diff --git a/tests/memories/trans_sp.v b/tests/memories/trans_sp.v
new file mode 100644
index 000000000..ddd41a13e
--- /dev/null
+++ b/tests/memories/trans_sp.v
@@ -0,0 +1,21 @@
+// expect-wr-ports 1
+// expect-rd-ports 1
+// expect-rd-clk \clk
+// expect-rd-en \re
+
+module top(input clk, we, re, input [7:0] addr, wd, output reg [7:0] rd);
+
+reg [7:0] mem[0:255];
+
+always @(posedge clk) begin
+	if (we)
+		mem[addr] <= wd;
+
+	if (re) begin
+		rd <= mem[addr];
+		if (we)
+			rd <= wd;
+	end
+end
+
+endmodule
diff --git a/tests/opt/memory_dff_trans.ys b/tests/opt/memory_dff_trans.ys
new file mode 100644
index 000000000..7599949f3
--- /dev/null
+++ b/tests/opt/memory_dff_trans.ys
@@ -0,0 +1,862 @@
+# Good case 1: single port.
+
+read_verilog << EOT
+
+module top(
+	input [3:0] addr,
+	input [3:0] wd,
+	input we,
+	input clk,
+	output reg [3:0] rd,
+);
+
+reg [3:0] mem[0:15];
+
+always @(posedge clk) begin
+	if (we) begin
+		mem[addr] <= wd;
+		rd <= wd;
+	end else begin
+		rd <= mem[addr];
+	end
+end
+
+endmodule
+
+EOT
+
+hierarchy -auto-top
+proc
+opt_dff
+opt_clean
+memory_dff
+memory_collect
+select -assert-count 1 t:$mem_v2
+select -assert-count 1 t:$mem_v2 r:RD_TRANSPARENCY_MASK=1'b1 r:RD_COLLISION_X_MASK=1'b0 %i %i
+
+design -reset
+
+# Good case 2: single port, exclusive.
+
+read_verilog << EOT
+
+module top(
+	input [3:0] addr,
+	input [3:0] wd,
+	input we,
+	input clk,
+	output reg [3:0] rd,
+);
+
+reg [3:0] mem[0:15];
+
+always @(posedge clk) begin
+	if (we) begin
+		mem[addr] <= wd;
+	end else begin
+		rd <= mem[addr];
+	end
+end
+
+endmodule
+
+EOT
+
+hierarchy -auto-top
+proc
+opt_dff
+opt_clean
+memory_dff
+memory_collect
+select -assert-count 1 t:$mem_v2
+select -assert-count 1 t:$mem_v2 r:RD_TRANSPARENCY_MASK=1'b0 r:RD_COLLISION_X_MASK=1'b1 %i %i
+
+design -reset
+
+# Good case 3: proper bypass muxes.
+
+read_verilog << EOT
+
+module top(
+	input [3:0] ra,
+	input [3:0] wa1,
+	input [3:0] wa2,
+	input [3:0] wd1,
+	input [3:0] wd2,
+	input we1, we2,
+	input re,
+	input clk,
+	output reg [3:0] rd,
+);
+
+reg [3:0] mem[0:15];
+
+always @(posedge clk) begin
+	if (we1)
+		mem[wa1] <= wd1;
+	if (we2)
+		mem[wa2] <= wd2;
+	if (re) begin
+		rd <= mem[ra];
+		if (we1 && wa1 == ra)
+			rd <= wd1;
+		if (we2 && wa2 == ra)
+			rd <= wd2;
+	end
+end
+
+endmodule
+
+EOT
+
+hierarchy -auto-top
+proc
+opt_dff
+opt_clean
+memory_dff
+memory_collect
+select -assert-count 1 t:$mem_v2
+select -assert-count 1 t:$mem_v2 r:RD_TRANSPARENCY_MASK=2'b11 r:RD_COLLISION_X_MASK=2'b00 %i %i
+
+design -reset
+
+# Good case 4: proper bypass mux, but only one.
+
+read_verilog << EOT
+
+module top(
+	input [3:0] ra,
+	input [3:0] wa1,
+	input [3:0] wa2,
+	input [3:0] wd1,
+	input [3:0] wd2,
+	input we1, we2,
+	input re,
+	input clk,
+	output reg [3:0] rd,
+);
+
+reg [3:0] mem[0:15];
+
+always @(posedge clk) begin
+	if (we1)
+		mem[wa1] <= wd1;
+	if (we2)
+		mem[wa2] <= wd2;
+	if (re) begin
+		rd <= mem[ra];
+		if (we1 && wa1 == ra)
+			rd <= wd1;
+	end
+end
+
+endmodule
+
+EOT
+
+hierarchy -auto-top
+proc
+opt_dff
+opt_clean
+memory_dff
+memory_collect
+select -assert-count 1 t:$mem_v2
+select -assert-count 1 t:$mem_v2 r:RD_TRANSPARENCY_MASK=2'b01 r:RD_COLLISION_X_MASK=2'b00 %i %i
+
+design -reset
+
+# Good case 5: proper bypass mux, but the other one.
+
+read_verilog << EOT
+
+module top(
+	input [3:0] ra,
+	input [3:0] wa1,
+	input [3:0] wa2,
+	input [3:0] wd1,
+	input [3:0] wd2,
+	input we1, we2,
+	input re,
+	input clk,
+	output reg [3:0] rd,
+);
+
+reg [3:0] mem[0:15];
+
+always @(posedge clk) begin
+	if (we1)
+		mem[wa1] <= wd1;
+	if (we2)
+		mem[wa2] <= wd2;
+	if (re) begin
+		rd <= mem[ra];
+		if (we2 && wa2 == ra)
+			rd <= wd2;
+	end
+end
+
+endmodule
+
+EOT
+
+hierarchy -auto-top
+proc
+opt_dff
+opt_clean
+memory_dff
+memory_collect
+select -assert-count 1 t:$mem_v2
+select -assert-count 1 t:$mem_v2 r:RD_TRANSPARENCY_MASK=2'b10 r:RD_COLLISION_X_MASK=2'b00 %i %i
+
+design -reset
+
+# Good case 6: 'x mux.
+
+read_verilog << EOT
+
+module top(
+	input [3:0] ra,
+	input [3:0] wa1,
+	input [3:0] wa2,
+	input [3:0] wd1,
+	input [3:0] wd2,
+	input we1, we2,
+	input re,
+	input clk,
+	output reg [3:0] rd,
+);
+
+reg [3:0] mem[0:15];
+
+always @(posedge clk) begin
+	if (we1)
+		mem[wa1] <= wd1;
+	if (we2)
+		mem[wa2] <= wd2;
+	if (re) begin
+		rd <= mem[ra];
+		if (we1 && wa1 == ra)
+			rd <= 4'hx;
+		if (we2 && wa2 == ra)
+			rd <= wd2;
+	end
+end
+
+endmodule
+
+EOT
+
+hierarchy -auto-top
+proc
+opt_dff
+opt_clean
+memory_dff
+memory_collect
+select -assert-count 1 t:$mem_v2
+select -assert-count 1 t:$mem_v2 r:RD_TRANSPARENCY_MASK=2'b10 r:RD_COLLISION_X_MASK=2'b01 %i %i
+
+design -reset
+
+# Good case 7: uncollidable addresses.
+
+read_verilog << EOT
+
+module top(
+	input [3:0] addr,
+	input [3:0] wd1,
+	input [3:0] wd2,
+	input we1, we2,
+	input re,
+	input clk,
+	output reg [3:0] rd,
+);
+
+reg [3:0] mem[0:15];
+
+wire [3:0] wa1 = addr;
+wire [3:0] wa2 = addr + 1;
+wire [3:0] ra = addr + 2;
+
+always @(posedge clk) begin
+	if (we1)
+		mem[wa1] <= wd1;
+	if (we2)
+		mem[wa2] <= wd2;
+	if (re) begin
+		rd <= mem[ra];
+	end
+end
+
+endmodule
+
+EOT
+
+hierarchy -auto-top
+proc
+opt_dff
+opt_clean
+memory_dff
+memory_collect
+select -assert-count 1 t:$mem_v2
+select -assert-count 1 t:$mem_v2 r:RD_TRANSPARENCY_MASK=2'b00 r:RD_COLLISION_X_MASK=2'b11 %i %i
+
+design -reset
+
+# Good case 8: uncollidable addresses, but still have soft transparency logic.
+
+read_verilog << EOT
+
+module top(
+	input [3:0] addr,
+	input [3:0] wd1,
+	input [3:0] wd2,
+	input we1, we2,
+	input re,
+	input clk,
+	output reg [3:0] rd,
+);
+
+reg [3:0] mem[0:15];
+
+wire [3:0] wa1 = addr;
+wire [3:0] wa2 = addr + 1;
+wire [3:0] ra = addr + 2;
+
+always @(posedge clk) begin
+	if (we1)
+		mem[wa1] <= wd1;
+	if (we2)
+		mem[wa2] <= wd2;
+	if (re) begin
+		rd <= mem[ra];
+		if (we1 && wa1 == ra)
+			rd <= wd1;
+		if (we2 && wa2 == ra)
+			rd <= wd2;
+	end
+end
+
+endmodule
+
+EOT
+
+hierarchy -auto-top
+proc
+opt_dff
+opt_clean
+memory_dff
+memory_collect
+select -assert-count 1 t:$mem_v2
+select -assert-count 1 t:$mem_v2 r:RD_TRANSPARENCY_MASK=2'b00 r:RD_COLLISION_X_MASK=2'b11 %i %i
+
+design -reset
+
+# Bad case 1: broken bypass signal.
+
+read_verilog << EOT
+
+module top(
+	input [3:0] ra,
+	input [3:0] wa1,
+	input [3:0] wa2,
+	input [3:0] wd1,
+	input [3:0] wd2,
+	input we1, we2,
+	input re,
+	input clk,
+	output reg [3:0] rd,
+);
+
+reg [3:0] mem[0:15];
+
+always @(posedge clk) begin
+	if (we1)
+		mem[wa1] <= wd1;
+	if (we2)
+		mem[wa2] <= wd2;
+	if (re) begin
+		rd <= mem[ra];
+		if (we1 && wa1 == ra)
+			rd <= wd1;
+		if (we2 && wa2 == ra && we1)
+			rd <= wd2;
+	end
+end
+
+endmodule
+
+EOT
+
+hierarchy -auto-top
+proc
+opt_dff
+opt_clean
+logger -expect log "FF found, but with a mux select that doesn't seem to correspond to transparency logic" 1
+memory_dff
+logger -check-expected
+memory_collect
+select -assert-count 1 t:$mem_v2
+select -assert-count 1 t:$mem_v2 r:RD_CLK_ENABLE=1'b0 %i
+
+design -reset
+
+# Bad case 2: bad data signal.
+
+read_verilog << EOT
+
+module top(
+	input [3:0] ra,
+	input [3:0] wa1,
+	input [3:0] wa2,
+	input [3:0] wd1,
+	input [3:0] wd2,
+	input we1, we2,
+	input re,
+	input clk,
+	output reg [3:0] rd,
+);
+
+reg [3:0] mem[0:15];
+
+always @(posedge clk) begin
+	if (we1)
+		mem[wa1] <= wd1;
+	if (we2)
+		mem[wa2] <= wd2;
+	if (re) begin
+		rd <= mem[ra];
+		if (we1 && wa1 == ra)
+			rd <= wd1;
+		if (we2 && wa2 == ra)
+			rd <= wd1;
+	end
+end
+
+endmodule
+
+EOT
+
+hierarchy -auto-top
+proc
+opt_dff
+opt_clean
+logger -expect log "FF found, but with a mux data input that doesn't seem to correspond to transparency logic" 1
+memory_dff
+logger -check-expected
+memory_collect
+select -assert-count 1 t:$mem_v2
+select -assert-count 1 t:$mem_v2 r:RD_CLK_ENABLE=1'b0 %i
+
+design -reset
+
+# Bad case 3: priority mismatch.
+
+read_verilog << EOT
+
+module top(
+	input [3:0] ra,
+	input [3:0] wa1,
+	input [3:0] wa2,
+	input [3:0] wd1,
+	input [3:0] wd2,
+	input we1, we2,
+	input re,
+	input clk,
+	output reg [3:0] rd,
+);
+
+reg [3:0] mem[0:15];
+
+always @(posedge clk) begin
+	if (we1)
+		mem[wa1] <= wd1;
+	if (we2)
+		mem[wa2] <= wd2;
+	if (re) begin
+		rd <= mem[ra];
+		if (we2 && wa2 == ra)
+			rd <= wd2;
+		if (we1 && wa1 == ra)
+			rd <= wd1;
+	end
+end
+
+endmodule
+
+EOT
+
+hierarchy -auto-top
+proc
+opt_dff
+opt_clean
+logger -expect log "FF found, but transparency logic priority doesn't match write priority." 1
+memory_dff
+logger -check-expected
+memory_collect
+select -assert-count 1 t:$mem_v2
+select -assert-count 1 t:$mem_v2 r:RD_CLK_ENABLE=1'b0 %i
+
+design -reset
+
+# Good case 10: priority mismatch, but since the second value is 'x, it's still OK.
+
+read_verilog << EOT
+
+module top(
+	input [3:0] ra,
+	input [3:0] wa1,
+	input [3:0] wa2,
+	input [3:0] wd1,
+	input [3:0] wd2,
+	input we1, we2,
+	input re,
+	input clk,
+	output reg [3:0] rd,
+);
+
+reg [3:0] mem[0:15];
+
+always @(posedge clk) begin
+	if (we1)
+		mem[wa1] <= wd1;
+	if (we2)
+		mem[wa2] <= wd2;
+	if (re) begin
+		rd <= mem[ra];
+		if (we2 && wa2 == ra)
+			rd <= wd2;
+		if (we1 && wa1 == ra)
+			rd <= 4'hx;
+	end
+end
+
+endmodule
+
+EOT
+
+hierarchy -auto-top
+proc
+opt_dff
+opt_clean
+memory_dff
+memory_collect
+select -assert-count 1 t:$mem_v2
+select -assert-count 1 t:$mem_v2 r:RD_TRANSPARENCY_MASK=2'b10 r:RD_COLLISION_X_MASK=2'b01 %i %i
+
+design -reset
+
+# Good case 11: priority mismatch, but since three-way collision cannot happen, it's still OK.
+
+read_verilog << EOT
+
+module top(
+	input [3:0] addr,
+	input [1:0] mode,
+	input [3:0] wd1,
+	input [3:0] wd2,
+	input we1, we2,
+	input re,
+	input clk,
+	output reg [3:0] rd,
+);
+
+reg [3:0] wa1, wa2, ra;
+
+always @* begin
+	case (mode)
+	0: begin
+		wa1 = addr+1;
+		wa2 = addr;
+		ra = addr;
+	end
+	1: begin
+		wa1 = addr;
+		wa2 = addr+1;
+		ra = addr;
+	end
+	2: begin
+		wa1 = addr;
+		wa2 = addr;
+		ra = addr+1;
+	end
+	3: begin
+		wa1 = addr;
+		wa2 = addr+1;
+		ra = addr+2;
+	end
+	endcase
+end
+
+reg [3:0] mem[0:15];
+
+always @(posedge clk) begin
+	if (we1)
+		mem[wa1] <= wd1;
+	if (we2)
+		mem[wa2] <= wd2;
+	if (re) begin
+		rd <= mem[ra];
+		if (we2 && wa2 == ra)
+			rd <= wd2;
+		if (we1 && wa1 == ra)
+			rd <= wd1;
+	end
+end
+
+endmodule
+
+EOT
+
+hierarchy -auto-top
+proc
+opt_dff
+opt_clean
+memory_dff
+memory_collect
+select -assert-count 1 t:$mem_v2
+select -assert-count 1 t:$mem_v2 r:RD_TRANSPARENCY_MASK=2'b11 r:RD_COLLISION_X_MASK=2'b00 %i %i
+
+design -reset
+
+# Bad case 4: half of the port is transparent.
+
+read_verilog << EOT
+
+module top(
+	input [3:0] ra,
+	input [3:0] wa1,
+	input [3:0] wa2,
+	input [3:0] wd1,
+	input [3:0] wd2,
+	input we1, we2,
+	input re,
+	input clk,
+	output reg [3:0] rd,
+);
+
+reg [3:0] mem[0:15];
+
+always @(posedge clk) begin
+	if (we1)
+		mem[wa1] <= wd1;
+	if (we2)
+		mem[wa2] <= wd2;
+	if (re) begin
+		rd <= mem[ra];
+		if (we1 && wa1 == ra)
+			rd <= wd1;
+		if (we2 && wa2 == ra)
+			rd[3:2] <= wd2[3:2];
+	end
+end
+
+endmodule
+
+EOT
+
+hierarchy -auto-top
+proc
+opt_dff
+opt_clean
+logger -expect log "FF found, but soft transparency logic is inconsistent for port 1." 1
+memory_dff
+logger -check-expected
+memory_collect
+select -assert-count 1 t:$mem_v2
+select -assert-count 1 t:$mem_v2 r:RD_CLK_ENABLE=1'b0 %i
+
+design -reset
+
+# Good case 12: like above, but the other bits aren't changed by the port anyway.
+
+read_verilog << EOT
+
+module top(
+	input [3:0] ra,
+	input [3:0] wa1,
+	input [3:0] wa2,
+	input [3:0] wd1,
+	input [3:0] wd2,
+	input we1, we2,
+	input re,
+	input clk,
+	output reg [3:0] rd,
+);
+
+reg [3:0] mem[0:15];
+
+always @(posedge clk) begin
+	if (we1)
+		mem[wa1] <= wd1;
+	if (we2)
+		mem[wa2][3:2] <= wd2[3:2];
+	if (re) begin
+		rd <= mem[ra];
+		if (we1 && wa1 == ra)
+			rd <= wd1;
+		if (we2 && wa2 == ra)
+			rd[3:2] <= wd2[3:2];
+	end
+end
+
+endmodule
+
+EOT
+
+hierarchy -auto-top
+proc
+opt_dff
+opt_clean
+memory_dff
+memory_collect
+select -assert-count 1 t:$mem_v2
+select -assert-count 1 t:$mem_v2 r:RD_TRANSPARENCY_MASK=2'b11 r:RD_COLLISION_X_MASK=2'b00 %i %i
+
+design -reset
+
+# Good case 13: wide read, narrow write.
+
+read_verilog << EOT
+
+module top(
+	input [7:0] addr,
+	input [7:0] wd,
+	input we,
+	input re,
+	input clk,
+	output reg [31:0] rd,
+);
+
+reg [7:0] mem[0:255];
+
+always @(posedge clk) begin
+	if (we)
+		mem[addr] <= wd;
+	if (re) begin
+		rd[7:0] <= mem[{addr[7:2], 2'b00}];
+		rd[15:8] <= mem[{addr[7:2], 2'b01}];
+		rd[23:16] <= mem[{addr[7:2], 2'b10}];
+		rd[31:24] <= mem[{addr[7:2], 2'b11}];
+		case ({we, addr[1:0]})
+		3'b100: rd[7:0] <= wd;
+		3'b101: rd[15:8] <= wd;
+		3'b110: rd[23:16] <= wd;
+		3'b111: rd[31:24] <= wd;
+		endcase
+	end
+end
+
+endmodule
+
+EOT
+
+hierarchy -auto-top
+proc
+opt_dff
+opt_clean
+dump
+memory_dff
+memory_collect
+select -assert-count 1 t:$mem_v2
+select -assert-count 1 t:$mem_v2 r:RD_TRANSPARENCY_MASK=4'b1111 r:RD_COLLISION_X_MASK=4'b0000 %i %i
+
+design -reset
+
+# Good case 14: narrow read, wide write.
+
+read_verilog << EOT
+
+module top(
+	input [7:0] addr,
+	input [31:0] wd,
+	input we,
+	input re,
+	input clk,
+	output reg [7:0] rd,
+);
+
+reg [7:0] mem[0:255];
+
+always @(posedge clk) begin
+	if (we) begin
+		mem[{addr[7:2], 2'b00}] <= wd[7:0];
+		mem[{addr[7:2], 2'b01}] <= wd[15:8];
+		mem[{addr[7:2], 2'b10}] <= wd[23:16];
+		mem[{addr[7:2], 2'b11}] <= wd[31:24];
+	end
+	if (re) begin
+		rd <= mem[addr];
+		case ({we, addr[1:0]})
+		3'b100: rd <= wd[7:0];
+		3'b101: rd <= wd[15:8];
+		3'b110: rd <= wd[23:16];
+		3'b111: rd <= wd[31:24];
+		endcase
+	end
+end
+
+endmodule
+
+EOT
+
+hierarchy -auto-top
+proc
+opt_dff
+opt_clean
+dump
+memory_dff
+memory_collect
+select -assert-count 1 t:$mem_v2
+select -assert-count 1 t:$mem_v2 r:RD_TRANSPARENCY_MASK=4'b1111 r:RD_COLLISION_X_MASK=4'b0000 %i %i
+
+design -reset
+
+# Good case 15: wide read, wide write.
+
+read_verilog << EOT
+
+module top(
+	input [7:0] addr,
+	input [31:0] wd,
+	input we,
+	input re,
+	input clk,
+	output reg [31:0] rd,
+);
+
+reg [7:0] mem[0:255];
+
+always @(posedge clk) begin
+	if (we) begin
+		mem[{addr[7:2], 2'b00}] <= wd[7:0];
+		mem[{addr[7:2], 2'b01}] <= wd[15:8];
+		mem[{addr[7:2], 2'b10}] <= wd[23:16];
+		mem[{addr[7:2], 2'b11}] <= wd[31:24];
+	end
+	if (re) begin
+		rd[7:0] <= mem[{addr[7:2], 2'b00}];
+		rd[15:8] <= mem[{addr[7:2], 2'b01}];
+		rd[23:16] <= mem[{addr[7:2], 2'b10}];
+		rd[31:24] <= mem[{addr[7:2], 2'b11}];
+		if (we)
+			rd <= wd;
+	end
+end
+
+endmodule
+
+EOT
+
+hierarchy -auto-top
+proc
+opt_dff
+opt_clean
+dump
+memory_dff
+select -assert-count 4 t:$memrd_v2
+select -assert-count 1 t:$memrd_v2 r:TRANSPARENCY_MASK=4'b0001 r:COLLISION_X_MASK=4'b1110 %i %i
+select -assert-count 1 t:$memrd_v2 r:TRANSPARENCY_MASK=4'b0010 r:COLLISION_X_MASK=4'b1101 %i %i
+select -assert-count 1 t:$memrd_v2 r:TRANSPARENCY_MASK=4'b0100 r:COLLISION_X_MASK=4'b1011 %i %i
+select -assert-count 1 t:$memrd_v2 r:TRANSPARENCY_MASK=4'b1000 r:COLLISION_X_MASK=4'b0111 %i %i
+
+design -reset
-- 
cgit v1.2.3


From 1f74ec3535dba67d3e71ab1b9bf509c86bdca560 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Marcelina=20Ko=C5=9Bcielnicka?= <mwk@0x04.net>
Date: Sat, 29 May 2021 17:45:05 +0200
Subject: memory_share: Add -nosat and -nowiden options.

This unlocks wide port recognition by default.
---
 tests/memories/run-test.sh          |  8 +++++++
 tests/memories/wide_read_async.v    | 27 ++++++++++++++++++++++
 tests/memories/wide_read_mixed.v    | 46 +++++++++++++++++++++++++++++++++++++
 tests/memories/wide_read_sync.v     | 32 ++++++++++++++++++++++++++
 tests/memories/wide_read_trans.v    | 40 ++++++++++++++++++++++++++++++++
 tests/memories/wide_thru_priority.v | 29 +++++++++++++++++++++++
 tests/memories/wide_write.v         | 29 +++++++++++++++++++++++
 tests/opt/memory_dff_trans.ys       | 12 ++++++++++
 tests/opt/opt_mem_priority.ys       |  6 ++++-
 9 files changed, 228 insertions(+), 1 deletion(-)
 create mode 100644 tests/memories/wide_read_async.v
 create mode 100644 tests/memories/wide_read_mixed.v
 create mode 100644 tests/memories/wide_read_sync.v
 create mode 100644 tests/memories/wide_read_trans.v
 create mode 100644 tests/memories/wide_thru_priority.v
 create mode 100644 tests/memories/wide_write.v

(limited to 'tests')

diff --git a/tests/memories/run-test.sh b/tests/memories/run-test.sh
index 49922e3da..b8657056a 100755
--- a/tests/memories/run-test.sh
+++ b/tests/memories/run-test.sh
@@ -23,6 +23,10 @@ for f in `egrep -l 'expect-(wr-ports|rd-ports|rd-clk)' *.v`; do
 		grep -q "parameter \\\\WR_PORTS $(gawk '/expect-wr-ports/ { print $3; }' $f)\$" ${f%.v}.dmp ||
 				{ echo " ERROR: Unexpected number of write ports."; false; }
 	fi
+	if grep -q expect-wr-wide-continuation $f; then
+		grep -q "parameter \\\\WR_WIDE_CONTINUATION $(gawk '/expect-wr-wide-continuation/ { print $3; }' $f)\$" ${f%.v}.dmp ||
+				{ echo " ERROR: Unexpected write wide continuation."; false; }
+	fi
 	if grep -q expect-rd-ports $f; then
 		grep -q "parameter \\\\RD_PORTS $(gawk '/expect-rd-ports/ { print $3; }' $f)\$" ${f%.v}.dmp ||
 				{ echo " ERROR: Unexpected number of read ports."; false; }
@@ -55,6 +59,10 @@ for f in `egrep -l 'expect-(wr-ports|rd-ports|rd-clk)' *.v`; do
 		grep -q "parameter \\\\RD_INIT_VALUE $(gawk '/expect-rd-init-val/ { print $3; }' $f)\$" ${f%.v}.dmp ||
 				{ echo " ERROR: Unexpected read init value."; false; }
 	fi
+	if grep -q expect-rd-wide-continuation $f; then
+		grep -q "parameter \\\\RD_WIDE_CONTINUATION $(gawk '/expect-rd-wide-continuation/ { print $3; }' $f)\$" ${f%.v}.dmp ||
+				{ echo " ERROR: Unexpected read wide continuation."; false; }
+	fi
 	if grep -q expect-no-rd-clk $f; then
 		grep -q "connect \\\\RD_CLK 1'x\$" ${f%.v}.dmp ||
 				{ echo " ERROR: Expected no read clock."; false; }
diff --git a/tests/memories/wide_read_async.v b/tests/memories/wide_read_async.v
new file mode 100644
index 000000000..aecdb1938
--- /dev/null
+++ b/tests/memories/wide_read_async.v
@@ -0,0 +1,27 @@
+// expect-wr-ports 1
+// expect-rd-ports 4
+// expect-rd-wide-continuation 4'1110
+
+module test(
+	input clk,
+	input we,
+	input [5:0] ra,
+	input [7:0] wa,
+	input [7:0] wd,
+	output [31:0] rd
+);
+
+reg [7:0] mem[0:255];
+
+assign rd[7:0] = mem[{ra, 2'b00}];
+assign rd[15:8] = mem[{ra, 2'b01}];
+assign rd[23:16] = mem[{ra, 2'b10}];
+assign rd[31:24] = mem[{ra, 2'b11}];
+
+always @(posedge clk) begin
+	if (we)
+		mem[wa] <= wd;
+end
+
+endmodule
+
diff --git a/tests/memories/wide_read_mixed.v b/tests/memories/wide_read_mixed.v
new file mode 100644
index 000000000..c36db3d31
--- /dev/null
+++ b/tests/memories/wide_read_mixed.v
@@ -0,0 +1,46 @@
+// expect-wr-ports 1
+// expect-rd-ports 4
+// expect-rd-wide-continuation 4'1110
+// expect-rd-srst-val 32'10000111011001010100001100100001
+// expect-rd-init-val 32'10101011110011011110111110101011
+
+// In this testcase, the byte-wide read ports are merged into a single
+// word-wide port despite mismatched transparency, with soft transparency
+// logic inserted on half the port to preserve the semantics.
+
+module test(
+	input clk,
+	input re, rr,
+	input we,
+	input [5:0] ra,
+	input [7:0] wa,
+	input [7:0] wd,
+	output reg [31:0] rd
+);
+
+reg [7:0] mem[0:255];
+
+initial rd = 32'habcdefab;
+
+always @(posedge clk) begin
+	if (rr) begin
+		rd <= 32'h87654321;
+	end else if (re) begin
+		rd[7:0] <= mem[{ra, 2'b00}];
+		rd[15:8] <= mem[{ra, 2'b01}];
+		rd[23:16] <= mem[{ra, 2'b10}];
+		rd[31:24] <= mem[{ra, 2'b11}];
+		if (we && wa == {ra, 2'b00})
+			rd [7:0] <= wd;
+		if (we && wa == {ra, 2'b01})
+			rd [15:8] <= wd;
+	end
+end
+
+always @(posedge clk) begin
+	if (we)
+		mem[wa] <= wd;
+end
+
+endmodule
+
diff --git a/tests/memories/wide_read_sync.v b/tests/memories/wide_read_sync.v
new file mode 100644
index 000000000..54ba3f256
--- /dev/null
+++ b/tests/memories/wide_read_sync.v
@@ -0,0 +1,32 @@
+// expect-wr-ports 1
+// expect-rd-ports 4
+// expect-rd-wide-continuation 4'1110
+
+module test(
+	input clk,
+	input re,
+	input we,
+	input [5:0] ra,
+	input [7:0] wa,
+	input [7:0] wd,
+	output reg [31:0] rd
+);
+
+reg [7:0] mem[0:255];
+
+always @(posedge clk) begin
+	if (re) begin
+		rd[7:0] <= mem[{ra, 2'b00}];
+		rd[15:8] <= mem[{ra, 2'b01}];
+		rd[23:16] <= mem[{ra, 2'b10}];
+		rd[31:24] <= mem[{ra, 2'b11}];
+	end
+end
+
+always @(posedge clk) begin
+	if (we)
+		mem[wa] <= wd;
+end
+
+endmodule
+
diff --git a/tests/memories/wide_read_trans.v b/tests/memories/wide_read_trans.v
new file mode 100644
index 000000000..fe3293500
--- /dev/null
+++ b/tests/memories/wide_read_trans.v
@@ -0,0 +1,40 @@
+// expect-wr-ports 1
+// expect-rd-ports 4
+// expect-rd-wide-continuation 4'1110
+
+module test(
+	input clk,
+	input re,
+	input we,
+	input [5:0] ra,
+	input [7:0] wa,
+	input [7:0] wd,
+	output reg [31:0] rd
+);
+
+reg [7:0] mem[0:255];
+
+always @(posedge clk) begin
+	if (re) begin
+		rd[7:0] <= mem[{ra, 2'b00}];
+		rd[15:8] <= mem[{ra, 2'b01}];
+		rd[23:16] <= mem[{ra, 2'b10}];
+		rd[31:24] <= mem[{ra, 2'b11}];
+		if (we && wa == {ra, 2'b00})
+			rd [7:0] <= wd;
+		if (we && wa == {ra, 2'b01})
+			rd [15:8] <= wd;
+		if (we && wa == {ra, 2'b10})
+			rd [23:16] <= wd;
+		if (we && wa == {ra, 2'b11})
+			rd [31:24] <= wd;
+	end
+end
+
+always @(posedge clk) begin
+	if (we)
+		mem[wa] <= wd;
+end
+
+endmodule
+
diff --git a/tests/memories/wide_thru_priority.v b/tests/memories/wide_thru_priority.v
new file mode 100644
index 000000000..10c0d837b
--- /dev/null
+++ b/tests/memories/wide_thru_priority.v
@@ -0,0 +1,29 @@
+// expect-wr-ports 3
+// expect-rd-ports 1
+// expect-wr-wide-continuation 3'010
+
+module test(
+	input clk,
+	input we1, we2,
+	input [5:0] ra,
+	input [4:0] wa1,
+	input [5:0] wa2,
+	input [15:0] wd1,
+	input [7:0] wd2,
+	output [7:0] rd
+);
+
+reg [7:0] mem[0:63];
+
+assign rd = mem[ra];
+
+always @(posedge clk) begin
+	if (we1)
+		mem[{wa1, 1'b0}] <= wd1[7:0];
+	if (we2)
+		mem[wa2] <= wd2;
+	if (we1)
+		mem[{wa1, 1'b1}] <= wd1[15:8];
+end
+
+endmodule
diff --git a/tests/memories/wide_write.v b/tests/memories/wide_write.v
new file mode 100644
index 000000000..5c4cc41f9
--- /dev/null
+++ b/tests/memories/wide_write.v
@@ -0,0 +1,29 @@
+// expect-wr-ports 4
+// expect-rd-ports 1
+// expect-wr-wide-continuation 4'1110
+
+module test(
+	input clk,
+	input [3:0] we,
+	input [7:0] ra,
+	input [5:0] wa,
+	input [31:0] wd,
+	output [7:0] rd
+);
+
+reg [7:0] mem[0:255];
+
+assign rd = mem[ra];
+
+always @(posedge clk) begin
+	if (we[0])
+		mem[{wa, 2'b00}] <= wd[7:0];
+	if (we[1])
+		mem[{wa, 2'b01}] <= wd[15:8];
+	if (we[2])
+		mem[{wa, 2'b10}] <= wd[23:16];
+	if (we[3])
+		mem[{wa, 2'b11}] <= wd[31:24];
+end
+
+endmodule
diff --git a/tests/opt/memory_dff_trans.ys b/tests/opt/memory_dff_trans.ys
index 7599949f3..102b36f26 100644
--- a/tests/opt/memory_dff_trans.ys
+++ b/tests/opt/memory_dff_trans.ys
@@ -759,6 +759,10 @@ memory_dff
 memory_collect
 select -assert-count 1 t:$mem_v2
 select -assert-count 1 t:$mem_v2 r:RD_TRANSPARENCY_MASK=4'b1111 r:RD_COLLISION_X_MASK=4'b0000 %i %i
+memory_share
+select -assert-count 1 t:$mem_v2
+select -assert-count 1 t:$mem_v2 r:RD_TRANSPARENCY_MASK=4'b1111 r:RD_COLLISION_X_MASK=4'b0000 %i %i
+select -assert-count 1 t:$mem_v2 r:RD_WIDE_CONTINUATION=4'b1110 %i
 
 design -reset
 
@@ -808,6 +812,10 @@ memory_dff
 memory_collect
 select -assert-count 1 t:$mem_v2
 select -assert-count 1 t:$mem_v2 r:RD_TRANSPARENCY_MASK=4'b1111 r:RD_COLLISION_X_MASK=4'b0000 %i %i
+memory_share
+select -assert-count 1 t:$mem_v2
+select -assert-count 1 t:$mem_v2 r:RD_TRANSPARENCY_MASK=4'b1111 r:RD_COLLISION_X_MASK=4'b0000 %i %i
+select -assert-count 1 t:$mem_v2 r:WR_WIDE_CONTINUATION=4'b1110 %i
 
 design -reset
 
@@ -858,5 +866,9 @@ select -assert-count 1 t:$memrd_v2 r:TRANSPARENCY_MASK=4'b0001 r:COLLISION_X_MAS
 select -assert-count 1 t:$memrd_v2 r:TRANSPARENCY_MASK=4'b0010 r:COLLISION_X_MASK=4'b1101 %i %i
 select -assert-count 1 t:$memrd_v2 r:TRANSPARENCY_MASK=4'b0100 r:COLLISION_X_MASK=4'b1011 %i %i
 select -assert-count 1 t:$memrd_v2 r:TRANSPARENCY_MASK=4'b1000 r:COLLISION_X_MASK=4'b0111 %i %i
+memory_share
+select -assert-count 1 t:$memrd_v2
+select -assert-count 1 t:$memwr_v2
+select -assert-count 1 t:$memrd_v2 r:TRANSPARENCY_MASK=1'b1 r:COLLISION_X_MASK=1'b0 %i %i
 
 design -reset
diff --git a/tests/opt/opt_mem_priority.ys b/tests/opt/opt_mem_priority.ys
index c1261ddf7..a4119e12a 100644
--- a/tests/opt/opt_mem_priority.ys
+++ b/tests/opt/opt_mem_priority.ys
@@ -200,6 +200,10 @@ EOT
 hierarchy -auto-top
 proc
 opt
-memory -nomap
+opt_mem_priority
+memory_collect
 select -assert-count 1 t:$mem_v2
 select -assert-count 1 t:$mem_v2 r:WR_PRIORITY_MASK=64'h0804020100000000 %i
+memory_share
+select -assert-count 1 t:$mem_v2 r:WR_PRIORITY_MASK=64'h0f0f0f0f00000000 %i
+select -assert-count 1 t:$mem_v2 r:WR_WIDE_CONTINUATION=8'hee %i
-- 
cgit v1.2.3


From f7913285067ed30bf5087f265db7e0bd523af2b6 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Marcelina=20Ko=C5=9Bcielnicka?= <mwk@0x04.net>
Date: Fri, 13 Aug 2021 00:43:15 +0200
Subject: Add opt_mem_widen pass.

If all of us are wide, then none of us are!
---
 tests/memories/wide_all.v | 36 ++++++++++++++++++++++++++++++++++++
 1 file changed, 36 insertions(+)
 create mode 100644 tests/memories/wide_all.v

(limited to 'tests')

diff --git a/tests/memories/wide_all.v b/tests/memories/wide_all.v
new file mode 100644
index 000000000..f7bc3e5ce
--- /dev/null
+++ b/tests/memories/wide_all.v
@@ -0,0 +1,36 @@
+// expect-wr-ports 2
+// expect-rd-ports 1
+// expect-wr-wide-continuation 2'10
+
+module test(
+	input clk,
+	input [3:0] we,
+	input [6:0] ra,
+	input [5:0] wa,
+	input [31:0] wd,
+	output [15:0] rd
+);
+
+reg [7:0] mem[3:254];
+
+assign rd[7:0] = mem[{ra, 1'b0}];
+assign rd[15:0] = mem[{ra, 1'b1}];
+
+initial begin
+	mem[5] = 8'h12;
+	mem[6] = 8'h34;
+	mem[7] = 8'h56;
+end
+
+always @(posedge clk) begin
+	if (we[0])
+		mem[{wa, 2'b00}] <= wd[7:0];
+	if (we[1])
+		mem[{wa, 2'b01}] <= wd[15:8];
+	if (we[2])
+		mem[{wa, 2'b10}] <= wd[23:16];
+	if (we[3])
+		mem[{wa, 2'b11}] <= wd[31:24];
+end
+
+endmodule
-- 
cgit v1.2.3


From faacc7ad897437a8169af9dbbab6818f88c7b1a9 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Marcelina=20Ko=C5=9Bcielnicka?= <mwk@0x04.net>
Date: Sat, 14 Aug 2021 14:23:12 +0200
Subject: proc_prune: Make assign removal and promotion per-bit, remember
 promoted bits.

Fixes #2962.
---
 tests/proc/bug2962.ys | 22 ++++++++++++++++++++++
 1 file changed, 22 insertions(+)
 create mode 100644 tests/proc/bug2962.ys

(limited to 'tests')

diff --git a/tests/proc/bug2962.ys b/tests/proc/bug2962.ys
new file mode 100644
index 000000000..99da8db5d
--- /dev/null
+++ b/tests/proc/bug2962.ys
@@ -0,0 +1,22 @@
+read_ilang << EOT
+module \top
+   wire width 4 input 1 \a
+   wire width 2 input 2 \b
+   wire input 3 \clk
+   wire width 4 output 4 \q
+   wire input 5 \en
+   wire width 4 \nq
+   process \p
+     assign \nq \a
+     assign \nq [1:0] \b
+     switch \en
+       case 1'1
+         assign \nq [3] 1'0
+     end
+     sync posedge \clk
+       update \q \nq
+   end
+end
+EOT
+proc
+check -assert
-- 
cgit v1.2.3


From c2d358484fa5188be350ef1a8496f88b60d69ef7 Mon Sep 17 00:00:00 2001
From: Pepijn de Vos <pepijndevos@gmail.com>
Date: Fri, 20 Aug 2021 21:21:06 +0200
Subject: Gowin: deal with active-low tristate (#2971)

* deal with active-low tristate

* remove empty port

* update sim models

* add expected lut1 to tests
---
 tests/arch/gowin/tribuf.ys | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

(limited to 'tests')

diff --git a/tests/arch/gowin/tribuf.ys b/tests/arch/gowin/tribuf.ys
index 5855b9d97..eef7e379f 100644
--- a/tests/arch/gowin/tribuf.ys
+++ b/tests/arch/gowin/tribuf.ys
@@ -9,5 +9,6 @@ design -load postopt # load the post-opt design (otherwise equiv_opt loads the p
 cd tristate # Constrain all select calls below inside the top module
 #Internal cell type used. Need support it.
 select -assert-count 1 t:TBUF
+select -assert-count 1 t:LUT1
 select -assert-count 2 t:IBUF
-select -assert-none t:TBUF t:IBUF %% t:* %D
+select -assert-none t:TBUF t:IBUF t:LUT1 %% t:* %D
\ No newline at end of file
-- 
cgit v1.2.3


From 62d41d46397a93d1efa2b8282203d192b256d824 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Marcelina=20Ko=C5=9Bcielnicka?= <mwk@0x04.net>
Date: Sat, 21 Aug 2021 23:36:00 +0200
Subject: opt_clean: Make the init attribute follow the FF's Q.

Previously, opt_clean would reconnect all ports (including FF Q ports)
to a "canonical" SigBit chosen by complex rules, but would leave the
init attribute on the old wire.  This change applies the same
canonicalization rules to the init attributes, ensuring that init moves
to wherever the Q port moved.

Part of another jab at #2920.
---
 tests/techmap/iopadmap.ys | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

(limited to 'tests')

diff --git a/tests/techmap/iopadmap.ys b/tests/techmap/iopadmap.ys
index df029b3a0..f8e6bc374 100644
--- a/tests/techmap/iopadmap.ys
+++ b/tests/techmap/iopadmap.ys
@@ -169,7 +169,7 @@ sub s2(.i(i[1]), .o(w[1]));
 assign o = oe ? w : 2'bz;
 endmodule
 
-module c(input i, oe, (* init=2'b00 *) inout io, output o1, o2);
+module c(input i, oe, (* init=1'b0 *) inout io, output o1, o2);
 assign io = oe ? i : 1'bz;
 assign {o1,o2} = {io,io};
 endmodule
@@ -182,5 +182,5 @@ select -assert-count 1 a/c:s %co a/a:init=1'b1 %i
 select -assert-count 1 a/a:init
 select -assert-count 1 b/c:s* %co %a b/a:init=2'b1x %i
 select -assert-count 1 b/a:init
-select -assert-count 1 c/t:iobuf %co c/a:init=2'b00 %i
+select -assert-count 1 c/t:iobuf %co c/a:init=1'b0 %i
 select -assert-count 1 c/a:init
-- 
cgit v1.2.3


From f0a52e3dd275ee57a1b3ffd0a734b591bf21f668 Mon Sep 17 00:00:00 2001
From: Zachary Snow <zach@zachjs.com>
Date: Mon, 30 Aug 2021 11:35:36 -0600
Subject: sv: support declaration in procedural for initialization

In line with other tools, this adds an extra wrapping block around such
for loops to appropriately scope the variable.
---
 tests/verilog/for_decl_no_init.ys |  9 +++++++++
 tests/verilog/for_decl_no_sv.ys   |  9 +++++++++
 tests/verilog/for_decl_shadow.sv  | 32 ++++++++++++++++++++++++++++++++
 tests/verilog/for_decl_shadow.ys  |  6 ++++++
 4 files changed, 56 insertions(+)
 create mode 100644 tests/verilog/for_decl_no_init.ys
 create mode 100644 tests/verilog/for_decl_no_sv.ys
 create mode 100644 tests/verilog/for_decl_shadow.sv
 create mode 100644 tests/verilog/for_decl_shadow.ys

(limited to 'tests')

diff --git a/tests/verilog/for_decl_no_init.ys b/tests/verilog/for_decl_no_init.ys
new file mode 100644
index 000000000..68c1584e0
--- /dev/null
+++ b/tests/verilog/for_decl_no_init.ys
@@ -0,0 +1,9 @@
+logger -expect error "For loop variable declaration is missing initialization!" 1
+read_verilog -sv <<EOT
+module top;
+    integer z;
+    initial
+        for (integer i; i < 10; i = i + 1)
+            z = i;
+endmodule
+EOT
diff --git a/tests/verilog/for_decl_no_sv.ys b/tests/verilog/for_decl_no_sv.ys
new file mode 100644
index 000000000..34edddff7
--- /dev/null
+++ b/tests/verilog/for_decl_no_sv.ys
@@ -0,0 +1,9 @@
+logger -expect error "For loop inline variable declaration is only supported in SystemVerilog mode!" 1
+read_verilog <<EOT
+module top;
+    integer z;
+    initial
+        for (integer i = 1; i < 10; i = i + 1)
+            z = i;
+endmodule
+EOT
diff --git a/tests/verilog/for_decl_shadow.sv b/tests/verilog/for_decl_shadow.sv
new file mode 100644
index 000000000..f6948f97e
--- /dev/null
+++ b/tests/verilog/for_decl_shadow.sv
@@ -0,0 +1,32 @@
+module gate(x);
+	output reg [15:0] x;
+	if (1) begin : gen
+		integer x;
+		initial begin
+			for (integer x = 5; x < 10; x++)
+				if (x == 5)
+					gen.x = 0;
+				else
+					gen.x += 2 ** x;
+			x = x * 2;
+		end
+	end
+	initial x = gen.x;
+endmodule
+
+module gold(x);
+	output reg [15:0] x;
+	if (1) begin : gen
+		integer x;
+		integer z;
+		initial begin
+			for (z = 5; z < 10; z++)
+				if (z == 5)
+					x = 0;
+				else
+					x += 2 ** z;
+			x = x * 2;
+		end
+	end
+	initial x = gen.x;
+endmodule
diff --git a/tests/verilog/for_decl_shadow.ys b/tests/verilog/for_decl_shadow.ys
new file mode 100644
index 000000000..d2dca715e
--- /dev/null
+++ b/tests/verilog/for_decl_shadow.ys
@@ -0,0 +1,6 @@
+read_verilog -sv for_decl_shadow.sv
+hierarchy
+proc
+equiv_make gold gate equiv
+equiv_simple
+equiv_status -assert
-- 
cgit v1.2.3


From b2e9717419e9a852f4e64f12891b8e9742900917 Mon Sep 17 00:00:00 2001
From: Zachary Snow <zach@zachjs.com>
Date: Tue, 31 Aug 2021 11:45:02 -0600
Subject: sv: support declaration in generate for initialization

This is accomplished by generating a unique name for the genvar,
renaming references to the genvar only in the loop's initialization,
guard, and incrementation, and finally adding a localparam inside the
loop body with the original name so that the genvar can be shadowed as
expected.
---
 tests/verilog/genfor_decl_no_init.ys |  7 +++++++
 tests/verilog/genfor_decl_no_sv.ys   |  7 +++++++
 tests/verilog/genvar_loop_decl_1.sv  | 18 ++++++++++++++++++
 tests/verilog/genvar_loop_decl_1.ys  | 14 ++++++++++++++
 tests/verilog/genvar_loop_decl_2.sv  | 30 ++++++++++++++++++++++++++++++
 tests/verilog/genvar_loop_decl_2.ys  |  5 +++++
 tests/verilog/genvar_loop_decl_3.sv  | 28 ++++++++++++++++++++++++++++
 tests/verilog/genvar_loop_decl_3.ys  |  5 +++++
 8 files changed, 114 insertions(+)
 create mode 100644 tests/verilog/genfor_decl_no_init.ys
 create mode 100644 tests/verilog/genfor_decl_no_sv.ys
 create mode 100644 tests/verilog/genvar_loop_decl_1.sv
 create mode 100644 tests/verilog/genvar_loop_decl_1.ys
 create mode 100644 tests/verilog/genvar_loop_decl_2.sv
 create mode 100644 tests/verilog/genvar_loop_decl_2.ys
 create mode 100644 tests/verilog/genvar_loop_decl_3.sv
 create mode 100644 tests/verilog/genvar_loop_decl_3.ys

(limited to 'tests')

diff --git a/tests/verilog/genfor_decl_no_init.ys b/tests/verilog/genfor_decl_no_init.ys
new file mode 100644
index 000000000..348899195
--- /dev/null
+++ b/tests/verilog/genfor_decl_no_init.ys
@@ -0,0 +1,7 @@
+logger -expect error "Generate for loop variable declaration is missing initialization!" 1
+read_verilog -sv <<EOT
+module top;
+    for (genvar i; i < 10; i = i + 1)
+        wire x;
+endmodule
+EOT
diff --git a/tests/verilog/genfor_decl_no_sv.ys b/tests/verilog/genfor_decl_no_sv.ys
new file mode 100644
index 000000000..124a27c28
--- /dev/null
+++ b/tests/verilog/genfor_decl_no_sv.ys
@@ -0,0 +1,7 @@
+logger -expect error "Generate for loop inline variable declaration is only supported in SystemVerilog mode!" 1
+read_verilog <<EOT
+module top;
+    for (genvar i = 1; i < 10; i = i + 1)
+        wire x;
+endmodule
+EOT
diff --git a/tests/verilog/genvar_loop_decl_1.sv b/tests/verilog/genvar_loop_decl_1.sv
new file mode 100644
index 000000000..b503f75da
--- /dev/null
+++ b/tests/verilog/genvar_loop_decl_1.sv
@@ -0,0 +1,18 @@
+`default_nettype none
+
+module gate(a);
+	for (genvar i = 0; i < 2; i++)
+		wire [i:0] x = '1;
+
+	output wire [32:0] a;
+	assign a = {1'b0, genblk1[0].x, 1'b0, genblk1[1].x, 1'b0};
+endmodule
+
+module gold(a);
+	genvar i;
+	for (i = 0; i < 2; i++)
+		wire [i:0] x = '1;
+
+	output wire [32:0] a;
+	assign a = {1'b0, genblk1[0].x, 1'b0, genblk1[1].x, 1'b0};
+endmodule
diff --git a/tests/verilog/genvar_loop_decl_1.ys b/tests/verilog/genvar_loop_decl_1.ys
new file mode 100644
index 000000000..ded486248
--- /dev/null
+++ b/tests/verilog/genvar_loop_decl_1.ys
@@ -0,0 +1,14 @@
+read_verilog -sv genvar_loop_decl_1.sv
+
+select -assert-count 1 gate/genblk1[0].x
+select -assert-count 1 gate/genblk1[1].x
+select -assert-count 0 gate/genblk1[2].x
+
+select -assert-count 1 gold/genblk1[0].x
+select -assert-count 1 gold/genblk1[1].x
+select -assert-count 0 gold/genblk1[2].x
+
+proc
+equiv_make gold gate equiv
+equiv_simple
+equiv_status -assert
diff --git a/tests/verilog/genvar_loop_decl_2.sv b/tests/verilog/genvar_loop_decl_2.sv
new file mode 100644
index 000000000..c5a85ef11
--- /dev/null
+++ b/tests/verilog/genvar_loop_decl_2.sv
@@ -0,0 +1,30 @@
+`default_nettype none
+
+module gate(out);
+    wire [3:0] x;
+    for (genvar x = 0; x < 2; x++) begin : blk
+        localparam w = x;
+        if (x == 0) begin : sub
+            wire [w:0] x;
+        end
+    end
+    assign x = 2;
+    assign blk[0].sub.x = '1;
+    output wire [9:0] out;
+    assign out = {1'bx, x, blk[0].sub.x};
+endmodule
+
+module gold(out);
+    wire [3:0] x;
+    genvar z;
+    for (z = 0; z < 2; z++) begin : blk
+        localparam w = z;
+        if (z == 0) begin : sub
+            wire [w:0] x;
+        end
+    end
+    assign x = 2;
+    assign blk[0].sub.x = '1;
+    output wire [9:0] out;
+    assign out = {1'bx, x, blk[0].sub.x};
+endmodule
diff --git a/tests/verilog/genvar_loop_decl_2.ys b/tests/verilog/genvar_loop_decl_2.ys
new file mode 100644
index 000000000..52fdeb49c
--- /dev/null
+++ b/tests/verilog/genvar_loop_decl_2.ys
@@ -0,0 +1,5 @@
+read_verilog -sv genvar_loop_decl_2.sv
+proc
+equiv_make gold gate equiv
+equiv_simple
+equiv_status -assert
diff --git a/tests/verilog/genvar_loop_decl_3.sv b/tests/verilog/genvar_loop_decl_3.sv
new file mode 100644
index 000000000..4d6d2366d
--- /dev/null
+++ b/tests/verilog/genvar_loop_decl_3.sv
@@ -0,0 +1,28 @@
+`default_nettype none
+
+module gate(x, y);
+    output reg [15:0] x, y;
+    if (1) begin : gen
+        integer x, y;
+        for (genvar x = 0; x < 2; x++)
+            if (x == 0)
+                initial gen.x = 10;
+        assign y = x + 1;
+    end
+    initial x = gen.x;
+    assign y = gen.y;
+endmodule
+
+module gold(x, y);
+    output reg [15:0] x, y;
+    if (1) begin : gen
+        integer x, y;
+        genvar z;
+        for (z = 0; z < 2; z++)
+            if (z == 0)
+                initial x = 10;
+        assign y = x + 1;
+    end
+    initial x = gen.x;
+    assign y = gen.y;
+endmodule
diff --git a/tests/verilog/genvar_loop_decl_3.ys b/tests/verilog/genvar_loop_decl_3.ys
new file mode 100644
index 000000000..19f754124
--- /dev/null
+++ b/tests/verilog/genvar_loop_decl_3.ys
@@ -0,0 +1,5 @@
+read_verilog -sv genvar_loop_decl_3.sv
+proc
+equiv_make gold gate equiv
+equiv_simple
+equiv_status -assert
-- 
cgit v1.2.3


From f03e2c30aa3ad92bffb7ecd7179fe859d1b993b0 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 9 Sep 2021 10:05:55 -0700
Subject: abc9: replace cell type/parameters if derived type already processed
 (#2991)

* Add close bracket

* Add testcase

* Replace cell type/param if in unmap_design

* Improve abc9_box error message too

* Update comment as per review
---
 tests/arch/ecp5/bug2731.ys | 7 +++++++
 1 file changed, 7 insertions(+)
 create mode 100644 tests/arch/ecp5/bug2731.ys

(limited to 'tests')

diff --git a/tests/arch/ecp5/bug2731.ys b/tests/arch/ecp5/bug2731.ys
new file mode 100644
index 000000000..c609cea3b
--- /dev/null
+++ b/tests/arch/ecp5/bug2731.ys
@@ -0,0 +1,7 @@
+read_verilog -icells <<EOF
+module top(input c, r, input [1:0] d, output reg [1:0] q);
+TRELLIS_FF #(.REGSET("SET")) ff1(.CLK(c), .LSR(r), .DI(d[0]), .Q(q[0]));
+TRELLIS_FF #(.REGSET("SET")) ff2(.CLK(c), .LSR(r), .DI(d[1]), .Q(q[1]));
+endmodule
+EOF
+synth_ecp5 -abc9 -dff
-- 
cgit v1.2.3


From 65316ec9262e1cc10fdc7215f2d3ead579d1e258 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 9 Sep 2021 10:06:20 -0700
Subject: abc9: holes module to instantiate cells with NEW_ID (#2992)

* Add testcase

* holes module to instantiate cells with NEW_ID
---
 tests/techmap/bug2759.ys | 14 ++++++++++++++
 1 file changed, 14 insertions(+)
 create mode 100644 tests/techmap/bug2759.ys

(limited to 'tests')

diff --git a/tests/techmap/bug2759.ys b/tests/techmap/bug2759.ys
new file mode 100644
index 000000000..05699bef8
--- /dev/null
+++ b/tests/techmap/bug2759.ys
@@ -0,0 +1,14 @@
+read_verilog -specify <<EOT
+(* abc9_box, whitebox *)
+module box(input [1:0] i, output o);
+specify
+(i *> o) = 1;
+endspecify
+assign o = ^i;
+endmodule
+
+module top(input [1:0] i, output o);
+box i1(i, o);
+endmodule
+EOT
+abc9 -lut 4
-- 
cgit v1.2.3


From 96b6410dcb7a82e7be8d4a2025835936f2ca84a7 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 9 Sep 2021 10:06:31 -0700
Subject: abc9: make re-entrant (#2993)

* Add testcase

* Cleanup some state at end of abc9

* Re-assign abc9_box_id from scratch

* Suppress delete unless prep_bypass did something
---
 tests/techmap/bug2972.ys | 20 ++++++++++++++++++++
 1 file changed, 20 insertions(+)
 create mode 100644 tests/techmap/bug2972.ys

(limited to 'tests')

diff --git a/tests/techmap/bug2972.ys b/tests/techmap/bug2972.ys
new file mode 100644
index 000000000..8ae895f56
--- /dev/null
+++ b/tests/techmap/bug2972.ys
@@ -0,0 +1,20 @@
+read_verilog -specify <<EOT
+(* abc9_box, blackbox*)
+module box(input clk, d, output reg q, output do);
+parameter P = 0;
+always @(posedge clk)
+    q <= d;
+assign do = d;
+specify
+    (posedge clk => (q : d)) = 1;
+    (d => do) = 1;
+endspecify
+endmodule
+
+module top(input clk, d, output q);
+box i1(clk, d, q);
+endmodule
+EOT
+hierarchy
+abc9 -lut 4
+abc9 -lut 4
-- 
cgit v1.2.3


From 6b7267b849abf7688938e5e53ae7017e8588ff18 Mon Sep 17 00:00:00 2001
From: Zachary Snow <zach@zachjs.com>
Date: Mon, 2 Aug 2021 18:42:34 -0600
Subject: verilog: fix multiple AST_PREFIX scope resolution issues

- Root AST_PREFIX nodes are now subject to genblk expansion to allow
  them to refer to a locally-visible generate block
- Part selects on AST_PREFIX member leafs can now refer to generate
  block items (previously would not resolve and raise an error)
- Add source location information to AST_PREFIX nodes
---
 tests/verilog/prefix.sv | 95 +++++++++++++++++++++++++++++++++++++++++++++++++
 tests/verilog/prefix.ys |  5 +++
 2 files changed, 100 insertions(+)
 create mode 100644 tests/verilog/prefix.sv
 create mode 100644 tests/verilog/prefix.ys

(limited to 'tests')

diff --git a/tests/verilog/prefix.sv b/tests/verilog/prefix.sv
new file mode 100644
index 000000000..2d7fbb134
--- /dev/null
+++ b/tests/verilog/prefix.sv
@@ -0,0 +1,95 @@
+module top;
+    genvar i, j;
+    if (1) begin : blk1
+        integer a = 1;
+        for (i = 0; i < 2; i = i + 1) begin : blk2
+            integer b = i;
+            for (j = 0; j < 2; j = j + 1) begin : blk3
+                integer c = j;
+                localparam x = i;
+                localparam y = j;
+                always @* begin
+                    assert (1 == a);
+                    assert (1 == blk1.a);
+                    assert (1 == top.blk1.a);
+                    assert (i == b);
+                    assert (i == blk2[i].b);
+                    assert (i == blk1.blk2[i].b);
+                    assert (i == top.blk1.blk2[i].b);
+                    assert (i == blk2[x].b);
+                    assert (i == blk1.blk2[x].b);
+                    assert (i == top.blk1.blk2[x].b);
+                    assert (j == c);
+                    assert (j == blk3[j].c);
+                    assert (j == blk2[x].blk3[j].c);
+                    assert (j == blk1.blk2[x].blk3[j].c);
+                    assert (j == top.blk1.blk2[x].blk3[j].c);
+                    assert (j == c);
+                    assert (j == blk3[y].c);
+                    assert (j == blk2[x].blk3[y].c);
+                    assert (j == blk1.blk2[x].blk3[y].c);
+                    assert (j == top.blk1.blk2[x].blk3[y].c);
+                    assert (j == top.blk1.blk2[x].blk3[y].c[0]);
+                    assert (0 == top.blk1.blk2[x].blk3[y].c[1]);
+                    assert (0 == top.blk1.blk2[x].blk3[y].c[j]);
+                end
+            end
+            always @* begin
+                assert (1 == a);
+                assert (1 == blk1.a);
+                assert (1 == top.blk1.a);
+                assert (i == b);
+                assert (i == blk2[i].b);
+                assert (i == blk1.blk2[i].b);
+                assert (i == top.blk1.blk2[i].b);
+                assert (0 == blk3[0].c);
+                assert (0 == blk2[i].blk3[0].c);
+                assert (0 == blk1.blk2[i].blk3[0].c);
+                assert (0 == top.blk1.blk2[i].blk3[0].c);
+                assert (1 == blk3[1].c);
+                assert (1 == blk2[i].blk3[1].c);
+                assert (1 == blk1.blk2[i].blk3[1].c);
+                assert (1 == top.blk1.blk2[i].blk3[1].c);
+            end
+        end
+        always @* begin
+            assert (1 == a);
+            assert (1 == blk1.a);
+            assert (1 == top.blk1.a);
+            assert (0 == blk2[0].b);
+            assert (0 == blk1.blk2[0].b);
+            assert (0 == top.blk1.blk2[0].b);
+            assert (1 == blk2[1].b);
+            assert (1 == blk1.blk2[1].b);
+            assert (1 == top.blk1.blk2[1].b);
+            assert (0 == blk2[0].blk3[0].c);
+            assert (0 == blk1.blk2[0].blk3[0].c);
+            assert (0 == top.blk1.blk2[0].blk3[0].c);
+            assert (1 == blk2[0].blk3[1].c);
+            assert (1 == blk1.blk2[0].blk3[1].c);
+            assert (1 == top.blk1.blk2[0].blk3[1].c);
+            assert (0 == blk2[1].blk3[0].c);
+            assert (0 == blk1.blk2[1].blk3[0].c);
+            assert (0 == top.blk1.blk2[1].blk3[0].c);
+            assert (1 == blk2[1].blk3[1].c);
+            assert (1 == blk1.blk2[1].blk3[1].c);
+            assert (1 == top.blk1.blk2[1].blk3[1].c);
+        end
+    end
+    always @* begin
+        assert (1 == blk1.a);
+        assert (1 == top.blk1.a);
+        assert (0 == blk1.blk2[0].b);
+        assert (0 == top.blk1.blk2[0].b);
+        assert (1 == blk1.blk2[1].b);
+        assert (1 == top.blk1.blk2[1].b);
+        assert (0 == blk1.blk2[0].blk3[0].c);
+        assert (0 == top.blk1.blk2[0].blk3[0].c);
+        assert (1 == blk1.blk2[0].blk3[1].c);
+        assert (1 == top.blk1.blk2[0].blk3[1].c);
+        assert (0 == blk1.blk2[1].blk3[0].c);
+        assert (0 == top.blk1.blk2[1].blk3[0].c);
+        assert (1 == blk1.blk2[1].blk3[1].c);
+        assert (1 == top.blk1.blk2[1].blk3[1].c);
+    end
+endmodule
diff --git a/tests/verilog/prefix.ys b/tests/verilog/prefix.ys
new file mode 100644
index 000000000..ed3b3a111
--- /dev/null
+++ b/tests/verilog/prefix.ys
@@ -0,0 +1,5 @@
+read_verilog -sv prefix.sv
+hierarchy
+proc
+select -module top
+sat -verify -seq 1 -prove-asserts -show-all
-- 
cgit v1.2.3


From d6fe6d4fb62be3bb5ec876f1f56356d757b65a41 Mon Sep 17 00:00:00 2001
From: Zachary Snow <zach@zachjs.com>
Date: Fri, 13 Aug 2021 20:51:28 -0700
Subject: sv: support wand and wor of data types

This enables the usage of declarations of wand or wor with a base type
of logic, integer, or a typename. Note that declarations of nets with
2-state base types is still permitted, in violation of the spec.
---
 tests/verilog/net_types.sv | 34 ++++++++++++++++++++++++++++++++++
 tests/verilog/net_types.ys |  5 +++++
 2 files changed, 39 insertions(+)
 create mode 100644 tests/verilog/net_types.sv
 create mode 100644 tests/verilog/net_types.ys

(limited to 'tests')

diff --git a/tests/verilog/net_types.sv b/tests/verilog/net_types.sv
new file mode 100644
index 000000000..7226a7ee5
--- /dev/null
+++ b/tests/verilog/net_types.sv
@@ -0,0 +1,34 @@
+module top;
+    wire logic wire_logic_0; assign wire_logic_0 = 0;
+    wire logic wire_logic_1; assign wire_logic_1 = 1;
+    wand logic wand_logic_0; assign wand_logic_0 = 0; assign wand_logic_0 = 1;
+    wand logic wand_logic_1; assign wand_logic_1 = 1; assign wand_logic_1 = 1;
+    wor logic wor_logic_0; assign wor_logic_0 = 0; assign wor_logic_0 = 0;
+    wor logic wor_logic_1; assign wor_logic_1 = 1; assign wor_logic_1 = 0;
+
+    wire integer wire_integer; assign wire_integer = 4'b1001;
+    wand integer wand_integer; assign wand_integer = 4'b1001; assign wand_integer = 4'b1010;
+    wor integer wor_integer; assign wor_integer = 4'b1001; assign wor_integer = 4'b1010;
+
+    typedef logic [3:0] typename;
+    wire typename wire_typename; assign wire_typename = 4'b1001;
+    wand typename wand_typename; assign wand_typename = 4'b1001; assign wand_typename = 4'b1010;
+    wor typename wor_typename; assign wor_typename = 4'b1001; assign wor_typename = 4'b1010;
+
+    always @* begin
+        assert (wire_logic_0 == 0);
+        assert (wire_logic_1 == 1);
+        assert (wand_logic_0 == 0);
+        assert (wand_logic_1 == 1);
+        assert (wor_logic_0 == 0);
+        assert (wor_logic_1 == 1);
+
+        assert (wire_integer == 4'b1001);
+        assert (wand_integer == 4'b1000);
+        assert (wor_integer == 4'b1011);
+
+        assert (wire_typename == 4'b1001);
+        assert (wand_typename == 4'b1000);
+        assert (wor_typename == 4'b1011);
+    end
+endmodule
diff --git a/tests/verilog/net_types.ys b/tests/verilog/net_types.ys
new file mode 100644
index 000000000..9f75812ea
--- /dev/null
+++ b/tests/verilog/net_types.ys
@@ -0,0 +1,5 @@
+read_verilog -sv net_types.sv
+hierarchy
+proc
+opt -full
+sat -verify -prove-asserts -show-all
-- 
cgit v1.2.3


From 15fb0107dcdfcf98c56f229727c7cd701ff9b4b3 Mon Sep 17 00:00:00 2001
From: Claire Xenia Wolf <claire@clairexen.net>
Date: Wed, 22 Sep 2021 17:34:20 +0200
Subject: Fix "make vgtest" so it runs to the end (but now it fails ;)

Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
---
 tests/simple/attrib01_module.v              |  6 +++---
 tests/simple/attrib02_port_decl.v           |  6 +++---
 tests/simple/attrib03_parameter.v           |  6 +++---
 tests/simple/attrib04_net_var.v             |  6 +++---
 tests/simple/attrib05_port_conn.v.DISABLED  |  6 +++---
 tests/simple/attrib06_operator_suffix.v     |  6 +++---
 tests/simple/attrib07_func_call.v.DISABLED  |  6 +++---
 tests/simple/attrib08_mod_inst.v            |  6 +++---
 tests/simple/attrib09_case.v                |  6 +++---
 tests/simple/case_expr_const.v              |  2 +-
 tests/simple/case_expr_non_const.v          |  2 +-
 tests/simple/case_large.v                   |  2 +-
 tests/simple/const_branch_finish.v          |  2 +-
 tests/simple/const_fold_func.v              |  2 +-
 tests/simple/const_func_shadow.v            |  2 +-
 tests/simple/defvalue.sv                    |  2 +-
 tests/simple/func_block.v                   |  2 +-
 tests/simple/func_recurse.v                 |  2 +-
 tests/simple/func_width_scope.v             |  2 +-
 tests/simple/genblk_collide.v               |  4 ++--
 tests/simple/genblk_dive.v                  |  2 +-
 tests/simple/genblk_order.v                 |  2 +-
 tests/simple/genblk_port_shadow.v           |  2 +-
 tests/simple/hierarchy.v                    |  2 +-
 tests/simple/ifdef_1.v                      |  2 +-
 tests/simple/ifdef_2.v                      |  2 +-
 tests/simple/local_loop_var.sv              |  2 +-
 tests/simple/loop_prefix_case.v             |  2 +-
 tests/simple/loop_var_shadow.v              |  2 +-
 tests/simple/macro_arg_spaces.sv            |  2 +-
 tests/simple/macro_arg_surrounding_spaces.v |  2 +-
 tests/simple/matching_end_labels.sv         |  2 +-
 tests/simple/mem2reg_bounds_tern.v          |  2 +-
 tests/simple/module_scope.v                 | 26 +++++++++++++-------------
 tests/simple/module_scope_case.v            |  8 ++++----
 tests/simple/named_genblk.v                 |  2 +-
 tests/simple/nested_genblk_resolve.v        |  2 +-
 tests/simple/string_format.v                |  2 +-
 tests/simple/unnamed_block_decl.sv          |  2 +-
 tests/simple/wandwor.v                      | 12 ++++++------
 40 files changed, 79 insertions(+), 79 deletions(-)

(limited to 'tests')

diff --git a/tests/simple/attrib01_module.v b/tests/simple/attrib01_module.v
index adef34f5b..d6e36fb80 100644
--- a/tests/simple/attrib01_module.v
+++ b/tests/simple/attrib01_module.v
@@ -1,4 +1,4 @@
-module bar(clk, rst, inp, out);
+module attrib01_bar(clk, rst, inp, out);
   input  wire clk;
   input  wire rst;
   input  wire inp;
@@ -10,12 +10,12 @@ module bar(clk, rst, inp, out);
 
 endmodule
 
-module foo(clk, rst, inp, out);
+module attrib01_foo(clk, rst, inp, out);
   input  wire clk;
   input  wire rst;
   input  wire inp;
   output wire out;
 
-  bar bar_instance (clk, rst, inp, out);
+  attrib01_bar bar_instance (clk, rst, inp, out);
 endmodule
 
diff --git a/tests/simple/attrib02_port_decl.v b/tests/simple/attrib02_port_decl.v
index 3505e7265..989213b77 100644
--- a/tests/simple/attrib02_port_decl.v
+++ b/tests/simple/attrib02_port_decl.v
@@ -1,4 +1,4 @@
-module bar(clk, rst, inp, out);
+module attrib02_bar(clk, rst, inp, out);
   (* this_is_clock = 1 *)
   input  wire clk;
   (* this_is_reset = 1 *)
@@ -13,13 +13,13 @@ module bar(clk, rst, inp, out);
 
 endmodule
 
-module foo(clk, rst, inp, out);
+module attrib02_foo(clk, rst, inp, out);
   (* this_is_the_master_clock *)
   input  wire clk;
   input  wire rst;
   input  wire inp;
   output wire out;
 
-  bar bar_instance (clk, rst, inp, out);
+  attrib02_bar bar_instance (clk, rst, inp, out);
 endmodule
 
diff --git a/tests/simple/attrib03_parameter.v b/tests/simple/attrib03_parameter.v
index 562d225cd..d2ae98978 100644
--- a/tests/simple/attrib03_parameter.v
+++ b/tests/simple/attrib03_parameter.v
@@ -1,4 +1,4 @@
-module bar(clk, rst, inp, out);
+module attrib03_bar(clk, rst, inp, out);
 
   (* bus_width *)
   parameter WIDTH = 2;
@@ -17,12 +17,12 @@ module bar(clk, rst, inp, out);
 
 endmodule
 
-module foo(clk, rst, inp, out);
+module attrib03_foo(clk, rst, inp, out);
   input  wire clk;
   input  wire rst;
   input  wire [7:0] inp;
   output wire [7:0] out;
 
-  bar # (.WIDTH(8)) bar_instance (clk, rst, inp, out);
+  attrib03_bar # (.WIDTH(8)) bar_instance (clk, rst, inp, out);
 endmodule
 
diff --git a/tests/simple/attrib04_net_var.v b/tests/simple/attrib04_net_var.v
index 8b5523406..98826e971 100644
--- a/tests/simple/attrib04_net_var.v
+++ b/tests/simple/attrib04_net_var.v
@@ -1,4 +1,4 @@
-module bar(clk, rst, inp, out);
+module attrib04_bar(clk, rst, inp, out);
   input  wire clk;
   input  wire rst;
   input  wire inp;
@@ -21,12 +21,12 @@ module bar(clk, rst, inp, out);
 
 endmodule
 
-module foo(clk, rst, inp, out);
+module attrib04_foo(clk, rst, inp, out);
   input  wire clk;
   input  wire rst;
   input  wire inp;
   output wire out;
 
-  bar bar_instance (clk, rst, inp, out);
+  attrib04_bar bar_instance (clk, rst, inp, out);
 endmodule
 
diff --git a/tests/simple/attrib05_port_conn.v.DISABLED b/tests/simple/attrib05_port_conn.v.DISABLED
index e20e66319..8cc471f4e 100644
--- a/tests/simple/attrib05_port_conn.v.DISABLED
+++ b/tests/simple/attrib05_port_conn.v.DISABLED
@@ -1,4 +1,4 @@
-module bar(clk, rst, inp, out);
+module attrib05_bar(clk, rst, inp, out);
   input  wire clk;
   input  wire rst;
   input  wire inp;
@@ -10,12 +10,12 @@ module bar(clk, rst, inp, out);
 
 endmodule
 
-module foo(clk, rst, inp, out);
+module attrib05_foo(clk, rst, inp, out);
   input  wire clk;
   input  wire rst;
   input  wire inp;
   output wire out;
 
-  bar bar_instance ( (* clock_connected *) clk, rst, (* this_is_the_input *) inp, out);
+  attrib05_bar bar_instance ( (* clock_connected *) clk, rst, (* this_is_the_input *) inp, out);
 endmodule
 
diff --git a/tests/simple/attrib06_operator_suffix.v b/tests/simple/attrib06_operator_suffix.v
index e21173c58..2bc136f9a 100644
--- a/tests/simple/attrib06_operator_suffix.v
+++ b/tests/simple/attrib06_operator_suffix.v
@@ -1,4 +1,4 @@
-module bar(clk, rst, inp_a, inp_b, out);
+module attrib06_bar(clk, rst, inp_a, inp_b, out);
   input  wire clk;
   input  wire rst;
   input  wire [7:0] inp_a;
@@ -11,13 +11,13 @@ module bar(clk, rst, inp_a, inp_b, out);
 
 endmodule
 
-module foo(clk, rst, inp_a, inp_b, out);
+module attrib06_foo(clk, rst, inp_a, inp_b, out);
   input  wire clk;
   input  wire rst;
   input  wire [7:0] inp_a;
   input  wire [7:0] inp_b;
   output wire [7:0] out;
 
-  bar bar_instance (clk, rst, inp_a, inp_b, out);
+  attrib06_bar bar_instance (clk, rst, inp_a, inp_b, out);
 endmodule
 
diff --git a/tests/simple/attrib07_func_call.v.DISABLED b/tests/simple/attrib07_func_call.v.DISABLED
index f55ef2316..282fc5da7 100644
--- a/tests/simple/attrib07_func_call.v.DISABLED
+++ b/tests/simple/attrib07_func_call.v.DISABLED
@@ -1,4 +1,4 @@
-function [7:0] do_add;
+function [7:0] attrib07_do_add;
   input [7:0] inp_a;
   input [7:0] inp_b;
 
@@ -6,7 +6,7 @@ function [7:0] do_add;
 
 endfunction
 
-module foo(clk, rst, inp_a, inp_b, out);
+module attri07_foo(clk, rst, inp_a, inp_b, out);
   input  wire clk;
   input  wire rst;
   input  wire [7:0] inp_a;
@@ -15,7 +15,7 @@ module foo(clk, rst, inp_a, inp_b, out);
 
   always @(posedge clk)
     if (rst) out <= 0;
-    else     out <= do_add (* combinational_adder *) (inp_a, inp_b);
+    else     out <= attrib07_do_add (* combinational_adder *) (inp_a, inp_b);
 
 endmodule
 
diff --git a/tests/simple/attrib08_mod_inst.v b/tests/simple/attrib08_mod_inst.v
index c5a32234e..759e67c7b 100644
--- a/tests/simple/attrib08_mod_inst.v
+++ b/tests/simple/attrib08_mod_inst.v
@@ -1,4 +1,4 @@
-module bar(clk, rst, inp, out);
+module attrib08_bar(clk, rst, inp, out);
   input  wire clk;
   input  wire rst;
   input  wire inp;
@@ -10,13 +10,13 @@ module bar(clk, rst, inp, out);
 
 endmodule
 
-module foo(clk, rst, inp, out);
+module attrib08_foo(clk, rst, inp, out);
   input  wire clk;
   input  wire rst;
   input  wire inp;
   output wire out;
 
   (* my_module_instance = 99 *)
-  bar bar_instance (clk, rst, inp, out);
+  attrib08_bar bar_instance (clk, rst, inp, out);
 endmodule
 
diff --git a/tests/simple/attrib09_case.v b/tests/simple/attrib09_case.v
index 8551bf9d0..a72b81dda 100644
--- a/tests/simple/attrib09_case.v
+++ b/tests/simple/attrib09_case.v
@@ -1,4 +1,4 @@
-module bar(clk, rst, inp, out);
+module attrib09_bar(clk, rst, inp, out);
   input  wire clk;
   input  wire rst;
   input  wire [1:0] inp;
@@ -15,12 +15,12 @@ module bar(clk, rst, inp, out);
 
 endmodule
 
-module foo(clk, rst, inp, out);
+module attrib09_foo(clk, rst, inp, out);
   input  wire clk;
   input  wire rst;
   input  wire [1:0] inp;
   output wire [1:0] out;
 
-  bar bar_instance (clk, rst, inp, out);
+  attrib09_bar bar_instance (clk, rst, inp, out);
 endmodule
 
diff --git a/tests/simple/case_expr_const.v b/tests/simple/case_expr_const.v
index 58267b965..d9169c084 100644
--- a/tests/simple/case_expr_const.v
+++ b/tests/simple/case_expr_const.v
@@ -1,6 +1,6 @@
 // Note: case_expr_{,non_}const.v should be modified in tandem to ensure both
 // the constant and non-constant case evaluation logic is covered
-module top(
+module case_expr_const_top(
 	// expected to output all 1s
     output reg a, b, c, d, e, f, g, h
 );
diff --git a/tests/simple/case_expr_non_const.v b/tests/simple/case_expr_non_const.v
index 7856e781c..6dfc2e54e 100644
--- a/tests/simple/case_expr_non_const.v
+++ b/tests/simple/case_expr_non_const.v
@@ -1,6 +1,6 @@
 // Note: case_expr_{,non_}const.v should be modified in tandem to ensure both
 // the constant and non-constant case evaluation logic is covered
-module top(
+module case_expr_non_const_top(
 	// expected to output all 1s
     output reg a, b, c, d, e, f, g, h
 );
diff --git a/tests/simple/case_large.v b/tests/simple/case_large.v
index a96ce86fe..ec8ed6038 100644
--- a/tests/simple/case_large.v
+++ b/tests/simple/case_large.v
@@ -1,4 +1,4 @@
-module top (
+module case_lage_top (
     input wire [127:0] x,
     output reg [31:0] y
 );
diff --git a/tests/simple/const_branch_finish.v b/tests/simple/const_branch_finish.v
index f585be87a..7e365eeb4 100644
--- a/tests/simple/const_branch_finish.v
+++ b/tests/simple/const_branch_finish.v
@@ -4,7 +4,7 @@
 		$finish; \
 	end
 
-module top;
+module case_branch_finish_top;
 	parameter WIDTH = 32;
 	integer j;
 	initial begin
diff --git a/tests/simple/const_fold_func.v b/tests/simple/const_fold_func.v
index ee2f12e06..b3f476ce3 100644
--- a/tests/simple/const_fold_func.v
+++ b/tests/simple/const_fold_func.v
@@ -1,4 +1,4 @@
-module top(
+module const_fold_func_top(
 	input wire [3:0] inp,
 	output wire [3:0] out1, out2, out3, out4, out5,
 	output reg [3:0] out6
diff --git a/tests/simple/const_func_shadow.v b/tests/simple/const_func_shadow.v
index ca63606d9..fb4f148f6 100644
--- a/tests/simple/const_func_shadow.v
+++ b/tests/simple/const_func_shadow.v
@@ -1,4 +1,4 @@
-module top(w, x, y, z);
+module const_func_shadow_top(w, x, y, z);
 	function [11:0] func;
 		input reg [2:0] x;
 		input reg [2:0] y;
diff --git a/tests/simple/defvalue.sv b/tests/simple/defvalue.sv
index b0a087ecb..77d7ba26b 100644
--- a/tests/simple/defvalue.sv
+++ b/tests/simple/defvalue.sv
@@ -1,4 +1,4 @@
-module top(input clock, input [3:0] delta, output [3:0] cnt1, cnt2);
+module defvalue_top(input clock, input [3:0] delta, output [3:0] cnt1, cnt2);
 	cnt #(1) foo (.clock, .cnt(cnt1), .delta);
 	cnt #(2) bar (.clock, .cnt(cnt2));
 endmodule
diff --git a/tests/simple/func_block.v b/tests/simple/func_block.v
index be759d1a9..0ac7ca3bf 100644
--- a/tests/simple/func_block.v
+++ b/tests/simple/func_block.v
@@ -1,6 +1,6 @@
 `default_nettype none
 
-module top(inp, out1, out2, out3);
+module func_block_top(inp, out1, out2, out3);
 	input wire [31:0] inp;
 
 	function automatic [31:0] func1;
diff --git a/tests/simple/func_recurse.v b/tests/simple/func_recurse.v
index d61c8cc06..02cfbcddf 100644
--- a/tests/simple/func_recurse.v
+++ b/tests/simple/func_recurse.v
@@ -1,4 +1,4 @@
-module top(
+module func_recurse_top(
 	input wire [3:0] inp,
 	output wire [3:0] out1, out2
 );
diff --git a/tests/simple/func_width_scope.v b/tests/simple/func_width_scope.v
index ce81e894e..2f82988ae 100644
--- a/tests/simple/func_width_scope.v
+++ b/tests/simple/func_width_scope.v
@@ -1,4 +1,4 @@
-module top(inp, out1, out2);
+module func_width_scope_top(inp, out1, out2);
 	input wire signed inp;
 
 	localparam WIDTH_A = 5;
diff --git a/tests/simple/genblk_collide.v b/tests/simple/genblk_collide.v
index f42dd2cfc..118c0b008 100644
--- a/tests/simple/genblk_collide.v
+++ b/tests/simple/genblk_collide.v
@@ -1,6 +1,6 @@
 `default_nettype none
 
-module top1;
+module genblock_collide_top1;
 	generate
 		if (1) begin : foo
 			if (1) begin : bar
@@ -12,7 +12,7 @@ module top1;
 	endgenerate
 endmodule
 
-module top2;
+module genblock_collide_top2;
 	genvar i;
 	generate
 		if (1) begin : foo
diff --git a/tests/simple/genblk_dive.v b/tests/simple/genblk_dive.v
index 98d0e1f4b..ca0c0d4a1 100644
--- a/tests/simple/genblk_dive.v
+++ b/tests/simple/genblk_dive.v
@@ -1,5 +1,5 @@
 `default_nettype none
-module top(output wire x);
+module genblk_dive_top(output wire x);
 	generate
 		if (1) begin : Z
 			if (1) begin : A
diff --git a/tests/simple/genblk_order.v b/tests/simple/genblk_order.v
index 7c3a7a756..c80c1ac1a 100644
--- a/tests/simple/genblk_order.v
+++ b/tests/simple/genblk_order.v
@@ -1,5 +1,5 @@
 `default_nettype none
-module top(
+module genblk_order_top(
 	output wire out1,
 	output wire out2
 );
diff --git a/tests/simple/genblk_port_shadow.v b/tests/simple/genblk_port_shadow.v
index a04631a20..c1348632c 100644
--- a/tests/simple/genblk_port_shadow.v
+++ b/tests/simple/genblk_port_shadow.v
@@ -1,4 +1,4 @@
-module top(x);
+module genblock_port_shadow_top(x);
 	generate
 		if (1) begin : blk
 			wire x;
diff --git a/tests/simple/hierarchy.v b/tests/simple/hierarchy.v
index 123afaeab..b03044fde 100644
--- a/tests/simple/hierarchy.v
+++ b/tests/simple/hierarchy.v
@@ -1,6 +1,6 @@
 
 (* top *)
-module top(a, b, y1, y2, y3, y4);
+module hierarchy_top(a, b, y1, y2, y3, y4);
 input [3:0] a;
 input signed [3:0] b;
 output [7:0] y1, y2, y3, y4;
diff --git a/tests/simple/ifdef_1.v b/tests/simple/ifdef_1.v
index fa962355c..f1358185c 100644
--- a/tests/simple/ifdef_1.v
+++ b/tests/simple/ifdef_1.v
@@ -1,4 +1,4 @@
-module top(o1, o2, o3, o4);
+module ifdef_1_top(o1, o2, o3, o4);
 
 `define FAIL input wire not_a_port;
 
diff --git a/tests/simple/ifdef_2.v b/tests/simple/ifdef_2.v
index 6dd89efed..9fae7570d 100644
--- a/tests/simple/ifdef_2.v
+++ b/tests/simple/ifdef_2.v
@@ -1,4 +1,4 @@
-module top(o1, o2, o3);
+module ifdef_2_top(o1, o2, o3);
 
 output wire o1;
 
diff --git a/tests/simple/local_loop_var.sv b/tests/simple/local_loop_var.sv
index 46b4e5c22..42860e218 100644
--- a/tests/simple/local_loop_var.sv
+++ b/tests/simple/local_loop_var.sv
@@ -1,4 +1,4 @@
-module top(out);
+module local_loop_top(out);
 	output integer out;
 	initial begin
 		integer i;
diff --git a/tests/simple/loop_prefix_case.v b/tests/simple/loop_prefix_case.v
index 7ee28ed70..0cfa00547 100644
--- a/tests/simple/loop_prefix_case.v
+++ b/tests/simple/loop_prefix_case.v
@@ -1,4 +1,4 @@
-module top(
+module loop_prefix_case_top(
 	input wire x,
 	output reg y
 );
diff --git a/tests/simple/loop_var_shadow.v b/tests/simple/loop_var_shadow.v
index 0222a4493..b75a15ab0 100644
--- a/tests/simple/loop_var_shadow.v
+++ b/tests/simple/loop_var_shadow.v
@@ -1,4 +1,4 @@
-module top(out);
+module loop_var_shadow_top(out);
 	genvar i;
 	generate
 		for (i = 0; i < 2; i = i + 1) begin : loop
diff --git a/tests/simple/macro_arg_spaces.sv b/tests/simple/macro_arg_spaces.sv
index 75c4cd136..5fc9e2881 100644
--- a/tests/simple/macro_arg_spaces.sv
+++ b/tests/simple/macro_arg_spaces.sv
@@ -1,4 +1,4 @@
-module top(
+module macro_arg_spaces_top(
 	input wire [31:0] i,
 	output wire [31:0] x, y, z
 );
diff --git a/tests/simple/macro_arg_surrounding_spaces.v b/tests/simple/macro_arg_surrounding_spaces.v
index 3dbb5ea01..e0239c08b 100644
--- a/tests/simple/macro_arg_surrounding_spaces.v
+++ b/tests/simple/macro_arg_surrounding_spaces.v
@@ -1,4 +1,4 @@
-module top(
+module macr_arg_surrounding_spaces_top(
 	IDENT_V_,
 	IDENT_W_,
 	IDENT_X_,
diff --git a/tests/simple/matching_end_labels.sv b/tests/simple/matching_end_labels.sv
index 09182ebcf..2d42e7e10 100644
--- a/tests/simple/matching_end_labels.sv
+++ b/tests/simple/matching_end_labels.sv
@@ -1,4 +1,4 @@
-module top(
+module matching_end_labels_top(
     output reg [7:0]
     out1, out2, out3, out4
 );
diff --git a/tests/simple/mem2reg_bounds_tern.v b/tests/simple/mem2reg_bounds_tern.v
index 89d6dd3e8..0e6852fe7 100644
--- a/tests/simple/mem2reg_bounds_tern.v
+++ b/tests/simple/mem2reg_bounds_tern.v
@@ -1,4 +1,4 @@
-module top(
+module mem2reg_bounds_term_top(
     input clk,
     input wire [1:0] sel,
     input wire [7:0] base,
diff --git a/tests/simple/module_scope.v b/tests/simple/module_scope.v
index 3e46b72ef..d07783912 100644
--- a/tests/simple/module_scope.v
+++ b/tests/simple/module_scope.v
@@ -1,29 +1,29 @@
 `default_nettype none
 
-module Example(o1, o2);
+module module_scope_Example(o1, o2);
    parameter [31:0] v1 = 10;
    parameter [31:0] v2 = 20;
    output [31:0] o1, o2;
-   assign Example.o1 = Example.v1;
-   assign Example.o2 = Example.v2;
+   assign module_scope_Example.o1 = module_scope_Example.v1;
+   assign module_scope_Example.o2 = module_scope_Example.v2;
 endmodule
 
-module ExampleLong(o1, o2);
+module module_scope_ExampleLong(o1, o2);
    parameter [31:0] ThisIsAnExtremelyLongParameterNameToTriggerTheSHA1Checksum1 = 10;
    parameter [31:0] ThisIsAnExtremelyLongParameterNameToTriggerTheSHA1Checksum2 = 20;
    output [31:0] o1, o2;
-   assign ExampleLong.o1 = ExampleLong.ThisIsAnExtremelyLongParameterNameToTriggerTheSHA1Checksum1;
-   assign ExampleLong.o2 = ExampleLong.ThisIsAnExtremelyLongParameterNameToTriggerTheSHA1Checksum2;
+   assign module_scope_ExampleLong.o1 = module_scope_ExampleLong.ThisIsAnExtremelyLongParameterNameToTriggerTheSHA1Checksum1;
+   assign module_scope_ExampleLong.o2 = module_scope_ExampleLong.ThisIsAnExtremelyLongParameterNameToTriggerTheSHA1Checksum2;
 endmodule
 
-module top(
+module module_scope_top(
    output [31:0] a1, a2, b1, b2, c1, c2,
    output [31:0] d1, d2, e1, e2, f1, f2
 );
-   Example a(a1, a2);
-   Example #(1) b(b1, b2);
-   Example #(1, 2) c(c1, c2);
-   ExampleLong d(d1, d2);
-   ExampleLong #(1) e(e1, e2);
-   ExampleLong #(1, 2) f(f1, f2);
+   module_scope_Example a(a1, a2);
+   module_scope_Example #(1) b(b1, b2);
+   module_scope_Example #(1, 2) c(c1, c2);
+   module_scope_ExampleLong d(d1, d2);
+   module_scope_ExampleLong #(1) e(e1, e2);
+   module_scope_ExampleLong #(1, 2) f(f1, f2);
 endmodule
diff --git a/tests/simple/module_scope_case.v b/tests/simple/module_scope_case.v
index 1472b6912..bceba4424 100644
--- a/tests/simple/module_scope_case.v
+++ b/tests/simple/module_scope_case.v
@@ -1,11 +1,11 @@
-module top(
+module module_scope_case_top(
 	input wire x,
 	output reg y
 );
 	always @* begin
-		case (top.x)
-			1: top.y = 0;
-			0: top.y = 1;
+		case (module_scope_case_top.x)
+			1: module_scope_case_top.y = 0;
+			0: module_scope_case_top.y = 1;
 		endcase
 	end
 endmodule
diff --git a/tests/simple/named_genblk.v b/tests/simple/named_genblk.v
index b8300fc4d..b98b7c8ce 100644
--- a/tests/simple/named_genblk.v
+++ b/tests/simple/named_genblk.v
@@ -1,5 +1,5 @@
 `default_nettype none
-module top;
+module named_genblk_top;
 	generate
 		if (1) begin
 			wire t;
diff --git a/tests/simple/nested_genblk_resolve.v b/tests/simple/nested_genblk_resolve.v
index da5593f8a..70bbc611b 100644
--- a/tests/simple/nested_genblk_resolve.v
+++ b/tests/simple/nested_genblk_resolve.v
@@ -1,5 +1,5 @@
 `default_nettype none
-module top;
+module nested_genblk_resolve_top;
     generate
         if (1) begin
             wire x;
diff --git a/tests/simple/string_format.v b/tests/simple/string_format.v
index ce45ca1e9..cb7b419ac 100644
--- a/tests/simple/string_format.v
+++ b/tests/simple/string_format.v
@@ -1,4 +1,4 @@
-module top;
+module string_format_top;
 	parameter STR = "something interesting";
 	initial begin
 		$display("A: %s", STR);
diff --git a/tests/simple/unnamed_block_decl.sv b/tests/simple/unnamed_block_decl.sv
index e81b457a8..e78c577da 100644
--- a/tests/simple/unnamed_block_decl.sv
+++ b/tests/simple/unnamed_block_decl.sv
@@ -1,4 +1,4 @@
-module top(z);
+module unnamed_block_decl(z);
 	output integer z;
 	initial begin
 		integer x;
diff --git a/tests/simple/wandwor.v b/tests/simple/wandwor.v
index 34404aa26..40502acfc 100644
--- a/tests/simple/wandwor.v
+++ b/tests/simple/wandwor.v
@@ -5,9 +5,9 @@ module wandwor_test0 (A, B, C, D, X, Y, Z);
 	output Z;
 
 	assign X = A, X = B, Y = C, Y = D;
-	foo foo_0 (C, D, X);
-	foo foo_1 (A, B, Y);
-	foo foo_2 (X, Y, Z);
+	wandwor_foo foo_0 (C, D, X);
+	wandwor_foo foo_1 (A, B, Y);
+	wandwor_foo foo_2 (X, Y, Z);
 endmodule
 
 module wandwor_test1 (A, B, C, D, X, Y, Z);
@@ -16,7 +16,7 @@ module wandwor_test1 (A, B, C, D, X, Y, Z);
 	output wand [3:0] Y;
 	output Z;
 
-	bar bar_inst (
+	wandwor_bar bar_inst (
 		.I0({A, B}),
 		.I1({B, A}),
 		.O({X, Y})
@@ -27,10 +27,10 @@ module wandwor_test1 (A, B, C, D, X, Y, Z);
 	assign Z = ^{X,Y};
 endmodule
 
-module foo(input I0, I1, output O);
+module wandwor_foo(input I0, I1, output O);
 	assign O = I0 ^ I1;
 endmodule
 
-module bar(input [7:0] I0, I1, output [7:0] O);
+module wandwor_bar(input [7:0] I0, I1, output [7:0] O);
 	assign O = I0 + I1;
 endmodule
-- 
cgit v1.2.3


From 4e70c3077562e511d6f840c91dd30ade87d66517 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Marcelina=20Ko=C5=9Bcielnicka?= <mwk@0x04.net>
Date: Wed, 6 Oct 2021 22:16:55 +0200
Subject: FfData: some refactoring.

- FfData now keeps track of the module and underlying cell, if any (so
  calling emit on FfData created from a cell will replace the existing cell)
- FfData implementation is split off to its own .cc file for faster
  compilation
- the "flip FF data sense by inserting inverters in front and after"
  functionality that zinit uses is moved onto FfData class and beefed up
  to have dffsr support, to support more use cases
---
 tests/arch/xilinx/fsm.ys | 5 +++--
 tests/techmap/zinit.ys   | 7 ++++---
 2 files changed, 7 insertions(+), 5 deletions(-)

(limited to 'tests')

diff --git a/tests/arch/xilinx/fsm.ys b/tests/arch/xilinx/fsm.ys
index ace646af4..3b1919627 100644
--- a/tests/arch/xilinx/fsm.ys
+++ b/tests/arch/xilinx/fsm.ys
@@ -31,6 +31,7 @@ stat
 select -assert-count 1 t:BUFG
 select -assert-count 6 t:FDRE
 select -assert-count 1 t:LUT1
-select -assert-count 8 t:LUT4
+select -assert-max 1 t:LUT3
+select -assert-max 8 t:LUT4
 select -assert-count 5 t:MUXF5
-select -assert-none t:BUFG t:FDRE t:LUT1 t:LUT4 t:MUXF5 %% t:* %D
+select -assert-none t:BUFG t:FDRE t:LUT1 t:LUT3 t:LUT4 t:MUXF5 %% t:* %D
diff --git a/tests/techmap/zinit.ys b/tests/techmap/zinit.ys
index 1670573dd..bc07f40e6 100644
--- a/tests/techmap/zinit.ys
+++ b/tests/techmap/zinit.ys
@@ -20,7 +20,8 @@ EOT
 equiv_opt -assert -multiclock zinit
 design -load postopt
 
-select -assert-count 20 t:$_NOT_
+select -assert-count 16 t:$_NOT_
+select -assert-count 4 t:$xor
 select -assert-count 1 w:unused a:init %i
 select -assert-count 1 w:Q a:init=13'bxxxx1xxxxxxxx %i
 select -assert-count 4 c:dff0 c:dff2 c:dff4 c:dff6 %% t:$_DFF_??1_ %i
@@ -52,7 +53,7 @@ design -load postopt
 
 select -assert-count 0 t:$_NOT_
 select -assert-count 1 w:unused a:init %i
-select -assert-count 1 w:Q a:init=13'bxxxx1xxxxxxxx %i
+select -assert-count 1 w:Q a:init=13'bx00x100000000 %i
 select -assert-count 4 c:dff0 c:dff2 c:dff4 c:dff6 %% t:$_DFF_??0_ %i
 select -assert-count 4 c:dff1 c:dff3 c:dff5 c:dff7 %% t:$_DFF_??1_ %i
 
@@ -142,7 +143,7 @@ EOT
 zinit
 
 select -assert-count 0 t:$_NOT_
-select -assert-count 0 w:Q a:init %i
+select -assert-count 1 w:Q a:init=24'b0 %i
 select -assert-count 4 c:dff0 c:dff2 c:dff4 c:dff6 %% t:$_DFFE_??0P_ %i
 select -assert-count 4 c:dff1 c:dff3 c:dff5 c:dff7 %% t:$_DFFE_??1P_ %i
 select -assert-count 4 c:dff8 c:dff10 c:dff12 c:dff14 %% t:$_SDFF_??0_ %i
-- 
cgit v1.2.3


From dc8da76282e806e7ffd632af3e6c11d645ff5699 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Marcelina=20Ko=C5=9Bcielnicka?= <mwk@0x04.net>
Date: Fri, 8 Oct 2021 14:51:57 +0200
Subject: Fix a regression from #3035.

---
 tests/memories/trans_addr_enable.v | 21 +++++++++++++++++++++
 1 file changed, 21 insertions(+)
 create mode 100644 tests/memories/trans_addr_enable.v

(limited to 'tests')

diff --git a/tests/memories/trans_addr_enable.v b/tests/memories/trans_addr_enable.v
new file mode 100644
index 000000000..f366f41ad
--- /dev/null
+++ b/tests/memories/trans_addr_enable.v
@@ -0,0 +1,21 @@
+// expect-wr-ports 1
+// expect-rd-ports 1
+// expect-rd-clk \clk
+
+module top(input clk, we, rae, input [7:0] addr, wd, output [7:0] rd);
+
+reg [7:0] mem[0:255];
+
+reg [7:0] rra;
+
+always @(posedge clk) begin
+	if (we)
+		mem[addr] <= wd;
+
+	if (rae)
+		rra <= addr;
+end
+
+assign rd = mem[rra];
+
+endmodule
-- 
cgit v1.2.3


From 83887495b80f8dba24c3c81c96cce6f464efb24e Mon Sep 17 00:00:00 2001
From: Claire Xenia Wolf <claire@clairexen.net>
Date: Tue, 19 Oct 2021 10:56:43 +0200
Subject: Fixes in vcdcd.pl for newer Perl versions

Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
---
 tests/tools/vcdcd.pl | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

(limited to 'tests')

diff --git a/tests/tools/vcdcd.pl b/tests/tools/vcdcd.pl
index 58a92b44d..0f33371fb 100755
--- a/tests/tools/vcdcd.pl
+++ b/tests/tools/vcdcd.pl
@@ -11,7 +11,7 @@ $| = 1;
 my $opt_width = 0;
 my $opt_delay = 0;
 
-while (1)
+while ($#ARGV >= 0)
 {
 	if ($ARGV[0] eq '-w') {
 		$opt_width = +$ARGV[1];
@@ -74,10 +74,10 @@ for my $net (sort keys %gold_signals_hash) {
 	# next unless $net eq "tst_bench_top.i2c_top.byte_controller.bit_controller.cnt";
 	my %orig_net_names;
 	print "common signal: $net";
-	for my $fullname (keys $gold_signals_hash{$net}) {
+	for my $fullname (keys %{$gold_signals_hash{$net}}) {
 		$orig_net_names{$fullname} = 1;
 	}
-	for my $fullname (keys $gate_signals_hash{$net}) {
+	for my $fullname (keys %{$gate_signals_hash{$net}}) {
 		$orig_net_names{$fullname} = 1;
 	}
 	for my $net (sort keys %orig_net_names) {
-- 
cgit v1.2.3


From e64456f92025c26f8b66e77901f78eca726d856a Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Marcelina=20Ko=C5=9Bcielnicka?= <mwk@0x04.net>
Date: Thu, 21 Oct 2021 02:58:10 +0200
Subject: extract_reduce: Refactor and fix input signal construction.

Fixes #3047.
---
 tests/opt/bug3047.ys | 12 ++++++++++++
 1 file changed, 12 insertions(+)
 create mode 100644 tests/opt/bug3047.ys

(limited to 'tests')

diff --git a/tests/opt/bug3047.ys b/tests/opt/bug3047.ys
new file mode 100644
index 000000000..6713877ce
--- /dev/null
+++ b/tests/opt/bug3047.ys
@@ -0,0 +1,12 @@
+read_verilog << EOT
+
+module test (A, B, C, D, Y);
+  input A, B, C, D;
+  output Y;
+  assign Y = A^B^C^D^A;
+endmodule
+
+EOT
+
+techmap
+equiv_opt -assert extract_reduce
-- 
cgit v1.2.3


From e833c6a418103feb30f0cc3e5c482da00ee9f820 Mon Sep 17 00:00:00 2001
From: Zachary Snow <zach@zachjs.com>
Date: Tue, 19 Oct 2021 18:46:26 -0600
Subject: verilog: use derived module info to elaborate cell connections

- Attempt to lookup a derived module if it potentially contains a port
  connection with elaboration ambiguities
- Mark the cell if module has not yet been derived
- This can be extended to implement automatic hierarchical port
  connections in a future change
---
 tests/simple/memwr_port_connection.sv | 13 +++++++++++++
 tests/simple/signed_full_slice.v      | 29 +++++++++++++++++++++++++++++
 tests/verilog/unbased_unsized_tern.sv | 31 +++++++++++++++++++++++++++++++
 tests/verilog/unbased_unsized_tern.ys |  6 ++++++
 4 files changed, 79 insertions(+)
 create mode 100644 tests/simple/memwr_port_connection.sv
 create mode 100644 tests/simple/signed_full_slice.v
 create mode 100644 tests/verilog/unbased_unsized_tern.sv
 create mode 100644 tests/verilog/unbased_unsized_tern.ys

(limited to 'tests')

diff --git a/tests/simple/memwr_port_connection.sv b/tests/simple/memwr_port_connection.sv
new file mode 100644
index 000000000..5bf414e08
--- /dev/null
+++ b/tests/simple/memwr_port_connection.sv
@@ -0,0 +1,13 @@
+module producer(
+    output logic [3:0] out
+);
+    assign out = 4'hA;
+endmodule
+
+module top(
+    output logic [3:0] out
+);
+    logic [3:0] v[0:0];
+    producer p(v[0]);
+    assign out = v[0];
+endmodule
diff --git a/tests/simple/signed_full_slice.v b/tests/simple/signed_full_slice.v
new file mode 100644
index 000000000..f8a331578
--- /dev/null
+++ b/tests/simple/signed_full_slice.v
@@ -0,0 +1,29 @@
+module pass_through_a(
+    input wire [31:0] inp,
+    output wire [31:0] out
+);
+    assign out[31:0] = inp[31:0];
+endmodule
+
+module top_a(
+    input wire signed [31:0] inp,
+    output wire signed [31:0] out
+);
+    pass_through_a pt(inp[31:0], out[31:0]);
+endmodule
+
+// tests both module declaration orderings
+
+module top_b(
+    input wire signed [31:0] inp,
+    output wire signed [31:0] out
+);
+    pass_through_b pt(inp[31:0], out[31:0]);
+endmodule
+
+module pass_through_b(
+    input wire [31:0] inp,
+    output wire [31:0] out
+);
+    assign out[31:0] = inp[31:0];
+endmodule
diff --git a/tests/verilog/unbased_unsized_tern.sv b/tests/verilog/unbased_unsized_tern.sv
new file mode 100644
index 000000000..ad8493394
--- /dev/null
+++ b/tests/verilog/unbased_unsized_tern.sv
@@ -0,0 +1,31 @@
+module pass_through #(
+	parameter WIDTH = 1
+) (
+	input logic [WIDTH-1:0] inp,
+	output logic [WIDTH-1:0] out
+);
+	assign out = inp;
+endmodule
+
+module gate (
+	input logic inp,
+	output logic [63:0]
+		out1, out2, out3, out4
+);
+	pass_through #(40) pt1('1, out1);
+	pass_through #(40) pt2(inp ? '1 : '0, out2);
+	pass_through #(40) pt3(inp ? '1 : 2'b10, out3);
+	pass_through #(40) pt4(inp ? '1 : inp, out4);
+endmodule
+
+module gold (
+	input logic inp,
+	output logic [63:0]
+		out1, out2, out3, out4
+);
+	localparam ONES = 40'hFF_FFFF_FFFF;
+	pass_through #(40) pt1(ONES, out1);
+	pass_through #(40) pt2(inp ? ONES : 0, out2);
+	pass_through #(40) pt3(inp ? ONES : 2'sb10, out3);
+	pass_through #(40) pt4(inp ? ONES : inp, out4);
+endmodule
diff --git a/tests/verilog/unbased_unsized_tern.ys b/tests/verilog/unbased_unsized_tern.ys
new file mode 100644
index 000000000..5ef63c559
--- /dev/null
+++ b/tests/verilog/unbased_unsized_tern.ys
@@ -0,0 +1,6 @@
+read_verilog -sv unbased_unsized_tern.sv
+hierarchy
+proc
+equiv_make gold gate equiv
+equiv_simple
+equiv_status -assert
-- 
cgit v1.2.3


From 0a0df8d38c8ef74b95d9649be5a78c18a928bf4d Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Marcelina=20Ko=C5=9Bcielnicka?= <mwk@0x04.net>
Date: Wed, 27 Oct 2021 10:14:07 +0200
Subject: dfflegalize: Refactor, add aldff support.

---
 tests/techmap/dfflegalize_adff_init.ys     | 26 ++++++++-----------
 tests/techmap/dfflegalize_adlatch_init.ys  |  4 +--
 tests/techmap/dfflegalize_dff.ys           | 17 ++++---------
 tests/techmap/dfflegalize_dff_init.ys      | 40 +++++++++---------------------
 tests/techmap/dfflegalize_dlatch_const.ys  |  8 +++---
 tests/techmap/dfflegalize_dlatchsr_init.ys |  8 +++---
 tests/techmap/dfflegalize_minsrst.ys       |  4 +--
 tests/techmap/dfflegalize_sr.ys            |  2 +-
 tests/techmap/dfflegalize_sr_init.ys       | 10 ++++----
 9 files changed, 46 insertions(+), 73 deletions(-)

(limited to 'tests')

diff --git a/tests/techmap/dfflegalize_adff_init.ys b/tests/techmap/dfflegalize_adff_init.ys
index 7764e15a5..27798ac52 100644
--- a/tests/techmap/dfflegalize_adff_init.ys
+++ b/tests/techmap/dfflegalize_adff_init.ys
@@ -144,9 +144,9 @@ design -load orig
 dfflegalize -cell $_DFFE_PP0P_ 0 -cell $_DLATCH_P_ 1
 
 select -assert-count 2 adff0/t:$_NOT_
-select -assert-count 16 adff1/t:$_NOT_
+select -assert-count 13 adff1/t:$_NOT_
 select -assert-count 3 adffe0/t:$_NOT_
-select -assert-count 22 adffe1/t:$_NOT_
+select -assert-count 18 adffe1/t:$_NOT_
 select -assert-count 0 adff0/t:$_MUX_
 select -assert-count 3 adff1/t:$_MUX_
 select -assert-count 0 adffe0/t:$_MUX_
@@ -164,9 +164,9 @@ select -assert-none t:$_DFFE_PP0P_ t:$_DLATCH_P_ t:$_MUX_ t:$_NOT_ top/* %% %n t
 design -load orig
 dfflegalize -cell $_DFFE_PP0P_ 1 -cell $_DLATCH_P_ 1
 
-select -assert-count 16 adff0/t:$_NOT_
+select -assert-count 13 adff0/t:$_NOT_
 select -assert-count 8 adff1/t:$_NOT_
-select -assert-count 22 adffe0/t:$_NOT_
+select -assert-count 18 adffe0/t:$_NOT_
 select -assert-count 11 adffe1/t:$_NOT_
 select -assert-count 3 adff0/t:$_MUX_
 select -assert-count 0 adff1/t:$_MUX_
@@ -185,31 +185,27 @@ select -assert-none t:$_DFFE_PP0P_ t:$_DLATCH_P_ t:$_MUX_ t:$_NOT_ top/* %% %n t
 design -load orig
 dfflegalize -cell $_DFFE_PP1P_ 0 -cell $_DLATCH_P_ 1
 
-select -assert-count 16 adff0/t:$_NOT_
+select -assert-count 10 adff0/t:$_NOT_
 select -assert-count 2 adff1/t:$_NOT_
-select -assert-count 22 adffe0/t:$_NOT_
+select -assert-count 14 adffe0/t:$_NOT_
 select -assert-count 3 adffe1/t:$_NOT_
 select -assert-count 3 adff0/t:$_MUX_
 select -assert-count 0 adff1/t:$_MUX_
 select -assert-count 4 adffe0/t:$_MUX_
 select -assert-count 0 adffe1/t:$_MUX_
-select -assert-count 6 adff0/t:$_DFFE_PP1P_
+select -assert-count 9 adff0/t:$_DFFE_PP1P_
 select -assert-count 3 adff1/t:$_DFFE_PP1P_
-select -assert-count 8 adffe0/t:$_DFFE_PP1P_
+select -assert-count 12 adffe0/t:$_DFFE_PP1P_
 select -assert-count 4 adffe1/t:$_DFFE_PP1P_
-select -assert-count 3 adff0/t:$_DLATCH_P_
-select -assert-count 0 adff1/t:$_DLATCH_P_
-select -assert-count 4 adffe0/t:$_DLATCH_P_
-select -assert-count 0 adffe1/t:$_DLATCH_P_
-select -assert-none t:$_DFFE_PP1P_ t:$_DLATCH_P_ t:$_MUX_ t:$_NOT_ top/* %% %n t:* %i
+select -assert-none t:$_DFFE_PP1P_ t:$_MUX_ t:$_NOT_ top/* %% %n t:* %i
 
 design -load orig
 dfflegalize -cell $_DFFE_PP1P_ 1 -cell $_DLATCH_P_ 1
 
 select -assert-count 8 adff0/t:$_NOT_
-select -assert-count 16 adff1/t:$_NOT_
+select -assert-count 13 adff1/t:$_NOT_
 select -assert-count 11 adffe0/t:$_NOT_
-select -assert-count 22 adffe1/t:$_NOT_
+select -assert-count 18 adffe1/t:$_NOT_
 select -assert-count 0 adff0/t:$_MUX_
 select -assert-count 3 adff1/t:$_MUX_
 select -assert-count 0 adffe0/t:$_MUX_
diff --git a/tests/techmap/dfflegalize_adlatch_init.ys b/tests/techmap/dfflegalize_adlatch_init.ys
index 7b22ea0c0..a55082d1d 100644
--- a/tests/techmap/dfflegalize_adlatch_init.ys
+++ b/tests/techmap/dfflegalize_adlatch_init.ys
@@ -45,7 +45,7 @@ select -assert-none t:$_DLATCH_PP0_ t:$_MUX_ t:$_NOT_ top/* %% %n t:* %i
 design -load orig
 dfflegalize -cell $_DLATCH_PP0_ 1
 
-select -assert-count 16 adlatch0/t:$_NOT_
+select -assert-count 13 adlatch0/t:$_NOT_
 select -assert-count 8 adlatch1/t:$_NOT_
 select -assert-count 3 adlatch0/t:$_MUX_
 select -assert-count 0 adlatch1/t:$_MUX_
@@ -68,7 +68,7 @@ design -load orig
 dfflegalize -cell $_DLATCH_PP1_ 1
 
 select -assert-count 8 adlatch0/t:$_NOT_
-select -assert-count 16 adlatch1/t:$_NOT_
+select -assert-count 13 adlatch1/t:$_NOT_
 select -assert-count 0 adlatch0/t:$_MUX_
 select -assert-count 3 adlatch1/t:$_MUX_
 select -assert-count 3 adlatch0/t:$_DLATCH_PP1_
diff --git a/tests/techmap/dfflegalize_dff.ys b/tests/techmap/dfflegalize_dff.ys
index 63ab47865..4022da5f4 100644
--- a/tests/techmap/dfflegalize_dff.ys
+++ b/tests/techmap/dfflegalize_dff.ys
@@ -237,25 +237,18 @@ select -assert-count 2 sdff0/t:$_NOT_
 select -assert-count 8 sdff1/t:$_NOT_
 select -assert-count 2 sdffe0/t:$_NOT_
 select -assert-count 10 sdffe1/t:$_NOT_
-select -assert-count 2 sdffce0/t:$_NOT_
-select -assert-count 10 sdffce1/t:$_NOT_
+select -assert-count 1 sdffce0/t:$_NOT_
+select -assert-count 1 sdffce1/t:$_NOT_
 select -assert-count 0 dff/t:$_MUX_
 select -assert-count 3 dffe/t:$_MUX_
 select -assert-count 0 sdff0/t:$_MUX_
 select -assert-count 0 sdff1/t:$_MUX_
 select -assert-count 4 sdffe0/t:$_MUX_
 select -assert-count 4 sdffe1/t:$_MUX_
-select -assert-count 4 sdffce0/t:$_MUX_
-select -assert-count 4 sdffce1/t:$_MUX_
-select -assert-count 0 t:$_AND_ t:$_ORNOT_ t:$_ANDNOT_ %% sdffce0/* sdffce1/* %u %n %i
-select -assert-count 2 sdffce0/t:$_AND_
-select -assert-count 2 sdffce1/t:$_AND_
-select -assert-count 1 sdffce0/t:$_ORNOT_
-select -assert-count 1 sdffce1/t:$_ORNOT_
-select -assert-count 1 sdffce0/t:$_ANDNOT_
-select -assert-count 1 sdffce1/t:$_ANDNOT_
+select -assert-count 8 sdffce0/t:$_MUX_
+select -assert-count 8 sdffce1/t:$_MUX_
 select -assert-count 27 t:$_SDFF_PP0_
-select -assert-none t:$_SDFF_PP0_ t:$_MUX_ t:$_NOT_ t:$_AND_ t:$_ORNOT_ t:$_ANDNOT_ top/* %% %n t:* %i
+select -assert-none t:$_SDFF_PP0_ t:$_MUX_ t:$_NOT_ top/* %% %n t:* %i
 
 
 # Convert everything to SDFFEs.
diff --git a/tests/techmap/dfflegalize_dff_init.ys b/tests/techmap/dfflegalize_dff_init.ys
index 741ac39d0..ccde4c324 100644
--- a/tests/techmap/dfflegalize_dff_init.ys
+++ b/tests/techmap/dfflegalize_dff_init.ys
@@ -476,7 +476,7 @@ select -assert-count 2 sdff0/t:$_NOT_
 select -assert-count 1 sdff1/t:$_NOT_
 select -assert-count 2 sdffe0/t:$_NOT_
 select -assert-count 1 sdffe1/t:$_NOT_
-select -assert-count 2 sdffce0/t:$_NOT_
+select -assert-count 1 sdffce0/t:$_NOT_
 select -assert-count 1 sdffce1/t:$_NOT_
 select -assert-count 0 dff/t:$_MUX_
 select -assert-count 3 dffe/t:$_MUX_
@@ -484,14 +484,10 @@ select -assert-count 0 sdff0/t:$_MUX_
 select -assert-count 3 sdff1/t:$_MUX_
 select -assert-count 4 sdffe0/t:$_MUX_
 select -assert-count 8 sdffe1/t:$_MUX_
-select -assert-count 4 sdffce0/t:$_MUX_
+select -assert-count 8 sdffce0/t:$_MUX_
 select -assert-count 8 sdffce1/t:$_MUX_
-select -assert-count 0 t:$_AND_ t:$_ORNOT_ t:$_ANDNOT_ %% sdffce0/* %n %i
-select -assert-count 2 sdffce0/t:$_AND_
-select -assert-count 1 sdffce0/t:$_ORNOT_
-select -assert-count 1 sdffce0/t:$_ANDNOT_
 select -assert-count 27 t:$_SDFF_PP0_
-select -assert-none t:$_SDFF_PP0_ t:$_MUX_ t:$_NOT_ t:$_AND_ t:$_ORNOT_ t:$_ANDNOT_ top/* %% %n t:* %i
+select -assert-none t:$_SDFF_PP0_ t:$_MUX_ t:$_NOT_ top/* %% %n t:* %i
 
 design -load orig
 dfflegalize -cell $_SDFF_PP0_ 1
@@ -503,7 +499,7 @@ select -assert-count 8 sdff1/t:$_NOT_
 select -assert-count 9 sdffe0/t:$_NOT_
 select -assert-count 10 sdffe1/t:$_NOT_
 select -assert-count 9 sdffce0/t:$_NOT_
-select -assert-count 10 sdffce1/t:$_NOT_
+select -assert-count 9 sdffce1/t:$_NOT_
 select -assert-count 0 dff/t:$_MUX_
 select -assert-count 3 dffe/t:$_MUX_
 select -assert-count 3 sdff0/t:$_MUX_
@@ -511,13 +507,9 @@ select -assert-count 0 sdff1/t:$_MUX_
 select -assert-count 8 sdffe0/t:$_MUX_
 select -assert-count 4 sdffe1/t:$_MUX_
 select -assert-count 8 sdffce0/t:$_MUX_
-select -assert-count 4 sdffce1/t:$_MUX_
-select -assert-count 0 t:$_AND_ t:$_ORNOT_ t:$_ANDNOT_ %% sdffce1/* %n %i
-select -assert-count 2 sdffce1/t:$_AND_
-select -assert-count 1 sdffce1/t:$_ORNOT_
-select -assert-count 1 sdffce1/t:$_ANDNOT_
+select -assert-count 8 sdffce1/t:$_MUX_
 select -assert-count 27 t:$_SDFF_PP0_
-select -assert-none t:$_SDFF_PP0_ t:$_MUX_ t:$_NOT_ t:$_AND_ t:$_ORNOT_ t:$_ANDNOT_ top/* %% %n t:* %i
+select -assert-none t:$_SDFF_PP0_ t:$_MUX_ t:$_NOT_ top/* %% %n t:* %i
 
 design -load orig
 dfflegalize -cell $_SDFF_PP1_ 0
@@ -529,7 +521,7 @@ select -assert-count 2 sdff1/t:$_NOT_
 select -assert-count 1 sdffe0/t:$_NOT_
 select -assert-count 2 sdffe1/t:$_NOT_
 select -assert-count 1 sdffce0/t:$_NOT_
-select -assert-count 2 sdffce1/t:$_NOT_
+select -assert-count 1 sdffce1/t:$_NOT_
 select -assert-count 0 dff/t:$_MUX_
 select -assert-count 3 dffe/t:$_MUX_
 select -assert-count 3 sdff0/t:$_MUX_
@@ -537,13 +529,9 @@ select -assert-count 0 sdff1/t:$_MUX_
 select -assert-count 8 sdffe0/t:$_MUX_
 select -assert-count 4 sdffe1/t:$_MUX_
 select -assert-count 8 sdffce0/t:$_MUX_
-select -assert-count 4 sdffce1/t:$_MUX_
-select -assert-count 0 t:$_AND_ t:$_ORNOT_ t:$_ANDNOT_ %% sdffce1/* %n %i
-select -assert-count 2 sdffce1/t:$_AND_
-select -assert-count 1 sdffce1/t:$_ORNOT_
-select -assert-count 1 sdffce1/t:$_ANDNOT_
+select -assert-count 8 sdffce1/t:$_MUX_
 select -assert-count 27 t:$_SDFF_PP1_
-select -assert-none t:$_SDFF_PP1_ t:$_MUX_ t:$_NOT_ t:$_AND_ t:$_ORNOT_ t:$_ANDNOT_ top/* %% %n t:* %i
+select -assert-none t:$_SDFF_PP1_ t:$_MUX_ t:$_NOT_ top/* %% %n t:* %i
 
 design -load orig
 dfflegalize -cell $_SDFF_PP1_ 1
@@ -554,7 +542,7 @@ select -assert-count 8 sdff0/t:$_NOT_
 select -assert-count 7 sdff1/t:$_NOT_
 select -assert-count 10 sdffe0/t:$_NOT_
 select -assert-count 9 sdffe1/t:$_NOT_
-select -assert-count 10 sdffce0/t:$_NOT_
+select -assert-count 9 sdffce0/t:$_NOT_
 select -assert-count 9 sdffce1/t:$_NOT_
 select -assert-count 0 dff/t:$_MUX_
 select -assert-count 3 dffe/t:$_MUX_
@@ -562,14 +550,10 @@ select -assert-count 0 sdff0/t:$_MUX_
 select -assert-count 3 sdff1/t:$_MUX_
 select -assert-count 4 sdffe0/t:$_MUX_
 select -assert-count 8 sdffe1/t:$_MUX_
-select -assert-count 4 sdffce0/t:$_MUX_
+select -assert-count 8 sdffce0/t:$_MUX_
 select -assert-count 8 sdffce1/t:$_MUX_
-select -assert-count 0 t:$_AND_ t:$_ORNOT_ t:$_ANDNOT_ %% sdffce0/* %n %i
-select -assert-count 2 sdffce0/t:$_AND_
-select -assert-count 1 sdffce0/t:$_ORNOT_
-select -assert-count 1 sdffce0/t:$_ANDNOT_
 select -assert-count 27 t:$_SDFF_PP1_
-select -assert-none t:$_SDFF_PP1_ t:$_MUX_ t:$_NOT_ t:$_AND_ t:$_ORNOT_ t:$_ANDNOT_ top/* %% %n t:* %i
+select -assert-none t:$_SDFF_PP1_ t:$_MUX_ t:$_NOT_ top/* %% %n t:* %i
 
 
 # Convert everything to SDFFEs.
diff --git a/tests/techmap/dfflegalize_dlatch_const.ys b/tests/techmap/dfflegalize_dlatch_const.ys
index f30a534fd..159692249 100644
--- a/tests/techmap/dfflegalize_dlatch_const.ys
+++ b/tests/techmap/dfflegalize_dlatch_const.ys
@@ -24,14 +24,14 @@ equiv_opt -assert -multiclock dfflegalize -cell $_DFFSRE_PPPP_ 1
 design -load orig
 dfflegalize -cell $_DFF_PP0_ 01
 
-select -assert-count 12 t:$_NOT_
+select -assert-count 8 t:$_NOT_
 select -assert-count 8 t:$_DFF_PP0_
 select -assert-none t:$_DFF_PP0_ t:$_NOT_ %% %n t:* %i
 
 design -load orig
 dfflegalize -cell $_DFF_PP?_ 0
 
-select -assert-count 12 t:$_NOT_
+select -assert-count 8 t:$_NOT_
 select -assert-count 4 t:$_DFF_PP0_
 select -assert-count 4 t:$_DFF_PP1_
 select -assert-none t:$_DFF_PP0_ t:$_DFF_PP1_ t:$_NOT_ %% %n t:* %i
@@ -41,13 +41,13 @@ select -assert-none t:$_DFF_PP0_ t:$_DFF_PP1_ t:$_NOT_ %% %n t:* %i
 design -load orig
 dfflegalize -cell $_DFFSRE_PPPP_ 0
 
-select -assert-count 12 t:$_NOT_
+select -assert-count 8 t:$_NOT_
 select -assert-count 8 t:$_DFFSRE_PPPP_
 select -assert-none t:$_DFFSRE_PPPP_ t:$_NOT_ %% %n t:* %i
 
 design -load orig
 dfflegalize -cell $_DFFSRE_PPPP_ 1
 
-select -assert-count 12 t:$_NOT_
+select -assert-count 8 t:$_NOT_
 select -assert-count 8 t:$_DFFSRE_PPPP_
 select -assert-none t:$_DFFSRE_PPPP_ t:$_NOT_ %% %n t:* %i
diff --git a/tests/techmap/dfflegalize_dlatchsr_init.ys b/tests/techmap/dfflegalize_dlatchsr_init.ys
index 2d33634d1..b38a9eb3b 100644
--- a/tests/techmap/dfflegalize_dlatchsr_init.ys
+++ b/tests/techmap/dfflegalize_dlatchsr_init.ys
@@ -66,8 +66,8 @@ select -assert-none t:$_DLATCH_PP0_ t:$_MUX_ t:$_NOT_ t:$_AND_ t:$_ANDNOT_ t:$_O
 design -load orig
 dfflegalize -cell $_DLATCH_PP1_ 0
 
-select -assert-count 22 dlatchsr0/t:$_NOT_
-select -assert-count 26 dlatchsr1/t:$_NOT_
+select -assert-count 18 dlatchsr0/t:$_NOT_
+select -assert-count 22 dlatchsr1/t:$_NOT_
 select -assert-count 4 dlatchsr0/t:$_MUX_
 select -assert-count 4 dlatchsr1/t:$_MUX_
 select -assert-count 12 dlatchsr0/t:$_DLATCH_PP1_
@@ -81,8 +81,8 @@ select -assert-none t:$_DLATCH_PP1_ t:$_MUX_ t:$_NOT_ t:$_AND_ t:$_ANDNOT_ t:$_O
 design -load orig
 dfflegalize -cell $_DLATCH_PP1_ 1
 
-select -assert-count 22 dlatchsr0/t:$_NOT_
-select -assert-count 26 dlatchsr1/t:$_NOT_
+select -assert-count 18 dlatchsr0/t:$_NOT_
+select -assert-count 22 dlatchsr1/t:$_NOT_
 select -assert-count 4 dlatchsr0/t:$_MUX_
 select -assert-count 4 dlatchsr1/t:$_MUX_
 select -assert-count 12 dlatchsr0/t:$_DLATCH_PP1_
diff --git a/tests/techmap/dfflegalize_minsrst.ys b/tests/techmap/dfflegalize_minsrst.ys
index 0fc40dc08..689066147 100644
--- a/tests/techmap/dfflegalize_minsrst.ys
+++ b/tests/techmap/dfflegalize_minsrst.ys
@@ -23,9 +23,9 @@ design -load postopt
 
 select -assert-count 5 t:$_SDFF_PP0_
 select -assert-count 1 t:$_SDFF_PP1_
-select -assert-count 3 t:$_SDFFE_PP0P_
+select -assert-count 1 t:$_SDFFE_PP0P_
 select -assert-count 1 t:$_SDFFE_PP1P_
-select -assert-count 1 t:$_SDFFCE_PP0P_
+select -assert-count 3 t:$_SDFFCE_PP0P_
 select -assert-count 1 t:$_SDFFCE_PP1P_
 select -assert-count 8 t:$_MUX_
 select -assert-count 0 n:ff0 %ci %ci t:$_MUX_ %i
diff --git a/tests/techmap/dfflegalize_sr.ys b/tests/techmap/dfflegalize_sr.ys
index 27e83be91..ee59a6e3c 100644
--- a/tests/techmap/dfflegalize_sr.ys
+++ b/tests/techmap/dfflegalize_sr.ys
@@ -39,7 +39,7 @@ select -assert-none t:$_DLATCH_PP0_ t:$_NOT_ %% %n t:* %i
 design -load orig
 dfflegalize -cell $_DLATCH_PP1_ x
 
-select -assert-count 8 t:$_NOT_
+select -assert-count 5 t:$_NOT_
 select -assert-count 3 t:$_DLATCH_PP1_
 select -assert-none t:$_DLATCH_PP1_ t:$_NOT_ %% %n t:* %i
 
diff --git a/tests/techmap/dfflegalize_sr_init.ys b/tests/techmap/dfflegalize_sr_init.ys
index 52b797b9e..9d724de29 100644
--- a/tests/techmap/dfflegalize_sr_init.ys
+++ b/tests/techmap/dfflegalize_sr_init.ys
@@ -12,7 +12,7 @@ $_SR_PN_ ff1 (.R(R), .S(S), .Q(Q[1]));
 $_SR_NP_ ff2 (.R(R), .S(S), .Q(Q[2]));
 endmodule
 
-module top(input C, E, R, D, output [5:0] Q);
+module top(input R, S, output [5:0] Q);
 sr0 sr0_(.S(S), .R(R), .Q(Q[2:0]));
 sr1 sr1_(.S(S), .R(R), .Q(Q[5:3]));
 endmodule
@@ -103,8 +103,8 @@ select -assert-none t:$_DLATCH_PP0_ t:$_NOT_ t:$_ANDNOT_ t:$_OR_ t:$_AND_ top/*
 design -load orig
 dfflegalize -cell $_DLATCH_PP1_ 0
 
-select -assert-count 11 sr0/t:$_NOT_
-select -assert-count 8 sr1/t:$_NOT_
+select -assert-count 8 sr0/t:$_NOT_
+select -assert-count 5 sr1/t:$_NOT_
 select -assert-count 3 sr0/t:$_DLATCH_PP1_
 select -assert-count 3 sr1/t:$_DLATCH_PP1_
 select -assert-count 1 sr0/t:$_ANDNOT_
@@ -118,8 +118,8 @@ select -assert-none t:$_DLATCH_PP1_ t:$_NOT_ t:$_ANDNOT_ t:$_OR_ t:$_AND_ top/*
 design -load orig
 dfflegalize -cell $_DLATCH_PP1_ 1
 
-select -assert-count 8 sr0/t:$_NOT_
-select -assert-count 11 sr1/t:$_NOT_
+select -assert-count 5 sr0/t:$_NOT_
+select -assert-count 8 sr1/t:$_NOT_
 select -assert-count 3 sr0/t:$_DLATCH_PP1_
 select -assert-count 3 sr1/t:$_DLATCH_PP1_
 select -assert-count 0 sr0/t:$_ANDNOT_
-- 
cgit v1.2.3


From 54c79af64f8c84b8a9d8c1be2be5a6862910c2bb Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Marcelina=20Ko=C5=9Bcielnicka?= <mwk@0x04.net>
Date: Wed, 27 Oct 2021 13:14:34 +0200
Subject: dfflegalize: Add tests targetting aldff.

---
 tests/techmap/dfflegalize_adff.ys        | 32 +++++++++++
 tests/techmap/dfflegalize_adff_init.ys   | 58 +++++++++++++++++++
 tests/techmap/dfflegalize_dff.ys         | 52 +++++++++++++++++
 tests/techmap/dfflegalize_dff_init.ys    | 98 ++++++++++++++++++++++++++++++++
 tests/techmap/dfflegalize_dlatch.ys      | 22 +++++++
 tests/techmap/dfflegalize_dlatch_init.ys | 38 +++++++++++++
 tests/techmap/dfflegalize_inv.ys         | 27 ++++++---
 7 files changed, 320 insertions(+), 7 deletions(-)

(limited to 'tests')

diff --git a/tests/techmap/dfflegalize_adff.ys b/tests/techmap/dfflegalize_adff.ys
index 135ae0ab7..fc579e7d6 100644
--- a/tests/techmap/dfflegalize_adff.ys
+++ b/tests/techmap/dfflegalize_adff.ys
@@ -39,6 +39,8 @@ design -save orig
 flatten
 equiv_opt -assert -multiclock dfflegalize -cell $_DFF_PP0_ x
 equiv_opt -assert -multiclock dfflegalize -cell $_DFFE_PP0P_ x
+equiv_opt -assert -multiclock dfflegalize -cell $_ALDFF_PP_ x
+equiv_opt -assert -multiclock dfflegalize -cell $_ALDFFE_PPP_ x
 equiv_opt -assert -multiclock dfflegalize -cell $_DFFSR_PPP_ x
 equiv_opt -assert -multiclock dfflegalize -cell $_DFFSRE_PPPP_ x
 
@@ -73,6 +75,36 @@ select -assert-count 14 t:$_DFFE_PP0P_
 select -assert-none t:$_DFFE_PP0P_ t:$_NOT_ top/* %% %n t:* %i
 
 
+# Convert everything to ALDFFs.
+
+design -load orig
+dfflegalize -cell $_ALDFF_PP_ x
+
+select -assert-count 2 adff0/t:$_NOT_
+select -assert-count 2 adff1/t:$_NOT_
+select -assert-count 2 adffe0/t:$_NOT_
+select -assert-count 2 adffe1/t:$_NOT_
+select -assert-count 0 adff0/t:$_MUX_
+select -assert-count 0 adff1/t:$_MUX_
+select -assert-count 4 adffe0/t:$_MUX_
+select -assert-count 4 adffe1/t:$_MUX_
+select -assert-count 14 t:$_ALDFF_PP_
+select -assert-none t:$_ALDFF_PP_ t:$_MUX_ t:$_NOT_ top/* %% %n t:* %i
+
+
+# Convert everything to ALDFFEs.
+
+design -load orig
+dfflegalize -cell $_ALDFFE_PPP_ x
+
+select -assert-count 2 adff0/t:$_NOT_
+select -assert-count 2 adff1/t:$_NOT_
+select -assert-count 3 adffe0/t:$_NOT_
+select -assert-count 3 adffe1/t:$_NOT_
+select -assert-count 14 t:$_ALDFFE_PPP_
+select -assert-none t:$_ALDFFE_PPP_ t:$_NOT_ top/* %% %n t:* %i
+
+
 # Convert everything to DFFSRs.
 
 design -load orig
diff --git a/tests/techmap/dfflegalize_adff_init.ys b/tests/techmap/dfflegalize_adff_init.ys
index 27798ac52..25ed59307 100644
--- a/tests/techmap/dfflegalize_adff_init.ys
+++ b/tests/techmap/dfflegalize_adff_init.ys
@@ -45,6 +45,10 @@ equiv_opt -assert -multiclock dfflegalize -cell $_DFFE_PP0P_ 0 -cell $_DLATCH_P_
 equiv_opt -assert -multiclock dfflegalize -cell $_DFFE_PP0P_ 1 -cell $_DLATCH_P_ 1
 equiv_opt -assert -multiclock dfflegalize -cell $_DFFE_PP1P_ 0 -cell $_DLATCH_P_ 1
 equiv_opt -assert -multiclock dfflegalize -cell $_DFFE_PP1P_ 1 -cell $_DLATCH_P_ 1
+equiv_opt -assert -multiclock dfflegalize -cell $_ALDFF_PP_ 0
+equiv_opt -assert -multiclock dfflegalize -cell $_ALDFF_PP_ 1
+equiv_opt -assert -multiclock dfflegalize -cell $_ALDFFE_PPP_ 0
+equiv_opt -assert -multiclock dfflegalize -cell $_ALDFFE_PPP_ 1
 equiv_opt -assert -multiclock dfflegalize -cell $_DFFSR_PPP_ 0
 equiv_opt -assert -multiclock dfflegalize -cell $_DFFSR_PPP_ 1
 equiv_opt -assert -multiclock dfflegalize -cell $_DFFSRE_PPPP_ 0
@@ -221,6 +225,60 @@ select -assert-count 4 adffe1/t:$_DLATCH_P_
 select -assert-none t:$_DFFE_PP1P_ t:$_DLATCH_P_ t:$_MUX_ t:$_NOT_ top/* %% %n t:* %i
 
 
+# Convert everything to ALDFFs.
+
+design -load orig
+dfflegalize -cell $_ALDFF_PP_ 0
+
+select -assert-count 2 adff0/t:$_NOT_
+select -assert-count 2 adff1/t:$_NOT_
+select -assert-count 2 adffe0/t:$_NOT_
+select -assert-count 2 adffe1/t:$_NOT_
+select -assert-count 0 adff0/t:$_MUX_
+select -assert-count 0 adff1/t:$_MUX_
+select -assert-count 4 adffe0/t:$_MUX_
+select -assert-count 4 adffe1/t:$_MUX_
+select -assert-count 14 t:$_ALDFF_PP_
+select -assert-none t:$_ALDFF_PP_ t:$_MUX_ t:$_NOT_ top/* %% %n t:* %i
+
+design -load orig
+dfflegalize -cell $_ALDFF_PP_ 1
+
+select -assert-count 8 adff0/t:$_NOT_
+select -assert-count 8 adff1/t:$_NOT_
+select -assert-count 10 adffe0/t:$_NOT_
+select -assert-count 10 adffe1/t:$_NOT_
+select -assert-count 0 adff0/t:$_MUX_
+select -assert-count 0 adff1/t:$_MUX_
+select -assert-count 4 adffe0/t:$_MUX_
+select -assert-count 4 adffe1/t:$_MUX_
+select -assert-count 14 t:$_ALDFF_PP_
+select -assert-none t:$_ALDFF_PP_ t:$_MUX_ t:$_NOT_ top/* %% %n t:* %i
+
+
+# Convert everything to ALDFFEs.
+
+design -load orig
+dfflegalize -cell $_ALDFFE_PPP_ 0
+
+select -assert-count 2 adff0/t:$_NOT_
+select -assert-count 2 adff1/t:$_NOT_
+select -assert-count 3 adffe0/t:$_NOT_
+select -assert-count 3 adffe1/t:$_NOT_
+select -assert-count 14 t:$_ALDFFE_PPP_
+select -assert-none t:$_ALDFFE_PPP_ t:$_NOT_ top/* %% %n t:* %i
+
+design -load orig
+dfflegalize -cell $_ALDFFE_PPP_ 1
+
+select -assert-count 8 adff0/t:$_NOT_
+select -assert-count 8 adff1/t:$_NOT_
+select -assert-count 11 adffe0/t:$_NOT_
+select -assert-count 11 adffe1/t:$_NOT_
+select -assert-count 14 t:$_ALDFFE_PPP_
+select -assert-none t:$_ALDFFE_PPP_ t:$_NOT_ top/* %% %n t:* %i
+
+
 # Convert everything to DFFSRs.
 
 design -load orig
diff --git a/tests/techmap/dfflegalize_dff.ys b/tests/techmap/dfflegalize_dff.ys
index 4022da5f4..374289678 100644
--- a/tests/techmap/dfflegalize_dff.ys
+++ b/tests/techmap/dfflegalize_dff.ys
@@ -70,6 +70,8 @@ equiv_opt -assert -multiclock dfflegalize -cell $_DFF_P_ x
 equiv_opt -assert -multiclock dfflegalize -cell $_DFFE_PP_ x
 equiv_opt -assert -multiclock dfflegalize -cell $_DFF_PP0_ x
 equiv_opt -assert -multiclock dfflegalize -cell $_DFFE_PP0P_ x
+equiv_opt -assert -multiclock dfflegalize -cell $_ALDFF_PP_ x
+equiv_opt -assert -multiclock dfflegalize -cell $_ALDFFE_PPP_ x
 equiv_opt -assert -multiclock dfflegalize -cell $_DFFSR_PPP_ x
 equiv_opt -assert -multiclock dfflegalize -cell $_DFFSRE_PPPP_ x
 equiv_opt -assert -multiclock dfflegalize -cell $_SDFF_PP0_ x
@@ -176,6 +178,56 @@ select -assert-count 27 t:$_DFFE_PP0P_
 select -assert-none t:$_DFFE_PP0P_ t:$_MUX_ t:$_NOT_ top/* %% %n t:* %i
 
 
+# Convert everything to ALDFFs.
+
+design -load orig
+dfflegalize -cell $_ALDFF_PP_ x
+
+select -assert-count 1 dff/t:$_NOT_
+select -assert-count 1 dffe/t:$_NOT_
+select -assert-count 1 sdff0/t:$_NOT_
+select -assert-count 1 sdff1/t:$_NOT_
+select -assert-count 1 sdffe0/t:$_NOT_
+select -assert-count 1 sdffe1/t:$_NOT_
+select -assert-count 1 sdffce0/t:$_NOT_
+select -assert-count 1 sdffce1/t:$_NOT_
+select -assert-count 0 dff/t:$_MUX_
+select -assert-count 3 dffe/t:$_MUX_
+select -assert-count 3 sdff0/t:$_MUX_
+select -assert-count 3 sdff1/t:$_MUX_
+select -assert-count 8 sdffe0/t:$_MUX_
+select -assert-count 8 sdffe1/t:$_MUX_
+select -assert-count 8 sdffce0/t:$_MUX_
+select -assert-count 8 sdffce1/t:$_MUX_
+select -assert-count 27 t:$_ALDFF_PP_
+select -assert-none t:$_ALDFF_PP_ t:$_MUX_ t:$_NOT_ top/* %% %n t:* %i
+
+
+# Convert everything to ALDFFEs.
+
+design -load orig
+dfflegalize -cell $_ALDFFE_PPP_ x
+
+select -assert-count 1 dff/t:$_NOT_
+select -assert-count 2 dffe/t:$_NOT_
+select -assert-count 1 sdff0/t:$_NOT_
+select -assert-count 1 sdff1/t:$_NOT_
+select -assert-count 1 sdffe0/t:$_NOT_
+select -assert-count 1 sdffe1/t:$_NOT_
+select -assert-count 2 sdffce0/t:$_NOT_
+select -assert-count 2 sdffce1/t:$_NOT_
+select -assert-count 0 dff/t:$_MUX_
+select -assert-count 0 dffe/t:$_MUX_
+select -assert-count 3 sdff0/t:$_MUX_
+select -assert-count 3 sdff1/t:$_MUX_
+select -assert-count 8 sdffe0/t:$_MUX_
+select -assert-count 8 sdffe1/t:$_MUX_
+select -assert-count 4 sdffce0/t:$_MUX_
+select -assert-count 4 sdffce1/t:$_MUX_
+select -assert-count 27 t:$_ALDFFE_PPP_
+select -assert-none t:$_ALDFFE_PPP_ t:$_MUX_ t:$_NOT_ top/* %% %n t:* %i
+
+
 # Convert everything to DFFSRs.
 
 design -load orig
diff --git a/tests/techmap/dfflegalize_dff_init.ys b/tests/techmap/dfflegalize_dff_init.ys
index ccde4c324..a170249c7 100644
--- a/tests/techmap/dfflegalize_dff_init.ys
+++ b/tests/techmap/dfflegalize_dff_init.ys
@@ -78,6 +78,10 @@ equiv_opt -assert -multiclock dfflegalize -cell $_DFFE_PP0P_ 0
 equiv_opt -assert -multiclock dfflegalize -cell $_DFFE_PP0P_ 1
 equiv_opt -assert -multiclock dfflegalize -cell $_DFFE_PP1P_ 0
 equiv_opt -assert -multiclock dfflegalize -cell $_DFFE_PP1P_ 1
+equiv_opt -assert -multiclock dfflegalize -cell $_ALDFF_PP_ 0
+equiv_opt -assert -multiclock dfflegalize -cell $_ALDFF_PP_ 1
+equiv_opt -assert -multiclock dfflegalize -cell $_ALDFFE_PPP_ 0
+equiv_opt -assert -multiclock dfflegalize -cell $_ALDFFE_PPP_ 1
 equiv_opt -assert -multiclock dfflegalize -cell $_DFFSR_PPP_ 0
 equiv_opt -assert -multiclock dfflegalize -cell $_DFFSR_PPP_ 1
 equiv_opt -assert -multiclock dfflegalize -cell $_DFFSRE_PPPP_ 0
@@ -371,6 +375,100 @@ select -assert-count 27 t:$_DFFE_PP1P_
 select -assert-none t:$_DFFE_PP1P_ t:$_MUX_ t:$_NOT_ top/* %% %n t:* %i
 
 
+# Convert everything to ALDFFs.
+
+design -load orig
+dfflegalize -cell $_ALDFF_PP_ 0
+
+select -assert-count 1 dff/t:$_NOT_
+select -assert-count 1 dffe/t:$_NOT_
+select -assert-count 1 sdff0/t:$_NOT_
+select -assert-count 1 sdff1/t:$_NOT_
+select -assert-count 1 sdffe0/t:$_NOT_
+select -assert-count 1 sdffe1/t:$_NOT_
+select -assert-count 1 sdffce0/t:$_NOT_
+select -assert-count 1 sdffce1/t:$_NOT_
+select -assert-count 0 dff/t:$_MUX_
+select -assert-count 3 dffe/t:$_MUX_
+select -assert-count 3 sdff0/t:$_MUX_
+select -assert-count 3 sdff1/t:$_MUX_
+select -assert-count 8 sdffe0/t:$_MUX_
+select -assert-count 8 sdffe1/t:$_MUX_
+select -assert-count 8 sdffce0/t:$_MUX_
+select -assert-count 8 sdffce1/t:$_MUX_
+select -assert-count 27 t:$_ALDFF_PP_
+select -assert-none t:$_ALDFF_PP_ t:$_MUX_ t:$_NOT_ top/* %% %n t:* %i
+
+design -load orig
+dfflegalize -cell $_ALDFF_PP_ 1
+
+select -assert-count 5 dff/t:$_NOT_
+select -assert-count 7 dffe/t:$_NOT_
+select -assert-count 7 sdff0/t:$_NOT_
+select -assert-count 7 sdff1/t:$_NOT_
+select -assert-count 9 sdffe0/t:$_NOT_
+select -assert-count 9 sdffe1/t:$_NOT_
+select -assert-count 9 sdffce0/t:$_NOT_
+select -assert-count 9 sdffce1/t:$_NOT_
+select -assert-count 0 dff/t:$_MUX_
+select -assert-count 3 dffe/t:$_MUX_
+select -assert-count 3 sdff0/t:$_MUX_
+select -assert-count 3 sdff1/t:$_MUX_
+select -assert-count 8 sdffe0/t:$_MUX_
+select -assert-count 8 sdffe1/t:$_MUX_
+select -assert-count 8 sdffce0/t:$_MUX_
+select -assert-count 8 sdffce1/t:$_MUX_
+select -assert-count 27 t:$_ALDFF_PP_
+select -assert-none t:$_ALDFF_PP_ t:$_MUX_ t:$_NOT_ top/* %% %n t:* %i
+
+
+# Convert everything to ALDFFEs.
+
+design -load orig
+dfflegalize -cell $_ALDFFE_PPP_ 0
+
+select -assert-count 1 dff/t:$_NOT_
+select -assert-count 2 dffe/t:$_NOT_
+select -assert-count 1 sdff0/t:$_NOT_
+select -assert-count 1 sdff1/t:$_NOT_
+select -assert-count 1 sdffe0/t:$_NOT_
+select -assert-count 1 sdffe1/t:$_NOT_
+select -assert-count 2 sdffce0/t:$_NOT_
+select -assert-count 2 sdffce1/t:$_NOT_
+select -assert-count 0 dff/t:$_MUX_
+select -assert-count 0 dffe/t:$_MUX_
+select -assert-count 3 sdff0/t:$_MUX_
+select -assert-count 3 sdff1/t:$_MUX_
+select -assert-count 8 sdffe0/t:$_MUX_
+select -assert-count 8 sdffe1/t:$_MUX_
+select -assert-count 4 sdffce0/t:$_MUX_
+select -assert-count 4 sdffce1/t:$_MUX_
+select -assert-count 27 t:$_ALDFFE_PPP_
+select -assert-none t:$_ALDFFE_PPP_ t:$_MUX_ t:$_NOT_ top/* %% %n t:* %i
+
+design -load orig
+dfflegalize -cell $_ALDFFE_PPP_ 1
+
+select -assert-count 5 dff/t:$_NOT_
+select -assert-count 8 dffe/t:$_NOT_
+select -assert-count 7 sdff0/t:$_NOT_
+select -assert-count 7 sdff1/t:$_NOT_
+select -assert-count 9 sdffe0/t:$_NOT_
+select -assert-count 9 sdffe1/t:$_NOT_
+select -assert-count 10 sdffce0/t:$_NOT_
+select -assert-count 10 sdffce1/t:$_NOT_
+select -assert-count 0 dff/t:$_MUX_
+select -assert-count 0 dffe/t:$_MUX_
+select -assert-count 3 sdff0/t:$_MUX_
+select -assert-count 3 sdff1/t:$_MUX_
+select -assert-count 8 sdffe0/t:$_MUX_
+select -assert-count 8 sdffe1/t:$_MUX_
+select -assert-count 4 sdffce0/t:$_MUX_
+select -assert-count 4 sdffce1/t:$_MUX_
+select -assert-count 27 t:$_ALDFFE_PPP_
+select -assert-none t:$_ALDFFE_PPP_ t:$_MUX_ t:$_NOT_ top/* %% %n t:* %i
+
+
 # Convert everything to DFFSRs.
 
 design -load orig
diff --git a/tests/techmap/dfflegalize_dlatch.ys b/tests/techmap/dfflegalize_dlatch.ys
index b68ea741e..11683bc1a 100644
--- a/tests/techmap/dfflegalize_dlatch.ys
+++ b/tests/techmap/dfflegalize_dlatch.ys
@@ -11,6 +11,8 @@ design -save orig
 equiv_opt -assert -multiclock dfflegalize -cell $_DLATCH_P_ x
 equiv_opt -assert -multiclock dfflegalize -cell $_DLATCH_PP0_ x
 equiv_opt -assert -multiclock dfflegalize -cell $_DLATCHSR_PPP_ x
+equiv_opt -assert -multiclock dfflegalize -cell $_ALDFF_PP_ x
+equiv_opt -assert -multiclock dfflegalize -cell $_ALDFFE_PPP_ x
 
 # Convert everything to DFFs.
 
@@ -40,3 +42,23 @@ dfflegalize -cell $_DLATCHSR_PPP_ x
 select -assert-count 1 t:$_NOT_
 select -assert-count 2 t:$_DLATCHSR_PPP_
 select -assert-none t:$_DLATCHSR_PPP_ t:$_NOT_ %% %n t:* %i
+
+
+# Convert everything to ALDFFs.
+
+design -load orig
+dfflegalize -cell $_ALDFF_PP_ x
+
+select -assert-count 1 t:$_NOT_
+select -assert-count 2 t:$_ALDFF_PP_
+select -assert-none t:$_ALDFF_PP_ t:$_NOT_ %% %n t:* %i
+
+
+# Convert everything to ALDFFEs.
+
+design -load orig
+dfflegalize -cell $_ALDFFE_PPP_ x
+
+select -assert-count 1 t:$_NOT_
+select -assert-count 2 t:$_ALDFFE_PPP_
+select -assert-none t:$_ALDFFE_PPP_ t:$_NOT_ %% %n t:* %i
diff --git a/tests/techmap/dfflegalize_dlatch_init.ys b/tests/techmap/dfflegalize_dlatch_init.ys
index ccc9e41d7..9324c6691 100644
--- a/tests/techmap/dfflegalize_dlatch_init.ys
+++ b/tests/techmap/dfflegalize_dlatch_init.ys
@@ -16,6 +16,10 @@ equiv_opt -assert -multiclock dfflegalize -cell $_DLATCH_PP1_ 0
 equiv_opt -assert -multiclock dfflegalize -cell $_DLATCH_PP1_ 1
 equiv_opt -assert -multiclock dfflegalize -cell $_DLATCHSR_PPP_ 0
 equiv_opt -assert -multiclock dfflegalize -cell $_DLATCHSR_PPP_ 1
+equiv_opt -assert -multiclock dfflegalize -cell $_ALDFF_PP_ 0
+equiv_opt -assert -multiclock dfflegalize -cell $_ALDFF_PP_ 1
+equiv_opt -assert -multiclock dfflegalize -cell $_ALDFFE_PPP_ 0
+equiv_opt -assert -multiclock dfflegalize -cell $_ALDFFE_PPP_ 1
 
 # Convert everything to DFFs.
 
@@ -80,3 +84,37 @@ dfflegalize -cell $_DLATCHSR_PPP_ 1
 select -assert-count 5 t:$_NOT_
 select -assert-count 2 t:$_DLATCHSR_PPP_
 select -assert-none t:$_DLATCHSR_PPP_ t:$_NOT_ %% %n t:* %i
+
+
+# Convert everything to ALDFFs.
+
+design -load orig
+dfflegalize -cell $_ALDFF_PP_ 0
+
+select -assert-count 1 t:$_NOT_
+select -assert-count 2 t:$_ALDFF_PP_
+select -assert-none t:$_ALDFF_PP_ t:$_NOT_ %% %n t:* %i
+
+design -load orig
+dfflegalize -cell $_ALDFF_PP_ 1
+
+select -assert-count 5 t:$_NOT_
+select -assert-count 2 t:$_ALDFF_PP_
+select -assert-none t:$_ALDFF_PP_ t:$_NOT_ %% %n t:* %i
+
+
+# Convert everything to ALDFFEs.
+
+design -load orig
+dfflegalize -cell $_ALDFFE_PPP_ 0
+
+select -assert-count 1 t:$_NOT_
+select -assert-count 2 t:$_ALDFFE_PPP_
+select -assert-none t:$_ALDFFE_PPP_ t:$_NOT_ %% %n t:* %i
+
+design -load orig
+dfflegalize -cell $_ALDFFE_PPP_ 1
+
+select -assert-count 5 t:$_NOT_
+select -assert-count 2 t:$_ALDFFE_PPP_
+select -assert-none t:$_ALDFFE_PPP_ t:$_NOT_ %% %n t:* %i
diff --git a/tests/techmap/dfflegalize_inv.ys b/tests/techmap/dfflegalize_inv.ys
index cb42e01a8..a74d74161 100644
--- a/tests/techmap/dfflegalize_inv.ys
+++ b/tests/techmap/dfflegalize_inv.ys
@@ -2,7 +2,7 @@
 
 read_verilog -icells <<EOT
 
-module top(input C, E, R, S, D, output [64:0] Q);
+module top(input C, E, R, S, D, L, AD, output [71:0] Q);
 
 $_DFF_P_ ff0 (.C(C), .D(D), .Q(Q[0]));
 $_DFF_N_ ff1 (.C(C), .D(D), .Q(Q[1]));
@@ -88,16 +88,25 @@ $_SR_PP_ ff62 (.R(R), .S(S), .Q(Q[62]));
 $_SR_PN_ ff63 (.R(R), .S(S), .Q(Q[63]));
 $_SR_NP_ ff64 (.R(R), .S(S), .Q(Q[64]));
 
+$_ALDFF_PP_ ff65 (.C(C), .L(L), .AD(AD), .D(D), .Q(Q[65]));
+$_ALDFF_PN_ ff66 (.C(C), .L(L), .AD(AD), .D(D), .Q(Q[66]));
+$_ALDFF_NP_ ff67 (.C(C), .L(L), .AD(AD), .D(D), .Q(Q[67]));
+
+$_ALDFFE_PPP_ ff68 (.C(C), .L(L), .AD(AD), .D(D), .E(E), .Q(Q[68]));
+$_ALDFFE_PPN_ ff69 (.C(C), .L(L), .AD(AD), .D(D), .E(E), .Q(Q[69]));
+$_ALDFFE_PNP_ ff70 (.C(C), .L(L), .AD(AD), .D(D), .E(E), .Q(Q[70]));
+$_ALDFFE_NPP_ ff71 (.C(C), .L(L), .AD(AD), .D(D), .E(E), .Q(Q[71]));
+
 endmodule
 
 EOT
 
 design -save orig
 
-equiv_opt -assert -multiclock dfflegalize -cell $_DFF_P_ x -cell $_DFFE_PP_ x -cell $_DFF_PP?_ x -cell $_DFFE_PP?P_ x -cell $_DFFSR_PPP_ x -cell $_DFFSRE_PPPP_ x -cell $_SDFF_PP?_ x -cell $_SDFFE_PP?P_ x -cell $_SDFFCE_PP?P_ x -cell $_DLATCH_P_ x -cell $_DLATCH_PP?_ x -cell $_DLATCHSR_PPP_ x -cell $_SR_PP_ x
+equiv_opt -assert -multiclock dfflegalize -cell $_DFF_P_ x -cell $_DFFE_PP_ x -cell $_DFF_PP?_ x -cell $_DFFE_PP?P_ x -cell $_DFFSR_PPP_ x -cell $_DFFSRE_PPPP_ x -cell $_SDFF_PP?_ x -cell $_SDFFE_PP?P_ x -cell $_SDFFCE_PP?P_ x -cell $_DLATCH_P_ x -cell $_DLATCH_PP?_ x -cell $_DLATCHSR_PPP_ x -cell $_SR_PP_ x -cell $_ALDFF_PP_ x -cell $_ALDFFE_PPP_ x
 design -load postopt
 
-select -assert-count 46 t:$_NOT_
+select -assert-count 51 t:$_NOT_
 select -assert-count 2 t:$_DFF_P_
 select -assert-count 3 t:$_DFFE_PP_
 select -assert-count 3 t:$_DFF_PP0_
@@ -117,16 +126,18 @@ select -assert-count 3 t:$_DLATCH_PP0_
 select -assert-count 3 t:$_DLATCH_PP1_
 select -assert-count 4 t:$_DLATCHSR_PPP_
 select -assert-count 3 t:$_SR_PP_
-select -assert-none t:$_DFF_P_ t:$_DFFE_PP_ t:$_DFF_PP?_ t:$_DFFE_PP?P_ t:$_DFFSR_PPP_ t:$_DFFSRE_PPPP_ t:$_SDFF_PP?_ t:$_SDFFE_PP?P_ t:$_SDFFCE_PP?P_ t:$_DLATCH_P_ t:$_DLATCH_PP?_ t:$_DLATCHSR_PPP_ t:$_SR_PP_ t:$_NOT_ %% %n t:* %i
+select -assert-count 3 t:$_ALDFF_PP_
+select -assert-count 4 t:$_ALDFFE_PPP_
+select -assert-none t:$_DFF_P_ t:$_DFFE_PP_ t:$_DFF_PP?_ t:$_DFFE_PP?P_ t:$_DFFSR_PPP_ t:$_DFFSRE_PPPP_ t:$_SDFF_PP?_ t:$_SDFFE_PP?P_ t:$_SDFFCE_PP?P_ t:$_DLATCH_P_ t:$_DLATCH_PP?_ t:$_DLATCHSR_PPP_ t:$_SR_PP_ t:$_ALDFF_PP_ t:$_ALDFFE_PPP_ t:$_NOT_ %% %n t:* %i
 
 # Now try it again, targetting the opposite cells.
 
 design -load orig
 
-equiv_opt -assert -multiclock dfflegalize -cell $_DFF_N_ x -cell $_DFFE_NN_ x -cell $_DFF_NN?_ x -cell $_DFFE_NN?N_ x -cell $_DFFSR_NNN_ x -cell $_DFFSRE_NNNN_ x -cell $_SDFF_NN?_ x -cell $_SDFFE_NN?N_ x -cell $_SDFFCE_NN?N_ x -cell $_DLATCH_N_ x -cell $_DLATCH_NN?_ x -cell $_DLATCHSR_NNN_ x -cell $_SR_NN_ x
+equiv_opt -assert -multiclock dfflegalize -cell $_DFF_N_ x -cell $_DFFE_NN_ x -cell $_DFF_NN?_ x -cell $_DFFE_NN?N_ x -cell $_DFFSR_NNN_ x -cell $_DFFSRE_NNNN_ x -cell $_SDFF_NN?_ x -cell $_SDFFE_NN?N_ x -cell $_SDFFCE_NN?N_ x -cell $_DLATCH_N_ x -cell $_DLATCH_NN?_ x -cell $_DLATCHSR_NNN_ x -cell $_SR_NN_ x -cell $_ALDFF_NN_ x -cell $_ALDFFE_NNN_ x
 design -load postopt
 
-select -assert-count 122 t:$_NOT_
+select -assert-count 135 t:$_NOT_
 select -assert-count 2 t:$_DFF_N_
 select -assert-count 3 t:$_DFFE_NN_
 select -assert-count 3 t:$_DFF_NN0_
@@ -146,7 +157,9 @@ select -assert-count 3 t:$_DLATCH_NN0_
 select -assert-count 3 t:$_DLATCH_NN1_
 select -assert-count 4 t:$_DLATCHSR_NNN_
 select -assert-count 3 t:$_SR_NN_
-select -assert-none t:$_DFF_N_ t:$_DFFE_NN_ t:$_DFF_NN?_ t:$_DFFE_NN?N_ t:$_DFFSR_NNN_ t:$_DFFSRE_NNNN_ t:$_SDFF_NN?_ t:$_SDFFE_NN?N_ t:$_SDFFCE_NN?N_ t:$_DLATCH_N_ t:$_DLATCH_NN?_ t:$_DLATCHSR_NNN_ t:$_SR_NN_ t:$_NOT_ %% %n t:* %i
+select -assert-count 3 t:$_ALDFF_NN_
+select -assert-count 4 t:$_ALDFFE_NNN_
+select -assert-none t:$_DFF_N_ t:$_DFFE_NN_ t:$_DFF_NN?_ t:$_DFFE_NN?N_ t:$_DFFSR_NNN_ t:$_DFFSRE_NNNN_ t:$_SDFF_NN?_ t:$_SDFFE_NN?N_ t:$_SDFFCE_NN?N_ t:$_DLATCH_N_ t:$_DLATCH_NN?_ t:$_DLATCHSR_NNN_ t:$_SR_NN_ t:$_ALDFF_NN_ t:$_ALDFFE_NNN_ t:$_NOT_ %% %n t:* %i
 
 
 # Second test: make sure set/reset/enable are inverted before clock.
-- 
cgit v1.2.3


From 0b31cb598eee42fd903909fae64e9a76e3b702e3 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Marcelina=20Ko=C5=9Bcielnicka?= <mwk@0x04.net>
Date: Wed, 27 Oct 2021 13:37:26 +0200
Subject: dfflegalize: Add tests for aldff lowering.

---
 tests/techmap/dfflegalize_aldff.ys      |  92 ++++++++++++++++++++
 tests/techmap/dfflegalize_aldff_init.ys | 148 ++++++++++++++++++++++++++++++++
 2 files changed, 240 insertions(+)
 create mode 100644 tests/techmap/dfflegalize_aldff.ys
 create mode 100644 tests/techmap/dfflegalize_aldff_init.ys

(limited to 'tests')

diff --git a/tests/techmap/dfflegalize_aldff.ys b/tests/techmap/dfflegalize_aldff.ys
new file mode 100644
index 000000000..1ee9e3af6
--- /dev/null
+++ b/tests/techmap/dfflegalize_aldff.ys
@@ -0,0 +1,92 @@
+read_verilog -icells <<EOT
+
+module aldff(input C, L, AD, D, output [2:0] Q);
+$_ALDFF_PP_ ff0 (.C(C), .L(L), .AD(AD), .D(D), .Q(Q[0]));
+$_ALDFF_PN_ ff1 (.C(C), .L(L), .AD(AD), .D(D), .Q(Q[1]));
+$_ALDFF_NP_ ff2 (.C(C), .L(L), .AD(AD), .D(D), .Q(Q[2]));
+endmodule
+
+module aldffe(input C, E, L, AD, D, output [3:0] Q);
+$_ALDFFE_PPP_ ff0 (.C(C), .L(L), .AD(AD), .E(E), .D(D), .Q(Q[0]));
+$_ALDFFE_PPN_ ff1 (.C(C), .L(L), .AD(AD), .E(E), .D(D), .Q(Q[1]));
+$_ALDFFE_PNP_ ff2 (.C(C), .L(L), .AD(AD), .E(E), .D(D), .Q(Q[2]));
+$_ALDFFE_NPP_ ff3 (.C(C), .L(L), .AD(AD), .E(E), .D(D), .Q(Q[3]));
+endmodule
+
+module top(input C, E, L, AD, D, output [6:0] Q);
+aldff aldff_(.C(C), .L(L), .AD(AD), .D(D), .Q(Q[2:0]));
+aldffe aldffe_(.C(C), .L(L), .AD(AD), .E(E), .D(D), .Q(Q[6:3]));
+endmodule
+
+EOT
+
+design -save orig
+flatten
+equiv_opt -assert -multiclock dfflegalize -cell $_ALDFF_PP_ x
+equiv_opt -assert -multiclock dfflegalize -cell $_ALDFFE_PPP_ x
+#equiv_opt -assert -multiclock dfflegalize -cell $_DFFSR_PPP_ x
+#equiv_opt -assert -multiclock dfflegalize -cell $_DFFSRE_PPPP_ x
+
+
+# Convert everything to ALDFFs.
+
+design -load orig
+dfflegalize -cell $_ALDFF_PP_ x
+
+select -assert-count 2 aldff/t:$_NOT_
+select -assert-count 2 aldffe/t:$_NOT_
+select -assert-count 0 aldff/t:$_MUX_
+select -assert-count 4 aldffe/t:$_MUX_
+select -assert-count 7 t:$_ALDFF_PP_
+select -assert-none t:$_ALDFF_PP_ t:$_MUX_ t:$_NOT_ top/* %% %n t:* %i
+
+
+# Convert everything to ALDFFEs.
+
+design -load orig
+dfflegalize -cell $_ALDFFE_PPP_ x
+
+select -assert-count 2 aldff/t:$_NOT_
+select -assert-count 3 aldffe/t:$_NOT_
+select -assert-count 7 t:$_ALDFFE_PPP_
+select -assert-none t:$_ALDFFE_PPP_ t:$_NOT_ top/* %% %n t:* %i
+
+
+# Convert everything to DFFSRs.
+
+design -load orig
+dfflegalize -cell $_DFFSR_PPP_ x
+
+select -assert-count 2 aldff/t:$_AND_
+select -assert-count 3 aldffe/t:$_AND_
+select -assert-count 2 aldff/t:$_ANDNOT_
+select -assert-count 3 aldffe/t:$_ANDNOT_
+select -assert-count 1 aldff/t:$_OR_
+select -assert-count 1 aldffe/t:$_OR_
+select -assert-count 1 aldff/t:$_ORNOT_
+select -assert-count 1 aldffe/t:$_ORNOT_
+select -assert-count 3 aldff/t:$_NOT_
+select -assert-count 3 aldffe/t:$_NOT_
+select -assert-count 0 aldff/t:$_MUX_
+select -assert-count 4 aldffe/t:$_MUX_
+select -assert-count 7 t:$_DFFSR_PPP_
+select -assert-none t:$_DFFSR_PPP_ t:$_MUX_ t:$_NOT_ t:$_AND_ t:$_ANDNOT_ t:$_OR_ t:$_ORNOT_ top/* %% %n t:* %i
+
+
+# Convert everything to DFFSREs.
+
+design -load orig
+dfflegalize -cell $_DFFSRE_PPPP_ x
+
+select -assert-count 2 aldff/t:$_AND_
+select -assert-count 3 aldffe/t:$_AND_
+select -assert-count 2 aldff/t:$_ANDNOT_
+select -assert-count 3 aldffe/t:$_ANDNOT_
+select -assert-count 1 aldff/t:$_OR_
+select -assert-count 1 aldffe/t:$_OR_
+select -assert-count 1 aldff/t:$_ORNOT_
+select -assert-count 1 aldffe/t:$_ORNOT_
+select -assert-count 3 aldff/t:$_NOT_
+select -assert-count 4 aldffe/t:$_NOT_
+select -assert-count 7 t:$_DFFSRE_PPPP_
+select -assert-none t:$_DFFSRE_PPPP_ t:$_NOT_ t:$_AND_ t:$_ANDNOT_ t:$_OR_ t:$_ORNOT_ top/* %% %n t:* %i
diff --git a/tests/techmap/dfflegalize_aldff_init.ys b/tests/techmap/dfflegalize_aldff_init.ys
new file mode 100644
index 000000000..f4db8dd32
--- /dev/null
+++ b/tests/techmap/dfflegalize_aldff_init.ys
@@ -0,0 +1,148 @@
+read_verilog -icells <<EOT
+
+module aldff(input C, L, AD, D, (* init = 3'b000 *) output [2:0] Q);
+$_ALDFF_PP_ ff0 (.C(C), .L(L), .AD(AD), .D(D), .Q(Q[0]));
+$_ALDFF_PN_ ff1 (.C(C), .L(L), .AD(AD), .D(D), .Q(Q[1]));
+$_ALDFF_NP_ ff2 (.C(C), .L(L), .AD(AD), .D(D), .Q(Q[2]));
+endmodule
+
+module aldffe(input C, E, L, AD, D, (* init = 4'b0000 *) output [3:0] Q);
+$_ALDFFE_PPP_ ff0 (.C(C), .L(L), .AD(AD), .E(E), .D(D), .Q(Q[0]));
+$_ALDFFE_PPN_ ff1 (.C(C), .L(L), .AD(AD), .E(E), .D(D), .Q(Q[1]));
+$_ALDFFE_PNP_ ff2 (.C(C), .L(L), .AD(AD), .E(E), .D(D), .Q(Q[2]));
+$_ALDFFE_NPP_ ff3 (.C(C), .L(L), .AD(AD), .E(E), .D(D), .Q(Q[3]));
+endmodule
+
+module top(input C, E, L, AD, D, output [6:0] Q);
+aldff aldff_(.C(C), .L(L), .AD(AD), .D(D), .Q(Q[2:0]));
+aldffe aldffe_(.C(C), .L(L), .AD(AD), .E(E), .D(D), .Q(Q[6:3]));
+endmodule
+
+EOT
+
+design -save orig
+flatten
+equiv_opt -assert -multiclock dfflegalize -cell $_ALDFF_PP_ 0
+equiv_opt -assert -multiclock dfflegalize -cell $_ALDFF_PP_ 1
+equiv_opt -assert -multiclock dfflegalize -cell $_ALDFFE_PPP_ 0
+equiv_opt -assert -multiclock dfflegalize -cell $_ALDFFE_PPP_ 1
+#equiv_opt -assert -multiclock dfflegalize -cell $_DFFSR_PPP_ 0
+#equiv_opt -assert -multiclock dfflegalize -cell $_DFFSR_PPP_ 1
+#equiv_opt -assert -multiclock dfflegalize -cell $_DFFSRE_PPPP_ 0
+#equiv_opt -assert -multiclock dfflegalize -cell $_DFFSRE_PPPP_ 1
+
+
+# Convert everything to ALDFFs.
+
+design -load orig
+dfflegalize -cell $_ALDFF_PP_ 0
+
+select -assert-count 2 aldff/t:$_NOT_
+select -assert-count 2 aldffe/t:$_NOT_
+select -assert-count 0 aldff/t:$_MUX_
+select -assert-count 4 aldffe/t:$_MUX_
+select -assert-count 7 t:$_ALDFF_PP_
+select -assert-none t:$_ALDFF_PP_ t:$_MUX_ t:$_NOT_ top/* %% %n t:* %i
+
+design -load orig
+dfflegalize -cell $_ALDFF_PP_ 1
+
+select -assert-count 11 aldff/t:$_NOT_
+select -assert-count 14 aldffe/t:$_NOT_
+select -assert-count 0 aldff/t:$_MUX_
+select -assert-count 4 aldffe/t:$_MUX_
+select -assert-count 7 t:$_ALDFF_PP_
+select -assert-none t:$_ALDFF_PP_ t:$_MUX_ t:$_NOT_ top/* %% %n t:* %i
+
+
+# Convert everything to ALDFFEs.
+
+design -load orig
+dfflegalize -cell $_ALDFFE_PPP_ 0
+
+select -assert-count 2 aldff/t:$_NOT_
+select -assert-count 3 aldffe/t:$_NOT_
+select -assert-count 7 t:$_ALDFFE_PPP_
+select -assert-none t:$_ALDFFE_PPP_ t:$_NOT_ top/* %% %n t:* %i
+
+design -load orig
+dfflegalize -cell $_ALDFFE_PPP_ 1
+
+select -assert-count 11 aldff/t:$_NOT_
+select -assert-count 15 aldffe/t:$_NOT_
+select -assert-count 7 t:$_ALDFFE_PPP_
+select -assert-none t:$_ALDFFE_PPP_ t:$_NOT_ top/* %% %n t:* %i
+
+
+# Convert everything to DFFSRs.
+
+design -load orig
+dfflegalize -cell $_DFFSR_PPP_ 0
+
+select -assert-count 2 aldff/t:$_AND_
+select -assert-count 3 aldffe/t:$_AND_
+select -assert-count 2 aldff/t:$_ANDNOT_
+select -assert-count 3 aldffe/t:$_ANDNOT_
+select -assert-count 1 aldff/t:$_OR_
+select -assert-count 1 aldffe/t:$_OR_
+select -assert-count 1 aldff/t:$_ORNOT_
+select -assert-count 1 aldffe/t:$_ORNOT_
+select -assert-count 3 aldff/t:$_NOT_
+select -assert-count 3 aldffe/t:$_NOT_
+select -assert-count 0 aldff/t:$_MUX_
+select -assert-count 4 aldffe/t:$_MUX_
+select -assert-count 7 t:$_DFFSR_PPP_
+select -assert-none t:$_DFFSR_PPP_ t:$_MUX_ t:$_NOT_ t:$_AND_ t:$_ANDNOT_ t:$_OR_ t:$_ORNOT_ top/* %% %n t:* %i
+
+design -load orig
+dfflegalize -cell $_DFFSR_PPP_ 1
+
+select -assert-count 2 aldff/t:$_AND_
+select -assert-count 3 aldffe/t:$_AND_
+select -assert-count 2 aldff/t:$_ANDNOT_
+select -assert-count 3 aldffe/t:$_ANDNOT_
+select -assert-count 1 aldff/t:$_OR_
+select -assert-count 1 aldffe/t:$_OR_
+select -assert-count 1 aldff/t:$_ORNOT_
+select -assert-count 1 aldffe/t:$_ORNOT_
+select -assert-count 12 aldff/t:$_NOT_
+select -assert-count 15 aldffe/t:$_NOT_
+select -assert-count 0 aldff/t:$_MUX_
+select -assert-count 4 aldffe/t:$_MUX_
+select -assert-count 7 t:$_DFFSR_PPP_
+select -assert-none t:$_DFFSR_PPP_ t:$_MUX_ t:$_NOT_ t:$_AND_ t:$_ANDNOT_ t:$_OR_ t:$_ORNOT_ top/* %% %n t:* %i
+
+
+# Convert everything to DFFSREs.
+
+design -load orig
+dfflegalize -cell $_DFFSRE_PPPP_ 0
+
+select -assert-count 2 aldff/t:$_AND_
+select -assert-count 3 aldffe/t:$_AND_
+select -assert-count 2 aldff/t:$_ANDNOT_
+select -assert-count 3 aldffe/t:$_ANDNOT_
+select -assert-count 1 aldff/t:$_OR_
+select -assert-count 1 aldffe/t:$_OR_
+select -assert-count 1 aldff/t:$_ORNOT_
+select -assert-count 1 aldffe/t:$_ORNOT_
+select -assert-count 3 aldff/t:$_NOT_
+select -assert-count 4 aldffe/t:$_NOT_
+select -assert-count 7 t:$_DFFSRE_PPPP_
+select -assert-none t:$_DFFSRE_PPPP_ t:$_NOT_ t:$_AND_ t:$_ANDNOT_ t:$_OR_ t:$_ORNOT_ top/* %% %n t:* %i
+
+design -load orig
+dfflegalize -cell $_DFFSRE_PPPP_ 1
+
+select -assert-count 2 aldff/t:$_AND_
+select -assert-count 3 aldffe/t:$_AND_
+select -assert-count 2 aldff/t:$_ANDNOT_
+select -assert-count 3 aldffe/t:$_ANDNOT_
+select -assert-count 1 aldff/t:$_OR_
+select -assert-count 1 aldffe/t:$_OR_
+select -assert-count 1 aldff/t:$_ORNOT_
+select -assert-count 1 aldffe/t:$_ORNOT_
+select -assert-count 12 aldff/t:$_NOT_
+select -assert-count 16 aldffe/t:$_NOT_
+select -assert-count 7 t:$_DFFSRE_PPPP_
+select -assert-none t:$_DFFSRE_PPPP_ t:$_NOT_ t:$_AND_ t:$_ANDNOT_ t:$_OR_ t:$_ORNOT_ top/* %% %n t:* %i
-- 
cgit v1.2.3


From 15b0d717ed658b342ce5f74df5a65827eed04a94 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Marcelina=20Ko=C5=9Bcielnicka?= <mwk@0x04.net>
Date: Tue, 9 Nov 2021 11:22:48 +0100
Subject: iopadmap: Add native support for negative-polarity output enable.

---
 tests/arch/machxo2/mux.ys    | 2 +-
 tests/arch/machxo2/tribuf.ys | 4 ++--
 2 files changed, 3 insertions(+), 3 deletions(-)

(limited to 'tests')

diff --git a/tests/arch/machxo2/mux.ys b/tests/arch/machxo2/mux.ys
index 6c8aa857c..7b7e62d4c 100644
--- a/tests/arch/machxo2/mux.ys
+++ b/tests/arch/machxo2/mux.ys
@@ -35,6 +35,6 @@ proc
 equiv_opt -assert -map +/machxo2/cells_sim.v synth_machxo2 # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd mux16 # Constrain all select calls below inside the top module
-select -assert-count 11 t:LUT4
+select -assert-max 12 t:LUT4
 
 select -assert-none t:LUT4 t:FACADE_IO %% t:* %D
diff --git a/tests/arch/machxo2/tribuf.ys b/tests/arch/machxo2/tribuf.ys
index 9c00a8bcf..fce342e18 100644
--- a/tests/arch/machxo2/tribuf.ys
+++ b/tests/arch/machxo2/tribuf.ys
@@ -6,5 +6,5 @@ equiv_opt -assert -map +/machxo2/cells_sim.v synth_machxo2 # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd tristate # Constrain all select calls below inside the top module
 select -assert-count 3 t:FACADE_IO
-select -assert-count 1 t:$not
-select -assert-none t:FACADE_IO t:$not %% t:* %D
+select -assert-count 1 t:LUT4
+select -assert-none t:FACADE_IO t:LUT4 %% t:* %D
-- 
cgit v1.2.3


From 240d289ffff69f991e096a630028839048b6fefd Mon Sep 17 00:00:00 2001
From: Patrick Urban <patrick.urban@web.de>
Date: Mon, 13 Sep 2021 17:16:15 +0200
Subject: synth_gatemate: Initial implementation

Signed-off-by: Patrick Urban <patrick.urban@web.de>
---
 tests/arch/gatemate/add_sub.ys  |  9 +++++
 tests/arch/gatemate/adffs.ys    | 43 ++++++++++++++++++++++
 tests/arch/gatemate/counter.ys  | 12 +++++++
 tests/arch/gatemate/dffs.ys     | 21 +++++++++++
 tests/arch/gatemate/fsm.ys      | 20 +++++++++++
 tests/arch/gatemate/latches.ys  | 29 +++++++++++++++
 tests/arch/gatemate/logic.ys    | 10 ++++++
 tests/arch/gatemate/memory.ys   | 34 ++++++++++++++++++
 tests/arch/gatemate/mul.v       | 79 +++++++++++++++++++++++++++++++++++++++++
 tests/arch/gatemate/mul.ys      | 33 +++++++++++++++++
 tests/arch/gatemate/mux.ys      | 20 +++++++++++
 tests/arch/gatemate/run-test.sh |  4 +++
 tests/arch/gatemate/shifter.ys  | 10 ++++++
 tests/arch/gatemate/tribuf.ys   | 13 +++++++
 14 files changed, 337 insertions(+)
 create mode 100644 tests/arch/gatemate/add_sub.ys
 create mode 100644 tests/arch/gatemate/adffs.ys
 create mode 100644 tests/arch/gatemate/counter.ys
 create mode 100644 tests/arch/gatemate/dffs.ys
 create mode 100644 tests/arch/gatemate/fsm.ys
 create mode 100644 tests/arch/gatemate/latches.ys
 create mode 100644 tests/arch/gatemate/logic.ys
 create mode 100644 tests/arch/gatemate/memory.ys
 create mode 100644 tests/arch/gatemate/mul.v
 create mode 100644 tests/arch/gatemate/mul.ys
 create mode 100644 tests/arch/gatemate/mux.ys
 create mode 100755 tests/arch/gatemate/run-test.sh
 create mode 100644 tests/arch/gatemate/shifter.ys
 create mode 100644 tests/arch/gatemate/tribuf.ys

(limited to 'tests')

diff --git a/tests/arch/gatemate/add_sub.ys b/tests/arch/gatemate/add_sub.ys
new file mode 100644
index 000000000..c0055e521
--- /dev/null
+++ b/tests/arch/gatemate/add_sub.ys
@@ -0,0 +1,9 @@
+read_verilog ../common/add_sub.v
+hierarchy -top top
+proc
+equiv_opt -assert -map +/gatemate/cells_sim.v synth_gatemate -noiopad # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd top # Constrain all select calls below inside the top module
+select -assert-count 8 t:CC_ADDF
+select -assert-count 4 t:CC_LUT1
+select -assert-none t:CC_ADDF t:CC_LUT1 %% t:* %D
diff --git a/tests/arch/gatemate/adffs.ys b/tests/arch/gatemate/adffs.ys
new file mode 100644
index 000000000..7bba699f6
--- /dev/null
+++ b/tests/arch/gatemate/adffs.ys
@@ -0,0 +1,43 @@
+read_verilog ../common/adffs.v
+design -save read
+
+hierarchy -top adff
+proc
+equiv_opt -async2sync -assert -map +/gatemate/cells_sim.v synth_gatemate -noiopad # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd adff # Constrain all select calls below inside the top module
+select -assert-count 1 t:CC_BUFG
+select -assert-count 1 t:CC_DFF
+select -assert-none t:CC_BUFG t:CC_DFF %% t:* %D
+
+design -load read
+hierarchy -top adffn
+proc
+equiv_opt -async2sync -assert -map +/gatemate/cells_sim.v synth_gatemate -noiopad # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd adffn # Constrain all select calls below inside the top module
+select -assert-count 1 t:CC_BUFG
+select -assert-count 1 t:CC_DFF
+select -assert-none t:CC_BUFG t:CC_DFF %% t:* %D
+
+design -load read
+hierarchy -top dffs
+proc
+equiv_opt -async2sync -assert -map +/gatemate/cells_sim.v synth_gatemate -noiopad # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd dffs # Constrain all select calls below inside the top module
+select -assert-count 1 t:CC_BUFG
+select -assert-count 1 t:CC_DFF
+select -assert-count 1 t:CC_LUT2
+select -assert-none t:CC_BUFG t:CC_DFF t:CC_LUT2 %% t:* %D
+
+design -load read
+hierarchy -top ndffnr
+proc
+equiv_opt -async2sync -assert -map +/gatemate/cells_sim.v synth_gatemate -noiopad # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd ndffnr # Constrain all select calls below inside the top module
+select -assert-count 1 t:CC_BUFG
+select -assert-count 1 t:CC_DFF
+select -assert-count 1 t:CC_LUT2
+select -assert-none t:CC_BUFG t:CC_DFF t:CC_LUT2 %% t:* %D
diff --git a/tests/arch/gatemate/counter.ys b/tests/arch/gatemate/counter.ys
new file mode 100644
index 000000000..77ed858b3
--- /dev/null
+++ b/tests/arch/gatemate/counter.ys
@@ -0,0 +1,12 @@
+read_verilog ../common/counter.v
+hierarchy -top top
+proc
+flatten
+equiv_opt -assert -async2sync -map +/gatemate/cells_sim.v synth_gatemate -noiopad # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd top # Constrain all select calls below inside the top module
+
+select -assert-count 8 t:CC_ADDF
+select -assert-count 1 t:CC_BUFG
+select -assert-count 8 t:CC_DFF
+select -assert-none t:CC_ADDF t:CC_BUFG t:CC_DFF %% t:* %D
diff --git a/tests/arch/gatemate/dffs.ys b/tests/arch/gatemate/dffs.ys
new file mode 100644
index 000000000..0a3944e50
--- /dev/null
+++ b/tests/arch/gatemate/dffs.ys
@@ -0,0 +1,21 @@
+read_verilog ../common/dffs.v
+design -save read
+
+hierarchy -top dff
+proc
+equiv_opt -assert -async2sync -map +/gatemate/cells_sim.v synth_gatemate -noiopad # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd dff # Constrain all select calls below inside the top module
+select -assert-count 1 t:CC_BUFG
+select -assert-count 1 t:CC_DFF
+select -assert-none t:CC_BUFG t:CC_DFF %% t:* %D
+
+design -load read
+hierarchy -top dffe
+proc
+equiv_opt -assert -async2sync -map +/gatemate/cells_sim.v synth_gatemate -noiopad # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd dffe # Constrain all select calls below inside the top module
+select -assert-count 1 t:CC_BUFG
+select -assert-count 1 t:CC_DFF
+select -assert-none t:CC_BUFG t:CC_DFF %% t:* %D
diff --git a/tests/arch/gatemate/fsm.ys b/tests/arch/gatemate/fsm.ys
new file mode 100644
index 000000000..39b74c9e0
--- /dev/null
+++ b/tests/arch/gatemate/fsm.ys
@@ -0,0 +1,20 @@
+read_verilog ../common/fsm.v
+hierarchy -top fsm
+proc
+flatten
+
+equiv_opt -run :prove -map +/gatemate/cells_sim.v synth_gatemate -noiopad
+async2sync
+miter -equiv -make_assert -flatten gold gate miter
+stat
+sat -verify -prove-asserts -show-public -set-at 1 in_reset 1 -seq 20 -prove-skip 1 miter
+
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd fsm # Constrain all select calls below inside the top module
+
+select -assert-count 1 t:CC_BUFG
+select -assert-count 6 t:CC_DFF
+select -assert-count 3 t:CC_LUT2
+select -assert-count 4 t:CC_LUT3
+select -assert-count 8 t:CC_LUT4
+select -assert-none t:CC_BUFG t:CC_DFF t:CC_LUT2 t:CC_LUT3 t:CC_LUT4 %% t:* %D
diff --git a/tests/arch/gatemate/latches.ys b/tests/arch/gatemate/latches.ys
new file mode 100644
index 000000000..807650b81
--- /dev/null
+++ b/tests/arch/gatemate/latches.ys
@@ -0,0 +1,29 @@
+read_verilog ../common/latches.v
+design -save read
+
+hierarchy -top latchp
+proc
+equiv_opt -async2sync -assert -map +/gatemate/cells_sim.v synth_gatemate -noiopad # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd latchp # Constrain all select calls below inside the top module
+select -assert-count 1 t:CC_DLT
+select -assert-none t:CC_DLT %% t:* %D
+
+design -load read
+hierarchy -top latchn
+proc
+equiv_opt -async2sync -assert -map +/gatemate/cells_sim.v synth_gatemate -noiopad # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd latchn # Constrain all select calls below inside the top module
+select -assert-count 1 t:CC_DLT
+select -assert-none t:CC_DLT %% t:* %D
+
+design -load read
+hierarchy -top latchsr
+proc
+equiv_opt -async2sync -assert -map +/gatemate/cells_sim.v synth_gatemate -noiopad # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd latchsr # Constrain all select calls below inside the top module
+select -assert-count 1 t:CC_DLT
+select -assert-count 2 t:CC_LUT3
+select -assert-none t:CC_DLT t:CC_LUT3 %% t:* %D
diff --git a/tests/arch/gatemate/logic.ys b/tests/arch/gatemate/logic.ys
new file mode 100644
index 000000000..2718375a2
--- /dev/null
+++ b/tests/arch/gatemate/logic.ys
@@ -0,0 +1,10 @@
+read_verilog ../common/logic.v
+hierarchy -top top
+proc
+equiv_opt -assert -map +/gatemate/cells_sim.v synth_gatemate -noiopad # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd top # Constrain all select calls below inside the top module
+select -assert-count 1 t:CC_LUT1
+select -assert-count 6 t:CC_LUT2
+select -assert-count 2 t:CC_LUT4
+select -assert-none t:CC_LUT1 t:CC_LUT2 t:CC_LUT4 %% t:* %D
diff --git a/tests/arch/gatemate/memory.ys b/tests/arch/gatemate/memory.ys
new file mode 100644
index 000000000..e919920f8
--- /dev/null
+++ b/tests/arch/gatemate/memory.ys
@@ -0,0 +1,34 @@
+# 512 x 40 bit -> CC_BRAM_20K SDP RAM
+read_verilog ../common/blockram.v
+chparam -set ADDRESS_WIDTH 9 -set DATA_WIDTH 40 sync_ram_sdp
+synth_gatemate -top sync_ram_sdp -noiopad
+cd sync_ram_sdp
+select -assert-count 1 t:CC_BUFG
+select -assert-count 1 t:CC_BRAM_20K
+
+# 512 x 80 bit -> CC_BRAM_40K SDP RAM
+design -reset
+read_verilog ../common/blockram.v
+chparam -set ADDRESS_WIDTH 9 -set DATA_WIDTH 80 sync_ram_sdp
+synth_gatemate -top sync_ram_sdp -noiopad
+cd sync_ram_sdp
+select -assert-count 1 t:CC_BUFG
+select -assert-count 1 t:CC_BRAM_40K
+
+# 512 x 40 bit -> CC_BRAM_20K SDP ROM
+design -reset
+read_verilog ../common/blockrom.v
+chparam -set ADDRESS_WIDTH 9 -set DATA_WIDTH 40 sync_rom
+synth_gatemate -top sync_rom -noiopad
+cd sync_rom
+select -assert-count 1 t:CC_BUFG
+select -assert-count 1 t:CC_BRAM_20K
+
+# 512 x 80 bit -> CC_BRAM_40K SDP ROM
+design -reset
+read_verilog ../common/blockrom.v
+chparam -set ADDRESS_WIDTH 9 -set DATA_WIDTH 80 sync_rom
+synth_gatemate -top sync_rom -noiopad
+cd sync_rom
+select -assert-count 1 t:CC_BUFG
+select -assert-count 1 t:CC_BRAM_40K
diff --git a/tests/arch/gatemate/mul.v b/tests/arch/gatemate/mul.v
new file mode 100644
index 000000000..55e8f9006
--- /dev/null
+++ b/tests/arch/gatemate/mul.v
@@ -0,0 +1,79 @@
+
+module mul_plain(a, b, p);
+
+    parameter M = 6;
+    parameter N = 6;
+
+    input wire [M-1:0] a;
+    input wire [N-1:0] b;
+    output wire [M+N-1:0] p;
+
+    assign p = a * b;
+
+endmodule
+
+module mul_signed_async (clk, rst, en, a, b, p);
+
+    parameter M = 8;
+    parameter N = 6;
+
+    input wire signed clk, rst, en;
+    input wire signed [M-1:0] a;
+    input wire signed [N-1:0] b;
+    output reg signed [M+N-1:0] p;
+
+    reg signed [M-1:0] a_reg;
+    reg signed [N-1:0] b_reg;
+
+    // signed M*N multiplier with
+    // - input and output pipeline registers
+    // - asynchronous reset (active high)
+    // - clock enable (active high)
+    always @(posedge clk or posedge rst)
+    begin
+        if (rst) begin
+            a_reg <= 0;
+            b_reg <= 0;
+            p <= 0;
+        end
+        else if (en) begin
+            a_reg <= a;
+            b_reg <= b;
+            p <= a_reg * b_reg;
+        end
+    end
+
+endmodule
+
+module mul_unsigned_sync (clk, rst, en, a, b, p);
+
+    parameter M = 6;
+    parameter N = 3;
+
+    input wire clk, rst, en;
+    input wire [M-1:0] a;
+    input wire [N-1:0] b;
+    output reg [M+N-1:0] p;
+
+    reg [M-1:0] a_reg;
+    reg [N-1:0] b_reg;
+
+    // unsigned M*N multiplier with
+    // - input and output pipeline registers
+    // - synchronous reset (active high)
+    // - clock enable (active high)
+    always @(posedge clk)
+    begin
+        if (rst) begin
+            a_reg <= 0;
+            b_reg <= 0;
+            p <= 0;
+        end
+        else if (en) begin
+            a_reg <= a;
+            b_reg <= b;
+            p <= a_reg * b_reg;
+        end
+    end
+
+endmodule
diff --git a/tests/arch/gatemate/mul.ys b/tests/arch/gatemate/mul.ys
new file mode 100644
index 000000000..d10d07f1e
--- /dev/null
+++ b/tests/arch/gatemate/mul.ys
@@ -0,0 +1,33 @@
+read_verilog mul.v
+design -save read
+
+hierarchy -top mul_plain
+proc
+equiv_opt -assert -map +/gatemate/cells_sim.v synth_gatemate -noiopad # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd mul_plain # Constrain all select calls below inside the top module
+select -assert-count 1 t:CC_MULT
+select -assert-none t:CC_MULT %% t:* %D
+
+design -load read
+hierarchy -top mul_signed_async
+proc
+equiv_opt -assert -async2sync -map +/gatemate/cells_sim.v synth_gatemate -noiopad # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd mul_signed_async # Constrain all select calls below inside the top module
+select -assert-count 1 t:CC_MULT
+select -assert-count 1 t:CC_BUFG
+select -assert-count 28 t:CC_DFF
+select -assert-none t:CC_MULT t:CC_BUFG t:CC_DFF %% t:* %D
+
+design -load read
+hierarchy -top mul_unsigned_sync
+proc
+equiv_opt -assert -async2sync -map +/gatemate/cells_sim.v synth_gatemate -noiopad # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd mul_unsigned_sync # Constrain all select calls below inside the top module
+select -assert-count 1 t:CC_MULT
+select -assert-count 1 t:CC_BUFG
+select -assert-count 18 t:CC_LUT4
+select -assert-count 18 t:CC_DFF
+select -assert-none t:CC_MULT t:CC_BUFG t:CC_LUT4 t:CC_DFF %% t:* %D
diff --git a/tests/arch/gatemate/mux.ys b/tests/arch/gatemate/mux.ys
new file mode 100644
index 000000000..28396482b
--- /dev/null
+++ b/tests/arch/gatemate/mux.ys
@@ -0,0 +1,20 @@
+read_verilog ../common/mux.v
+design -save read
+
+design -load read
+hierarchy -top mux4
+proc
+equiv_opt -assert -map +/gatemate/cells_sim.v synth_gatemate -noiopad # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd mux4 # Constrain all select calls below inside the top module
+select -assert-count 1 t:CC_MX4
+select -assert-none t:CC_MX4 %% t:* %D
+
+design -load read
+hierarchy -top mux8
+proc
+equiv_opt -assert -map +/gatemate/cells_sim.v synth_gatemate -noiopad # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd mux8 # Constrain all select calls below inside the top module
+select -assert-count 1 t:CC_MX8
+select -assert-none t:CC_MX8 %% t:* %D
diff --git a/tests/arch/gatemate/run-test.sh b/tests/arch/gatemate/run-test.sh
new file mode 100755
index 000000000..4be4b70ae
--- /dev/null
+++ b/tests/arch/gatemate/run-test.sh
@@ -0,0 +1,4 @@
+#!/usr/bin/env bash
+set -eu
+source ../../gen-tests-makefile.sh
+run_tests --yosys-scripts --bash --yosys-args "-w 'Yosys has only limited support for tri-state logic at the moment.'"
diff --git a/tests/arch/gatemate/shifter.ys b/tests/arch/gatemate/shifter.ys
new file mode 100644
index 000000000..03df36ebc
--- /dev/null
+++ b/tests/arch/gatemate/shifter.ys
@@ -0,0 +1,10 @@
+read_verilog ../common/shifter.v
+hierarchy -top top
+proc
+flatten
+equiv_opt -assert -async2sync -map +/gatemate/cells_sim.v synth_gatemate -noiopad # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd top # Constrain all select calls below inside the top module
+select -assert-count 1 t:CC_BUFG
+select -assert-count 8 t:CC_DFF
+select -assert-none t:CC_BUFG t:CC_DFF %% t:* %D
diff --git a/tests/arch/gatemate/tribuf.ys b/tests/arch/gatemate/tribuf.ys
new file mode 100644
index 000000000..96cb05bfe
--- /dev/null
+++ b/tests/arch/gatemate/tribuf.ys
@@ -0,0 +1,13 @@
+read_verilog ../common/tribuf.v
+hierarchy -top tristate
+proc
+tribuf
+flatten
+synth
+equiv_opt -assert -map +/gatemate/cells_sim.v -map +/simcells.v synth_gatemate # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd tristate # Constrain all select calls below inside the top module
+select -assert-count 2 t:CC_IBUF
+select -assert-count 1 t:CC_LUT1
+select -assert-count 1 t:CC_TOBUF
+select -assert-none t:CC_IBUF t:CC_LUT1 t:CC_TOBUF %% t:* %D
-- 
cgit v1.2.3


From acb993b27b7027112bf10796efbf2886815f8630 Mon Sep 17 00:00:00 2001
From: Patrick Urban <patrick.urban@web.de>
Date: Fri, 24 Sep 2021 21:50:26 +0200
Subject: Allow initial blocks to be disabled during tests

Wrap initial blocks with a NO_INIT so that tests for archs without register initialization feature don't fail.
---
 tests/arch/common/adffs.v      | 8 ++++++++
 tests/arch/common/dffs.v       | 2 ++
 tests/arch/common/shifter.v    | 8 +++++++-
 tests/arch/gatemate/adffs.ys   | 2 +-
 tests/arch/gatemate/dffs.ys    | 2 +-
 tests/arch/gatemate/shifter.ys | 2 +-
 6 files changed, 20 insertions(+), 4 deletions(-)

(limited to 'tests')

diff --git a/tests/arch/common/adffs.v b/tests/arch/common/adffs.v
index 576bd81a6..966e7c2b8 100644
--- a/tests/arch/common/adffs.v
+++ b/tests/arch/common/adffs.v
@@ -1,7 +1,9 @@
 module adff( input d, clk, clr, output reg q );
+`ifndef NO_INIT
     initial begin
         q = 0;
     end
+`endif
 	  always @( posedge clk, posedge clr )
       if ( clr )
         q <= 1'b0;
@@ -10,9 +12,11 @@ module adff( input d, clk, clr, output reg q );
 endmodule
 
 module adffn( input d, clk, clr, output reg q );
+`ifndef NO_INIT
     initial begin
       q = 0;
     end
+`endif
 	  always @( posedge clk, negedge clr )
 		  if ( !clr )
 			  q <= 1'b0;
@@ -21,9 +25,11 @@ module adffn( input d, clk, clr, output reg q );
 endmodule
 
 module dffs( input d, clk, pre, clr, output reg q );
+`ifndef NO_INIT
     initial begin
       q = 0;
     end
+`endif
     always @( posedge clk )
       if ( pre )
         q <= 1'b1;
@@ -32,9 +38,11 @@ module dffs( input d, clk, pre, clr, output reg q );
 endmodule
 
 module ndffnr( input d, clk, pre, clr, output reg q );
+`ifndef NO_INIT
     initial begin
       q = 0;
     end
+`endif
     always @( negedge clk )
       if ( !clr )
         q <= 1'b0;
diff --git a/tests/arch/common/dffs.v b/tests/arch/common/dffs.v
index 636252d16..0c607af50 100644
--- a/tests/arch/common/dffs.v
+++ b/tests/arch/common/dffs.v
@@ -4,9 +4,11 @@ module dff ( input d, clk, output reg q );
 endmodule
 
 module dffe( input d, clk, en, output reg q );
+`ifndef NO_INIT
     initial begin
         q = 0;
     end
+`endif
 	  always @( posedge clk )
         if ( en )
               q <= d;
diff --git a/tests/arch/common/shifter.v b/tests/arch/common/shifter.v
index 3030608ab..06e63c9af 100644
--- a/tests/arch/common/shifter.v
+++ b/tests/arch/common/shifter.v
@@ -1,7 +1,13 @@
 module top(out, clk, in);
     output [7:0] out;
     input signed clk, in;
-    reg signed [7:0] out = 0;
+    reg signed [7:0] out;
+
+`ifndef NO_INIT
+    initial begin
+        out = 0;
+    end
+`endif
 
     always @(posedge clk)
 	begin
diff --git a/tests/arch/gatemate/adffs.ys b/tests/arch/gatemate/adffs.ys
index 7bba699f6..3f9401d68 100644
--- a/tests/arch/gatemate/adffs.ys
+++ b/tests/arch/gatemate/adffs.ys
@@ -1,4 +1,4 @@
-read_verilog ../common/adffs.v
+read_verilog -D NO_INIT ../common/adffs.v
 design -save read
 
 hierarchy -top adff
diff --git a/tests/arch/gatemate/dffs.ys b/tests/arch/gatemate/dffs.ys
index 0a3944e50..022322419 100644
--- a/tests/arch/gatemate/dffs.ys
+++ b/tests/arch/gatemate/dffs.ys
@@ -1,4 +1,4 @@
-read_verilog ../common/dffs.v
+read_verilog -D NO_INIT ../common/dffs.v
 design -save read
 
 hierarchy -top dff
diff --git a/tests/arch/gatemate/shifter.ys b/tests/arch/gatemate/shifter.ys
index 03df36ebc..0006a298a 100644
--- a/tests/arch/gatemate/shifter.ys
+++ b/tests/arch/gatemate/shifter.ys
@@ -1,4 +1,4 @@
-read_verilog ../common/shifter.v
+read_verilog -D NO_INIT ../common/shifter.v
 hierarchy -top top
 proc
 flatten
-- 
cgit v1.2.3


From 76bf96d310659864c47838aa5e0f43cdfe2bc3e6 Mon Sep 17 00:00:00 2001
From: Patrick Urban <patrick.urban@web.de>
Date: Mon, 11 Oct 2021 10:31:03 +0200
Subject: synth_gatemate: Fix fsm test

---
 tests/arch/gatemate/fsm.ys | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

(limited to 'tests')

diff --git a/tests/arch/gatemate/fsm.ys b/tests/arch/gatemate/fsm.ys
index 39b74c9e0..6e3e3a1be 100644
--- a/tests/arch/gatemate/fsm.ys
+++ b/tests/arch/gatemate/fsm.ys
@@ -14,7 +14,7 @@ cd fsm # Constrain all select calls below inside the top module
 
 select -assert-count 1 t:CC_BUFG
 select -assert-count 6 t:CC_DFF
-select -assert-count 3 t:CC_LUT2
-select -assert-count 4 t:CC_LUT3
+select -assert-count 4 t:CC_LUT2
+select -assert-count 2 t:CC_LUT3
 select -assert-count 8 t:CC_LUT4
 select -assert-none t:CC_BUFG t:CC_DFF t:CC_LUT2 t:CC_LUT3 t:CC_LUT4 %% t:* %D
-- 
cgit v1.2.3


From 97d03c2b3b3c5bee9685786f17d1d14ab77c6f6e Mon Sep 17 00:00:00 2001
From: Patrick Urban <patrick.urban@web.de>
Date: Mon, 18 Oct 2021 10:46:18 +0200
Subject: synth_gatemate: Apply new test practice with assert-max

---
 tests/arch/gatemate/add_sub.ys | 2 +-
 tests/arch/gatemate/adffs.ys   | 4 ++--
 tests/arch/gatemate/fsm.ys     | 6 +++---
 tests/arch/gatemate/latches.ys | 2 +-
 tests/arch/gatemate/logic.ys   | 6 +++---
 tests/arch/gatemate/mul.ys     | 2 +-
 tests/arch/gatemate/tribuf.ys  | 2 +-
 7 files changed, 12 insertions(+), 12 deletions(-)

(limited to 'tests')

diff --git a/tests/arch/gatemate/add_sub.ys b/tests/arch/gatemate/add_sub.ys
index c0055e521..bf261ba5a 100644
--- a/tests/arch/gatemate/add_sub.ys
+++ b/tests/arch/gatemate/add_sub.ys
@@ -5,5 +5,5 @@ equiv_opt -assert -map +/gatemate/cells_sim.v synth_gatemate -noiopad # equivale
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd top # Constrain all select calls below inside the top module
 select -assert-count 8 t:CC_ADDF
-select -assert-count 4 t:CC_LUT1
+select -assert-max 4 t:CC_LUT1
 select -assert-none t:CC_ADDF t:CC_LUT1 %% t:* %D
diff --git a/tests/arch/gatemate/adffs.ys b/tests/arch/gatemate/adffs.ys
index 3f9401d68..b2ded6e9d 100644
--- a/tests/arch/gatemate/adffs.ys
+++ b/tests/arch/gatemate/adffs.ys
@@ -28,7 +28,7 @@ design -load postopt # load the post-opt design (otherwise equiv_opt loads the p
 cd dffs # Constrain all select calls below inside the top module
 select -assert-count 1 t:CC_BUFG
 select -assert-count 1 t:CC_DFF
-select -assert-count 1 t:CC_LUT2
+select -assert-max 1 t:CC_LUT2
 select -assert-none t:CC_BUFG t:CC_DFF t:CC_LUT2 %% t:* %D
 
 design -load read
@@ -39,5 +39,5 @@ design -load postopt # load the post-opt design (otherwise equiv_opt loads the p
 cd ndffnr # Constrain all select calls below inside the top module
 select -assert-count 1 t:CC_BUFG
 select -assert-count 1 t:CC_DFF
-select -assert-count 1 t:CC_LUT2
+select -assert-max 1 t:CC_LUT2
 select -assert-none t:CC_BUFG t:CC_DFF t:CC_LUT2 %% t:* %D
diff --git a/tests/arch/gatemate/fsm.ys b/tests/arch/gatemate/fsm.ys
index 6e3e3a1be..6b43ead7a 100644
--- a/tests/arch/gatemate/fsm.ys
+++ b/tests/arch/gatemate/fsm.ys
@@ -14,7 +14,7 @@ cd fsm # Constrain all select calls below inside the top module
 
 select -assert-count 1 t:CC_BUFG
 select -assert-count 6 t:CC_DFF
-select -assert-count 4 t:CC_LUT2
-select -assert-count 2 t:CC_LUT3
-select -assert-count 8 t:CC_LUT4
+select -assert-max 5 t:CC_LUT2
+select -assert-max 4 t:CC_LUT3
+select -assert-max 9 t:CC_LUT4
 select -assert-none t:CC_BUFG t:CC_DFF t:CC_LUT2 t:CC_LUT3 t:CC_LUT4 %% t:* %D
diff --git a/tests/arch/gatemate/latches.ys b/tests/arch/gatemate/latches.ys
index 807650b81..5f64c6db5 100644
--- a/tests/arch/gatemate/latches.ys
+++ b/tests/arch/gatemate/latches.ys
@@ -25,5 +25,5 @@ equiv_opt -async2sync -assert -map +/gatemate/cells_sim.v synth_gatemate -noiopa
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd latchsr # Constrain all select calls below inside the top module
 select -assert-count 1 t:CC_DLT
-select -assert-count 2 t:CC_LUT3
+select -assert-max 2 t:CC_LUT3
 select -assert-none t:CC_DLT t:CC_LUT3 %% t:* %D
diff --git a/tests/arch/gatemate/logic.ys b/tests/arch/gatemate/logic.ys
index 2718375a2..026406bc8 100644
--- a/tests/arch/gatemate/logic.ys
+++ b/tests/arch/gatemate/logic.ys
@@ -4,7 +4,7 @@ proc
 equiv_opt -assert -map +/gatemate/cells_sim.v synth_gatemate -noiopad # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd top # Constrain all select calls below inside the top module
-select -assert-count 1 t:CC_LUT1
-select -assert-count 6 t:CC_LUT2
-select -assert-count 2 t:CC_LUT4
+select -assert-max 1 t:CC_LUT1
+select -assert-max 6 t:CC_LUT2
+select -assert-max 2 t:CC_LUT4
 select -assert-none t:CC_LUT1 t:CC_LUT2 t:CC_LUT4 %% t:* %D
diff --git a/tests/arch/gatemate/mul.ys b/tests/arch/gatemate/mul.ys
index d10d07f1e..ded5fe729 100644
--- a/tests/arch/gatemate/mul.ys
+++ b/tests/arch/gatemate/mul.ys
@@ -28,6 +28,6 @@ design -load postopt # load the post-opt design (otherwise equiv_opt loads the p
 cd mul_unsigned_sync # Constrain all select calls below inside the top module
 select -assert-count 1 t:CC_MULT
 select -assert-count 1 t:CC_BUFG
-select -assert-count 18 t:CC_LUT4
+select -assert-max 18 t:CC_LUT4
 select -assert-count 18 t:CC_DFF
 select -assert-none t:CC_MULT t:CC_BUFG t:CC_LUT4 t:CC_DFF %% t:* %D
diff --git a/tests/arch/gatemate/tribuf.ys b/tests/arch/gatemate/tribuf.ys
index 96cb05bfe..d900fa5e4 100644
--- a/tests/arch/gatemate/tribuf.ys
+++ b/tests/arch/gatemate/tribuf.ys
@@ -8,6 +8,6 @@ equiv_opt -assert -map +/gatemate/cells_sim.v -map +/simcells.v synth_gatemate #
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd tristate # Constrain all select calls below inside the top module
 select -assert-count 2 t:CC_IBUF
-select -assert-count 1 t:CC_LUT1
+select -assert-max 1 t:CC_LUT1
 select -assert-count 1 t:CC_TOBUF
 select -assert-none t:CC_IBUF t:CC_LUT1 t:CC_TOBUF %% t:* %D
-- 
cgit v1.2.3


From 81964d6d6f09050858886d5e0c9c6e20f4f80a53 Mon Sep 17 00:00:00 2001
From: Patrick Urban <patrick.urban@web.de>
Date: Mon, 25 Oct 2021 11:10:00 +0200
Subject: synth_gatemate: Update pass

* remove `write_edif` and `write_blif` options
* remove redundant `abc` call before muxcover
* update style
---
 tests/arch/gatemate/mux.ys | 12 ++++++++----
 1 file changed, 8 insertions(+), 4 deletions(-)

(limited to 'tests')

diff --git a/tests/arch/gatemate/mux.ys b/tests/arch/gatemate/mux.ys
index 28396482b..320ff33d7 100644
--- a/tests/arch/gatemate/mux.ys
+++ b/tests/arch/gatemate/mux.ys
@@ -7,8 +7,10 @@ proc
 equiv_opt -assert -map +/gatemate/cells_sim.v synth_gatemate -noiopad # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd mux4 # Constrain all select calls below inside the top module
-select -assert-count 1 t:CC_MX4
-select -assert-none t:CC_MX4 %% t:* %D
+select -assert-max 1 t:CC_LUT2
+select -assert-max 2 t:CC_LUT4
+select -assert-max 1 t:CC_MX2
+select -assert-none t:CC_LUT2 t:CC_LUT4 t:CC_MX2 %% t:* %D
 
 design -load read
 hierarchy -top mux8
@@ -16,5 +18,7 @@ proc
 equiv_opt -assert -map +/gatemate/cells_sim.v synth_gatemate -noiopad # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd mux8 # Constrain all select calls below inside the top module
-select -assert-count 1 t:CC_MX8
-select -assert-none t:CC_MX8 %% t:* %D
+select -assert-max 1 t:CC_LUT3
+select -assert-max 5 t:CC_LUT4
+select -assert-max 1 t:CC_MX2
+select -assert-none t:CC_LUT3 t:CC_LUT4 t:CC_MX2 %% t:* %D
-- 
cgit v1.2.3


From fdb19a5b3a10572b1b84a26306ec5e83a4eff613 Mon Sep 17 00:00:00 2001
From: Kamil Rakoczy <krakoczy@antmicro.com>
Date: Tue, 16 Nov 2021 10:59:54 +0100
Subject: Support parameters using struct as a wiretype (#3050)

Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
---
 tests/various/param_struct.ys | 51 +++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 51 insertions(+)
 create mode 100644 tests/various/param_struct.ys

(limited to 'tests')

diff --git a/tests/various/param_struct.ys b/tests/various/param_struct.ys
new file mode 100644
index 000000000..6d7a7c6ad
--- /dev/null
+++ b/tests/various/param_struct.ys
@@ -0,0 +1,51 @@
+read_verilog -sv << EOF
+package p;
+typedef struct packed {
+  logic a;
+  logic b;
+} struct_t;
+
+typedef struct packed {
+  struct_t g;
+  logic [2:0] h;
+} nested_struct_t;
+
+typedef union packed {
+  logic [4:0] x;
+} nested_union_t;
+
+parameter struct_t c = {1'b1, 1'b0};
+parameter nested_struct_t x = {{1'b1, 1'b0}, 1'b1, 1'b1, 1'b1};
+endpackage
+
+module dut ();
+parameter p::struct_t d = p::c;
+parameter p::nested_struct_t i = p::x;
+
+parameter p::nested_union_t u = {5'b11001};
+
+localparam e = d.a;
+localparam f = d.b;
+
+localparam j = i.g.a;
+localparam k = i.g.b;
+localparam l = i.h;
+localparam m = i.g;
+
+localparam o = u.x;
+
+always_comb begin
+  assert(d == 2'b10);
+  assert(e == 1'b1);
+  assert(f == 1'b0);
+  assert(j == 1'b1);
+  assert(k == 1'b0);
+  assert(l == 3'b111);
+// TODO: support access to whole sub-structs and unions
+//  assert(m == 2'b10);
+  assert(u == 5'b11001);
+end
+endmodule
+EOF
+hierarchy; proc; opt
+sat -verify -seq 1 -tempinduct -prove-asserts -show-all
-- 
cgit v1.2.3


From 77327b2544a30b15e8efc79e1f62661ff25d306c Mon Sep 17 00:00:00 2001
From: Lofty <dan.ravensloft@gmail.com>
Date: Wed, 24 Nov 2021 21:21:08 +0000
Subject: sta: very crude static timing analysis pass

Co-authored-by: Eddie Hung <eddie@fpgeh.com>
---
 tests/various/sta.ys | 81 ++++++++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 81 insertions(+)
 create mode 100644 tests/various/sta.ys

(limited to 'tests')

diff --git a/tests/various/sta.ys b/tests/various/sta.ys
new file mode 100644
index 000000000..156c31c47
--- /dev/null
+++ b/tests/various/sta.ys
@@ -0,0 +1,81 @@
+read_verilog -specify <<EOT
+module buffer(input i, output o);
+specify
+(i => o) = 10;
+endspecify
+endmodule
+
+module top(input i);
+wire w;
+buffer b(.i(i), .o(w));
+endmodule
+EOT
+
+logger -expect warning "Critical-path does not terminate in a recognised endpoint\." 1
+sta
+
+
+design -reset
+read_verilog -specify <<EOT
+module top(input i, output o, p);
+assign o = i;
+endmodule
+EOT
+
+logger -expect log "No timing paths found\." 1
+sta
+
+
+design -reset
+read_verilog -specify <<EOT
+module buffer(input i, output o);
+specify
+(i => o) = 10;
+endspecify
+endmodule
+
+module top(input i, output o, p);
+buffer b(.i(i), .o(o));
+endmodule
+EOT
+
+sta
+
+
+design -reset
+read_verilog -specify <<EOT
+module buffer(input i, output o);
+specify
+(i => o) = 10;
+endspecify
+endmodule
+
+module top(input i, output o, p);
+buffer b(.i(i), .o(o));
+const0 c(.o(p));
+endmodule
+EOT
+
+logger -expect warning "Cell type 'const0' not recognised! Ignoring\." 1
+sta
+
+
+design -reset
+read_verilog -specify <<EOT
+module buffer(input i, output o);
+specify
+(i => o) = 10;
+endspecify
+endmodule
+module const0(output o);
+endmodule
+
+module top(input i, output o, p);
+buffer b(.i(i), .o(o));
+const0 c(.o(p));
+endmodule
+EOT
+
+sta
+
+logger -expect-no-warnings
-- 
cgit v1.2.3


From d65942b9acc20e4d485ed2fe319b04ddd75ac174 Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Fri, 3 Dec 2021 09:56:37 +0100
Subject: Add gitignore for gatemate

---
 tests/arch/gatemate/.gitignore | 4 ++++
 1 file changed, 4 insertions(+)
 create mode 100644 tests/arch/gatemate/.gitignore

(limited to 'tests')

diff --git a/tests/arch/gatemate/.gitignore b/tests/arch/gatemate/.gitignore
new file mode 100644
index 000000000..9a71dca69
--- /dev/null
+++ b/tests/arch/gatemate/.gitignore
@@ -0,0 +1,4 @@
+*.log
+/run-test.mk
++*_synth.v
++*_testbench
-- 
cgit v1.2.3


From d6e4d3f1ba9191f0f3bbed2d47a9ef80b8614e77 Mon Sep 17 00:00:00 2001
From: Claire Xenia Wolf <claire@clairexen.net>
Date: Fri, 10 Dec 2021 00:22:37 +0100
Subject: Fix the tests we just broke

Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
---
 tests/arch/xilinx/tribuf.sh             | 4 ++--
 tests/bram/run-single.sh                | 2 +-
 tests/memories/run-test.sh              | 2 +-
 tests/techmap/mem_simple_4x1_runtest.sh | 2 +-
 tests/techmap/recursive_runtest.sh      | 2 +-
 tests/various/async.sh                  | 8 ++++----
 6 files changed, 10 insertions(+), 10 deletions(-)

(limited to 'tests')

diff --git a/tests/arch/xilinx/tribuf.sh b/tests/arch/xilinx/tribuf.sh
index bd44395cb..eca33e490 100644
--- a/tests/arch/xilinx/tribuf.sh
+++ b/tests/arch/xilinx/tribuf.sh
@@ -1,5 +1,5 @@
-! ../../../yosys -qp "synth_xilinx" ../common/tribuf.v
-../../../yosys -qp "synth_xilinx -iopad; \
+../../../yosys -f verilog -qp "synth_xilinx" ../common/tribuf.v
+../../../yosys -f verilog -qp "synth_xilinx -iopad; \
 select -assert-count 2 t:IBUF; \
 select -assert-count 1 t:INV; \
 select -assert-count 1 t:OBUFT" ../common/tribuf.v
diff --git a/tests/bram/run-single.sh b/tests/bram/run-single.sh
index 98a45b613..429a79e3c 100644
--- a/tests/bram/run-single.sh
+++ b/tests/bram/run-single.sh
@@ -1,6 +1,6 @@
 #!/bin/bash
 set -e
-../../yosys -qq -p "proc; opt; memory -nomap -bram temp/brams_${2}.txt; opt -fast -full" \
+../../yosys -qq -f verilog -p "proc; opt; memory -nomap -bram temp/brams_${2}.txt; opt -fast -full" \
 		-l temp/synth_${1}_${2}.log -o temp/synth_${1}_${2}.v temp/brams_${1}.v
 iverilog -Dvcd_file=\"temp/tb_${1}_${2}.vcd\" -DSIMLIB_MEMDELAY=1 -o temp/tb_${1}_${2}.tb temp/brams_${1}_tb.v \
 		temp/brams_${1}_ref.v temp/synth_${1}_${2}.v temp/brams_${2}.v ../../techlibs/common/simlib.v
diff --git a/tests/memories/run-test.sh b/tests/memories/run-test.sh
index b8657056a..c65066a9c 100755
--- a/tests/memories/run-test.sh
+++ b/tests/memories/run-test.sh
@@ -18,7 +18,7 @@ ${MAKE:-make} -f ../tools/autotest.mk SEED="$seed" EXTRA_FLAGS="$abcopt" *.v
 
 for f in `egrep -l 'expect-(wr-ports|rd-ports|rd-clk)' *.v`; do
 	echo -n "Testing expectations for $f .."
-	../../yosys -qp "proc; opt; memory -nomap;; dump -outfile ${f%.v}.dmp t:\$mem_v2" $f
+	../../yosys -f verilog -qp "proc; opt; memory -nomap;; dump -outfile ${f%.v}.dmp t:\$mem_v2" $f
 	if grep -q expect-wr-ports $f; then
 		grep -q "parameter \\\\WR_PORTS $(gawk '/expect-wr-ports/ { print $3; }' $f)\$" ${f%.v}.dmp ||
 				{ echo " ERROR: Unexpected number of write ports."; false; }
diff --git a/tests/techmap/mem_simple_4x1_runtest.sh b/tests/techmap/mem_simple_4x1_runtest.sh
index 9c41fa56a..b486de5c7 100644
--- a/tests/techmap/mem_simple_4x1_runtest.sh
+++ b/tests/techmap/mem_simple_4x1_runtest.sh
@@ -2,7 +2,7 @@
 
 set -e
 
-../../yosys -b 'verilog -noattr' -o mem_simple_4x1_synth.v -p 'proc; opt; memory -nomap; techmap -map mem_simple_4x1_map.v;; techmap; opt; abc;; stat' mem_simple_4x1_uut.v
+../../yosys -b 'verilog -noattr' -o mem_simple_4x1_synth.v -p 'read_verilog mem_simple_4x1_uut.v; proc; opt; memory -nomap; techmap -map mem_simple_4x1_map.v;; techmap; opt; abc;; stat'
 
 iverilog -o mem_simple_4x1_gold_tb mem_simple_4x1_tb.v mem_simple_4x1_uut.v
 iverilog -o mem_simple_4x1_gate_tb mem_simple_4x1_tb.v mem_simple_4x1_synth.v mem_simple_4x1_cells.v
diff --git a/tests/techmap/recursive_runtest.sh b/tests/techmap/recursive_runtest.sh
index 0725ccf40..564d678fa 100644
--- a/tests/techmap/recursive_runtest.sh
+++ b/tests/techmap/recursive_runtest.sh
@@ -1,3 +1,3 @@
 set -e
 
-../../yosys -p 'hierarchy -top top; techmap -map recursive_map.v -max_iter 1; select -assert-count 2 t:sub; select -assert-count 2 t:bar' recursive.v
+../../yosys -p 'read_verilog recursive.v; hierarchy -top top; techmap -map recursive_map.v -max_iter 1; select -assert-count 2 t:sub; select -assert-count 2 t:bar'
diff --git a/tests/various/async.sh b/tests/various/async.sh
index 7c41d6d94..e83935d02 100644
--- a/tests/various/async.sh
+++ b/tests/various/async.sh
@@ -1,9 +1,9 @@
 #!/bin/bash
 set -ex
-../../yosys -q -o async_syn.v -p 'synth; rename uut syn' async.v
-../../yosys -q -o async_prp.v -p 'prep; rename uut prp' async.v
-../../yosys -q -o async_a2s.v -p 'prep; async2sync; rename uut a2s' async.v
-../../yosys -q -o async_ffl.v -p 'prep; clk2fflogic; rename uut ffl' async.v
+../../yosys -q -o async_syn.v -r uut -p 'synth; rename uut syn' async.v
+../../yosys -q -o async_prp.v -r uut -p 'prep; rename uut prp' async.v
+../../yosys -q -o async_a2s.v -r uut -p 'prep; async2sync; rename uut a2s' async.v
+../../yosys -q -o async_ffl.v -r uut -p 'prep; clk2fflogic; rename uut ffl' async.v
 iverilog -o async_sim -DTESTBENCH async.v async_???.v
 vvp -N async_sim > async.out
 tail async.out
-- 
cgit v1.2.3


From 4cd2f03e36d09f936d39f8499e26fb0a2bc897f9 Mon Sep 17 00:00:00 2001
From: Thomas Sailer <sailer@tsailer.ch>
Date: Wed, 25 Aug 2021 21:34:26 +0200
Subject: preprocessor: do not destroy double slash escaped identifiers

The preprocessor currently destroys double slash containing escaped
identifiers (for example \a//b ). This is due to next_token trying to
convert single line comments (//) into /* */ comments. This then leads
to an unintuitive error message like this:
ERROR: syntax error, unexpected '*'

This patch fixes the error by recognizing escaped identifiers and
returning them as single token. It also adds a testcase.
---
 tests/verilog/doubleslash.ys | 19 +++++++++++++++++++
 1 file changed, 19 insertions(+)
 create mode 100644 tests/verilog/doubleslash.ys

(limited to 'tests')

diff --git a/tests/verilog/doubleslash.ys b/tests/verilog/doubleslash.ys
new file mode 100644
index 000000000..8a51f12c2
--- /dev/null
+++ b/tests/verilog/doubleslash.ys
@@ -0,0 +1,19 @@
+read_verilog -sv <<EOT
+module doubleslash
+  (input  logic   a,
+   input  logic   b,
+   output logic   z);
+
+  logic \a//b ;
+
+  assign \a//b = a & b;
+  assign z = ~\a//b ;
+
+endmodule : doubleslash
+EOT
+
+hierarchy
+proc
+opt -full
+
+write_verilog doubleslash.v
-- 
cgit v1.2.3


From c2b7ad3b28ebd7865c8b2e795b2942d5d1bd00f5 Mon Sep 17 00:00:00 2001
From: Icenowy Zheng <icenowy@aosc.io>
Date: Fri, 17 Dec 2021 20:25:32 +0800
Subject: anlogic: support BRAM mapping

Anlogic FPGAs all have two kinds of BRAMs, one is 9bit*1K when being
true dual port (or 18bit*512 when simple dual port), the other is
16bit*2K.

Supports mapping of these two kinds of BRAMs. 9Kbit BRAM in SDP mode and
32Kbit BRAM with 8bit width are not support yet.

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
---
 tests/arch/anlogic/blockram.ys | 13 +++++++++++++
 tests/arch/anlogic/lutram.ys   |  2 +-
 2 files changed, 14 insertions(+), 1 deletion(-)
 create mode 100644 tests/arch/anlogic/blockram.ys

(limited to 'tests')

diff --git a/tests/arch/anlogic/blockram.ys b/tests/arch/anlogic/blockram.ys
new file mode 100644
index 000000000..da23409ba
--- /dev/null
+++ b/tests/arch/anlogic/blockram.ys
@@ -0,0 +1,13 @@
+read_verilog ../common/blockram.v
+hierarchy -top sync_ram_sp
+proc
+memory -nomap
+equiv_opt -run :prove -map +/anlogic/cells_sim.v synth_anlogic
+memory
+opt -full
+
+design -load postopt
+cd sync_ram_sp
+
+select -assert-count 1 t:EG_PHY_BRAM
+select -assert-none t:EG_PHY_BRAM %% t:* %D
diff --git a/tests/arch/anlogic/lutram.ys b/tests/arch/anlogic/lutram.ys
index 6dbdbdac3..fe6135c73 100644
--- a/tests/arch/anlogic/lutram.ys
+++ b/tests/arch/anlogic/lutram.ys
@@ -2,7 +2,7 @@ read_verilog ../common/lutram.v
 hierarchy -top lutram_1w1r
 proc
 memory -nomap
-equiv_opt -run :prove -map +/anlogic/cells_sim.v synth_anlogic
+equiv_opt -run :prove -map +/anlogic/cells_sim.v synth_anlogic -nobram
 memory
 opt -full
 
-- 
cgit v1.2.3


From 7608985d2c6237b869a4774c6b1659282e7473ad Mon Sep 17 00:00:00 2001
From: Zachary Snow <zach@zachjs.com>
Date: Wed, 15 Dec 2021 18:15:09 -0700
Subject: fix width detection of array querying function in case and case item
 expressions

I also removed the unnecessary shadowing of `width_hint` and `sign_hint`
in the corresponding case in `simplify()`.
---
 tests/simple/case_expr_extend.sv | 11 +++++++++++
 tests/simple/case_expr_query.sv  | 32 ++++++++++++++++++++++++++++++++
 2 files changed, 43 insertions(+)
 create mode 100644 tests/simple/case_expr_extend.sv
 create mode 100644 tests/simple/case_expr_query.sv

(limited to 'tests')

diff --git a/tests/simple/case_expr_extend.sv b/tests/simple/case_expr_extend.sv
new file mode 100644
index 000000000..61bd14df1
--- /dev/null
+++ b/tests/simple/case_expr_extend.sv
@@ -0,0 +1,11 @@
+module top(
+    output logic [5:0] out
+);
+always_comb begin
+    out = '0;
+    case (1'b1 << 1)
+        2'b10: out = '1;
+        default: out = '0;
+    endcase
+end
+endmodule
diff --git a/tests/simple/case_expr_query.sv b/tests/simple/case_expr_query.sv
new file mode 100644
index 000000000..63a0a8b7a
--- /dev/null
+++ b/tests/simple/case_expr_query.sv
@@ -0,0 +1,32 @@
+module top(
+    output logic [5:0] out
+);
+always_comb begin
+    out = '0;
+    case ($bits (out)) 6:
+    case ($size (out)) 6:
+    case ($high (out)) 5:
+    case ($low  (out)) 0:
+    case ($left (out)) 5:
+    case ($right(out)) 0:
+    case (6) $bits (out):
+    case (6) $size (out):
+    case (5) $high (out):
+    case (0) $low  (out):
+    case (5) $left (out):
+    case (0) $right(out):
+        out = '1;
+    endcase
+    endcase
+    endcase
+    endcase
+    endcase
+    endcase
+    endcase
+    endcase
+    endcase
+    endcase
+    endcase
+    endcase
+end
+endmodule
-- 
cgit v1.2.3


From f84c9d8e17fbbfa3c0f8b533475e10142e046556 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Marcelina=20Ko=C5=9Bcielnicka?= <mwk@0x04.net>
Date: Mon, 20 Dec 2021 17:10:30 +0100
Subject: memory_share: Fix SAT-based sharing for wide ports.

Fixes #3117.
---
 tests/opt/bug3117.ys | 34 ++++++++++++++++++++++++++++++++++
 1 file changed, 34 insertions(+)
 create mode 100644 tests/opt/bug3117.ys

(limited to 'tests')

diff --git a/tests/opt/bug3117.ys b/tests/opt/bug3117.ys
new file mode 100644
index 000000000..177b3ab9a
--- /dev/null
+++ b/tests/opt/bug3117.ys
@@ -0,0 +1,34 @@
+read_verilog << EOT
+
+module test (...);
+
+input [7:1] wa1;
+input [7:1] wa2;
+input [7:0] ra;
+output [7:0] rd;
+input clk;
+input we1, we2;
+input [15:0] wd1, wd2;
+
+reg [7:0] mem [0:255];
+
+assign rd = mem[ra];
+
+always @(posedge clk) begin
+        if (we1) begin
+                mem[{wa1, 1'b0}] <= wd1[7:0];
+                mem[{wa1, 1'b1}] <= wd1[15:8];
+        end else begin
+                mem[{wa2, 1'b0}] <= wd2[7:0];
+                mem[{wa2, 1'b1}] <= wd2[15:8];
+        end
+end
+
+endmodule
+
+EOT
+
+proc
+opt
+memory_share
+select -assert-count 1 t:$memwr_v2
-- 
cgit v1.2.3


From 8c509a5659d540dc41f6cc19ee6989fc249f519d Mon Sep 17 00:00:00 2001
From: Zachary Snow <zach@zachjs.com>
Date: Thu, 30 Dec 2021 00:01:30 -0700
Subject: sv: fix size cast clipping expression width

---
 tests/simple/lesser_size_cast.sv | 7 +++++++
 1 file changed, 7 insertions(+)
 create mode 100644 tests/simple/lesser_size_cast.sv

(limited to 'tests')

diff --git a/tests/simple/lesser_size_cast.sv b/tests/simple/lesser_size_cast.sv
new file mode 100644
index 000000000..8c0bc9814
--- /dev/null
+++ b/tests/simple/lesser_size_cast.sv
@@ -0,0 +1,7 @@
+module top (
+    input signed [1:0] a,
+    input signed [2:0] b,
+    output signed [4:0] c
+);
+    assign c = 2'(a) * b;
+endmodule
-- 
cgit v1.2.3


From 207af4196b588546344db80df6cb3f77df784aaf Mon Sep 17 00:00:00 2001
From: Zachary Snow <zach@zachjs.com>
Date: Thu, 30 Dec 2021 00:06:23 -0700
Subject: fixup verilog doubleslash test

- add generated doubleslash.v to .gitignore
- ensure backend verilog can be read again
---
 tests/verilog/.gitignore     | 1 +
 tests/verilog/doubleslash.ys | 2 ++
 2 files changed, 3 insertions(+)

(limited to 'tests')

diff --git a/tests/verilog/.gitignore b/tests/verilog/.gitignore
index 34da23437..96ebe20ba 100644
--- a/tests/verilog/.gitignore
+++ b/tests/verilog/.gitignore
@@ -3,3 +3,4 @@
 /run-test.mk
 /const_arst.v
 /const_sr.v
+/doubleslash.v
diff --git a/tests/verilog/doubleslash.ys b/tests/verilog/doubleslash.ys
index 8a51f12c2..c41673ee5 100644
--- a/tests/verilog/doubleslash.ys
+++ b/tests/verilog/doubleslash.ys
@@ -17,3 +17,5 @@ proc
 opt -full
 
 write_verilog doubleslash.v
+design -reset
+read_verilog doubleslash.v
-- 
cgit v1.2.3


From e0e4dfb55ea1812521aa4c0e79240987653538da Mon Sep 17 00:00:00 2001
From: Zachary Snow <zach@zachjs.com>
Date: Wed, 29 Dec 2021 10:38:55 -0700
Subject: fix iverilog compatibility for new case expr tests

---
 tests/simple/case_expr_extend.sv | 2 +-
 tests/simple/case_expr_query.sv  | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

(limited to 'tests')

diff --git a/tests/simple/case_expr_extend.sv b/tests/simple/case_expr_extend.sv
index 61bd14df1..d4ca2aa9b 100644
--- a/tests/simple/case_expr_extend.sv
+++ b/tests/simple/case_expr_extend.sv
@@ -1,7 +1,7 @@
 module top(
     output logic [5:0] out
 );
-always_comb begin
+initial begin
     out = '0;
     case (1'b1 << 1)
         2'b10: out = '1;
diff --git a/tests/simple/case_expr_query.sv b/tests/simple/case_expr_query.sv
index 63a0a8b7a..844dfb713 100644
--- a/tests/simple/case_expr_query.sv
+++ b/tests/simple/case_expr_query.sv
@@ -1,7 +1,7 @@
 module top(
     output logic [5:0] out
 );
-always_comb begin
+initial begin
     out = '0;
     case ($bits (out)) 6:
     case ($size (out)) 6:
-- 
cgit v1.2.3


From 66447e8fafa53396510b9a2c789fef6e5df0d6ac Mon Sep 17 00:00:00 2001
From: Zachary Snow <zach@zachjs.com>
Date: Mon, 3 Jan 2022 20:12:22 -0700
Subject: logger: fix unmatched expected warnings and errors

- Prevent unmatched expected error patterns from self-matching
- Prevent infinite recursion on unmatched expected warnings
- Always print the error message for unmatched error patterns
- Add test coverage for all unmatched message types
- Add test coverage for excess matched logs and warnings
---
 tests/various/logger_fail.sh | 42 ++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 42 insertions(+)
 create mode 100755 tests/various/logger_fail.sh

(limited to 'tests')

diff --git a/tests/various/logger_fail.sh b/tests/various/logger_fail.sh
new file mode 100755
index 000000000..19b650007
--- /dev/null
+++ b/tests/various/logger_fail.sh
@@ -0,0 +1,42 @@
+#!/bin/bash
+
+fail() {
+	echo "$1" >&2
+	exit 1
+}
+
+runTest() {
+	desc="$1"
+	want="$2"
+	shift 2
+	echo "running '$desc' with args $@"
+	output=`../../yosys -q "$@" 2>&1`
+	if [ $? -ne 1 ]; then
+		fail "exit code for '$desc' was not 1"
+	fi
+	if [ "$output" != "$want" ]; then
+		fail "output for '$desc' did not match"
+	fi
+}
+
+unmet() {
+	kind=$1
+	runTest "unmet $kind" \
+		"ERROR: Expected $kind pattern 'foobar' not found !" \
+		-p "logger -expect $kind \"foobar\" 1"
+}
+
+unmet log
+unmet warning
+unmet error
+
+runTest "too many logs" \
+	"ERROR: Expected log pattern 'statistics' found 2 time(s), instead of 1 time(s) !" \
+	-p "logger -expect log \"statistics\" 1" -p stat -p stat
+
+runTest "too many warnings" \
+	"Warning: Found log message matching -W regex:
+Printing statistics.
+ERROR: Expected warning pattern 'statistics' found 2 time(s), instead of 1 time(s) !" \
+	-p "logger -warn \"Printing statistics\"" \
+	-p "logger -expect warning \"statistics\" 1" -p stat -p stat
-- 
cgit v1.2.3


From 828e85068f8dd52a508e4cbb84deea0e621aa038 Mon Sep 17 00:00:00 2001
From: Zachary Snow <zach@zachjs.com>
Date: Wed, 5 Jan 2022 23:33:08 -0700
Subject: sv: fix size cast internal expression extension

---
 tests/verilog/size_cast.sv | 140 +++++++++++++++++++++++++++++++++++++++++++++
 tests/verilog/size_cast.ys |   5 ++
 2 files changed, 145 insertions(+)
 create mode 100644 tests/verilog/size_cast.sv
 create mode 100644 tests/verilog/size_cast.ys

(limited to 'tests')

diff --git a/tests/verilog/size_cast.sv b/tests/verilog/size_cast.sv
new file mode 100644
index 000000000..1636f8d70
--- /dev/null
+++ b/tests/verilog/size_cast.sv
@@ -0,0 +1,140 @@
+module top;
+    logic L1b0 = 0;
+    logic L1b1 = 1;
+
+    logic signed L1sb0 = 0;
+    logic signed L1sb1 = 1;
+
+    logic [1:0] L2b00 = 0;
+    logic [1:0] L2b01 = 1;
+    logic [1:0] L2b10 = 2;
+    logic [1:0] L2b11 = 3;
+
+    logic signed [1:0] L2sb00 = 0;
+    logic signed [1:0] L2sb01 = 1;
+    logic signed [1:0] L2sb10 = 2;
+    logic signed [1:0] L2sb11 = 3;
+
+    logic y = 1;
+
+    always @* begin
+
+        assert (1'(L1b0  ) == 1'b0);
+        assert (1'(L1b1  ) == 1'b1);
+        assert (1'(L1sb0 ) == 1'b0);
+        assert (1'(L1sb1 ) == 1'b1);
+        assert (1'(L2b00 ) == 1'b0);
+        assert (1'(L2b01 ) == 1'b1);
+        assert (1'(L2b10 ) == 1'b0);
+        assert (1'(L2b11 ) == 1'b1);
+        assert (1'(L2sb00) == 1'b0);
+        assert (1'(L2sb01) == 1'b1);
+        assert (1'(L2sb10) == 1'b0);
+        assert (1'(L2sb11) == 1'b1);
+
+        assert (2'(L1b0  ) == 2'b00);
+        assert (2'(L1b1  ) == 2'b01);
+        assert (2'(L1sb0 ) == 2'b00);
+        assert (2'(L1sb1 ) == 2'b11);
+        assert (2'(L2b00 ) == 2'b00);
+        assert (2'(L2b01 ) == 2'b01);
+        assert (2'(L2b10 ) == 2'b10);
+        assert (2'(L2b11 ) == 2'b11);
+        assert (2'(L2sb00) == 2'b00);
+        assert (2'(L2sb01) == 2'b01);
+        assert (2'(L2sb10) == 2'b10);
+        assert (2'(L2sb11) == 2'b11);
+
+        assert (3'(L1b0  ) == 3'b000);
+        assert (3'(L1b1  ) == 3'b001);
+        assert (3'(L1sb0 ) == 3'b000);
+        assert (3'(L1sb1 ) == 3'b111);
+        assert (3'(L2b00 ) == 3'b000);
+        assert (3'(L2b01 ) == 3'b001);
+        assert (3'(L2b10 ) == 3'b010);
+        assert (3'(L2b11 ) == 3'b011);
+        assert (3'(L2sb00) == 3'b000);
+        assert (3'(L2sb01) == 3'b001);
+        assert (3'(L2sb10) == 3'b110);
+        assert (3'(L2sb11) == 3'b111);
+
+        assert (3'(L1b0   | '1) == 3'b111);
+        assert (3'(L1b1   | '1) == 3'b111);
+        assert (3'(L1sb0  | '1) == 3'b111);
+        assert (3'(L1sb1  | '1) == 3'b111);
+        assert (3'(L2b00  | '1) == 3'b111);
+        assert (3'(L2b01  | '1) == 3'b111);
+        assert (3'(L2b10  | '1) == 3'b111);
+        assert (3'(L2b11  | '1) == 3'b111);
+        assert (3'(L2sb00 | '1) == 3'b111);
+        assert (3'(L2sb01 | '1) == 3'b111);
+        assert (3'(L2sb10 | '1) == 3'b111);
+        assert (3'(L2sb11 | '1) == 3'b111);
+
+        assert (3'(L1b0   | '0) == 3'b000);
+        assert (3'(L1b1   | '0) == 3'b001);
+        assert (3'(L1sb0  | '0) == 3'b000);
+        assert (3'(L1sb1  | '0) == 3'b001);
+        assert (3'(L2b00  | '0) == 3'b000);
+        assert (3'(L2b01  | '0) == 3'b001);
+        assert (3'(L2b10  | '0) == 3'b010);
+        assert (3'(L2b11  | '0) == 3'b011);
+        assert (3'(L2sb00 | '0) == 3'b000);
+        assert (3'(L2sb01 | '0) == 3'b001);
+        assert (3'(L2sb10 | '0) == 3'b010);
+        assert (3'(L2sb11 | '0) == 3'b011);
+
+        assert (3'(y ? L1b0   : '1) == 3'b000);
+        assert (3'(y ? L1b1   : '1) == 3'b001);
+        assert (3'(y ? L1sb0  : '1) == 3'b000);
+        assert (3'(y ? L1sb1  : '1) == 3'b001);
+        assert (3'(y ? L2b00  : '1) == 3'b000);
+        assert (3'(y ? L2b01  : '1) == 3'b001);
+        assert (3'(y ? L2b10  : '1) == 3'b010);
+        assert (3'(y ? L2b11  : '1) == 3'b011);
+        assert (3'(y ? L2sb00 : '1) == 3'b000);
+        assert (3'(y ? L2sb01 : '1) == 3'b001);
+        assert (3'(y ? L2sb10 : '1) == 3'b010);
+        assert (3'(y ? L2sb11 : '1) == 3'b011);
+
+        assert (3'(y ? L1b0   : '0) == 3'b000);
+        assert (3'(y ? L1b1   : '0) == 3'b001);
+        assert (3'(y ? L1sb0  : '0) == 3'b000);
+        assert (3'(y ? L1sb1  : '0) == 3'b001);
+        assert (3'(y ? L2b00  : '0) == 3'b000);
+        assert (3'(y ? L2b01  : '0) == 3'b001);
+        assert (3'(y ? L2b10  : '0) == 3'b010);
+        assert (3'(y ? L2b11  : '0) == 3'b011);
+        assert (3'(y ? L2sb00 : '0) == 3'b000);
+        assert (3'(y ? L2sb01 : '0) == 3'b001);
+        assert (3'(y ? L2sb10 : '0) == 3'b010);
+        assert (3'(y ? L2sb11 : '0) == 3'b011);
+
+        assert (3'(y ? L1b0   : 1'sb0) == 3'b000);
+        assert (3'(y ? L1b1   : 1'sb0) == 3'b001);
+        assert (3'(y ? L1sb0  : 1'sb0) == 3'b000);
+        assert (3'(y ? L1sb1  : 1'sb0) == 3'b111);
+        assert (3'(y ? L2b00  : 1'sb0) == 3'b000);
+        assert (3'(y ? L2b01  : 1'sb0) == 3'b001);
+        assert (3'(y ? L2b10  : 1'sb0) == 3'b010);
+        assert (3'(y ? L2b11  : 1'sb0) == 3'b011);
+        assert (3'(y ? L2sb00 : 1'sb0) == 3'b000);
+        assert (3'(y ? L2sb01 : 1'sb0) == 3'b001);
+        assert (3'(y ? L2sb10 : 1'sb0) == 3'b110);
+        assert (3'(y ? L2sb11 : 1'sb0) == 3'b111);
+
+        assert (3'(y ? L1b0   : 1'sb1) == 3'b000);
+        assert (3'(y ? L1b1   : 1'sb1) == 3'b001);
+        assert (3'(y ? L1sb0  : 1'sb1) == 3'b000);
+        assert (3'(y ? L1sb1  : 1'sb1) == 3'b111);
+        assert (3'(y ? L2b00  : 1'sb1) == 3'b000);
+        assert (3'(y ? L2b01  : 1'sb1) == 3'b001);
+        assert (3'(y ? L2b10  : 1'sb1) == 3'b010);
+        assert (3'(y ? L2b11  : 1'sb1) == 3'b011);
+        assert (3'(y ? L2sb00 : 1'sb1) == 3'b000);
+        assert (3'(y ? L2sb01 : 1'sb1) == 3'b001);
+        assert (3'(y ? L2sb10 : 1'sb1) == 3'b110);
+        assert (3'(y ? L2sb11 : 1'sb1) == 3'b111);
+
+    end
+endmodule
diff --git a/tests/verilog/size_cast.ys b/tests/verilog/size_cast.ys
new file mode 100644
index 000000000..6890cd2d5
--- /dev/null
+++ b/tests/verilog/size_cast.ys
@@ -0,0 +1,5 @@
+read_verilog -sv size_cast.sv
+proc
+opt -full
+select -module top
+sat -verify -prove-asserts -show-all
-- 
cgit v1.2.3


From aa35f24290b0d7339860c8c8a6145703425fa154 Mon Sep 17 00:00:00 2001
From: Zachary Snow <zach@zachjs.com>
Date: Thu, 6 Jan 2022 22:04:00 -0700
Subject: sv: auto add nosync to certain always_comb local vars

If a local variable is always assigned before it is used, then adding
nosync prevents latches from being needlessly generated.
---
 tests/verilog/always_comb_latch_1.ys   | 13 +++++++++++++
 tests/verilog/always_comb_latch_2.ys   | 15 +++++++++++++++
 tests/verilog/always_comb_latch_3.ys   | 20 ++++++++++++++++++++
 tests/verilog/always_comb_latch_4.ys   | 17 +++++++++++++++++
 tests/verilog/always_comb_nolatch_1.ys | 16 ++++++++++++++++
 tests/verilog/always_comb_nolatch_2.ys | 17 +++++++++++++++++
 tests/verilog/always_comb_nolatch_3.ys | 21 +++++++++++++++++++++
 tests/verilog/always_comb_nolatch_4.ys | 16 ++++++++++++++++
 8 files changed, 135 insertions(+)
 create mode 100644 tests/verilog/always_comb_latch_1.ys
 create mode 100644 tests/verilog/always_comb_latch_2.ys
 create mode 100644 tests/verilog/always_comb_latch_3.ys
 create mode 100644 tests/verilog/always_comb_latch_4.ys
 create mode 100644 tests/verilog/always_comb_nolatch_1.ys
 create mode 100644 tests/verilog/always_comb_nolatch_2.ys
 create mode 100644 tests/verilog/always_comb_nolatch_3.ys
 create mode 100644 tests/verilog/always_comb_nolatch_4.ys

(limited to 'tests')

diff --git a/tests/verilog/always_comb_latch_1.ys b/tests/verilog/always_comb_latch_1.ys
new file mode 100644
index 000000000..c98c79fa2
--- /dev/null
+++ b/tests/verilog/always_comb_latch_1.ys
@@ -0,0 +1,13 @@
+read_verilog -sv <<EOF
+module top;
+logic x;
+always_comb begin
+    logic y;
+    if (x)
+        y = 1;
+    x = y;
+end
+endmodule
+EOF
+logger -expect error "^Latch inferred for signal `\\top\.\$unnamed_block\$1\.y' from always_comb process" 1
+proc
diff --git a/tests/verilog/always_comb_latch_2.ys b/tests/verilog/always_comb_latch_2.ys
new file mode 100644
index 000000000..567205a53
--- /dev/null
+++ b/tests/verilog/always_comb_latch_2.ys
@@ -0,0 +1,15 @@
+read_verilog -sv <<EOF
+module top;
+logic x;
+always_comb begin
+    logic y;
+    if (x)
+        x = 1;
+    else
+        y = 1;
+    x = y;
+end
+endmodule
+EOF
+logger -expect error "^Latch inferred for signal `\\top\.\$unnamed_block\$1\.y' from always_comb process" 1
+proc
diff --git a/tests/verilog/always_comb_latch_3.ys b/tests/verilog/always_comb_latch_3.ys
new file mode 100644
index 000000000..b9b028ac7
--- /dev/null
+++ b/tests/verilog/always_comb_latch_3.ys
@@ -0,0 +1,20 @@
+read_verilog -sv <<EOF
+module top;
+logic x;
+logic z;
+assign z = 1'b1;
+always_comb begin
+    logic y;
+    case (x)
+    1'b0:
+        y = 1;
+    endcase
+    if (z)
+        x = y;
+    else
+        x = 1'b0;
+end
+endmodule
+EOF
+logger -expect error "^Latch inferred for signal `\\top\.\$unnamed_block\$1\.y' from always_comb process" 1
+proc
diff --git a/tests/verilog/always_comb_latch_4.ys b/tests/verilog/always_comb_latch_4.ys
new file mode 100644
index 000000000..46b78801b
--- /dev/null
+++ b/tests/verilog/always_comb_latch_4.ys
@@ -0,0 +1,17 @@
+read_verilog -sv <<EOF
+module top;
+parameter AVOID_LATCH = 0;
+logic x, z;
+assign z = 1'b1;
+always_comb begin
+    logic y;
+    if (z)
+        y = 0;
+    for (int i = 1; i == AVOID_LATCH; i++)
+        y = 1;
+    x = z ? y : 1'b0;
+end
+endmodule
+EOF
+logger -expect error "^Latch inferred for signal `\\top\.\$unnamed_block\$3\.y' from always_comb process" 1
+proc
diff --git a/tests/verilog/always_comb_nolatch_1.ys b/tests/verilog/always_comb_nolatch_1.ys
new file mode 100644
index 000000000..4d1952b52
--- /dev/null
+++ b/tests/verilog/always_comb_nolatch_1.ys
@@ -0,0 +1,16 @@
+read_verilog -sv <<EOF
+module top;
+logic [4:0] x;
+logic z;
+assign z = 1'b1;
+always_comb begin
+    x = '0;
+    if (z) begin
+        for (int i = 0; i < 5; i++) begin
+            x[i] = 1'b1;
+        end
+    end
+end
+endmodule
+EOF
+proc
diff --git a/tests/verilog/always_comb_nolatch_2.ys b/tests/verilog/always_comb_nolatch_2.ys
new file mode 100644
index 000000000..2ec6ca0f4
--- /dev/null
+++ b/tests/verilog/always_comb_nolatch_2.ys
@@ -0,0 +1,17 @@
+read_verilog -sv <<EOF
+module top;
+logic [4:0] x;
+logic z;
+assign z = 1'b1;
+always_comb begin
+    x = '0;
+    if (z) begin
+        int i;
+        for (i = 0; i < 5; i++) begin
+            x[i] = 1'b1;
+        end
+    end
+end
+endmodule
+EOF
+proc
diff --git a/tests/verilog/always_comb_nolatch_3.ys b/tests/verilog/always_comb_nolatch_3.ys
new file mode 100644
index 000000000..33f9833a2
--- /dev/null
+++ b/tests/verilog/always_comb_nolatch_3.ys
@@ -0,0 +1,21 @@
+read_verilog -sv <<EOF
+module top;
+logic x;
+logic z;
+assign z = 1'b1;
+always_comb begin
+    logic y;
+    case (x)
+    1'b0:
+        y = 1;
+    default:
+        y = 0;
+    endcase
+    if (z)
+        x = y;
+    else
+        x = 1'b0;
+end
+endmodule
+EOF
+proc
diff --git a/tests/verilog/always_comb_nolatch_4.ys b/tests/verilog/always_comb_nolatch_4.ys
new file mode 100644
index 000000000..bc29b2771
--- /dev/null
+++ b/tests/verilog/always_comb_nolatch_4.ys
@@ -0,0 +1,16 @@
+read_verilog -sv <<EOF
+module top;
+parameter AVOID_LATCH = 1;
+logic x, z;
+assign z = 1'b1;
+always_comb begin
+    logic y;
+    if (z)
+        y = 0;
+    for (int i = 1; i == AVOID_LATCH; i++)
+        y = 1;
+    x = z ? y : 1'b0;
+end
+endmodule
+EOF
+proc
-- 
cgit v1.2.3


From 07a657fb0ca08012af3de410520458af255b1097 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Marcelina=20Ko=C5=9Bcielnicka?= <mwk@0x04.net>
Date: Sat, 29 Jan 2022 01:01:21 +0100
Subject: opt_reduce: Add $bmux and $demux optimization patterns.

---
 tests/opt/opt_reduce_bmux.ys  | 117 ++++++++++++++++++++++++++++++++++++++++++
 tests/opt/opt_reduce_demux.ys |  91 ++++++++++++++++++++++++++++++++
 2 files changed, 208 insertions(+)
 create mode 100644 tests/opt/opt_reduce_bmux.ys
 create mode 100644 tests/opt/opt_reduce_demux.ys

(limited to 'tests')

diff --git a/tests/opt/opt_reduce_bmux.ys b/tests/opt/opt_reduce_bmux.ys
new file mode 100644
index 000000000..55e0b6d4b
--- /dev/null
+++ b/tests/opt/opt_reduce_bmux.ys
@@ -0,0 +1,117 @@
+read_ilang << EOT
+
+module \top
+  wire width 12 input 0 \A
+  wire width 2 input 1 \S
+  wire width 6 output 2 \Y
+
+  cell $bmux $0
+    parameter \WIDTH 6
+    parameter \S_WIDTH 2
+    connect \A { \A [11:10] \A [3:2] \A [10:9] \A [7] \A [7] \A [8] \A [2] \A [7:6] \A [5] \A [5] \A [3:2] \A [5:4] \A [1] \A [1] \A [3:0] }
+    connect \S \S
+    connect \Y \Y
+  end
+end
+
+EOT
+
+equiv_opt -assert opt_reduce -fine
+opt_reduce -fine
+select -assert-count 1 t:$bmux r:WIDTH=4 %i
+
+design -reset
+
+read_ilang << EOT
+
+module \top
+  wire width 6 input 0 \A
+  wire width 2 input 1 \S
+  wire width 6 output 2 \Y
+
+  cell $bmux $0
+    parameter \WIDTH 6
+    parameter \S_WIDTH 2
+    connect \A { \A [5:0] \A [5:0] \A [5:0] \A [5:0] }
+    connect \S \S
+    connect \Y \Y
+  end
+end
+
+EOT
+
+equiv_opt -assert opt_reduce -fine
+opt_reduce -fine
+select -assert-count 0 t:$bmux
+
+design -reset
+
+read_ilang << EOT
+
+module \top
+  wire width 160 input 0 \A
+  wire width 2 input 1 \S
+  wire width 5 output 2 \Y
+
+  cell $bmux $0
+    parameter \WIDTH 5
+    parameter \S_WIDTH 5
+    connect \A \A
+    connect \S { \S [1] 1'1 \S [0] \S [1] 1'0 }
+    connect \Y \Y
+  end
+end
+
+EOT
+
+equiv_opt -assert opt_reduce -fine
+opt_reduce -fine
+select -assert-count 1 t:$bmux r:S_WIDTH=2 %i
+
+design -reset
+
+read_ilang << EOT
+
+module \top
+  wire width 10 input 0 \A
+  wire input 1 \S
+  wire width 5 output 2 \Y
+
+  cell $bmux $0
+    parameter \WIDTH 5
+    parameter \S_WIDTH 1
+    connect \A \A
+    connect \S \S
+    connect \Y \Y
+  end
+end
+
+EOT
+
+equiv_opt -assert opt_reduce -fine
+opt_reduce -fine
+select -assert-count 0 t:$bmux
+select -assert-count 1 t:$mux
+
+design -reset
+
+read_ilang << EOT
+
+module \top
+  wire width 5 input 0 \A
+  wire width 5 output 1 \Y
+
+  cell $bmux $0
+    parameter \WIDTH 5
+    parameter \S_WIDTH 0
+    connect \A \A
+    connect \S { }
+    connect \Y \Y
+  end
+end
+
+EOT
+
+equiv_opt -assert opt_reduce -fine
+opt_reduce -fine
+select -assert-count 0 t:$bmux
diff --git a/tests/opt/opt_reduce_demux.ys b/tests/opt/opt_reduce_demux.ys
new file mode 100644
index 000000000..3c5bd7d43
--- /dev/null
+++ b/tests/opt/opt_reduce_demux.ys
@@ -0,0 +1,91 @@
+read_ilang << EOT
+
+module \top
+  wire width 4 input 0 \A
+  wire width 2 input 1 \S
+  wire width 24 output 2 \Y
+
+  cell $demux $0
+    parameter \WIDTH 6
+    parameter \S_WIDTH 2
+    connect \A { \A [3] \A [1] 1'0 \A [2:0] }
+    connect \S \S
+    connect \Y \Y
+  end
+end
+
+EOT
+
+equiv_opt -assert opt_reduce -fine
+opt_reduce -fine
+select -assert-count 1 t:$demux r:WIDTH=4 %i
+
+design -reset
+
+read_ilang << EOT
+
+module \top
+  wire width 2 input 1 \S
+  wire width 24 output 2 \Y
+
+  cell $demux $0
+    parameter \WIDTH 6
+    parameter \S_WIDTH 2
+    connect \A 6'000000
+    connect \S \S
+    connect \Y \Y
+  end
+end
+
+EOT
+
+equiv_opt -assert opt_reduce -fine
+opt_reduce -fine
+select -assert-count 0 t:$demux
+
+design -reset
+
+read_ilang << EOT
+
+module \top
+  wire width 5 input 0 \A
+  wire width 2 input 1 \S
+  wire width 160 output 2 \Y
+
+  cell $demux $0
+    parameter \WIDTH 5
+    parameter \S_WIDTH 5
+    connect \A \A
+    connect \S { \S [0] \S [1] 1'1 \S [0] 1'0 }
+    connect \Y \Y
+  end
+end
+
+EOT
+
+equiv_opt -assert opt_reduce -fine
+opt_reduce -fine
+select -assert-count 1 t:$demux r:S_WIDTH=2 %i
+
+design -reset
+
+read_ilang << EOT
+
+module \top
+  wire width 5 input 0 \A
+  wire width 20 output 2 \Y
+
+  cell $demux $0
+    parameter \WIDTH 5
+    parameter \S_WIDTH 2
+    connect \A \A
+    connect \S { 2'10 }
+    connect \Y \Y
+  end
+end
+
+EOT
+
+equiv_opt -assert opt_reduce -fine
+opt_reduce -fine
+select -assert-count 0 t:$demux
-- 
cgit v1.2.3


From 7ef6da4c7d418b53ea2868ea452a856cfb2d5b21 Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Wed, 2 Feb 2022 13:22:44 +0100
Subject: Add test cases for co-simulation

---
 tests/sat/.gitignore      |   2 +
 tests/sat/alu.v           |  79 +++++
 tests/sat/grom.ys         |   9 +
 tests/sat/grom_computer.v |  31 ++
 tests/sat/grom_cpu.v      | 747 ++++++++++++++++++++++++++++++++++++++++++++++
 tests/sat/ram_memory.v    |  37 +++
 tests/sat/sim_counter.ys  |  48 +++
 7 files changed, 953 insertions(+)
 create mode 100644 tests/sat/alu.v
 create mode 100644 tests/sat/grom.ys
 create mode 100644 tests/sat/grom_computer.v
 create mode 100644 tests/sat/grom_cpu.v
 create mode 100644 tests/sat/ram_memory.v
 create mode 100644 tests/sat/sim_counter.ys

(limited to 'tests')

diff --git a/tests/sat/.gitignore b/tests/sat/.gitignore
index 8355de9dc..664425d73 100644
--- a/tests/sat/.gitignore
+++ b/tests/sat/.gitignore
@@ -1,2 +1,4 @@
 *.log
 run-test.mk
+*.vcd
+*.fst
diff --git a/tests/sat/alu.v b/tests/sat/alu.v
new file mode 100644
index 000000000..9826fe05d
--- /dev/null
+++ b/tests/sat/alu.v
@@ -0,0 +1,79 @@
+module alu(
+	input clk,
+	input [7:0] A,
+	input [7:0] B,
+	input [3:0] operation,
+	output reg [7:0] result,
+	output reg CF,
+	output reg ZF,
+	output reg SF
+);
+
+	localparam ALU_OP_ADD /* verilator public_flat */ = 4'b0000;
+	localparam ALU_OP_SUB /* verilator public_flat */ = 4'b0001;
+	localparam ALU_OP_ADC /* verilator public_flat */ = 4'b0010;
+	localparam ALU_OP_SBC /* verilator public_flat */ = 4'b0011;
+
+	localparam ALU_OP_AND /* verilator public_flat */ = 4'b0100;
+	localparam ALU_OP_OR  /* verilator public_flat */ = 4'b0101;
+	localparam ALU_OP_NOT /* verilator public_flat */ = 4'b0110;
+	localparam ALU_OP_XOR /* verilator public_flat */ = 4'b0111;
+
+	localparam ALU_OP_SHL /* verilator public_flat */ = 4'b1000;
+	localparam ALU_OP_SHR /* verilator public_flat */ = 4'b1001;
+	localparam ALU_OP_SAL /* verilator public_flat */ = 4'b1010;
+	localparam ALU_OP_SAR /* verilator public_flat */ = 4'b1011;
+
+	localparam ALU_OP_ROL /* verilator public_flat */ = 4'b1100;
+	localparam ALU_OP_ROR /* verilator public_flat */ = 4'b1101;
+	localparam ALU_OP_RCL /* verilator public_flat */ = 4'b1110;
+	localparam ALU_OP_RCR /* verilator public_flat */ = 4'b1111;
+
+	reg [8:0] tmp;
+
+	always @(posedge clk)
+	begin
+		case (operation)
+			ALU_OP_ADD :
+				tmp = A + B;
+			ALU_OP_SUB :
+				tmp = A - B;
+			ALU_OP_ADC :
+				tmp = A + B + { 7'b0000000, CF };
+			ALU_OP_SBC :
+				tmp = A - B - { 7'b0000000, CF };
+			ALU_OP_AND :
+				tmp = {1'b0, A & B };
+			ALU_OP_OR :
+				tmp = {1'b0, A | B };
+			ALU_OP_NOT :
+				tmp = {1'b0, ~B };
+			ALU_OP_XOR :
+				tmp = {1'b0, A ^ B};
+			ALU_OP_SHL :
+				tmp = { A[7], A[6:0], 1'b0};
+			ALU_OP_SHR :
+				tmp = { A[0], 1'b0, A[7:1]};
+			ALU_OP_SAL :
+				// Same as SHL
+				tmp = { A[7], A[6:0], 1'b0};
+			ALU_OP_SAR :
+				tmp = { A[0], A[7], A[7:1]};
+			ALU_OP_ROL :
+				tmp = { A[7], A[6:0], A[7]};
+			ALU_OP_ROR :
+				tmp = { A[0], A[0], A[7:1]};
+			ALU_OP_RCL :
+				tmp = { A[7], A[6:0], CF};
+			ALU_OP_RCR :
+				tmp = { A[0], CF, A[7:1]};
+		endcase
+
+		CF <= tmp[8];
+		ZF <= tmp[7:0] == 0;
+		SF <= tmp[7];
+
+		result <= tmp[7:0];
+	end
+endmodule
+
diff --git a/tests/sat/grom.ys b/tests/sat/grom.ys
new file mode 100644
index 000000000..2c2cd71da
--- /dev/null
+++ b/tests/sat/grom.ys
@@ -0,0 +1,9 @@
+read_verilog grom_computer.v grom_cpu.v alu.v ram_memory.v;
+prep -top grom_computer; 
+sim -clock clk -reset reset -fst grom.fst -vcd grom.vcd -a -n 80
+
+sim -clock clk -r grom.fst -scope grom_computer -start 25ns -stop 100ns -sim-cmp
+
+sim -clock clk -r grom.fst -scope grom_computer -stop 100ns -sim-gold
+
+sim -clock clk -r grom.fst -scope grom_computer -n 10 -sim-gate -a
diff --git a/tests/sat/grom_computer.v b/tests/sat/grom_computer.v
new file mode 100644
index 000000000..63a5c8ff8
--- /dev/null
+++ b/tests/sat/grom_computer.v
@@ -0,0 +1,31 @@
+module grom_computer
+  (input  clk,     // Main Clock
+   input  reset,   // reset
+   output hlt,
+   output reg[7:0] display_out
+  );
+
+ wire [11:0] addr;
+ wire [7:0] memory_out;
+ wire [7:0] memory_in;
+ wire mem_enable;
+ wire  we;
+ wire ioreq;
+
+ grom_cpu cpu(.clk(clk),.reset(reset),.addr(addr),.data_in(memory_out),.data_out(memory_in),.we(we),.ioreq(ioreq),.hlt(hlt));
+
+ assign mem_enable = we & ~ioreq;
+
+ ram_memory memory(.clk(clk),.addr(addr),.data_in(memory_in),.we(mem_enable),.data_out(memory_out));
+
+ always @(posedge clk)
+	begin
+		if(ioreq==1 && we==1)
+		begin
+			display_out <= memory_in;
+			`ifdef DISASSEMBLY
+			$display("Display output : %h", memory_in);
+			`endif
+		end
+	end
+endmodule
diff --git a/tests/sat/grom_cpu.v b/tests/sat/grom_cpu.v
new file mode 100644
index 000000000..f9fef043b
--- /dev/null
+++ b/tests/sat/grom_cpu.v
@@ -0,0 +1,747 @@
+module grom_cpu(
+	input clk,
+	input reset,
+	output reg [11:0] addr,
+	input [7:0] data_in,
+	output reg [7:0] data_out,
+	output reg we,
+	output reg ioreq,
+	output reg hlt
+);
+
+	reg[11:0] PC /* verilator public_flat */;    		// Program counter
+	reg[7:0] IR /* verilator public_flat */;    	    // Instruction register
+	reg[7:0] VALUE /* verilator public_flat */;   		// Temp reg for storing 2nd operand
+	reg[3:0] CS /* verilator public_flat */;    		// Code segment regiser
+	reg[3:0] DS /* verilator public_flat */;    		// Data segment regiser
+	reg[11:0] SP /* verilator public_flat */;    		// Stack pointer regiser
+	reg[7:0] R[0:3] /* verilator public_flat */; 		// General purpose registers
+	reg[11:0] FUTURE_PC /* verilator public_flat */;    // PC to jump to
+
+	localparam STATE_RESET             /*verilator public_flat*/ = 5'b00000;
+	localparam STATE_FETCH_PREP        /*verilator public_flat*/ = 5'b00001;
+	localparam STATE_FETCH_WAIT        /*verilator public_flat*/ = 5'b00010;
+	localparam STATE_FETCH             /*verilator public_flat*/ = 5'b00011;
+	localparam STATE_EXECUTE           /*verilator public_flat*/ = 5'b00100;
+	localparam STATE_FETCH_VALUE_PREP  /*verilator public_flat*/ = 5'b00101;
+	localparam STATE_FETCH_VALUE       /*verilator public_flat*/ = 5'b00110;
+	localparam STATE_EXECUTE_DBL       /*verilator public_flat*/ = 5'b00111;
+	localparam STATE_LOAD_VALUE        /*verilator public_flat*/ = 5'b01000;
+	localparam STATE_LOAD_VALUE_WAIT   /*verilator public_flat*/ = 5'b01001;
+	localparam STATE_ALU_RESULT_WAIT   /*verilator public_flat*/ = 5'b01010;
+	localparam STATE_ALU_RESULT        /*verilator public_flat*/ = 5'b01011;
+	localparam STATE_PUSH_PC_LOW       /*verilator public_flat*/ = 5'b01100;
+	localparam STATE_JUMP              /*verilator public_flat*/ = 5'b01101;
+	localparam STATE_RET_VALUE_WAIT    /*verilator public_flat*/ = 5'b01110;
+	localparam STATE_RET_VALUE         /*verilator public_flat*/ = 5'b01111;
+	localparam STATE_RET_VALUE_WAIT2   /*verilator public_flat*/ = 5'b10000;
+	localparam STATE_RET_VALUE2        /*verilator public_flat*/ = 5'b10001;
+
+	reg [4:0] state /* verilator public_flat */ = STATE_RESET;
+
+	reg [7:0]  alu_a /* verilator public_flat */;
+	reg [7:0]  alu_b /* verilator public_flat */;
+	reg [3:0]  alu_op /* verilator public_flat */;
+
+	reg [1:0]  RESULT_REG /* verilator public_flat */;
+
+	wire [7:0] alu_res /* verilator public_flat */;
+	wire alu_CF /* verilator public_flat */;
+	wire alu_ZF /* verilator public_flat */;
+	wire alu_SF /* verilator public_flat */;
+	reg jump;
+
+	alu alu(.clk(clk),.A(alu_a),.B(alu_b),.operation(alu_op),.result(alu_res),.CF(alu_CF),.ZF(alu_ZF),.SF(alu_SF));
+
+	always @(posedge clk)
+	begin
+		if (reset)
+		begin
+			state <= STATE_RESET;
+			hlt   <= 0;
+		end
+		else
+		begin
+			case (state)
+				STATE_RESET :
+					begin
+						PC    <= 12'h000;
+						state <= STATE_FETCH_PREP;
+						CS    <= 4'h0;
+						DS    <= 4'h0;
+						R[0]  <= 8'h00;
+						R[1]  <= 8'h00;
+						R[2]  <= 8'h00;
+						R[3]  <= 8'h00;
+						SP    <= 12'hfff;
+					end
+
+				STATE_FETCH_PREP :
+					begin
+						addr  <= PC;
+						we    <= 0;
+						ioreq <= 0;
+
+						state <= STATE_FETCH_WAIT;
+					end
+
+				STATE_FETCH_WAIT :
+					begin
+						// Sync with memory due to CLK
+						state <= (hlt) ? STATE_FETCH_PREP : STATE_FETCH;
+					end
+
+				STATE_FETCH :
+					begin
+						IR    <= data_in;
+						PC    <= PC + 1;
+
+						state <= STATE_EXECUTE;
+					end
+				STATE_EXECUTE :
+					begin
+						`ifdef DISASSEMBLY
+						$display("    PC %h R0 %h R1 %h R2 %h R3 %h CS %h DS %h SP %h ALU [%d %d %d]", PC, R[0], R[1], R[2], R[3], CS, DS, SP, alu_CF,alu_SF,alu_ZF);
+						`endif
+						if (IR[7])
+						begin
+							addr  <= PC;
+							state <= STATE_FETCH_VALUE_PREP;
+							PC    <= PC + 1;
+						end
+						else
+						begin
+							case(IR[6:4])
+								3'b000 :
+									begin
+										`ifdef DISASSEMBLY
+										$display("MOV R%d,R%d",IR[3:2],IR[1:0]);
+										`endif
+										R[IR[3:2]] <= R[IR[1:0]];
+										state <= STATE_FETCH_PREP;
+									end
+								3'b001 :
+									begin
+										alu_a   <= R[0];      // first input R0
+										alu_b   <= R[IR[1:0]];
+										RESULT_REG <= 0;         // result in R0
+										alu_op  <= { 2'b00, IR[3:2] };
+
+										state   <= STATE_ALU_RESULT_WAIT;
+
+										`ifdef DISASSEMBLY
+										case(IR[3:2])
+											2'b00 : begin
+													$display("ADD R%d",IR[1:0]);
+													end
+											2'b01 : begin
+													$display("SUB R%d",IR[1:0]);
+													end
+											2'b10 : begin
+													$display("ADC R%d",IR[1:0]);
+													end
+											2'b11 : begin
+													$display("SBC R%d",IR[1:0]);
+													end
+										endcase
+										`endif
+									end
+								3'b010 :
+									begin
+										alu_a   <= R[0];      // first input R0
+										alu_b   <= R[IR[1:0]];
+										RESULT_REG <= 0;         // result in R0
+										alu_op  <= { 2'b01, IR[3:2] };
+										state   <= STATE_ALU_RESULT_WAIT;
+										`ifdef DISASSEMBLY
+										case(IR[3:2])
+											2'b00 : begin
+													$display("AND R%d",IR[1:0]);
+													end
+											2'b01 : begin
+													$display("OR R%d",IR[1:0]);
+													end
+											2'b10 : begin
+													$display("NOT R%d",IR[1:0]);
+													end
+											2'b11 : begin
+													$display("XOR R%d",IR[1:0]);
+													end
+										endcase
+										`endif
+									end
+								3'b011 :
+									begin
+										RESULT_REG <= IR[1:0];  // result in REG
+										// CMP and TEST are not storing result										
+										state   <= IR[3] ? STATE_FETCH_PREP : STATE_ALU_RESULT_WAIT;
+										// CMP and TEST are having first input R0, for INC and DEC is REG
+										alu_a   <= IR[3] ? R[0] : R[IR[1:0]];								
+										// CMP and TEST are having second input REG, for INC and DEC is 1
+										alu_b   <= IR[3] ? R[IR[1:0]] : 8'b00000001;								
+
+										case(IR[3:2])
+											2'b00 : begin
+													`ifdef DISASSEMBLY
+													$display("INC R%d",IR[1:0]);
+													`endif
+													alu_op  <= 4'b0001;     // ALU_OP_ADD
+													end
+											2'b01 : begin
+													`ifdef DISASSEMBLY
+													$display("DEC R%d",IR[1:0]);
+													`endif
+													alu_op  <= 4'b0001;     // ALU_OP_SUB
+													end
+											2'b10 : begin
+													`ifdef DISASSEMBLY
+													$display("CMP R%d",IR[1:0]);
+													`endif
+													alu_op  <= 4'b0001;     // ALU_OP_SUB
+													end
+											2'b11 : begin
+													`ifdef DISASSEMBLY
+													$display("TST R%d",IR[1:0]);
+													`endif
+													alu_op  <= 4'b0100;     // ALU_OP_AND
+													end
+										endcase
+									end
+								3'b100 :
+									begin
+										if (IR[3]==0)
+										begin
+											alu_a   <= R[0];      // first input R0
+											// no 2nd input
+											RESULT_REG <= 0;         // result in R0
+											alu_op  <= { 1'b1, IR[2:0] };
+											`ifdef DISASSEMBLY
+											case(IR[2:0])
+												3'b000 : begin
+														$display("SHL");
+														end
+												3'b001 : begin
+														$display("SHR");
+														end
+												3'b010 : begin
+														$display("SAL");
+														end
+												3'b011 : begin
+														$display("SAR");
+														end
+												3'b100 : begin
+														$display("ROL");
+														end
+												3'b101 : begin
+														$display("ROR");
+														end
+												3'b110 : begin
+														$display("RCL");
+														end
+												3'b111 : begin
+														$display("RCR");
+														end
+											endcase
+											`endif
+											state   <= STATE_ALU_RESULT_WAIT;
+										end
+										else
+										begin
+											if (IR[2]==0)
+											begin
+												`ifdef DISASSEMBLY
+												$display("PUSH R%d",IR[1:0]);
+												`endif
+												addr     <= SP;
+												we       <= 1;
+												ioreq    <= 0;
+												data_out <= R[IR[1:0]];
+												SP       <= SP - 1;
+												state    <= STATE_FETCH_PREP;
+											end
+											else
+											begin
+												`ifdef DISASSEMBLY
+												$display("POP R%d",IR[1:0]);
+												`endif
+												addr  <= SP + 1;
+												we    <= 0;
+												ioreq <= 0;
+												RESULT_REG <= IR[1:0];
+												SP    <= SP + 1;
+												state <= STATE_LOAD_VALUE_WAIT;
+											end
+										end
+									end
+								3'b101 :
+									begin
+										`ifdef DISASSEMBLY
+										$display("LOAD R%d,[R%d]", IR[3:2], IR[1:0]);
+										`endif
+										addr  <= { DS, R[IR[1:0]] };
+										we    <= 0;
+										ioreq <= 0;
+										RESULT_REG <= IR[3:2];
+
+										state <= STATE_LOAD_VALUE_WAIT;
+									end
+								3'b110 :
+									begin
+										`ifdef DISASSEMBLY
+										$display("STORE [R%d],R%d", IR[3:2], IR[1:0]);
+										`endif
+										addr     <= { DS, R[IR[3:2]] };
+										we       <= 1;
+										ioreq    <= 0;
+										data_out <= R[IR[1:0]];
+
+										state    <= STATE_FETCH_PREP;
+									end
+								3'b111 :
+									begin
+										// Special instuctions
+										case(IR[3:2])
+											2'b00 : begin
+													CS <= R[IR[1:0]][3:0];
+													state <= STATE_FETCH_PREP;
+													`ifdef DISASSEMBLY
+													$display("MOV CS,R%d",IR[1:0]);
+													`endif
+													end
+											2'b01 : begin
+													DS <= R[IR[1:0]][3:0];
+													state <= STATE_FETCH_PREP;
+													`ifdef DISASSEMBLY
+													$display("MOV DS,R%d",IR[1:0]);
+													`endif
+													end
+											2'b10 : begin
+														case(IR[1:0])
+															2'b00 : begin
+																	`ifdef DISASSEMBLY
+																	$display("PUSH CS");
+																	`endif
+																	addr     <= SP;
+																	we       <= 1;
+																	ioreq    <= 0;
+																	data_out <= { 4'b0000, CS};
+																	SP       <= SP - 1;
+																	state    <= STATE_FETCH_PREP;
+																	end
+															2'b01 : begin
+																	`ifdef DISASSEMBLY
+																	$display("PUSH DS");
+																	`endif
+																	addr     <= SP;
+																	we       <= 1;
+																	ioreq    <= 0;
+																	data_out <= { 4'b0000, DS};
+																	SP       <= SP - 1;
+																	state    <= STATE_FETCH_PREP;
+																	end
+															2'b10 : begin
+																	`ifdef DISASSEMBLY
+																	$display("Unused opcode");
+																	`endif
+																	end
+															2'b11 : begin
+																	`ifdef DISASSEMBLY
+																	$display("Unused opcode");
+																	`endif
+																end
+														endcase
+														state <= STATE_FETCH_PREP;
+													end
+											2'b11 : begin
+														case(IR[1:0])
+															2'b00 : begin
+																	`ifdef DISASSEMBLY
+																	$display("Unused opcode");
+																	`endif
+																	state <= STATE_FETCH_PREP;
+																	end
+															2'b01 : begin
+																	`ifdef DISASSEMBLY
+																	$display("Unused opcode");
+																	`endif
+																	state <= STATE_FETCH_PREP;
+																	end
+															2'b10 : begin
+																	`ifdef DISASSEMBLY
+																	$display("RET");
+																	`endif
+																	addr  <= SP + 1;
+																	we    <= 0;
+																	ioreq <= 0;
+																	SP    <= SP + 1;
+																	state <= STATE_RET_VALUE_WAIT;
+																	end
+															2'b11 : begin
+																	hlt <= 1;
+																	`ifdef DISASSEMBLY
+																	$display("HALT");
+																	`endif
+																	state <= STATE_FETCH_PREP;
+																	end
+														endcase
+												end
+										endcase
+									end
+							endcase
+						end
+					end
+				STATE_FETCH_VALUE_PREP :
+					begin
+						// Sync with memory due to CLK
+						state <= STATE_FETCH_VALUE;
+					end
+				STATE_FETCH_VALUE :
+					begin
+						VALUE <= data_in;
+						state <= STATE_EXECUTE_DBL;
+					end
+				STATE_EXECUTE_DBL :
+					begin
+						case(IR[6:4])
+							3'b000 :
+								begin
+								if (IR[3]==0)
+									begin
+										case(IR[2:0])
+											3'b000 :
+												begin
+													`ifdef DISASSEMBLY
+													$display("JMP %h ",{ CS, VALUE[7:0] });
+													`endif
+													jump = 1;
+												end
+											3'b001 :
+												begin
+													`ifdef DISASSEMBLY
+													$display("JC %h ",{CS, VALUE[7:0] });
+													`endif
+													jump = (alu_CF==1);
+												end
+											3'b010 :
+												begin
+													`ifdef DISASSEMBLY
+													$display("JNC %h ",{CS, VALUE[7:0] });
+													`endif
+													jump = (alu_CF==0);
+												end
+											3'b011 :
+												begin
+													`ifdef DISASSEMBLY
+													$display("JM %h ",{CS, VALUE[7:0] });
+													`endif
+													jump = (alu_SF==1);
+												end
+											3'b100 :
+												begin
+													`ifdef DISASSEMBLY
+													$display("JP %h ",{CS, VALUE[7:0] });
+													`endif
+													jump = (alu_SF==0);
+												end
+											3'b101 :
+												begin
+													`ifdef DISASSEMBLY
+													$display("JZ %h ",{CS, VALUE[7:0] });
+													`endif
+													jump = (alu_ZF==1);
+												end
+											3'b110 :
+												begin
+													`ifdef DISASSEMBLY
+													$display("JNZ %h ",{CS, VALUE[7:0] });
+													`endif
+													jump = (alu_ZF==0);
+												end
+											3'b111 :
+												begin
+													`ifdef DISASSEMBLY
+													$display("Unused opcode %h",IR);
+													`endif
+													jump = 0;
+												end
+										endcase
+
+										if (jump)
+										begin
+											PC    <= { CS, VALUE[7:0] };
+											addr  <= { CS, VALUE[7:0] };
+											we    <= 0;
+											ioreq <= 0;
+										end
+										state <= STATE_FETCH_PREP;
+									end
+								else
+									begin
+										case(IR[2:0])
+											3'b000 :
+												begin
+													`ifdef DISASSEMBLY
+													$display("JR %h ", PC + {VALUE[7],VALUE[7],VALUE[7],VALUE[7],VALUE[7:0]} );
+													`endif
+													jump = 1;
+												end
+											3'b001 :
+												begin
+													`ifdef DISASSEMBLY
+													$display("JRC %h ",{CS, VALUE[7:0] });
+													`endif
+													jump = (alu_CF==1);
+												end
+											3'b010 :
+												begin
+													`ifdef DISASSEMBLY
+													$display("JRNC %h ",{CS, VALUE[7:0] });
+													`endif
+													jump = (alu_CF==0);
+												end
+											3'b011 :
+												begin
+													`ifdef DISASSEMBLY
+													$display("JRM %h ",{CS, VALUE[7:0] });
+													`endif
+													jump = (alu_SF==1);
+												end
+											3'b100 :
+												begin
+													`ifdef DISASSEMBLY
+													$display("JRP %h ",{CS, VALUE[7:0] });
+													`endif
+													jump = (alu_SF==0);
+												end
+											3'b101 :
+												begin
+													`ifdef DISASSEMBLY
+													$display("JRZ %h ",{CS, VALUE[7:0] });
+													`endif
+													jump = (alu_ZF==1);
+												end
+											3'b110 :
+												begin
+													`ifdef DISASSEMBLY
+													$display("JRNZ %h ",{CS, VALUE[7:0] });
+													`endif
+													jump = (alu_ZF==0);
+												end
+											3'b111 :
+												begin
+													`ifdef DISASSEMBLY
+													$display("Unused opcode %h",IR);
+													`endif
+													jump = 0;
+												end
+										endcase
+										if (jump)
+										begin
+											PC    <= PC + {VALUE[7],VALUE[7],VALUE[7],VALUE[7],VALUE[7:0]};
+											addr  <= PC + {VALUE[7],VALUE[7],VALUE[7],VALUE[7],VALUE[7:0]};
+											we    <= 0;
+											ioreq <= 0;
+										end
+										state <= STATE_FETCH_PREP;
+									end
+								end
+							3'b001 :
+								begin
+									`ifdef DISASSEMBLY
+									$display("JUMP %h ",{ IR[3:0], VALUE[7:0] });
+									`endif
+									PC    <= { IR[3:0], VALUE[7:0] };
+									addr  <= { IR[3:0], VALUE[7:0] };
+									we    <= 0;
+									ioreq <= 0;
+									state <= STATE_FETCH_PREP;
+								end
+							3'b010 :
+								begin
+									`ifdef DISASSEMBLY
+									$display("CALL %h ",{ IR[3:0], VALUE[7:0] });
+									`endif
+									FUTURE_PC <= { IR[3:0], VALUE[7:0] };
+									addr     <= SP;
+									we       <= 1;
+									ioreq    <= 0;
+									data_out <= { 4'b0000, PC[11:8]};
+									SP       <= SP - 1;
+									state    <= STATE_PUSH_PC_LOW;
+								end
+							3'b011 :
+								begin
+									`ifdef DISASSEMBLY
+									$display("MOV SP,%h ",{ IR[3:0], VALUE[7:0] });
+									`endif
+									SP <= { IR[3:0], VALUE[7:0] };
+									state <= STATE_FETCH_PREP;
+								end
+							3'b100 :
+								begin
+									`ifdef DISASSEMBLY
+									$display("IN R%d,[0x%h]",IR[1:0], VALUE);
+									`endif
+									ioreq <= 1;
+									we    <= 0;
+									addr  <= { 4'b0000, VALUE };
+									RESULT_REG <= IR[1:0];
+									state    <= STATE_LOAD_VALUE_WAIT;
+								end
+							3'b101 :
+								begin
+									`ifdef DISASSEMBLY
+									$display("OUT [0x%h],R%d",VALUE,IR[1:0]);
+									`endif
+									ioreq <= 1;
+									we    <= 1;
+									addr  <= { 4'b0000, VALUE };
+									data_out <= R[IR[1:0]];
+									state    <= STATE_FETCH_PREP;
+								end
+							3'b110 :
+								begin
+									// Special instuctions
+									case(IR[1:0])
+										2'b00 : begin
+												`ifdef DISASSEMBLY
+												$display("MOV CS,0x%h",VALUE);
+												`endif
+												CS <= VALUE[3:0];
+												state <= STATE_FETCH_PREP;
+												end
+										2'b01 : begin
+												`ifdef DISASSEMBLY
+												$display("MOV DS,0x%h",VALUE);
+												`endif
+												DS <= VALUE[3:0];
+												state <= STATE_FETCH_PREP;
+												end
+										2'b10 : begin
+												`ifdef DISASSEMBLY
+												$display("Unused opcode %h",IR);
+												`endif
+												state <= STATE_FETCH_PREP;
+												end
+										2'b11 : begin
+												`ifdef DISASSEMBLY
+												$display("Unused opcode %h",IR);
+												`endif
+												state <= STATE_FETCH_PREP;
+												end
+									endcase
+								end
+							3'b111 :
+								begin
+									case(IR[3:2])
+										2'b00 : begin
+													`ifdef DISASSEMBLY
+													$display("MOV R%d,0x%h",IR[1:0],VALUE);
+													`endif
+													R[IR[1:0]] <= VALUE;
+													state <= STATE_FETCH_PREP;
+												end
+										2'b01 : begin
+													`ifdef DISASSEMBLY
+													$display("LOAD R%d,[0x%h]",IR[1:0], {DS, VALUE});
+													`endif
+													addr  <= { DS, VALUE };
+													we    <= 0;
+													ioreq <= 0;
+													RESULT_REG <= IR[1:0];
+
+													state <= STATE_LOAD_VALUE_WAIT;
+												end
+										2'b10 : begin
+													`ifdef DISASSEMBLY
+													$display("STORE [0x%h],R%d", {DS, VALUE}, IR[1:0]);
+													`endif
+													addr     <= { DS, VALUE };
+													we       <= 1;
+													ioreq    <= 0;
+													data_out <= R[IR[1:0]];
+
+													state    <= STATE_FETCH_PREP;
+												end
+										2'b11 : begin
+													`ifdef DISASSEMBLY
+													$display("Unused opcode %h",IR);
+													`endif
+													state <= STATE_FETCH_PREP;
+												end
+									endcase
+								end
+						endcase
+					end
+				STATE_LOAD_VALUE_WAIT :
+					begin
+						// Sync with memory due to CLK
+						state <= STATE_LOAD_VALUE;
+					end
+				STATE_LOAD_VALUE :
+					begin
+						R[RESULT_REG] <= data_in;
+						we    <= 0;
+						state <= STATE_FETCH_PREP;
+					end
+				STATE_ALU_RESULT_WAIT :
+					begin
+						state <= STATE_ALU_RESULT;
+					end
+				STATE_ALU_RESULT :
+					begin
+						R[RESULT_REG] <= alu_res;
+						state <= STATE_FETCH_PREP;
+					end
+				STATE_PUSH_PC_LOW :
+					begin
+						addr     <= SP;
+						we       <= 1;
+						ioreq    <= 0;
+						data_out <= PC[7:0];
+						SP       <= SP - 1;
+						state    <= STATE_JUMP;
+					end
+				STATE_JUMP :
+					begin
+						`ifdef DISASSEMBLY
+						$display("Jumping to %h",FUTURE_PC);
+						`endif
+						PC <= FUTURE_PC;
+						state <= STATE_FETCH_PREP;
+					end
+				STATE_RET_VALUE_WAIT :
+					begin
+						// Sync with memory due to CLK
+						state <= STATE_RET_VALUE;
+					end
+				STATE_RET_VALUE :
+					begin
+						FUTURE_PC <= { 4'b0000, data_in };
+						we    <= 0;
+						state <= STATE_RET_VALUE_WAIT2;
+
+						addr  <= SP + 1;
+						we    <= 0;
+						ioreq <= 0;
+						SP    <= SP + 1;
+					end
+				STATE_RET_VALUE_WAIT2 :
+					begin
+						// Sync with memory due to CLK
+						state <= STATE_RET_VALUE2;
+					end
+				STATE_RET_VALUE2 :
+					begin
+						FUTURE_PC <= FUTURE_PC | ({ 4'b0000, data_in } << 8);
+						we    <= 0;
+						state <= STATE_JUMP;
+					end
+				default :
+					begin
+						state <= STATE_FETCH_PREP;
+					end
+			endcase
+		end
+	end
+endmodule
diff --git a/tests/sat/ram_memory.v b/tests/sat/ram_memory.v
new file mode 100644
index 000000000..053ef206c
--- /dev/null
+++ b/tests/sat/ram_memory.v
@@ -0,0 +1,37 @@
+module ram_memory(
+  input clk,
+  input [11:0] addr,
+  input [7:0] data_in,
+  input we,
+  output reg [7:0] data_out
+);
+
+  reg [7:0] store[0:4095] /* verilator public_flat */;
+
+  initial
+  begin
+	store[0] <= 8'b11100001; // MOV DS,2
+	store[1] <= 8'b00000010; //
+	store[2] <= 8'b01010100; // LOAD R1,[R0]
+	store[3] <= 8'b00110001; // INC R1
+	store[4] <= 8'b00110001; // INC R1
+	store[5] <= 8'b01100001; // STORE [R0],R1
+	store[6] <= 8'b11010001; // OUT [0],R1
+	store[7] <= 8'b00000000; //
+	store[8] <= 8'b00110001; // INC R1
+	store[9] <= 8'b10100001; // CALL 0x100
+	store[10] <= 8'b00000000; //
+	store[11] <= 8'b01111111; // HLT
+
+
+	store[256] <= 8'b11010001; // OUT [0],R1
+	store[257] <= 8'b00000000; //
+	store[258] <= 8'b01111110; // RET
+  end
+
+  always @(posedge clk)
+	if (we)
+	  store[addr] <= data_in;
+	else
+	  data_out <= store[addr];
+endmodule
diff --git a/tests/sat/sim_counter.ys b/tests/sat/sim_counter.ys
new file mode 100644
index 000000000..a0ff41b6e
--- /dev/null
+++ b/tests/sat/sim_counter.ys
@@ -0,0 +1,48 @@
+# Create stimulus file
+read_verilog <<EOT
+module top (clk, reset, cnt);
+
+input		clk;
+input		reset;
+output	[7:0]	cnt;
+
+reg	[7:0]	cnt;
+
+endmodule
+EOT
+prep -top top;
+sim -clock clk -reset reset -fst stimulus.fst -n 10
+design -reset
+
+# Counter implementation
+read_verilog <<EOT
+module top (clk, reset, cnt);
+
+input		clk;
+input		reset;
+output	[7:0]	cnt;
+
+reg	[7:0]	cnt;
+
+always @(posedge clk)
+	if (!reset)
+		cnt = cnt + 1;
+	else
+		cnt = 0;
+
+endmodule
+EOT
+prep -top top;
+
+# Simulate with stimulus
+sim -clock clk -scope top -r stimulus.fst
+
+# Stimulus does not have counter values
+# x in FST can match any value in simulation
+sim -clock clk -scope top -r stimulus.fst -sim-gate
+
+# Stimulus does not have counter values
+# x in simulation can match any value in FST
+# so we expect error
+logger -expect error "Signal difference" 1
+sim -clock clk -scope top -r stimulus.fst -sim-gold
-- 
cgit v1.2.3


From 6db23de7b13c57eb82489d4bf2f0658b6deb4488 Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Fri, 4 Feb 2022 10:01:06 +0100
Subject: bug fix and cleanups

---
 tests/sat/grom.ys | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

(limited to 'tests')

diff --git a/tests/sat/grom.ys b/tests/sat/grom.ys
index 2c2cd71da..da0f3b620 100644
--- a/tests/sat/grom.ys
+++ b/tests/sat/grom.ys
@@ -1,9 +1,9 @@
 read_verilog grom_computer.v grom_cpu.v alu.v ram_memory.v;
 prep -top grom_computer; 
-sim -clock clk -reset reset -fst grom.fst -vcd grom.vcd -a -n 80
+sim -clock clk -reset reset -fst grom.fst -vcd grom.vcd -n 80
 
 sim -clock clk -r grom.fst -scope grom_computer -start 25ns -stop 100ns -sim-cmp
 
 sim -clock clk -r grom.fst -scope grom_computer -stop 100ns -sim-gold
 
-sim -clock clk -r grom.fst -scope grom_computer -n 10 -sim-gate -a
+sim -clock clk -r grom.fst -scope grom_computer -n 10 -sim-gate
-- 
cgit v1.2.3


From f61f2a4078f36bbb1e44285d25c9e62869520cfa Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Marcelina=20Ko=C5=9Bcielnicka?= <mwk@0x04.net>
Date: Wed, 9 Feb 2022 06:13:34 +0100
Subject: gowin: Fix LUT RAM inference, add more models.

---
 tests/arch/gowin/lutram.ys | 5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)

(limited to 'tests')

diff --git a/tests/arch/gowin/lutram.ys b/tests/arch/gowin/lutram.ys
index 56f69e7c5..d668783a2 100644
--- a/tests/arch/gowin/lutram.ys
+++ b/tests/arch/gowin/lutram.ys
@@ -7,12 +7,11 @@ memory
 opt -full
 
 miter -equiv -flatten -make_assert -make_outputs gold gate miter
-#ERROR: Called with -verify and proof did fail!
-#sat -verify -prove-asserts -seq 5 -set-init-zero -show-inputs -show-outputs miter
+sat -verify -prove-asserts -seq 5 -set-init-zero -show-inputs -show-outputs miter
 sat -prove-asserts -seq 5 -set-init-zero -show-inputs -show-outputs miter
 
 design -load postopt
 cd lutram_1w1r
-select -assert-count 8 t:RAM16S4
+select -assert-count 8 t:RAM16SDP4
 # other logic present that is not simple
 #select -assert-none t:RAM16S4 %% t:* %D
-- 
cgit v1.2.3