From b515fd2d25851c90c9a0b08414c5ea5edeb916a0 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Tue, 30 Apr 2019 11:25:15 +0200 Subject: Add peepopt_muldiv, fixes #930 Signed-off-by: Clifford Wolf --- tests/simple/peepopt.v | 9 +++++++++ 1 file changed, 9 insertions(+) create mode 100644 tests/simple/peepopt.v (limited to 'tests') diff --git a/tests/simple/peepopt.v b/tests/simple/peepopt.v new file mode 100644 index 000000000..b27b9fe57 --- /dev/null +++ b/tests/simple/peepopt.v @@ -0,0 +1,9 @@ +module peepopt_shiftmul_0 #(parameter N=3, parameter W=3) (input [N*W-1:0] i, input [$clog2(N)-1:0] s, output [W-1:0] o); +assign o = i[s*W+:W]; +endmodule + +module peepopt_muldiv_0(input [1:0] i, output [1:0] o); +wire [3:0] t; +assign t = i * 3; +assign o = t / 3; +endmodule -- cgit v1.2.3 From e5cb9435a064461b56d55dc6ba1241ba1f179119 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Wed, 1 May 2019 09:32:07 +0200 Subject: Add additional test cases for for-loops Signed-off-by: Clifford Wolf --- tests/simple/forloops.v | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+) create mode 100644 tests/simple/forloops.v (limited to 'tests') diff --git a/tests/simple/forloops.v b/tests/simple/forloops.v new file mode 100644 index 000000000..8665222d8 --- /dev/null +++ b/tests/simple/forloops.v @@ -0,0 +1,25 @@ +module forloops01 (input clk, a, b, output reg [3:0] p, q, x, y); + integer k; + always @(posedge clk) begin + for (k=0; k<2; k=k+1) + p[2*k +: 2] = {a, b} ^ {2{k}}; + x <= k + {a, b}; + end + always @* begin + for (k=0; k<4; k=k+1) + q[k] = {~a, ~b, a, b} >> k[1:0]; + y = k - {a, b}; + end +endmodule + +module forloops02 (input clk, a, b, output reg [3:0] q, x, output [3:0] y); + integer k; + always @* begin + for (k=0; k<4; k=k+1) + q[k] = {~a, ~b, a, b} >> k[1:0]; + end + always @* begin + x = k + {a, b}; + end + assign y = k - {a, b}; +endmodule -- cgit v1.2.3 From 6bbe2fdbf32e6335cdbecc21547e54992c3a606d Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Wed, 1 May 2019 10:01:54 +0200 Subject: Add splitcmplxassign test case and silence splitcmplxassign warning Signed-off-by: Clifford Wolf --- tests/simple/mem2reg.v | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) (limited to 'tests') diff --git a/tests/simple/mem2reg.v b/tests/simple/mem2reg.v index 9839fd4a8..100426785 100644 --- a/tests/simple/mem2reg.v +++ b/tests/simple/mem2reg.v @@ -92,3 +92,25 @@ module mem2reg_test5(input ctrl, output out); assign out = bar[foo[0]]; endmodule +// ------------------------------------------------------ + +module mem2reg_test6 (din, dout); + input wire [3:0] din; + output reg [3:0] dout; + + reg [1:0] din_array [1:0]; + reg [1:0] dout_array [1:0]; + + always @* begin + din_array[0] = din[0 +: 2]; + din_array[1] = din[2 +: 2]; + + dout_array[0] = din_array[0]; + dout_array[1] = din_array[1]; + + {dout_array[0][1], dout_array[0][0]} = dout_array[0][0] + dout_array[1][0]; + + dout[0 +: 2] = dout_array[0]; + dout[2 +: 2] = dout_array[1]; + end +endmodule -- cgit v1.2.3 From 98ffe5fb007c0e0d348f961a4e99d8b2f241eac1 Mon Sep 17 00:00:00 2001 From: Jakob Wenzel Date: Thu, 25 Apr 2019 15:12:24 +0200 Subject: fail svinterfaces testcases on yosys error exit --- tests/svinterfaces/runone.sh | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'tests') diff --git a/tests/svinterfaces/runone.sh b/tests/svinterfaces/runone.sh index 0adecc797..71c2d4976 100755 --- a/tests/svinterfaces/runone.sh +++ b/tests/svinterfaces/runone.sh @@ -11,13 +11,13 @@ echo "" > $STDERRFILE echo -n "Test: ${TESTNAME} -> " +set -e + $PWD/../../yosys -p "read_verilog -sv ${TESTNAME}.sv ; hierarchy -check -top TopModule ; synth ; write_verilog ${TESTNAME}_syn.v" >> $STDOUTFILE >> $STDERRFILE $PWD/../../yosys -p "read_verilog -sv ${TESTNAME}_ref.v ; hierarchy -check -top TopModule ; synth ; write_verilog ${TESTNAME}_ref_syn.v" >> $STDOUTFILE >> $STDERRFILE rm -f a.out reference_result.txt dut_result.txt -set -e - iverilog -g2012 ${TESTNAME}_syn.v iverilog -g2012 ${TESTNAME}_ref_syn.v -- cgit v1.2.3 From d2aa123226f39fb6d076b9a0add2ad4f0e596166 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Fri, 3 May 2019 14:40:51 +0200 Subject: Fix typo in tests/svinterfaces/runone.sh Signed-off-by: Clifford Wolf --- tests/svinterfaces/runone.sh | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'tests') diff --git a/tests/svinterfaces/runone.sh b/tests/svinterfaces/runone.sh index 71c2d4976..54cf5f2ec 100755 --- a/tests/svinterfaces/runone.sh +++ b/tests/svinterfaces/runone.sh @@ -13,8 +13,8 @@ echo -n "Test: ${TESTNAME} -> " set -e -$PWD/../../yosys -p "read_verilog -sv ${TESTNAME}.sv ; hierarchy -check -top TopModule ; synth ; write_verilog ${TESTNAME}_syn.v" >> $STDOUTFILE >> $STDERRFILE -$PWD/../../yosys -p "read_verilog -sv ${TESTNAME}_ref.v ; hierarchy -check -top TopModule ; synth ; write_verilog ${TESTNAME}_ref_syn.v" >> $STDOUTFILE >> $STDERRFILE +$PWD/../../yosys -p "read_verilog -sv ${TESTNAME}.sv ; hierarchy -check -top TopModule ; synth ; write_verilog ${TESTNAME}_syn.v" >> $STDOUTFILE 2>> $STDERRFILE +$PWD/../../yosys -p "read_verilog -sv ${TESTNAME}_ref.v ; hierarchy -check -top TopModule ; synth ; write_verilog ${TESTNAME}_ref_syn.v" >> $STDOUTFILE 2>> $STDERRFILE rm -f a.out reference_result.txt dut_result.txt -- cgit v1.2.3 From 1e5f072c0556158924387dedbb78b4cc61bfcf7a Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 3 May 2019 14:03:51 -0700 Subject: iverilog with simcells.v as well --- tests/tools/autotest.sh | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'tests') diff --git a/tests/tools/autotest.sh b/tests/tools/autotest.sh index bb9c3bfb5..920474a84 100755 --- a/tests/tools/autotest.sh +++ b/tests/tools/autotest.sh @@ -147,7 +147,8 @@ do fi if $genvcd; then sed -i 's,// \$dump,$dump,g' ${bn}_tb.v; fi compile_and_run ${bn}_tb_ref ${bn}_out_ref ${bn}_tb.v ${bn}_ref.v $libs \ - "$toolsdir"/../../techlibs/common/simlib.v + "$toolsdir"/../../techlibs/common/simlib.v \ + "$toolsdir"/../../techlibs/common/simcells.v if $genvcd; then mv testbench.vcd ${bn}_ref.vcd; fi test_count=0 -- cgit v1.2.3 From 09841c2ac1f36d06faada27093a2cf0cdfb6cb42 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 3 May 2019 15:35:26 -0700 Subject: Add quick-and-dirty specify tests --- tests/various/specify.v | 28 ++++++++++++++++++++++++++++ tests/various/specify.ys | 25 +++++++++++++++++++++++++ 2 files changed, 53 insertions(+) create mode 100644 tests/various/specify.v create mode 100644 tests/various/specify.ys (limited to 'tests') diff --git a/tests/various/specify.v b/tests/various/specify.v new file mode 100644 index 000000000..aea0d0fc5 --- /dev/null +++ b/tests/various/specify.v @@ -0,0 +1,28 @@ +module test ( + input EN, CLK, + input [3:0] D, + output reg [3:0] Q +); + always @(posedge CLK) + if (EN) Q <= D; + + specify + if (EN) (CLK *> (Q : D)) = (1, 2:3:4); + $setup(D, posedge CLK &&& EN, 5); + $hold(posedge CLK, D &&& EN, 6); + endspecify +endmodule + +module test2 ( + input A, B, + output Q +); + xor (Q, A, B); + specify + //specparam T_rise = 1; + //specparam T_fall = 2; + `define T_rise 1 + `define T_fall 2 + (A => Q) = (`T_rise,`T_fall); + endspecify +endmodule diff --git a/tests/various/specify.ys b/tests/various/specify.ys new file mode 100644 index 000000000..c4e901705 --- /dev/null +++ b/tests/various/specify.ys @@ -0,0 +1,25 @@ +read_verilog -specify specify.v +prep +cd test +select t:$specify2 -assert-count 0 +select t:$specify3 -assert-count 1 +select t:$specrule -assert-count 2 +cd test2 +select t:$specify2 -assert-count 1 +select t:$specify3 -assert-count 0 +select t:$specrule -assert-count 0 +write_verilog specify.out +design -stash gold + +read_verilog -specify specify.out +cd test +select t:$specify2 -assert-count 0 +select t:$specify3 -assert-count 1 +select t:$specrule -assert-count 2 +cd test2 +select t:$specify2 -assert-count 1 +select t:$specify3 -assert-count 0 +select t:$specrule -assert-count 0 +design -stash gate + +# TODO: How to check $specify and $specrule-s are equivalent? -- cgit v1.2.3 From bfb8b3018bbe2017ab35fbdc21813f69c56514bb Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 3 May 2019 15:42:02 -0700 Subject: Fix spacing --- tests/various/specify.v | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) (limited to 'tests') diff --git a/tests/various/specify.v b/tests/various/specify.v index aea0d0fc5..68d3e33fc 100644 --- a/tests/various/specify.v +++ b/tests/various/specify.v @@ -14,15 +14,15 @@ module test ( endmodule module test2 ( - input A, B, + input A, B, output Q ); - xor (Q, A, B); + xor (Q, A, B); specify //specparam T_rise = 1; - //specparam T_fall = 2; - `define T_rise 1 - `define T_fall 2 - (A => Q) = (`T_rise,`T_fall); + //specparam T_fall = 2; + `define T_rise 1 + `define T_fall 2 + (A => Q) = (`T_rise,`T_fall); endspecify endmodule -- cgit v1.2.3 From 554c58715aa4f8f5ed9fb4293946ac420d3f67a2 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 3 May 2019 15:54:25 -0700 Subject: More testing --- tests/various/specify.v | 2 ++ tests/various/specify.ys | 5 +++-- 2 files changed, 5 insertions(+), 2 deletions(-) (limited to 'tests') diff --git a/tests/various/specify.v b/tests/various/specify.v index 68d3e33fc..afc421da8 100644 --- a/tests/various/specify.v +++ b/tests/various/specify.v @@ -24,5 +24,7 @@ module test2 ( `define T_rise 1 `define T_fall 2 (A => Q) = (`T_rise,`T_fall); + //(B => Q) = (`T_rise+`T_fall)/2.0; + (B => Q) = 1.5; endspecify endmodule diff --git a/tests/various/specify.ys b/tests/various/specify.ys index c4e901705..87d98e0a0 100644 --- a/tests/various/specify.ys +++ b/tests/various/specify.ys @@ -5,7 +5,7 @@ select t:$specify2 -assert-count 0 select t:$specify3 -assert-count 1 select t:$specrule -assert-count 2 cd test2 -select t:$specify2 -assert-count 1 +select t:$specify2 -assert-count 2 select t:$specify3 -assert-count 0 select t:$specrule -assert-count 0 write_verilog specify.out @@ -17,9 +17,10 @@ select t:$specify2 -assert-count 0 select t:$specify3 -assert-count 1 select t:$specrule -assert-count 2 cd test2 -select t:$specify2 -assert-count 1 +select t:$specify2 -assert-count 2 select t:$specify3 -assert-count 0 select t:$specrule -assert-count 0 design -stash gate # TODO: How to check $specify and $specrule-s are equivalent? +# Otherwise, need more select statements to check parameter values are as expected? -- cgit v1.2.3 From 8c6e94d57c430fc516dbcfbde312dbd7c860477b Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Mon, 6 May 2019 12:26:15 +0200 Subject: Improve tests/various/specify.ys Signed-off-by: Clifford Wolf --- tests/various/specify.ys | 34 ++++++++++++++++++++++++++++++++-- 1 file changed, 32 insertions(+), 2 deletions(-) (limited to 'tests') diff --git a/tests/various/specify.ys b/tests/various/specify.ys index 87d98e0a0..a5ca07219 100644 --- a/tests/various/specify.ys +++ b/tests/various/specify.ys @@ -8,10 +8,12 @@ cd test2 select t:$specify2 -assert-count 2 select t:$specify3 -assert-count 0 select t:$specrule -assert-count 0 +cd write_verilog specify.out design -stash gold read_verilog -specify specify.out +prep cd test select t:$specify2 -assert-count 0 select t:$specify3 -assert-count 1 @@ -20,7 +22,35 @@ cd test2 select t:$specify2 -assert-count 2 select t:$specify3 -assert-count 0 select t:$specrule -assert-count 0 +cd design -stash gate -# TODO: How to check $specify and $specrule-s are equivalent? -# Otherwise, need more select statements to check parameter values are as expected? +design -copy-from gold -as gold test +design -copy-from gate -as gate test +rename -hide +rename -enumerate -pattern A_% t:$specify3 +rename -enumerate -pattern B_% t:$specrule r:TYPE=$setup %i +rename -enumerate -pattern C_% t:$specrule r:TYPE=$hold %i +select n:A_* -assert-count 2 +select n:B_* -assert-count 2 +select n:C_* -assert-count 2 +equiv_make gold gate equiv +hierarchy -top equiv +equiv_struct +equiv_induct -seq 5 +equiv_status -assert +design -reset + +design -copy-from gold -as gold test2 +design -copy-from gate -as gate test2 +rename -hide +rename -enumerate -pattern A_% t:$specify2 r:T_RISE_TYP=1 %i +rename -enumerate -pattern B_% t:$specify2 n:A_* %d +select n:A_* -assert-count 2 +select n:B_* -assert-count 2 +equiv_make gold gate equiv +hierarchy -top equiv +equiv_struct +equiv_induct -seq 5 +equiv_status -assert +design -reset -- cgit v1.2.3 From d97c644bc140655853854a09400383afc4b084d5 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Mon, 6 May 2019 16:03:15 +0200 Subject: Add tests/various/chparam.sh Signed-off-by: Clifford Wolf --- tests/various/chparam.sh | 52 ++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 52 insertions(+) create mode 100644 tests/various/chparam.sh (limited to 'tests') diff --git a/tests/various/chparam.sh b/tests/various/chparam.sh new file mode 100644 index 000000000..9bb8d81db --- /dev/null +++ b/tests/various/chparam.sh @@ -0,0 +1,52 @@ +#!/bin/bash + +trap 'echo "ERROR in chparam.sh" >&2; exit 1' ERR + +cat > chparam1.sv << "EOT" +module top #( + parameter [31:0] X = 0 +) ( + input [31:0] din, + output [31:0] dout +); + assign dout = X-din; +endmodule + +module top_props #( + parameter [31:0] X = 0 +) ( + input [31:0] dout +); + always @* assert (dout != X); +endmodule + +bind top top_props #(.X(123456789)) props (.*); +EOT + +cat > chparam2.sv << "EOT" +module top #( + parameter [31:0] X = 0 +) ( + input [31:0] din, + output [31:0] dout +); + assign dout = X-din; + always @* assert (dout != 123456789); +endmodule +EOT + +if ../../yosys -q -p 'verific -sv chparam1.sv'; then + ../../yosys -q -p 'verific -sv chparam1.sv; hierarchy -chparam X 123123123 -top top; prep -flatten' \ + -p 'sat -verify -prove-asserts -show-ports -set din[0] 1' \ + -p 'sat -falsify -prove-asserts -show-ports -set din[0] 0' + + ../../yosys -q -p 'verific -sv chparam2.sv; hierarchy -chparam X 123123123 -top top; prep -flatten' \ + -p 'sat -verify -prove-asserts -show-ports -set din[0] 1' \ + -p 'sat -falsify -prove-asserts -show-ports -set din[0] 0' +fi +../../yosys -q -p 'read_verilog -sv chparam2.sv; hierarchy -chparam X 123123123 -top top; prep -flatten' \ + -p 'sat -verify -prove-asserts -show-ports -set din[0] 1' \ + -p 'sat -falsify -prove-asserts -show-ports -set din[0] 0' + +rm chparam1.sv +rm chparam2.sv -- cgit v1.2.3 From b7ec698d4063f0e0ae021050782004c523302b0c Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Tue, 7 May 2019 19:58:04 +0200 Subject: Add test case from #997 Signed-off-by: Clifford Wolf --- tests/simple/dff_init.v | 12 ++++++++++++ 1 file changed, 12 insertions(+) (limited to 'tests') diff --git a/tests/simple/dff_init.v b/tests/simple/dff_init.v index be947042e..375ea5c4d 100644 --- a/tests/simple/dff_init.v +++ b/tests/simple/dff_init.v @@ -40,3 +40,15 @@ module dff1a_test(n1, n1_inv, clk); n1 <= n1_inv; assign n1_inv = ~n1; endmodule + +module dff_test_997 (y, clk, wire4); +// https://github.com/YosysHQ/yosys/issues/997 + output wire [1:0] y; + input clk; + input signed wire4; + reg [1:0] reg10 = 0; + always @(posedge clk) begin + reg10 <= wire4; + end + assign y = reg10; +endmodule -- cgit v1.2.3 From 1f52332b8d4621d6c5ab1447e82b6e2e53600e52 Mon Sep 17 00:00:00 2001 From: Maciej Kurc Date: Thu, 16 May 2019 12:53:43 +0200 Subject: Added tests for Verilog frontent for attributes on parameters and localparams Signed-off-by: Maciej Kurc --- tests/simple/localparam_attr.v | 11 +++++++++++ tests/simple/param_attr.v | 11 +++++++++++ 2 files changed, 22 insertions(+) create mode 100644 tests/simple/localparam_attr.v create mode 100644 tests/simple/param_attr.v (limited to 'tests') diff --git a/tests/simple/localparam_attr.v b/tests/simple/localparam_attr.v new file mode 100644 index 000000000..2ef76c71c --- /dev/null +++ b/tests/simple/localparam_attr.v @@ -0,0 +1,11 @@ +module uut_localparam_attr (I, O); + +(* LOCALPARAM_ATTRIBUTE = "attribute_content" *) +localparam WIDTH = 1; + +input wire [WIDTH-1:0] I; +output wire [WIDTH-1:0] O; + +assign O = I; + +endmodule diff --git a/tests/simple/param_attr.v b/tests/simple/param_attr.v new file mode 100644 index 000000000..34d63a34e --- /dev/null +++ b/tests/simple/param_attr.v @@ -0,0 +1,11 @@ +module uut_param_attr (I, O); + +(* PARAMETER_ATTRIBUTE = "attribute_content" *) +parameter WIDTH = 1; + +input wire [WIDTH-1:0] I; +output wire [WIDTH-1:0] O; + +assign O = I; + +endmodule -- cgit v1.2.3