From 3b52121d328d45a5d4269fd0e8de9af948c0216e Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sat, 5 Jul 2014 11:17:40 +0200 Subject: now ignore init attributes on non-register wires in sat command --- tests/sat/initval.v | 15 +++++++++++++++ tests/sat/initval.ys | 4 ++++ 2 files changed, 19 insertions(+) create mode 100644 tests/sat/initval.v create mode 100644 tests/sat/initval.ys (limited to 'tests') diff --git a/tests/sat/initval.v b/tests/sat/initval.v new file mode 100644 index 000000000..5b661f8d6 --- /dev/null +++ b/tests/sat/initval.v @@ -0,0 +1,15 @@ +module test(input clk, input [3:0] bar, output [3:0] foo); + reg [3:0] foo = 0; + reg [3:0] last_bar = 0; + + always @* + foo[1:0] <= bar[1:0]; + + always @(posedge clk) + foo[3:2] <= bar[3:2]; + + always @(posedge clk) + last_bar <= bar; + + assert property (foo == {last_bar[3:2], bar[1:0]}); +endmodule diff --git a/tests/sat/initval.ys b/tests/sat/initval.ys new file mode 100644 index 000000000..2079d2f34 --- /dev/null +++ b/tests/sat/initval.ys @@ -0,0 +1,4 @@ +read_verilog -sv initval.v +proc;; + +sat -seq 10 -prove-asserts -- cgit v1.2.3