From f20be90436b32e853d68c7e102a65d43f3843d91 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sat, 17 Aug 2019 14:05:10 +0200 Subject: Add test for pmtest_test "reduce" demo pattern Signed-off-by: Clifford Wolf --- tests/various/pmgen_reduce.ys | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) create mode 100644 tests/various/pmgen_reduce.ys (limited to 'tests') diff --git a/tests/various/pmgen_reduce.ys b/tests/various/pmgen_reduce.ys new file mode 100644 index 000000000..c214d3f25 --- /dev/null +++ b/tests/various/pmgen_reduce.ys @@ -0,0 +1,21 @@ +test_pmgen -generate reduce +hierarchy -top pmtest_test_pmgen_pm_reduce +flatten; opt_clean + +design -save gold +test_pmgen -reduce_chain +design -stash gate + +design -copy-from gold -as gold pmtest_test_pmgen_pm_reduce +design -copy-from gate -as gate pmtest_test_pmgen_pm_reduce +miter -equiv -flatten -make_assert gold gate miter +sat -verify -prove-asserts miter + +design -load gold +test_pmgen -reduce_tree +design -stash gate + +design -copy-from gold -as gold pmtest_test_pmgen_pm_reduce +design -copy-from gate -as gate pmtest_test_pmgen_pm_reduce +miter -equiv -flatten -make_assert gold gate miter +sat -verify -prove-asserts miter -- cgit v1.2.3 From 6ffb910d12a93e64182b52a58e69386851f2d595 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Tue, 20 Aug 2019 11:38:21 +0200 Subject: Add test case for real parameters Signed-off-by: Clifford Wolf --- tests/simple/realexpr.v | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) (limited to 'tests') diff --git a/tests/simple/realexpr.v b/tests/simple/realexpr.v index 5b756e6be..74ed8faa5 100644 --- a/tests/simple/realexpr.v +++ b/tests/simple/realexpr.v @@ -1,4 +1,3 @@ - module demo_001(y1, y2, y3, y4); output [7:0] y1, y2, y3, y4; @@ -22,3 +21,13 @@ module demo_002(y0, y1, y2, y3); assign y3 = 1 ? -1 : 'd0; endmodule +module demo_003(output A, B); + parameter real p = 0; + assign A = (p==1.0); + assign B = (p!="1.000000"); +endmodule + +module demo_004(output A, B, C, D); + demo_003 #(1.0) demo_real (A, B); + demo_003 #(1) demo_int (C, D); +endmodule -- cgit v1.2.3 From fce8dc7db20d722646cea83ca841160d3d07445e Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Tue, 20 Aug 2019 20:05:16 -0700 Subject: Add test --- tests/techmap/recursive.v | 8 ++++++++ tests/techmap/recursive_map.v | 4 ++++ tests/techmap/recursive_runtest.sh | 3 +++ 3 files changed, 15 insertions(+) create mode 100644 tests/techmap/recursive.v create mode 100644 tests/techmap/recursive_map.v create mode 100644 tests/techmap/recursive_runtest.sh (limited to 'tests') diff --git a/tests/techmap/recursive.v b/tests/techmap/recursive.v new file mode 100644 index 000000000..d281b21d8 --- /dev/null +++ b/tests/techmap/recursive.v @@ -0,0 +1,8 @@ +module top; +sub s0(); +foo f0(); +endmodule + +module foo; +sub s0(); +endmodule diff --git a/tests/techmap/recursive_map.v b/tests/techmap/recursive_map.v new file mode 100644 index 000000000..934256552 --- /dev/null +++ b/tests/techmap/recursive_map.v @@ -0,0 +1,4 @@ +module sub; + sub _TECHMAP_REPLACE_ (); + bar f0(); +endmodule diff --git a/tests/techmap/recursive_runtest.sh b/tests/techmap/recursive_runtest.sh new file mode 100644 index 000000000..30c79bf03 --- /dev/null +++ b/tests/techmap/recursive_runtest.sh @@ -0,0 +1,3 @@ +set -ev + +../../yosys -p 'hierarchy -top top; techmap -map recursive_map.v -max_iter 1; select -assert-count 2 t:sub; select -assert-count 2 t:bar' recursive.v -- cgit v1.2.3 From a6776ee35ee5404ca7d5b63fd2daccc46354112c Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Wed, 21 Aug 2019 13:36:01 -0700 Subject: mem2reg to preserve user attributes and src --- tests/various/mem2reg.ys | 13 +++++++++++++ 1 file changed, 13 insertions(+) create mode 100644 tests/various/mem2reg.ys (limited to 'tests') diff --git a/tests/various/mem2reg.ys b/tests/various/mem2reg.ys new file mode 100644 index 000000000..00389c700 --- /dev/null +++ b/tests/various/mem2reg.ys @@ -0,0 +1,13 @@ +read_verilog < Date: Wed, 21 Aug 2019 21:58:20 -0700 Subject: Add test --- tests/opt/opt_expr.ys | 14 ++++++++++++++ 1 file changed, 14 insertions(+) (limited to 'tests') diff --git a/tests/opt/opt_expr.ys b/tests/opt/opt_expr.ys index f0306efa1..4affc1ac8 100644 --- a/tests/opt/opt_expr.ys +++ b/tests/opt/opt_expr.ys @@ -221,3 +221,17 @@ check equiv_opt opt_expr -fine design -load postopt select -assert-count 1 t:$alu r:A_WIDTH=8 r:B_WIDTH=8 r:Y_WIDTH=9 %i %i %i + +########### + +design -reset +read_verilog -icells < Date: Thu, 22 Aug 2019 08:22:23 -0700 Subject: Handle $shift and Y_WIDTH > 1 as per @cliffordwolf --- tests/opt/opt_expr.ys | 44 +++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 43 insertions(+), 1 deletion(-) (limited to 'tests') diff --git a/tests/opt/opt_expr.ys b/tests/opt/opt_expr.ys index 4affc1ac8..02be20a62 100644 --- a/tests/opt/opt_expr.ys +++ b/tests/opt/opt_expr.ys @@ -226,7 +226,7 @@ select -assert-count 1 t:$alu r:A_WIDTH=8 r:B_WIDTH=8 r:Y_WIDTH=9 %i %i %i design -reset read_verilog -icells < Date: Thu, 22 Aug 2019 08:37:27 -0700 Subject: Respect opt_expr -keepdc as per @cliffordwolf --- tests/opt/opt_expr.ys | 14 ++++++++++++++ 1 file changed, 14 insertions(+) (limited to 'tests') diff --git a/tests/opt/opt_expr.ys b/tests/opt/opt_expr.ys index 02be20a62..ecc2c8da8 100644 --- a/tests/opt/opt_expr.ys +++ b/tests/opt/opt_expr.ys @@ -277,3 +277,17 @@ check equiv_opt opt_expr design -load postopt select -assert-count 1 t:$shift r:A_WIDTH=10 %i + +########### + +design -reset +read_verilog -icells < Date: Thu, 22 Aug 2019 16:42:19 -0700 Subject: In sat: 'x' in init attr should not override constant --- tests/sat/initval.v | 4 ++++ tests/sat/initval.ys | 2 +- 2 files changed, 5 insertions(+), 1 deletion(-) (limited to 'tests') diff --git a/tests/sat/initval.v b/tests/sat/initval.v index 5b661f8d6..d46ccae48 100644 --- a/tests/sat/initval.v +++ b/tests/sat/initval.v @@ -1,6 +1,7 @@ module test(input clk, input [3:0] bar, output [3:0] foo); reg [3:0] foo = 0; reg [3:0] last_bar = 0; + reg [3:0] asdf = 4'b1xxx; always @* foo[1:0] <= bar[1:0]; @@ -11,5 +12,8 @@ module test(input clk, input [3:0] bar, output [3:0] foo); always @(posedge clk) last_bar <= bar; + always @* + asdf[2:0] <= 3'b111; + assert property (foo == {last_bar[3:2], bar[1:0]}); endmodule diff --git a/tests/sat/initval.ys b/tests/sat/initval.ys index 2079d2f34..3d88aa971 100644 --- a/tests/sat/initval.ys +++ b/tests/sat/initval.ys @@ -1,4 +1,4 @@ read_verilog -sv initval.v -proc;; +proc; sat -seq 10 -prove-asserts -- cgit v1.2.3 From fe1b2337fd7950e1d563be5b8ccbaa81688261e4 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 22 Aug 2019 16:57:59 -0700 Subject: Do not propagate mem2reg attribute through to result --- tests/various/mem2reg.ys | 1 + 1 file changed, 1 insertion(+) (limited to 'tests') diff --git a/tests/various/mem2reg.ys b/tests/various/mem2reg.ys index 00389c700..85d6267c5 100644 --- a/tests/various/mem2reg.ys +++ b/tests/various/mem2reg.ys @@ -11,3 +11,4 @@ proc cd top select -assert-count 1 m:data1 a:src=< Date: Fri, 23 Aug 2019 09:11:04 -0700 Subject: Blocking assignment --- tests/sat/initval.v | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'tests') diff --git a/tests/sat/initval.v b/tests/sat/initval.v index d46ccae48..fcec9dd8c 100644 --- a/tests/sat/initval.v +++ b/tests/sat/initval.v @@ -13,7 +13,7 @@ module test(input clk, input [3:0] bar, output [3:0] foo); last_bar <= bar; always @* - asdf[2:0] <= 3'b111; + asdf[2:0] = 3'b111; assert property (foo == {last_bar[3:2], bar[1:0]}); endmodule -- cgit v1.2.3 From d62c10d641c5af4b1d395caa042681788df1aae4 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 23 Aug 2019 11:09:50 -0700 Subject: tests/techmap/run-test.sh to cope with *.ys --- tests/techmap/.gitignore | 1 + tests/techmap/run-test.sh | 24 +++++++++++++++++------- 2 files changed, 18 insertions(+), 7 deletions(-) (limited to 'tests') diff --git a/tests/techmap/.gitignore b/tests/techmap/.gitignore index 397b4a762..cfed22fc5 100644 --- a/tests/techmap/.gitignore +++ b/tests/techmap/.gitignore @@ -1 +1,2 @@ *.log +/*.mk diff --git a/tests/techmap/run-test.sh b/tests/techmap/run-test.sh index e2fc11e52..96489ff15 100755 --- a/tests/techmap/run-test.sh +++ b/tests/techmap/run-test.sh @@ -1,10 +1,20 @@ -#!/bin/bash +#!/usr/bin/env bash set -e -for x in *_runtest.sh; do - echo "Running $x.." - if ! bash $x &> ${x%.sh}.log; then - tail ${x%.sh}.log - echo ERROR - exit 1 +{ +echo "all::" +for x in *.ys; do + echo "all:: run-$x" + echo "run-$x:" + echo " @echo 'Running $x..'" + echo " @../../yosys -ql ${x%.ys}.log $x" +done +for s in *.sh; do + if [ "$s" != "run-test.sh" ]; then + echo "all:: run-$s" + echo "run-$s:" + echo " @echo 'Running $s..'" + echo " @bash $s > ${s%.sh}.log 2>&1" fi done +} > run-test.mk +exec ${MAKE:-make} -f run-test.mk -- cgit v1.2.3 From 5628e2ec53c3a1d5f1828b8f522c5c09c9856b0d Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 23 Aug 2019 11:10:02 -0700 Subject: Add simple clkbufmap tests --- tests/techmap/clkbufmap.ys | 52 ++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 52 insertions(+) create mode 100644 tests/techmap/clkbufmap.ys (limited to 'tests') diff --git a/tests/techmap/clkbufmap.ys b/tests/techmap/clkbufmap.ys new file mode 100644 index 000000000..eb8970af4 --- /dev/null +++ b/tests/techmap/clkbufmap.ys @@ -0,0 +1,52 @@ +read_verilog < Date: Fri, 23 Aug 2019 11:15:26 -0700 Subject: Check clkbuf_inhibit=1 is ignored for custom selection --- tests/techmap/clkbufmap.ys | 1 + 1 file changed, 1 insertion(+) (limited to 'tests') diff --git a/tests/techmap/clkbufmap.ys b/tests/techmap/clkbufmap.ys index eb8970af4..46ff4d694 100644 --- a/tests/techmap/clkbufmap.ys +++ b/tests/techmap/clkbufmap.ys @@ -35,6 +35,7 @@ select -assert-count 1 t:clkbuf # ---------------------- design -load ref +setattr -set clkbuf_inhibit 1 w:clk1 setattr -set buffer_type "bufg" w:clk2 clkbufmap -buf clkbuf o:i w:* a:buffer_type=none a:buffer_type=bufr %u %d select -assert-count 1 w:clk1 %a %co t:clkbuf %i -- cgit v1.2.3 From dc87372a97d515563ccccd517ef8f35662870fe6 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Sat, 24 Aug 2019 15:05:44 -0700 Subject: Wire with init on FF part, 1'bx on non-FF part --- tests/sat/initval.v | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) (limited to 'tests') diff --git a/tests/sat/initval.v b/tests/sat/initval.v index fcec9dd8c..81f71b5ba 100644 --- a/tests/sat/initval.v +++ b/tests/sat/initval.v @@ -1,4 +1,4 @@ -module test(input clk, input [3:0] bar, output [3:0] foo); +module test(input clk, input [3:0] bar, output [3:0] foo, asdf); reg [3:0] foo = 0; reg [3:0] last_bar = 0; reg [3:0] asdf = 4'b1xxx; @@ -12,6 +12,8 @@ module test(input clk, input [3:0] bar, output [3:0] foo); always @(posedge clk) last_bar <= bar; + always @(posedge clk) + asdf[3] <= bar[3]; always @* asdf[2:0] = 3'b111; -- cgit v1.2.3 From 528f1c86877d247700bd9445e03c85b3eb437b5c Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Mon, 26 Aug 2019 13:45:16 -0700 Subject: Improve tests to check that clkbuf is connected to expected --- tests/techmap/clkbufmap.ys | 27 +++++++++++++++++++++------ 1 file changed, 21 insertions(+), 6 deletions(-) (limited to 'tests') diff --git a/tests/techmap/clkbufmap.ys b/tests/techmap/clkbufmap.ys index 46ff4d694..5847c3ce5 100644 --- a/tests/techmap/clkbufmap.ys +++ b/tests/techmap/clkbufmap.ys @@ -18,9 +18,15 @@ design -save ref design -load ref clkbufmap -buf clkbuf o:i -select -assert-count 1 w:clk1 %a %co t:clkbuf %i -select -assert-count 1 w:clk2 %a %co t:clkbuf %i select -assert-count 2 t:clkbuf +select -set clk1 w:clk1 %a %co t:clkbuf %i # Find 'clk1' fanouts that are 'clkbuf' +select -assert-count 1 @clk1 # Check there is one such fanout +select -assert-count 1 @clk1 %x:+[o] %co c:s* %i # Check that the 'o' of that clkbuf drives one fanout +select -assert-count 1 @clk1 %x:+[o] %co c:s0 %i # And that one fanout is 's0' +select -set clk2 w:clk2 %a %co t:clkbuf %i +select -assert-count 1 @clk2 +select -assert-count 1 @clk2 %x:+[o] %co c:s* %i +select -assert-count 1 @clk2 %x:+[o] %co c:s1 %i # ---------------------- @@ -28,9 +34,12 @@ design -load ref setattr -set clkbuf_inhibit 0 w:clk1 setattr -set clkbuf_inhibit 1 w:clk2 clkbufmap -buf clkbuf o:i -select -assert-count 1 w:clk1 %a %co t:clkbuf %i -select -assert-count 0 w:clk2 %a %co t:clkbuf %i select -assert-count 1 t:clkbuf +select -set clk1 w:clk1 %a %co t:clkbuf %i # Find 'clk1' fanouts that are 'clkbuf' +select -assert-count 1 @clk1 # Check there is one such fanout +select -assert-count 1 @clk1 %x:+[o] %co c:s* %i # Check that the 'o' of that clkbuf drives one fanout +select -assert-count 1 @clk1 %x:+[o] %co c:s0 %i # And that one fanout is 's0' +select -assert-count 0 w:clk2 %a %co t:clkbuf %i # ---------------------- @@ -38,9 +47,15 @@ design -load ref setattr -set clkbuf_inhibit 1 w:clk1 setattr -set buffer_type "bufg" w:clk2 clkbufmap -buf clkbuf o:i w:* a:buffer_type=none a:buffer_type=bufr %u %d -select -assert-count 1 w:clk1 %a %co t:clkbuf %i -select -assert-count 1 w:clk2 %a %co t:clkbuf %i select -assert-count 2 t:clkbuf +select -set clk1 w:clk1 %a %co t:clkbuf %i # Find 'clk1' fanouts that are 'clkbuf' +select -assert-count 1 @clk1 # Check there is one such fanout +select -assert-count 1 @clk1 %x:+[o] %co c:s* %i # Check that the 'o' of that clkbuf drives one fanout +select -assert-count 1 @clk1 %x:+[o] %co c:s0 %i # And that one fanout is 's0' +select -set clk2 w:clk2 %a %co t:clkbuf %i # Find 'clk1' fanouts that are 'clkbuf' +select -assert-count 1 @clk2 # Check there is one such fanout +select -assert-count 1 @clk2 %x:+[o] %co c:s* %i # Check that the 'o' of that clkbuf drives one fanout +select -assert-count 1 @clk2 %x:+[o] %co c:s1 %i # And that one fanout is 's0' # ---------------------- -- cgit v1.2.3 From 5fb4b12cb50b870b546d76f9c702678d8f0aa60a Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Marcin=20Ko=C5=9Bcielnicki?= Date: Tue, 27 Aug 2019 17:26:47 +0200 Subject: improve clkbuf_inhibit propagation upwards through hierarchy --- tests/techmap/clkbufmap.ys | 38 +++++++++++++++++++++++++++++++++----- 1 file changed, 33 insertions(+), 5 deletions(-) (limited to 'tests') diff --git a/tests/techmap/clkbufmap.ys b/tests/techmap/clkbufmap.ys index 5847c3ce5..f1277864e 100644 --- a/tests/techmap/clkbufmap.ys +++ b/tests/techmap/clkbufmap.ys @@ -3,11 +3,26 @@ module clkbuf (input i, (* clkbuf_driver *) output o); endmodule module dff ((* clkbuf_sink *) input clk, input d, output q); endmodule module dffe ((* clkbuf_sink *) input c, input d, e, output q); endmodule module latch (input e, d, output q); endmodule +module clkgen (output o); endmodule -module top(input clk1, clk2, clk3, d, e, output [2:0] q); +module top(input clk1, clk2, clk3, d, e, output [4:0] q); +wire clk4, clk5, clk6; dff s0 (.clk(clk1), .d(d), .q(q[0])); dffe s1 (.c(clk2), .d(d), .e(e), .q(q[1])); latch s2 (.e(clk3), .d(d), .q(q[2])); +sub s3 (.sclk4(clk4), .sclk5(clk5), .sclk6(clk6), .sd(d), .sq(q[3])); +dff s4 (.clk(clk4), .d(d), .q(q[4])); +dff s5 (.clk(clk5), .d(d), .q(q[4])); +dff s6 (.clk(clk6), .d(d), .q(q[4])); +endmodule + +module sub(output sclk4, output sclk5, output sclk6, input sd, output sq); +wire tmp; +clkgen s7(.o(sclk4)); +clkgen s8(.o(sclk5)); +clkgen s9(.o(tmp)); +clkbuf s10(.i(tmp), .o(sclk6)); +dff s11(.clk(sclk4), .d(sd), .q(sq)); endmodule EOT @@ -18,7 +33,8 @@ design -save ref design -load ref clkbufmap -buf clkbuf o:i -select -assert-count 2 t:clkbuf +select -assert-count 3 top/t:clkbuf +select -assert-count 2 sub/t:clkbuf select -set clk1 w:clk1 %a %co t:clkbuf %i # Find 'clk1' fanouts that are 'clkbuf' select -assert-count 1 @clk1 # Check there is one such fanout select -assert-count 1 @clk1 %x:+[o] %co c:s* %i # Check that the 'o' of that clkbuf drives one fanout @@ -27,6 +43,14 @@ select -set clk2 w:clk2 %a %co t:clkbuf %i select -assert-count 1 @clk2 select -assert-count 1 @clk2 %x:+[o] %co c:s* %i select -assert-count 1 @clk2 %x:+[o] %co c:s1 %i +select -set clk5 w:clk5 %a %ci t:clkbuf %i +select -assert-count 1 @clk5 +select -assert-count 1 @clk5 %x:+[o] %co c:s5 %i +select -assert-count 1 @clk5 %x:+[i] %ci c:s3 %i +select -set sclk4 w:sclk4 %a %ci t:clkbuf %i +select -assert-count 1 @sclk4 +select -assert-count 1 @sclk4 %x:+[o] %co c:s11 %i +select -assert-count 1 @sclk4 %x:+[i] %ci c:s7 %i # ---------------------- @@ -34,7 +58,7 @@ design -load ref setattr -set clkbuf_inhibit 0 w:clk1 setattr -set clkbuf_inhibit 1 w:clk2 clkbufmap -buf clkbuf o:i -select -assert-count 1 t:clkbuf +select -assert-count 2 top/t:clkbuf select -set clk1 w:clk1 %a %co t:clkbuf %i # Find 'clk1' fanouts that are 'clkbuf' select -assert-count 1 @clk1 # Check there is one such fanout select -assert-count 1 @clk1 %x:+[o] %co c:s* %i # Check that the 'o' of that clkbuf drives one fanout @@ -47,7 +71,8 @@ design -load ref setattr -set clkbuf_inhibit 1 w:clk1 setattr -set buffer_type "bufg" w:clk2 clkbufmap -buf clkbuf o:i w:* a:buffer_type=none a:buffer_type=bufr %u %d -select -assert-count 2 t:clkbuf +select -assert-count 3 top/t:clkbuf +select -assert-count 2 sub/t:clkbuf select -set clk1 w:clk1 %a %co t:clkbuf %i # Find 'clk1' fanouts that are 'clkbuf' select -assert-count 1 @clk1 # Check there is one such fanout select -assert-count 1 @clk1 %x:+[o] %co c:s* %i # Check that the 'o' of that clkbuf drives one fanout @@ -62,7 +87,10 @@ select -assert-count 1 @clk2 %x:+[o] %co c:s1 %i # And that one fanout is 's0 design -load ref setattr -set buffer_type "none" w:clk1 setattr -set buffer_type "bufr" w:clk2 +setattr -set buffer_type "bufr" w:sclk4 +setattr -set buffer_type "bufr" w:sclk5 clkbufmap -buf clkbuf o:i w:* a:buffer_type=none a:buffer_type=bufr %u %d select -assert-count 0 w:clk1 %a %co t:clkbuf %i select -assert-count 0 w:clk2 %a %co t:clkbuf %i -select -assert-count 0 t:clkbuf +select -assert-count 0 top/t:clkbuf +select -assert-count 1 sub/t:clkbuf -- cgit v1.2.3 From 00387f39277ab817b3b17e72b59793e6d5dfcde8 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Tue, 27 Aug 2019 09:24:32 -0700 Subject: Revert to using clean --- tests/sat/initval.ys | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'tests') diff --git a/tests/sat/initval.ys b/tests/sat/initval.ys index 3d88aa971..2079d2f34 100644 --- a/tests/sat/initval.ys +++ b/tests/sat/initval.ys @@ -1,4 +1,4 @@ read_verilog -sv initval.v -proc; +proc;; sat -seq 10 -prove-asserts -- cgit v1.2.3