From 99706b3bf48de121e58b76d4341d601f0bcc26cd Mon Sep 17 00:00:00 2001 From: Larry Doolittle Date: Fri, 28 Dec 2018 08:24:31 -0800 Subject: Squelch a little more trailing whitespace --- tests/sva/basic01.sv | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'tests') diff --git a/tests/sva/basic01.sv b/tests/sva/basic01.sv index 74ab93430..d5ad497dd 100644 --- a/tests/sva/basic01.sv +++ b/tests/sva/basic01.sv @@ -6,7 +6,7 @@ module top (input logic clock, ctrl); write <= ctrl; ready <= write; end - + a_rw: assert property ( @(posedge clock) !(read && write) ); `ifdef FAIL a_wr: assert property ( @(posedge clock) write |-> ready ); -- cgit v1.2.3 From 42c356c49c04a735fe27e672ff31452170f84b40 Mon Sep 17 00:00:00 2001 From: whitequark Date: Mon, 31 Dec 2018 23:53:23 +0000 Subject: opt_lut: eliminate LUTs evaluating to constants or inputs. --- tests/opt/opt_lut_elim.il | 19 +++++++++++++++++++ tests/opt/opt_lut_elim.ys | 3 +++ tests/opt/opt_lut_port.ys | 1 + 3 files changed, 23 insertions(+) create mode 100644 tests/opt/opt_lut_elim.il create mode 100644 tests/opt/opt_lut_elim.ys (limited to 'tests') diff --git a/tests/opt/opt_lut_elim.il b/tests/opt/opt_lut_elim.il new file mode 100644 index 000000000..75675d983 --- /dev/null +++ b/tests/opt/opt_lut_elim.il @@ -0,0 +1,19 @@ +module \test + wire input 1 \i + + wire output 2 \o1 + cell $lut $1 + parameter \LUT 16'0110100110010110 + parameter \WIDTH 4 + connect \A { \i 3'000 } + connect \Y \o1 + end + + wire output 2 \o2 + cell $lut $2 + parameter \LUT 16'0110100010010110 + parameter \WIDTH 4 + connect \A { \i 3'000 } + connect \Y \o2 + end +end diff --git a/tests/opt/opt_lut_elim.ys b/tests/opt/opt_lut_elim.ys new file mode 100644 index 000000000..8e5e23aea --- /dev/null +++ b/tests/opt/opt_lut_elim.ys @@ -0,0 +1,3 @@ +read_ilang opt_lut_elim.il +opt_lut +select -assert-count 0 t:$lut diff --git a/tests/opt/opt_lut_port.ys b/tests/opt/opt_lut_port.ys index 51dfd988b..3cb4ecb23 100644 --- a/tests/opt/opt_lut_port.ys +++ b/tests/opt/opt_lut_port.ys @@ -1,2 +1,3 @@ read_ilang opt_lut_port.il +opt_lut select -assert-count 2 t:$lut -- cgit v1.2.3 From 8e53d2e0bf3584709cd320447ad5a89a80dcfd94 Mon Sep 17 00:00:00 2001 From: whitequark Date: Wed, 2 Jan 2019 02:45:49 +0000 Subject: opt_expr: simplify any unsigned comparisons with all-0 and all-1. Before this commit, only unsigned comparisons with all-0 would be simplified. This commit also makes the code handling such comparisons to be more rigorous and not abort on unexpected input. --- tests/opt/opt_expr_cmp.v | 11 +++++++++++ tests/opt/opt_expr_cmp.ys | 4 ++++ 2 files changed, 15 insertions(+) create mode 100644 tests/opt/opt_expr_cmp.v create mode 100644 tests/opt/opt_expr_cmp.ys (limited to 'tests') diff --git a/tests/opt/opt_expr_cmp.v b/tests/opt/opt_expr_cmp.v new file mode 100644 index 000000000..7eb65d531 --- /dev/null +++ b/tests/opt/opt_expr_cmp.v @@ -0,0 +1,11 @@ +module top(...); + input [3:0] a; + output o1 = 4'b0000 > a; + output o2 = 4'b0000 <= a; + output o3 = 4'b1111 < a; + output o4 = 4'b1111 >= a; + output o5 = a < 4'b0000; + output o6 = a >= 4'b0000; + output o7 = a > 4'b1111; + output o8 = a <= 4'b1111; +endmodule diff --git a/tests/opt/opt_expr_cmp.ys b/tests/opt/opt_expr_cmp.ys new file mode 100644 index 000000000..214ce8b11 --- /dev/null +++ b/tests/opt/opt_expr_cmp.ys @@ -0,0 +1,4 @@ +read_verilog opt_expr_cmp.v +equiv_opt -assert opt_expr -fine +design -load postopt +select -assert-count 0 t:$gt t:$ge t:$lt t:$le -- cgit v1.2.3 From 9e9846a6ead700756fbd7a5e6c72ccb424006934 Mon Sep 17 00:00:00 2001 From: whitequark Date: Wed, 2 Jan 2019 03:01:25 +0000 Subject: opt_expr: refactor simplification of signed X>=0 and X<0. NFCI. --- tests/opt/opt_expr_cmp.v | 22 ++++++++++++++-------- 1 file changed, 14 insertions(+), 8 deletions(-) (limited to 'tests') diff --git a/tests/opt/opt_expr_cmp.v b/tests/opt/opt_expr_cmp.v index 7eb65d531..72372bdf0 100644 --- a/tests/opt/opt_expr_cmp.v +++ b/tests/opt/opt_expr_cmp.v @@ -1,11 +1,17 @@ module top(...); input [3:0] a; - output o1 = 4'b0000 > a; - output o2 = 4'b0000 <= a; - output o3 = 4'b1111 < a; - output o4 = 4'b1111 >= a; - output o5 = a < 4'b0000; - output o6 = a >= 4'b0000; - output o7 = a > 4'b1111; - output o8 = a <= 4'b1111; + + output o1_1 = 4'b0000 > a; + output o1_2 = 4'b0000 <= a; + output o1_3 = 4'b1111 < a; + output o1_4 = 4'b1111 >= a; + output o1_5 = a < 4'b0000; + output o1_6 = a >= 4'b0000; + output o1_7 = a > 4'b1111; + output o1_8 = a <= 4'b1111; + + output o2_1 = 4'sb0000 > $signed(a); + output o2_2 = 4'sb0000 <= $signed(a); + output o2_3 = $signed(a) < 4'sb0000; + output o2_4 = $signed(a) >= 4'sb0000; endmodule -- cgit v1.2.3 From 4fd458290c3da4c3f372f2e1fdd99829a9462a38 Mon Sep 17 00:00:00 2001 From: whitequark Date: Wed, 2 Jan 2019 04:31:20 +0000 Subject: opt_expr: refactor simplification of unsigned X=onehot. NFCI. --- tests/opt/opt_expr_cmp.v | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'tests') diff --git a/tests/opt/opt_expr_cmp.v b/tests/opt/opt_expr_cmp.v index 72372bdf0..500b15f1b 100644 --- a/tests/opt/opt_expr_cmp.v +++ b/tests/opt/opt_expr_cmp.v @@ -14,4 +14,9 @@ module top(...); output o2_2 = 4'sb0000 <= $signed(a); output o2_3 = $signed(a) < 4'sb0000; output o2_4 = $signed(a) >= 4'sb0000; + + output o3_1 = 4'b0100 > a; + output o3_2 = 4'b0100 <= a; + output o3_3 = a < 4'b0100; + output o3_4 = a >= 4'b0100; endmodule -- cgit v1.2.3 From a91892bba422bbe8de080a105a6fb4b44f96df1a Mon Sep 17 00:00:00 2001 From: whitequark Date: Wed, 2 Jan 2019 07:53:31 +0000 Subject: cmp2lut: new techmap pass. --- tests/lut/check_map.ys | 6 ++++-- tests/lut/map_cmp.v | 29 +++++++++++++++++++++++++++++ tests/lut/run-test.sh | 0 3 files changed, 33 insertions(+), 2 deletions(-) create mode 100644 tests/lut/map_cmp.v mode change 100644 => 100755 tests/lut/run-test.sh (limited to 'tests') diff --git a/tests/lut/check_map.ys b/tests/lut/check_map.ys index dc0aaffc2..46854e82e 100644 --- a/tests/lut/check_map.ys +++ b/tests/lut/check_map.ys @@ -1,4 +1,6 @@ simplemap -equiv_opt -assert techmap -map +/gate2lut.v -D LUT_WIDTH=4 +equiv_opt -assert techmap -D LUT_WIDTH=4 -map +/cmp2lut.v design -load postopt -select -assert-count 1 t:$lut +equiv_opt -assert techmap -D LUT_WIDTH=4 -map +/gate2lut.v +design -load postopt +select -assert-count 0 t:* t:$lut %d diff --git a/tests/lut/map_cmp.v b/tests/lut/map_cmp.v new file mode 100644 index 000000000..5e413f894 --- /dev/null +++ b/tests/lut/map_cmp.v @@ -0,0 +1,29 @@ +module top(...); + input [3:0] a; + + output o1_1 = 4'b1010 <= a; + output o1_2 = 4'b1010 < a; + output o1_3 = 4'b1010 >= a; + output o1_4 = 4'b1010 > a; + output o1_5 = 4'b1010 == a; + output o1_6 = 4'b1010 != a; + + output o2_1 = a <= 4'b1010; + output o2_2 = a < 4'b1010; + output o2_3 = a >= 4'b1010; + output o2_4 = a > 4'b1010; + output o2_5 = a == 4'b1010; + output o2_6 = a != 4'b1010; + + output o3_1 = 4'sb0101 <= $signed(a); + output o3_2 = 4'sb0101 < $signed(a); + output o3_3 = 4'sb0101 >= $signed(a); + output o3_4 = 4'sb0101 > $signed(a); + output o3_5 = 4'sb0101 == $signed(a); + output o3_6 = 4'sb0101 != $signed(a); + + output o4_1 = $signed(a) <= 4'sb0000; + output o4_2 = $signed(a) < 4'sb0000; + output o4_3 = $signed(a) >= 4'sb0000; + output o4_4 = $signed(a) > 4'sb0000; +endmodule diff --git a/tests/lut/run-test.sh b/tests/lut/run-test.sh old mode 100644 new mode 100755 -- cgit v1.2.3 From bf8db55ef36f6839827cd8bc69f673fd3fd43cca Mon Sep 17 00:00:00 2001 From: whitequark Date: Wed, 2 Jan 2019 05:04:28 +0000 Subject: opt_expr: improve simplification of comparisons with large constants. The idea behind this simplification is that a N-bit signal X being compared with an M-bit constant where M>N and the constant has Nth or higher bit set, it either always succeeds or always fails. However, the existing implementation only worked with one-hot signals for some reason. It also printed incorrect messages. This commit adjusts the simplification to have as much power as possible, and fixes other bugs. --- tests/opt/opt_expr_cmp.v | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) (limited to 'tests') diff --git a/tests/opt/opt_expr_cmp.v b/tests/opt/opt_expr_cmp.v index 500b15f1b..5aff4b80f 100644 --- a/tests/opt/opt_expr_cmp.v +++ b/tests/opt/opt_expr_cmp.v @@ -19,4 +19,22 @@ module top(...); output o3_2 = 4'b0100 <= a; output o3_3 = a < 4'b0100; output o3_4 = a >= 4'b0100; + + output o4_1 = 5'b10000 > a; + output o4_2 = 5'b10000 >= a; + output o4_3 = 5'b10000 < a; + output o4_4 = 5'b10000 <= a; + output o4_5 = a < 5'b10000; + output o4_6 = a <= 5'b10000; + output o4_7 = a > 5'b10000; + output o4_8 = a >= 5'b10000; + + output o5_1 = 5'b10100 > a; + output o5_2 = 5'b10100 >= a; + output o5_3 = 5'b10100 < a; + output o5_4 = 5'b10100 <= a; + output o5_5 = a < 5'b10100; + output o5_6 = a <= 5'b10100; + output o5_7 = a > 5'b10100; + output o5_8 = a >= 5'b10100; endmodule -- cgit v1.2.3 From 9666cca9ddba2e6d242006e80d66277b8b4df0fd Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sun, 27 Jan 2019 09:17:02 +0100 Subject: Remove asicworld tests for (unsupported) switch-level modelling Signed-off-by: Clifford Wolf --- tests/asicworld/code_hdl_models_misc1.v | 22 ---------------------- tests/asicworld/code_hdl_models_mux21_switch.v | 22 ---------------------- tests/asicworld/code_hdl_models_nand_switch.v | 14 -------------- tests/asicworld/code_hdl_models_t_gate_switch.v | 11 ----------- 4 files changed, 69 deletions(-) delete mode 100644 tests/asicworld/code_hdl_models_misc1.v delete mode 100644 tests/asicworld/code_hdl_models_mux21_switch.v delete mode 100644 tests/asicworld/code_hdl_models_nand_switch.v delete mode 100644 tests/asicworld/code_hdl_models_t_gate_switch.v (limited to 'tests') diff --git a/tests/asicworld/code_hdl_models_misc1.v b/tests/asicworld/code_hdl_models_misc1.v deleted file mode 100644 index e3d9d5d64..000000000 --- a/tests/asicworld/code_hdl_models_misc1.v +++ /dev/null @@ -1,22 +0,0 @@ -module misc1 (a,b,c,d,y); -input a, b,c,d; -output y; - -wire net1,net2,net3; - -supply1 vdd; -supply0 vss; - -// y = !((a+b+c).d) - -pmos p1 (vdd,net1,a); -pmos p2 (net1,net2,b); -pmos p3 (net2,y,c); -pmos p4 (vdd,y,d); - -nmos n1 (vss,net3,a); -nmos n2 (vss,net3,b); -nmos n3 (vss,net3,c); -nmos n4 (net3,y,d); - -endmodule diff --git a/tests/asicworld/code_hdl_models_mux21_switch.v b/tests/asicworld/code_hdl_models_mux21_switch.v deleted file mode 100644 index 519c07fc5..000000000 --- a/tests/asicworld/code_hdl_models_mux21_switch.v +++ /dev/null @@ -1,22 +0,0 @@ -//----------------------------------------------------- -// Design Name : mux21_switch -// File Name : mux21_switch.v -// Function : 2:1 Mux using Switch Primitives -// Coder : Deepak Kumar Tala -//----------------------------------------------------- -module mux21_switch (out, ctrl, in1, in2); - - output out; - input ctrl, in1, in2; - wire w; - - supply1 power; - supply0 ground; - - pmos N1 (w, power, ctrl); - nmos N2 (w, ground, ctrl); - - cmos C1 (out, in1, w, ctrl); - cmos C2 (out, in2, ctrl, w); - -endmodule diff --git a/tests/asicworld/code_hdl_models_nand_switch.v b/tests/asicworld/code_hdl_models_nand_switch.v deleted file mode 100644 index 1ccdd3a7c..000000000 --- a/tests/asicworld/code_hdl_models_nand_switch.v +++ /dev/null @@ -1,14 +0,0 @@ -module nand_switch(a,b,out); -input a,b; -output out; - -supply0 vss; -supply1 vdd; -wire net1; - -pmos p1 (vdd,out,a); -pmos p2 (vdd,out,b); -nmos n1 (vss,net1,a); -nmos n2 (net1,out,b); - -endmodule \ No newline at end of file diff --git a/tests/asicworld/code_hdl_models_t_gate_switch.v b/tests/asicworld/code_hdl_models_t_gate_switch.v deleted file mode 100644 index 5a7e0eaff..000000000 --- a/tests/asicworld/code_hdl_models_t_gate_switch.v +++ /dev/null @@ -1,11 +0,0 @@ -module t_gate_switch (L,R,nC,C); - inout L; - inout R; - input nC; - input C; - - //Syntax: keyword unique_name (drain. source, gate); - pmos p1 (L,R,nC); - nmos p2 (L,R,C); - -endmodule -- cgit v1.2.3