From 1d5f3fe5064146955dafdabafe7180ff79c95d08 Mon Sep 17 00:00:00 2001 From: Zachary Snow Date: Sat, 6 Feb 2021 23:54:17 -0500 Subject: verlog: allow shadowing module ports within generate blocks This is a somewhat obscure edge case I encountered while working on test cases for earlier changes. Declarations in generate blocks should not be checked against the list of ports. This change also adds a check forbidding declarations within generate blocks being tagged as inputs or outputs. --- tests/simple/genblk_port_shadow.v | 10 ++++++++++ tests/verilog/genblk_port_decl.ys | 12 ++++++++++++ 2 files changed, 22 insertions(+) create mode 100644 tests/simple/genblk_port_shadow.v create mode 100644 tests/verilog/genblk_port_decl.ys (limited to 'tests') diff --git a/tests/simple/genblk_port_shadow.v b/tests/simple/genblk_port_shadow.v new file mode 100644 index 000000000..a04631a20 --- /dev/null +++ b/tests/simple/genblk_port_shadow.v @@ -0,0 +1,10 @@ +module top(x); + generate + if (1) begin : blk + wire x; + assign x = 0; + end + endgenerate + output wire x; + assign x = blk.x; +endmodule diff --git a/tests/verilog/genblk_port_decl.ys b/tests/verilog/genblk_port_decl.ys new file mode 100644 index 000000000..589d3d2e1 --- /dev/null +++ b/tests/verilog/genblk_port_decl.ys @@ -0,0 +1,12 @@ +logger -expect error "Cannot declare module port `\\x' within a generate block\." 1 +read_verilog <