From 9a468f81c412f8b63d25e739f28932815c6882fb Mon Sep 17 00:00:00 2001
From: Bogdan Vukobratovic <bogdan.vukobratovic@gmail.com>
Date: Tue, 28 May 2019 08:48:21 +0200
Subject: Optimizing DFFs whose initial value prevents their value from
 changing

This is a proof of concept implementation that invokes SAT solver via Pass::call
method.
---
 tests/opt/opt_ff_sat.v  | 15 +++++++++++++++
 tests/opt/opt_ff_sat.ys |  4 ++++
 2 files changed, 19 insertions(+)
 create mode 100644 tests/opt/opt_ff_sat.v
 create mode 100644 tests/opt/opt_ff_sat.ys

(limited to 'tests')

diff --git a/tests/opt/opt_ff_sat.v b/tests/opt/opt_ff_sat.v
new file mode 100644
index 000000000..fc1e61980
--- /dev/null
+++ b/tests/opt/opt_ff_sat.v
@@ -0,0 +1,15 @@
+module top(
+					 input 	clk,
+					 input 	a,
+					 output b
+					 );
+  reg 						b_reg;
+  initial begin
+    b_reg <= 0;
+  end
+
+  assign b = b_reg;
+  always @(posedge clk) begin
+    b_reg <= a && b_reg;
+  end
+endmodule
diff --git a/tests/opt/opt_ff_sat.ys b/tests/opt/opt_ff_sat.ys
new file mode 100644
index 000000000..13e4ad29b
--- /dev/null
+++ b/tests/opt/opt_ff_sat.ys
@@ -0,0 +1,4 @@
+read_verilog opt_ff_sat.v
+prep -flatten
+opt_rmdff -sat
+synth
-- 
cgit v1.2.3


From 2454ad99bf49afe752d6fd1c1567f59ee9e26736 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Thu, 20 Jun 2019 13:44:21 +0200
Subject: Refactor "opt_rmdff -sat"

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 tests/opt/opt_ff_sat.v  | 25 +++++++++++--------------
 tests/opt/opt_ff_sat.ys |  1 +
 2 files changed, 12 insertions(+), 14 deletions(-)

(limited to 'tests')

diff --git a/tests/opt/opt_ff_sat.v b/tests/opt/opt_ff_sat.v
index fc1e61980..5a0a6fe37 100644
--- a/tests/opt/opt_ff_sat.v
+++ b/tests/opt/opt_ff_sat.v
@@ -1,15 +1,12 @@
-module top(
-					 input 	clk,
-					 input 	a,
-					 output b
-					 );
-  reg 						b_reg;
-  initial begin
-    b_reg <= 0;
-  end
-
-  assign b = b_reg;
-  always @(posedge clk) begin
-    b_reg <= a && b_reg;
-  end
+module top (
+	input clk,
+	output reg [7:0] cnt
+);
+	initial cnt = 0;
+	always @(posedge clk) begin
+		if (cnt < 20)
+			cnt <= cnt + 1;
+		else
+			cnt <= 0;
+	end
 endmodule
diff --git a/tests/opt/opt_ff_sat.ys b/tests/opt/opt_ff_sat.ys
index 13e4ad29b..4e7cc6ca4 100644
--- a/tests/opt/opt_ff_sat.ys
+++ b/tests/opt/opt_ff_sat.ys
@@ -2,3 +2,4 @@ read_verilog opt_ff_sat.v
 prep -flatten
 opt_rmdff -sat
 synth
+select -assert-count 5 t:$_DFF_P_
-- 
cgit v1.2.3