From e7a8cdbccfa6f619f2e25c540b5af6d8e34ff431 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Wed, 12 Jun 2019 08:34:06 -0700 Subject: Add shregmap -tech xilinx test --- tests/various/shregmap.ys | 1 + 1 file changed, 1 insertion(+) (limited to 'tests') diff --git a/tests/various/shregmap.ys b/tests/various/shregmap.ys index 0e5fe882b..a717c54f1 100644 --- a/tests/various/shregmap.ys +++ b/tests/various/shregmap.ys @@ -64,3 +64,4 @@ sat -verify -prove-asserts -show-ports -seq 5 miter # design -load gate # stat + -- cgit v1.2.3 From 66607845eccb2e3bc17b017c4f6b109aeaecdf77 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 22 Aug 2019 16:18:07 -0700 Subject: Remove Xilinx test --- tests/various/shregmap.ys | 34 ---------------------------------- 1 file changed, 34 deletions(-) (limited to 'tests') diff --git a/tests/various/shregmap.ys b/tests/various/shregmap.ys index a717c54f1..16e5f40e1 100644 --- a/tests/various/shregmap.ys +++ b/tests/various/shregmap.ys @@ -31,37 +31,3 @@ sat -verify -prove-asserts -show-ports -seq 5 miter #design -load gate #stat - -########## - -design -load read -design -copy-to model $__XILINX_SHREG_ -hierarchy -top shregmap_variable_test -prep -design -save gold - -simplemap t:$dff t:$dffe -shregmap -tech xilinx - -#stat -# show -width -# write_verilog -noexpr -norename -select -assert-count 1 t:$_DFF_P_ -select -assert-count 2 t:$__XILINX_SHREG_ - -design -stash gate - -design -import gold -as gold -design -import gate -as gate -design -copy-from model -as $__XILINX_SHREG_ \$__XILINX_SHREG_ -prep - -miter -equiv -flatten -make_assert -make_outputs gold gate miter -sat -verify -prove-asserts -show-ports -seq 5 miter - -# design -load gold -# stat - -# design -load gate -# stat - -- cgit v1.2.3 From 2b37a093e95036b267481b2dae2046278eef4040 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 22 Aug 2019 16:42:19 -0700 Subject: In sat: 'x' in init attr should not override constant --- tests/sat/initval.v | 4 ++++ tests/sat/initval.ys | 2 +- 2 files changed, 5 insertions(+), 1 deletion(-) (limited to 'tests') diff --git a/tests/sat/initval.v b/tests/sat/initval.v index 5b661f8d6..d46ccae48 100644 --- a/tests/sat/initval.v +++ b/tests/sat/initval.v @@ -1,6 +1,7 @@ module test(input clk, input [3:0] bar, output [3:0] foo); reg [3:0] foo = 0; reg [3:0] last_bar = 0; + reg [3:0] asdf = 4'b1xxx; always @* foo[1:0] <= bar[1:0]; @@ -11,5 +12,8 @@ module test(input clk, input [3:0] bar, output [3:0] foo); always @(posedge clk) last_bar <= bar; + always @* + asdf[2:0] <= 3'b111; + assert property (foo == {last_bar[3:2], bar[1:0]}); endmodule diff --git a/tests/sat/initval.ys b/tests/sat/initval.ys index 2079d2f34..3d88aa971 100644 --- a/tests/sat/initval.ys +++ b/tests/sat/initval.ys @@ -1,4 +1,4 @@ read_verilog -sv initval.v -proc;; +proc; sat -seq 10 -prove-asserts -- cgit v1.2.3 From 6b5e65919a6ec14d4bfc85f80d1f7492d5b86c16 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Mon, 26 Aug 2019 17:52:57 -0700 Subject: Revert "In sat: 'x' in init attr should not override constant" This reverts commit 2b37a093e95036b267481b2dae2046278eef4040. --- tests/sat/initval.v | 4 ---- tests/sat/initval.ys | 2 +- 2 files changed, 1 insertion(+), 5 deletions(-) (limited to 'tests') diff --git a/tests/sat/initval.v b/tests/sat/initval.v index d46ccae48..5b661f8d6 100644 --- a/tests/sat/initval.v +++ b/tests/sat/initval.v @@ -1,7 +1,6 @@ module test(input clk, input [3:0] bar, output [3:0] foo); reg [3:0] foo = 0; reg [3:0] last_bar = 0; - reg [3:0] asdf = 4'b1xxx; always @* foo[1:0] <= bar[1:0]; @@ -12,8 +11,5 @@ module test(input clk, input [3:0] bar, output [3:0] foo); always @(posedge clk) last_bar <= bar; - always @* - asdf[2:0] <= 3'b111; - assert property (foo == {last_bar[3:2], bar[1:0]}); endmodule diff --git a/tests/sat/initval.ys b/tests/sat/initval.ys index 3d88aa971..2079d2f34 100644 --- a/tests/sat/initval.ys +++ b/tests/sat/initval.ys @@ -1,4 +1,4 @@ read_verilog -sv initval.v -proc; +proc;; sat -seq 10 -prove-asserts -- cgit v1.2.3 From 975aaf190f0bbbeacc253397ccada6889c69e8f7 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Wed, 28 Aug 2019 09:24:19 -0700 Subject: Add xilinx_srl test --- tests/xilinx/run-test.sh | 20 ++++++++++++++ tests/xilinx/xilinx_srl.v | 40 +++++++++++++++++++++++++++ tests/xilinx/xilinx_srl.ys | 67 ++++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 127 insertions(+) create mode 100755 tests/xilinx/run-test.sh create mode 100644 tests/xilinx/xilinx_srl.v create mode 100644 tests/xilinx/xilinx_srl.ys (limited to 'tests') diff --git a/tests/xilinx/run-test.sh b/tests/xilinx/run-test.sh new file mode 100755 index 000000000..ea56b70f0 --- /dev/null +++ b/tests/xilinx/run-test.sh @@ -0,0 +1,20 @@ +#!/usr/bin/env bash +set -e +{ +echo "all::" +for x in *.ys; do + echo "all:: run-$x" + echo "run-$x:" + echo " @echo 'Running $x..'" + echo " @../../yosys -ql ${x%.ys}.log $x" +done +for s in *.sh; do + if [ "$s" != "run-test.sh" ]; then + echo "all:: run-$s" + echo "run-$s:" + echo " @echo 'Running $s..'" + echo " @bash $s" + fi +done +} > run-test.mk +exec ${MAKE:-make} -f run-test.mk diff --git a/tests/xilinx/xilinx_srl.v b/tests/xilinx/xilinx_srl.v new file mode 100644 index 000000000..bc2a15ab2 --- /dev/null +++ b/tests/xilinx/xilinx_srl.v @@ -0,0 +1,40 @@ +module xilinx_srl_static_test(input i, clk, output [1:0] q); +reg head = 1'b0; +reg [3:0] shift1 = 4'b0000; +reg [3:0] shift2 = 4'b0000; + +always @(posedge clk) begin + head <= i; + shift1 <= {shift1[2:0], head}; + shift2 <= {shift2[2:0], head}; +end + +assign q = {shift2[3], shift1[3]}; +endmodule + +module xilinx_srl_variable_test(input i, clk, input [1:0] l1, l2, output [1:0] q); +reg head = 1'b0; +reg [3:0] shift1 = 4'b0000; +reg [3:0] shift2 = 4'b0000; + +always @(posedge clk) begin + head <= i; + shift1 <= {shift1[2:0], head}; + shift2 <= {shift2[2:0], head}; +end + +assign q = {shift2[l2], shift1[l1]}; +endmodule + +module $__XILINX_SHREG_(input C, D, E, input [1:0] L, output Q); +parameter CLKPOL = 1; +parameter ENPOL = 1; +parameter DEPTH = 1; +parameter [DEPTH-1:0] INIT = {DEPTH{1'b0}}; +reg [DEPTH-1:0] r = INIT; +wire clk = C ^ CLKPOL; +always @(posedge C) + if (E) + r <= { r[DEPTH-2:0], D }; +assign Q = r[L]; +endmodule diff --git a/tests/xilinx/xilinx_srl.ys b/tests/xilinx/xilinx_srl.ys new file mode 100644 index 000000000..4e3c44a98 --- /dev/null +++ b/tests/xilinx/xilinx_srl.ys @@ -0,0 +1,67 @@ +read_verilog xilinx_srl.v +design -save read + +design -copy-to model $__XILINX_SHREG_ +hierarchy -top xilinx_srl_static_test +prep +design -save gold + +techmap +xilinx_srl -fixed +opt + +# stat +# show -width +select -assert-count 1 t:$_DFF_P_ +select -assert-count 2 t:$__XILINX_SHREG_ + +design -stash gate + +design -import gold -as gold +design -import gate -as gate +design -copy-from model -as $__XILINX_SHREG_ \$__XILINX_SHREG_ +prep + +miter -equiv -flatten -make_assert -make_outputs gold gate miter +dump gate +sat -verify -prove-asserts -show-ports -seq 5 miter + +#design -load gold +#stat + +#design -load gate +#stat + +########## + +design -load read +design -copy-to model $__XILINX_SHREG_ +hierarchy -top xilinx_srl_variable_test +prep +design -save gold + +simplemap t:$dff t:$dffe +xilinx_srl -variable +opt + +#stat +# show -width +# write_verilog -noexpr -norename +select -assert-count 1 t:$_DFF_P_ +select -assert-count 2 t:$__XILINX_SHREG_ + +design -stash gate + +design -import gold -as gold +design -import gate -as gate +design -copy-from model -as $__XILINX_SHREG_ \$__XILINX_SHREG_ +prep + +miter -equiv -flatten -make_assert -make_outputs gold gate miter +sat -verify -prove-asserts -show-ports -seq 5 miter + +# design -load gold +# stat + +# design -load gate +# stat -- cgit v1.2.3 From 2e9e745efa03363f9f0d5cc47696401d55a8e5d2 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Wed, 28 Aug 2019 09:26:08 -0700 Subject: Do not simplemap for variable test --- tests/xilinx/xilinx_srl.ys | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'tests') diff --git a/tests/xilinx/xilinx_srl.ys b/tests/xilinx/xilinx_srl.ys index 4e3c44a98..b8df0e55a 100644 --- a/tests/xilinx/xilinx_srl.ys +++ b/tests/xilinx/xilinx_srl.ys @@ -40,14 +40,14 @@ hierarchy -top xilinx_srl_variable_test prep design -save gold -simplemap t:$dff t:$dffe xilinx_srl -variable opt #stat # show -width # write_verilog -noexpr -norename -select -assert-count 1 t:$_DFF_P_ +select -assert-count 1 t:$dff +select -assert-count 1 t:$dff r:WIDTH=1 %i select -assert-count 2 t:$__XILINX_SHREG_ design -stash gate -- cgit v1.2.3 From 2f493fb465d398a6fb4f24ffcd4af50d7e158fa9 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Wed, 28 Aug 2019 09:55:09 -0700 Subject: Use test_pmgen for xilinx_srl --- tests/xilinx/pmgen_xilinx_srl.ys | 57 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 57 insertions(+) create mode 100644 tests/xilinx/pmgen_xilinx_srl.ys (limited to 'tests') diff --git a/tests/xilinx/pmgen_xilinx_srl.ys b/tests/xilinx/pmgen_xilinx_srl.ys new file mode 100644 index 000000000..ea2f20487 --- /dev/null +++ b/tests/xilinx/pmgen_xilinx_srl.ys @@ -0,0 +1,57 @@ +read_verilog -icells < Date: Wed, 28 Aug 2019 09:55:34 -0700 Subject: Add .gitignore --- tests/xilinx/.gitignore | 3 +++ 1 file changed, 3 insertions(+) create mode 100644 tests/xilinx/.gitignore (limited to 'tests') diff --git a/tests/xilinx/.gitignore b/tests/xilinx/.gitignore new file mode 100644 index 000000000..b48f808a1 --- /dev/null +++ b/tests/xilinx/.gitignore @@ -0,0 +1,3 @@ +/*.log +/*.out +/run-test.mk -- cgit v1.2.3