From 3e76e3a6fa4355e7223b10bba394f986d6821551 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 6 Jun 2019 11:54:38 -0700
Subject: Add tests, fix for !=

---
 tests/various/muxpack.v  | 36 ++++++++++++++++++++++++++++++++++++
 tests/various/muxpack.ys | 42 ++++++++++++++++++++++++++++++++++++++++++
 2 files changed, 78 insertions(+)
 create mode 100644 tests/various/muxpack.v
 create mode 100644 tests/various/muxpack.ys

(limited to 'tests')

diff --git a/tests/various/muxpack.v b/tests/various/muxpack.v
new file mode 100644
index 000000000..abc87ba44
--- /dev/null
+++ b/tests/various/muxpack.v
@@ -0,0 +1,36 @@
+module mux_if_unbal_4_1 #(parameter N=4, parameter W=1) (input [N*W-1:0] i, input [$clog2(N)-1:0] s, output reg [W-1:0] o);
+always @*
+    if (s == 0) o <= i[0*W+:W];
+    else if (s == 1) o <= i[1*W+:W];
+    else if (s == 2) o <= i[2*W+:W];
+    else if (s == 3) o <= i[3*W+:W];
+    else o <= {W{1'bx}};
+
+endmodule
+
+module mux_if_unbal_5_3 #(parameter N=5, parameter W=3) (input [N*W-1:0] i, input [$clog2(N)-1:0] s, output reg [W-1:0] o);
+always @* begin
+    o <= {W{1'bx}};
+    if (s == 0) o <= i[0*W+:W];
+    if (s == 1) o <= i[1*W+:W];
+    if (s == 2) o <= i[2*W+:W];
+    if (s == 3) o <= i[3*W+:W];
+    if (s == 4) o <= i[4*W+:W];
+end
+
+endmodule
+
+module mux_if_unbal_5_3_invert #(parameter N=5, parameter W=3) (input [N*W-1:0] i, input [$clog2(N)-1:0] s, output reg [W-1:0] o);
+always @*
+    if (s != 0) 
+	   	if (s != 1) 
+			if (s != 2)
+				if (s != 3)
+					if (s != 4) o <= i[4*W+:W];
+					else o <= i[0*W+:W];
+				else o <= i[3*W+:W];
+			else o <= i[2*W+:W];
+		else o <= i[1*W+:W];
+    else o <= {W{1'bx}};
+
+endmodule
diff --git a/tests/various/muxpack.ys b/tests/various/muxpack.ys
new file mode 100644
index 000000000..58c01cf05
--- /dev/null
+++ b/tests/various/muxpack.ys
@@ -0,0 +1,42 @@
+read_verilog muxpack.v
+design -save read
+hierarchy -top mux_if_unbal_4_1
+prep
+design -save gold
+muxpack
+opt
+stat
+select -assert-count 1 t:$pmux
+design -stash gate
+design -import gold -as gold
+design -import gate -as gate
+miter -equiv -flatten -make_assert -make_outputs gold gate miter
+sat -verify -prove-asserts -show-ports miter
+
+design -load read
+hierarchy -top mux_if_unbal_5_3
+prep
+design -save gold
+muxpack
+opt
+stat
+select -assert-count 1 t:$pmux
+design -stash gate
+design -import gold -as gold
+design -import gate -as gate
+miter -equiv -flatten -make_assert -make_outputs gold gate miter
+sat -verify -prove-asserts -show-ports miter
+
+design -load read
+hierarchy -top mux_if_unbal_5_3_invert
+prep
+design -save gold
+muxpack
+opt
+stat
+select -assert-count 1 t:$pmux
+design -stash gate
+design -import gold -as gold
+design -import gate -as gate
+miter -equiv -flatten -make_assert -make_outputs gold gate miter
+sat -verify -prove-asserts -show-ports miter
-- 
cgit v1.2.3


From 5d4eca5a298d2f98de220cfd0efe5452ab4052d8 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 6 Jun 2019 11:59:41 -0700
Subject: Add a few more special case tests

---
 tests/various/muxpack.v  | 23 +++++++++++++++++++++++
 tests/various/muxpack.ys | 28 ++++++++++++++++++++++++++++
 2 files changed, 51 insertions(+)

(limited to 'tests')

diff --git a/tests/various/muxpack.v b/tests/various/muxpack.v
index abc87ba44..333908fcb 100644
--- a/tests/various/muxpack.v
+++ b/tests/various/muxpack.v
@@ -34,3 +34,26 @@ always @*
     else o <= {W{1'bx}};
 
 endmodule
+
+module mux_if_unbal_5_3_width_mismatch #(parameter N=5, parameter W=3) (input [N*W-1:0] i, input [$clog2(N)-1:0] s, output reg [W-1:0] o);
+always @* begin
+    o <= {W{1'bx}};
+    if (s == 0) o <= i[0*W+:W];
+    if (s == 1) o <= i[1*W+:W];
+    if (s == 2) o[W-2:0] <= i[2*W+:W-1];
+    if (s == 3) o <= i[3*W+:W];
+    if (s == 4) o <= i[4*W+:W];
+end
+
+endmodule
+
+module mux_if_unbal_5_3_missing #(parameter N=5, parameter W=3) (input [N*W-1:0] i, input [$clog2(N)-1:0] s, output reg [W-1:0] o);
+always @* begin
+    if (s == 0) o <= i[0*W+:W];
+//    else if (s == 1) o <= i[1*W+:W];
+//    else if (s == 2) o <= i[2*W+:W];
+    else if (s == 3) o <= i[3*W+:W];
+    else o <= {W{1'bx}};
+end
+
+endmodule
diff --git a/tests/various/muxpack.ys b/tests/various/muxpack.ys
index 58c01cf05..174eea74b 100644
--- a/tests/various/muxpack.ys
+++ b/tests/various/muxpack.ys
@@ -40,3 +40,31 @@ design -import gold -as gold
 design -import gate -as gate
 miter -equiv -flatten -make_assert -make_outputs gold gate miter
 sat -verify -prove-asserts -show-ports miter
+
+design -load read
+hierarchy -top mux_if_unbal_5_3_width_mismatch
+prep
+design -save gold
+muxpack
+opt
+stat
+select -assert-count 2 t:$pmux
+design -stash gate
+design -import gold -as gold
+design -import gate -as gate
+miter -equiv -flatten -make_assert -make_outputs gold gate miter
+sat -verify -prove-asserts -show-ports miter
+
+design -load read
+hierarchy -top mux_if_unbal_5_3_missing
+prep
+design -save gold
+muxpack
+opt
+stat
+select -assert-count 1 t:$pmux
+design -stash gate
+design -import gold -as gold
+design -import gate -as gate
+miter -equiv -flatten -make_assert -make_outputs gold gate miter
+sat -verify -prove-asserts -show-ports miter
-- 
cgit v1.2.3


From b8620f7b3dde4460e5a8ed3ea7fd7aef54aa7da1 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 6 Jun 2019 12:03:44 -0700
Subject: One more and tidy up

---
 tests/various/muxpack.v  | 18 +++++++++++++-----
 tests/various/muxpack.ys | 16 +++++++++++++++-
 2 files changed, 28 insertions(+), 6 deletions(-)

(limited to 'tests')

diff --git a/tests/various/muxpack.v b/tests/various/muxpack.v
index 333908fcb..c2c2537a0 100644
--- a/tests/various/muxpack.v
+++ b/tests/various/muxpack.v
@@ -5,7 +5,6 @@ always @*
     else if (s == 2) o <= i[2*W+:W];
     else if (s == 3) o <= i[3*W+:W];
     else o <= {W{1'bx}};
-
 endmodule
 
 module mux_if_unbal_5_3 #(parameter N=5, parameter W=3) (input [N*W-1:0] i, input [$clog2(N)-1:0] s, output reg [W-1:0] o);
@@ -17,7 +16,6 @@ always @* begin
     if (s == 3) o <= i[3*W+:W];
     if (s == 4) o <= i[4*W+:W];
 end
-
 endmodule
 
 module mux_if_unbal_5_3_invert #(parameter N=5, parameter W=3) (input [N*W-1:0] i, input [$clog2(N)-1:0] s, output reg [W-1:0] o);
@@ -32,7 +30,6 @@ always @*
 			else o <= i[2*W+:W];
 		else o <= i[1*W+:W];
     else o <= {W{1'bx}};
-
 endmodule
 
 module mux_if_unbal_5_3_width_mismatch #(parameter N=5, parameter W=3) (input [N*W-1:0] i, input [$clog2(N)-1:0] s, output reg [W-1:0] o);
@@ -44,10 +41,9 @@ always @* begin
     if (s == 3) o <= i[3*W+:W];
     if (s == 4) o <= i[4*W+:W];
 end
-
 endmodule
 
-module mux_if_unbal_5_3_missing #(parameter N=5, parameter W=3) (input [N*W-1:0] i, input [$clog2(N)-1:0] s, output reg [W-1:0] o);
+module mux_if_unbal_4_1_missing #(parameter N=5, parameter W=3) (input [N*W-1:0] i, input [$clog2(N)-1:0] s, output reg [W-1:0] o);
 always @* begin
     if (s == 0) o <= i[0*W+:W];
 //    else if (s == 1) o <= i[1*W+:W];
@@ -55,5 +51,17 @@ always @* begin
     else if (s == 3) o <= i[3*W+:W];
     else o <= {W{1'bx}};
 end
+endmodule
 
+module mux_if_unbal_5_3_order #(parameter N=5, parameter W=3) (input [N*W-1:0] i, input [$clog2(N)-1:0] s, output reg [W-1:0] o);
+always @* begin
+    o <= {W{1'bx}};
+    if (s == 3) o <= i[3*W+:W];
+    if (s == 2) o <= i[2*W+:W];
+    if (s == 1) o <= i[1*W+:W];
+    if (s == 4) o <= i[4*W+:W];
+    if (s == 0) o <= i[0*W+:W];
+end
 endmodule
+
+
diff --git a/tests/various/muxpack.ys b/tests/various/muxpack.ys
index 174eea74b..a967ddfef 100644
--- a/tests/various/muxpack.ys
+++ b/tests/various/muxpack.ys
@@ -56,7 +56,21 @@ miter -equiv -flatten -make_assert -make_outputs gold gate miter
 sat -verify -prove-asserts -show-ports miter
 
 design -load read
-hierarchy -top mux_if_unbal_5_3_missing
+hierarchy -top mux_if_unbal_4_1_missing
+prep
+design -save gold
+muxpack
+opt
+stat
+select -assert-count 1 t:$pmux
+design -stash gate
+design -import gold -as gold
+design -import gate -as gate
+miter -equiv -flatten -make_assert -make_outputs gold gate miter
+sat -verify -prove-asserts -show-ports miter
+
+design -load read
+hierarchy -top mux_if_unbal_5_3_order
 prep
 design -save gold
 muxpack
-- 
cgit v1.2.3


From 705388eb24022d2a310ae72cd81e67a2f0ce7586 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 6 Jun 2019 12:44:06 -0700
Subject: Add non exclusive test

---
 tests/various/muxpack.v  | 20 ++++++++++++++++++++
 tests/various/muxpack.ys | 36 ++++++++++++++++++++++++++++++++++++
 2 files changed, 56 insertions(+)

(limited to 'tests')

diff --git a/tests/various/muxpack.v b/tests/various/muxpack.v
index c2c2537a0..e847fef27 100644
--- a/tests/various/muxpack.v
+++ b/tests/various/muxpack.v
@@ -64,4 +64,24 @@ always @* begin
 end
 endmodule
 
+module mux_if_unbal_4_1_nonexcl #(parameter N=4, parameter W=1) (input [N*W-1:0] i, input [$clog2(N)-1:0] s, output reg [W-1:0] o);
+always @*
+    if (s == 0) o <= i[0*W+:W];
+    else if (s == 1) o <= i[1*W+:W];
+    else if (s == 2) o <= i[2*W+:W];
+    else if (s == 3) o <= i[3*W+:W];
+	else if (s == 0) o <= {W{1'b0}};
+    else o <= {W{1'bx}};
+endmodule
 
+module mux_if_unbal_5_3_nonexcl #(parameter N=4, parameter W=1) (input [N*W-1:0] i, input [$clog2(N)-1:0] s, output reg [W-1:0] o);
+always @* begin
+    o <= {W{1'bx}};
+    if (s == 0) o <= i[0*W+:W];
+    if (s == 1) o <= i[1*W+:W];
+    if (s == 2) o <= i[2*W+:W];
+    if (s == 3) o <= i[3*W+:W];
+    if (s == 4) o <= i[4*W+:W];
+	if (s == 0) o <= i[2*W+:W];
+end
+endmodule
diff --git a/tests/various/muxpack.ys b/tests/various/muxpack.ys
index a967ddfef..178860b88 100644
--- a/tests/various/muxpack.ys
+++ b/tests/various/muxpack.ys
@@ -6,6 +6,7 @@ design -save gold
 muxpack
 opt
 stat
+select -assert-count 0 t:$mux
 select -assert-count 1 t:$pmux
 design -stash gate
 design -import gold -as gold
@@ -20,6 +21,7 @@ design -save gold
 muxpack
 opt
 stat
+select -assert-count 0 t:$mux
 select -assert-count 1 t:$pmux
 design -stash gate
 design -import gold -as gold
@@ -34,6 +36,7 @@ design -save gold
 muxpack
 opt
 stat
+select -assert-count 0 t:$mux
 select -assert-count 1 t:$pmux
 design -stash gate
 design -import gold -as gold
@@ -48,6 +51,7 @@ design -save gold
 muxpack
 opt
 stat
+select -assert-count 0 t:$mux
 select -assert-count 2 t:$pmux
 design -stash gate
 design -import gold -as gold
@@ -62,6 +66,7 @@ design -save gold
 muxpack
 opt
 stat
+select -assert-count 0 t:$mux
 select -assert-count 1 t:$pmux
 design -stash gate
 design -import gold -as gold
@@ -76,6 +81,37 @@ design -save gold
 muxpack
 opt
 stat
+select -assert-count 0 t:$mux
+select -assert-count 1 t:$pmux
+design -stash gate
+design -import gold -as gold
+design -import gate -as gate
+miter -equiv -flatten -make_assert -make_outputs gold gate miter
+sat -verify -prove-asserts -show-ports miter
+
+design -load read
+hierarchy -top mux_if_unbal_4_1_nonexcl
+prep
+design -save gold
+muxpack
+opt
+stat
+select -assert-count 0 t:$mux
+select -assert-count 1 t:$pmux
+design -stash gate
+design -import gold -as gold
+design -import gate -as gate
+miter -equiv -flatten -make_assert -make_outputs gold gate miter
+sat -verify -prove-asserts -show-ports miter
+
+design -load read
+hierarchy -top mux_if_unbal_5_3_nonexcl
+prep
+design -save gold
+muxpack
+opt
+stat
+select -assert-count 0 t:$mux
 select -assert-count 1 t:$pmux
 design -stash gate
 design -import gold -as gold
-- 
cgit v1.2.3


From ccdf989025e57da7dfd5ab609676ebe3cfb2c2d6 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 6 Jun 2019 13:51:22 -0700
Subject: Support cascading $pmux.A with $mux.A and $mux.B

---
 tests/various/muxpack.v  | 25 +++++++++++++++++++++++++
 tests/various/muxpack.ys | 15 +++++++++++++++
 2 files changed, 40 insertions(+)

(limited to 'tests')

diff --git a/tests/various/muxpack.v b/tests/various/muxpack.v
index e847fef27..fe0150532 100644
--- a/tests/various/muxpack.v
+++ b/tests/various/muxpack.v
@@ -85,3 +85,28 @@ always @* begin
 	if (s == 0) o <= i[2*W+:W];
 end
 endmodule
+
+module mux_case_unbal_7_7#(parameter N=7, parameter W=7) (input [N*W-1:0] i, input [$clog2(N)-1:0] s, output reg [W-1:0] o);
+always @* begin
+    o <= {W{1'bx}};
+    case (s)
+    0: o <= i[0*W+:W];
+    default:
+        case (s)
+        1: o <= i[1*W+:W];
+        2: o <= i[2*W+:W];
+        default:
+            case (s)
+            3: o <= i[3*W+:W];
+            4: o <= i[4*W+:W];
+            5: o <= i[5*W+:W];
+            default:
+                case (s)
+                    6: o <= i[6*W+:W];
+                    default: o <= i[7*W+:W];
+                endcase
+            endcase
+        endcase
+    endcase
+end
+endmodule
diff --git a/tests/various/muxpack.ys b/tests/various/muxpack.ys
index 178860b88..4dcb9ed89 100644
--- a/tests/various/muxpack.ys
+++ b/tests/various/muxpack.ys
@@ -118,3 +118,18 @@ design -import gold -as gold
 design -import gate -as gate
 miter -equiv -flatten -make_assert -make_outputs gold gate miter
 sat -verify -prove-asserts -show-ports miter
+
+design -load read
+hierarchy -top mux_case_unbal_7_7
+prep
+design -save gold
+muxpack
+opt
+stat
+select -assert-count 0 t:$mux
+select -assert-count 1 t:$pmux
+design -stash gate
+design -import gold -as gold
+design -import gate -as gate
+miter -equiv -flatten -make_assert -make_outputs gold gate miter
+sat -verify -prove-asserts -show-ports miter
-- 
cgit v1.2.3


From 0a66720f6f67b087fe6342d01d45944506240942 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 6 Jun 2019 14:01:42 -0700
Subject: Fix warnings

---
 tests/various/muxpack.v  | 4 ++--
 tests/various/muxpack.ys | 2 +-
 2 files changed, 3 insertions(+), 3 deletions(-)

(limited to 'tests')

diff --git a/tests/various/muxpack.v b/tests/various/muxpack.v
index fe0150532..7c189fff8 100644
--- a/tests/various/muxpack.v
+++ b/tests/various/muxpack.v
@@ -74,7 +74,7 @@ always @*
     else o <= {W{1'bx}};
 endmodule
 
-module mux_if_unbal_5_3_nonexcl #(parameter N=4, parameter W=1) (input [N*W-1:0] i, input [$clog2(N)-1:0] s, output reg [W-1:0] o);
+module mux_if_unbal_5_3_nonexcl #(parameter N=5, parameter W=3) (input [N*W-1:0] i, input [$clog2(N)-1:0] s, output reg [W-1:0] o);
 always @* begin
     o <= {W{1'bx}};
     if (s == 0) o <= i[0*W+:W];
@@ -86,7 +86,7 @@ always @* begin
 end
 endmodule
 
-module mux_case_unbal_7_7#(parameter N=7, parameter W=7) (input [N*W-1:0] i, input [$clog2(N)-1:0] s, output reg [W-1:0] o);
+module mux_case_unbal_8_7#(parameter N=8, parameter W=7) (input [N*W-1:0] i, input [$clog2(N)-1:0] s, output reg [W-1:0] o);
 always @* begin
     o <= {W{1'bx}};
     case (s)
diff --git a/tests/various/muxpack.ys b/tests/various/muxpack.ys
index 4dcb9ed89..0c5b82818 100644
--- a/tests/various/muxpack.ys
+++ b/tests/various/muxpack.ys
@@ -120,7 +120,7 @@ miter -equiv -flatten -make_assert -make_outputs gold gate miter
 sat -verify -prove-asserts -show-ports miter
 
 design -load read
-hierarchy -top mux_case_unbal_7_7
+hierarchy -top mux_case_unbal_8_7
 prep
 design -save gold
 muxpack
-- 
cgit v1.2.3


From 5c277c6325b78bfe18cf294b63ea69ff272e69c5 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 6 Jun 2019 14:21:34 -0700
Subject: Fix and test for balanced case

---
 tests/various/muxpack.v  | 26 ++++++++++++++++++++++++++
 tests/various/muxpack.ys | 15 +++++++++++++++
 2 files changed, 41 insertions(+)

(limited to 'tests')

diff --git a/tests/various/muxpack.v b/tests/various/muxpack.v
index 7c189fff8..f1bd5ea8e 100644
--- a/tests/various/muxpack.v
+++ b/tests/various/muxpack.v
@@ -110,3 +110,29 @@ always @* begin
     endcase
 end
 endmodule
+
+module mux_if_bal_8_2 #(parameter N=8, parameter W=2) (input [N*W-1:0] i, input [$clog2(N)-1:0] s, output reg [W-1:0] o);
+always @*
+    if (s[0] == 1'b0)
+     if (s[1] == 1'b0)
+      if (s[2] == 1'b0)
+       o <= i[0*W+:W];
+      else
+       o <= i[1*W+:W];
+     else
+      if (s[2] == 1'b0)
+       o <= i[2*W+:W];
+      else
+       o <= i[3*W+:W];
+    else
+     if (s[1] == 1'b0)
+      if (s[2] == 1'b0)
+       o <= i[4*W+:W];
+      else
+       o <= i[5*W+:W];
+     else
+      if (s[2] == 1'b0)
+       o <= i[6*W+:W];
+      else
+       o <= i[7*W+:W];
+endmodule
diff --git a/tests/various/muxpack.ys b/tests/various/muxpack.ys
index 0c5b82818..9ea743b9f 100644
--- a/tests/various/muxpack.ys
+++ b/tests/various/muxpack.ys
@@ -133,3 +133,18 @@ design -import gold -as gold
 design -import gate -as gate
 miter -equiv -flatten -make_assert -make_outputs gold gate miter
 sat -verify -prove-asserts -show-ports miter
+
+design -load read
+hierarchy -top mux_if_bal_8_2
+prep
+design -save gold
+muxpack
+opt
+stat
+select -assert-count 7 t:$mux
+select -assert-count 0 t:$pmux
+design -stash gate
+design -import gold -as gold
+design -import gate -as gate
+miter -equiv -flatten -make_assert -make_outputs gold gate miter
+sat -verify -prove-asserts -show-ports miter
-- 
cgit v1.2.3


From 0f6e914ef63d06ae77b54d246b61118c19647f26 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 7 Jun 2019 08:34:58 -0700
Subject: Another muxpack test

---
 tests/various/muxpack.v  | 17 +++++++++++++++++
 tests/various/muxpack.ys | 15 +++++++++++++++
 2 files changed, 32 insertions(+)

(limited to 'tests')

diff --git a/tests/various/muxpack.v b/tests/various/muxpack.v
index f1bd5ea8e..41dfed396 100644
--- a/tests/various/muxpack.v
+++ b/tests/various/muxpack.v
@@ -136,3 +136,20 @@ always @*
       else
        o <= i[7*W+:W];
 endmodule
+
+module mux_if_bal_5_1 #(parameter N=5, parameter W=1) (input [N*W-1:0] i, input [$clog2(N)-1:0] s, output reg [W-1:0] o);
+always @*
+    if (s[0] == 1'b0)
+     if (s[1] == 1'b0)
+      if (s[2] == 1'b0)
+       o <= i[0*W+:W];
+      else
+       o <= i[1*W+:W];
+     else
+      if (s[2] == 1'b0)
+       o <= i[2*W+:W];
+      else
+       o <= i[3*W+:W];
+    else
+     o <= i[4*W+:W];
+endmodule
diff --git a/tests/various/muxpack.ys b/tests/various/muxpack.ys
index 9ea743b9f..dd3c143d8 100644
--- a/tests/various/muxpack.ys
+++ b/tests/various/muxpack.ys
@@ -148,3 +148,18 @@ design -import gold -as gold
 design -import gate -as gate
 miter -equiv -flatten -make_assert -make_outputs gold gate miter
 sat -verify -prove-asserts -show-ports miter
+
+design -load read
+hierarchy -top mux_if_bal_5_1
+prep
+design -save gold
+muxpack
+opt
+stat
+select -assert-count 2 t:$mux
+select -assert-count 1 t:$pmux
+design -stash gate
+design -import gold -as gold
+design -import gate -as gate
+miter -equiv -flatten -make_assert -make_outputs gold gate miter
+sat -verify -prove-asserts -show-ports miter
-- 
cgit v1.2.3


From e263bc249b905195120fbc074c6f80d03fb21cf8 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 7 Jun 2019 11:54:29 -0700
Subject: Add nonexclusive test from @cliffordwolf

---
 tests/various/muxpack.v  | 13 +++++++++++++
 tests/various/muxpack.ys | 15 +++++++++++++++
 2 files changed, 28 insertions(+)

(limited to 'tests')

diff --git a/tests/various/muxpack.v b/tests/various/muxpack.v
index 41dfed396..f3c25db8d 100644
--- a/tests/various/muxpack.v
+++ b/tests/various/muxpack.v
@@ -153,3 +153,16 @@ always @*
     else
      o <= i[4*W+:W];
 endmodule
+
+module cliffordwolf_nonexclusive_select (
+        input wire x, y, z,
+        input wire a, b, c, d,
+        output reg o
+);
+        always @* begin
+                o = a;
+                if (x) o = b;
+                if (y) o = c;
+                if (z) o = d;
+        end
+endmodule
diff --git a/tests/various/muxpack.ys b/tests/various/muxpack.ys
index dd3c143d8..7c3fe5070 100644
--- a/tests/various/muxpack.ys
+++ b/tests/various/muxpack.ys
@@ -163,3 +163,18 @@ design -import gold -as gold
 design -import gate -as gate
 miter -equiv -flatten -make_assert -make_outputs gold gate miter
 sat -verify -prove-asserts -show-ports miter
+
+design -load read
+hierarchy -top cliffordwolf_nonexclusive_select
+prep
+design -save gold
+muxpack
+opt
+stat
+select -assert-count 0 t:$mux
+select -assert-count 1 t:$pmux
+design -stash gate
+design -import gold -as gold
+design -import gate -as gate
+miter -equiv -flatten -make_assert -make_outputs gold gate miter
+sat -verify -prove-asserts -show-ports miter
-- 
cgit v1.2.3


From 1da12c5071a738504d22e68d66cab7c5c5afb07e Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 7 Jun 2019 12:12:11 -0700
Subject: Add @cliffordwolf freduce testcase

---
 tests/various/muxpack.v  | 13 +++++++++++++
 tests/various/muxpack.ys | 17 +++++++++++++++++
 2 files changed, 30 insertions(+)

(limited to 'tests')

diff --git a/tests/various/muxpack.v b/tests/various/muxpack.v
index f3c25db8d..d45ce4045 100644
--- a/tests/various/muxpack.v
+++ b/tests/various/muxpack.v
@@ -166,3 +166,16 @@ module cliffordwolf_nonexclusive_select (
                 if (z) o = d;
         end
 endmodule
+
+module cliffordwolf_freduce (
+        input wire [1:0] s,
+        input wire a, b, c, d,
+        output reg [3:0] o
+);
+        always @* begin
+                o = {4{a}};
+                if (s == 0) o = {3{b}};
+                if (s == 1) o = {2{c}};
+                if (s == 2) o = d;
+        end
+endmodule
diff --git a/tests/various/muxpack.ys b/tests/various/muxpack.ys
index 7c3fe5070..afdacdf30 100644
--- a/tests/various/muxpack.ys
+++ b/tests/various/muxpack.ys
@@ -178,3 +178,20 @@ design -import gold -as gold
 design -import gate -as gate
 miter -equiv -flatten -make_assert -make_outputs gold gate miter
 sat -verify -prove-asserts -show-ports miter
+
+design -load read
+hierarchy -top cliffordwolf_freduce
+prep
+design -save gold
+proc; opt; freduce; opt
+write_verilog -noexpr -norename
+muxpack
+opt
+stat
+select -assert-count 0 t:$mux
+select -assert-count 1 t:$pmux
+design -stash gate
+design -import gold -as gold
+design -import gate -as gate
+miter -equiv -flatten -make_assert -make_outputs gold gate miter
+sat -verify -prove-asserts -show-ports miter
-- 
cgit v1.2.3


From b959bf79c004fdf81ccc397d5aa774b67a09d6da Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 7 Jun 2019 15:35:15 -0700
Subject: Add nonexcl case test, comment out two others

---
 tests/various/muxpack.v  | 18 ++++++++++++++
 tests/various/muxpack.ys | 61 +++++++++++++++++++++++++++++++-----------------
 2 files changed, 57 insertions(+), 22 deletions(-)

(limited to 'tests')

diff --git a/tests/various/muxpack.v b/tests/various/muxpack.v
index d45ce4045..3a1086dbf 100644
--- a/tests/various/muxpack.v
+++ b/tests/various/muxpack.v
@@ -179,3 +179,21 @@ module cliffordwolf_freduce (
                 if (s == 2) o = d;
         end
 endmodule
+
+module case_nonexclusive_select (
+        input wire [1:0] x, y,
+        input wire a, b, c, d, e,
+        output reg o
+);
+        always @* begin
+            case (x)
+                0, 2: o = b;
+                1: o = c;
+                default: begin
+                    o = a;
+                    if (y == 0) o = d;
+                    if (y == 1) o = e;
+                end
+        endcase
+        end
+endmodule
diff --git a/tests/various/muxpack.ys b/tests/various/muxpack.ys
index afdacdf30..579dad8d3 100644
--- a/tests/various/muxpack.ys
+++ b/tests/various/muxpack.ys
@@ -1,5 +1,6 @@
 read_verilog muxpack.v
 design -save read
+
 hierarchy -top mux_if_unbal_4_1
 prep
 design -save gold
@@ -29,20 +30,21 @@ design -import gate -as gate
 miter -equiv -flatten -make_assert -make_outputs gold gate miter
 sat -verify -prove-asserts -show-ports miter
 
-design -load read
-hierarchy -top mux_if_unbal_5_3_invert
-prep
-design -save gold
-muxpack
-opt
-stat
-select -assert-count 0 t:$mux
-select -assert-count 1 t:$pmux
-design -stash gate
-design -import gold -as gold
-design -import gate -as gate
-miter -equiv -flatten -make_assert -make_outputs gold gate miter
-sat -verify -prove-asserts -show-ports miter
+# TODO: Currently ExclusiveDatabase only analyses $eq cells
+#design -load read
+#hierarchy -top mux_if_unbal_5_3_invert
+#prep
+#design -save gold
+#muxpack
+#opt
+#stat
+#select -assert-count 0 t:$mux
+#select -assert-count 1 t:$pmux
+#design -stash gate
+#design -import gold -as gold
+#design -import gate -as gate
+#miter -equiv -flatten -make_assert -make_outputs gold gate miter
+#sat -verify -prove-asserts -show-ports miter
 
 design -load read
 hierarchy -top mux_if_unbal_5_3_width_mismatch
@@ -156,8 +158,8 @@ design -save gold
 muxpack
 opt
 stat
-select -assert-count 2 t:$mux
-select -assert-count 1 t:$pmux
+select -assert-count 4 t:$mux
+select -assert-count 0 t:$pmux
 design -stash gate
 design -import gold -as gold
 design -import gate -as gate
@@ -171,25 +173,40 @@ design -save gold
 muxpack
 opt
 stat
-select -assert-count 0 t:$mux
-select -assert-count 1 t:$pmux
+select -assert-count 3 t:$mux
+select -assert-count 0 t:$pmux
 design -stash gate
 design -import gold -as gold
 design -import gate -as gate
 miter -equiv -flatten -make_assert -make_outputs gold gate miter
 sat -verify -prove-asserts -show-ports miter
 
+#design -load read
+#hierarchy -top cliffordwolf_freduce
+#prep
+#design -save gold
+#proc; opt; freduce; opt
+#show
+#muxpack
+#opt
+#stat
+#select -assert-count 0 t:$mux
+#select -assert-count 1 t:$pmux
+#design -stash gate
+#design -import gold -as gold
+#design -import gate -as gate
+#miter -equiv -flatten -make_assert -make_outputs gold gate miter
+#sat -verify -prove-asserts -show-ports miter
+
 design -load read
-hierarchy -top cliffordwolf_freduce
+hierarchy -top case_nonexclusive_select
 prep
 design -save gold
-proc; opt; freduce; opt
-write_verilog -noexpr -norename
 muxpack
 opt
 stat
 select -assert-count 0 t:$mux
-select -assert-count 1 t:$pmux
+select -assert-count 2 t:$pmux
 design -stash gate
 design -import gold -as gold
 design -import gate -as gate
-- 
cgit v1.2.3


From c314ca3c51579a9c5305cbf9a69635e123db0423 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Mon, 10 Jun 2019 16:16:26 -0700
Subject: Add test

---
 tests/various/shregmap.v  | 22 ++++++++++++++++++++++
 tests/various/shregmap.ys | 31 +++++++++++++++++++++++++++++++
 2 files changed, 53 insertions(+)
 create mode 100644 tests/various/shregmap.v
 create mode 100644 tests/various/shregmap.ys

(limited to 'tests')

diff --git a/tests/various/shregmap.v b/tests/various/shregmap.v
new file mode 100644
index 000000000..56e05c2c0
--- /dev/null
+++ b/tests/various/shregmap.v
@@ -0,0 +1,22 @@
+module shregmap_test(input i, clk, output [1:0] q);
+reg head = 1'b0;
+reg [3:0] shift1 = 4'b0000;
+reg [3:0] shift2 = 4'b0000;
+
+always @(posedge clk) begin
+    head <= i;
+    shift1 <= {shift1[2:0], head};
+    shift2 <= {shift2[2:0], head};
+end
+
+assign q = {shift2[3], shift1[3]};
+endmodule
+
+module $__SHREG_DFF_P_(input C, D, output Q);
+parameter DEPTH = 1;
+parameter [DEPTH-1:0] INIT = {DEPTH{1'b0}};
+reg [DEPTH-1:0] r = INIT;
+always @(posedge C) 
+    r <= { r[DEPTH-2:0], D };
+assign Q = r[DEPTH-1];
+endmodule
diff --git a/tests/various/shregmap.ys b/tests/various/shregmap.ys
new file mode 100644
index 000000000..ca7f47015
--- /dev/null
+++ b/tests/various/shregmap.ys
@@ -0,0 +1,31 @@
+read_verilog shregmap.v
+design -copy-to model $__SHREG_DFF_P_
+hierarchy -top shregmap_test
+prep
+design -save gold
+
+techmap
+shregmap -init
+
+opt
+
+stat
+# show -width
+select -assert-count 1 t:$_DFF_P_
+select -assert-count 2 t:$__SHREG_DFF_P_
+
+design -stash gate
+
+design -import gold -as gold
+design -import gate -as gate
+design -copy-from model -as $__SHREG_DFF_P_ \$__SHREG_DFF_P_
+prep
+
+miter -equiv -flatten -make_assert -make_outputs gold gate miter
+sat -verify -prove-asserts -show-ports -seq 5 miter
+
+design -load gold
+stat
+
+design -load gate
+stat
-- 
cgit v1.2.3


From 45c2a5f87694a83e0cf96477ede02567a93b32a8 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 12 Jun 2019 08:34:06 -0700
Subject: Add shregmap -tech xilinx test

---
 tests/various/shregmap.v  | 28 +++++++++++++++++++++++++++-
 tests/various/shregmap.ys | 37 ++++++++++++++++++++++++++++++++++++-
 2 files changed, 63 insertions(+), 2 deletions(-)

(limited to 'tests')

diff --git a/tests/various/shregmap.v b/tests/various/shregmap.v
index 56e05c2c0..604c2c976 100644
--- a/tests/various/shregmap.v
+++ b/tests/various/shregmap.v
@@ -1,4 +1,4 @@
-module shregmap_test(input i, clk, output [1:0] q);
+module shregmap_static_test(input i, clk, output [1:0] q);
 reg head = 1'b0;
 reg [3:0] shift1 = 4'b0000;
 reg [3:0] shift2 = 4'b0000;
@@ -20,3 +20,29 @@ always @(posedge C)
     r <= { r[DEPTH-2:0], D };
 assign Q = r[DEPTH-1];
 endmodule
+
+module shregmap_variable_test(input i, clk, input [1:0] l1, l2, output [1:0] q);
+reg head = 1'b0;
+reg [3:0] shift1 = 4'b0000;
+reg [3:0] shift2 = 4'b0000;
+
+always @(posedge clk) begin
+    head <= i;
+    shift1 <= {shift1[2:0], head};
+    shift2 <= {shift2[2:0], head};
+end
+
+assign q = {shift2[l2], shift1[l1]};
+endmodule
+
+module $__XILINX_SHREG_(input C, D, input [1:0] L, output Q);
+parameter CLKPOL = 1;
+parameter ENPOL = 1;
+parameter DEPTH = 1;
+parameter [DEPTH-1:0] INIT = {DEPTH{1'b0}};
+reg [DEPTH-1:0] r = INIT;
+wire clk = C ^ CLKPOL;
+always @(posedge C)
+    r <= { r[DEPTH-2:0], D };
+assign Q = r[L];
+endmodule
diff --git a/tests/various/shregmap.ys b/tests/various/shregmap.ys
index ca7f47015..d644a88aa 100644
--- a/tests/various/shregmap.ys
+++ b/tests/various/shregmap.ys
@@ -1,6 +1,8 @@
 read_verilog shregmap.v
+design -save read
+
 design -copy-to model $__SHREG_DFF_P_
-hierarchy -top shregmap_test
+hierarchy -top shregmap_static_test
 prep
 design -save gold
 
@@ -29,3 +31,36 @@ stat
 
 design -load gate
 stat
+
+##########
+
+design -load read
+design -copy-to model $__XILINX_SHREG_
+hierarchy -top shregmap_variable_test
+prep
+design -save gold
+
+simplemap t:$dff t:$dffe
+shregmap -tech xilinx
+
+stat
+# show -width
+write_verilog -noexpr -norename
+select -assert-count 1 t:$_DFF_P_
+select -assert-count 2 t:$__XILINX_SHREG_
+
+design -stash gate
+
+design -import gold -as gold
+design -import gate -as gate
+design -copy-from model -as $__XILINX_SHREG_ \$__XILINX_SHREG_
+prep
+
+miter -equiv -flatten -make_assert -make_outputs gold gate miter
+sat -verify -prove-asserts -show-ports -seq 5 miter
+
+design -load gold
+stat
+
+design -load gate
+stat
-- 
cgit v1.2.3


From a8c85d1b4b810e2ea31770e37e1414b7f1a15283 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Thu, 20 Jun 2019 14:27:57 +0200
Subject: Update some .gitignore files

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 tests/aiger/.gitignore   | 3 +--
 tests/various/.gitignore | 3 ++-
 2 files changed, 3 insertions(+), 3 deletions(-)

(limited to 'tests')

diff --git a/tests/aiger/.gitignore b/tests/aiger/.gitignore
index 073f46157..9a26bb8f4 100644
--- a/tests/aiger/.gitignore
+++ b/tests/aiger/.gitignore
@@ -1,2 +1 @@
-*.log
-*.out
+/*_ref.v
diff --git a/tests/various/.gitignore b/tests/various/.gitignore
index 397b4a762..7b3e8c68e 100644
--- a/tests/various/.gitignore
+++ b/tests/various/.gitignore
@@ -1 +1,2 @@
-*.log
+/*.log
+/*.out
-- 
cgit v1.2.3


From b98276fa61be7a1c589d6dac661d31982cfab16b Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 20 Jun 2019 10:10:43 -0700
Subject: Add test

---
 tests/various/signext.ys | 24 ++++++++++++++++++++++++
 1 file changed, 24 insertions(+)
 create mode 100644 tests/various/signext.ys

(limited to 'tests')

diff --git a/tests/various/signext.ys b/tests/various/signext.ys
new file mode 100644
index 000000000..26dab13a6
--- /dev/null
+++ b/tests/various/signext.ys
@@ -0,0 +1,24 @@
+
+read_verilog -formal <<EOT
+module gate(input clk, output [1:0] o);
+assign o = 1'bx;
+endmodule
+EOT
+
+
+## Example usage for "pmuxtree" and "muxcover"
+
+proc
+
+## Equivalence checking
+
+read_verilog -formal <<EOT
+module gold(input clk, output [1:0] o);
+assign o = 2'bxx;
+endmodule
+EOT
+
+proc
+
+miter -equiv -flatten -make_assert -make_outputs gold gate miter
+sat -verify -prove-asserts -show-ports -enable_undef miter
-- 
cgit v1.2.3


From b77322034c9234a8c24c6f53ed028fe29737b6b4 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 20 Jun 2019 10:15:04 -0700
Subject: Remove leftover comment

---
 tests/various/signext.ys | 3 ---
 1 file changed, 3 deletions(-)

(limited to 'tests')

diff --git a/tests/various/signext.ys b/tests/various/signext.ys
index 26dab13a6..ae44a0e06 100644
--- a/tests/various/signext.ys
+++ b/tests/various/signext.ys
@@ -5,9 +5,6 @@ assign o = 1'bx;
 endmodule
 EOT
 
-
-## Example usage for "pmuxtree" and "muxcover"
-
 proc
 
 ## Equivalence checking
-- 
cgit v1.2.3


From d0bbf9e4d4a508179b55a0cc7793d984f3318f7c Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 20 Jun 2019 12:43:59 -0700
Subject: Extend sign extension tests

---
 tests/various/signext.ys | 20 ++++++++++++++++----
 1 file changed, 16 insertions(+), 4 deletions(-)

(limited to 'tests')

diff --git a/tests/various/signext.ys b/tests/various/signext.ys
index ae44a0e06..0c8d671e7 100644
--- a/tests/various/signext.ys
+++ b/tests/various/signext.ys
@@ -1,7 +1,13 @@
 
 read_verilog -formal <<EOT
-module gate(input clk, output [1:0] o);
-assign o = 1'bx;
+module gate(input clk, output [32:0] o, p, q, r, s, t, u);
+assign o = 'bx;
+assign p = 1'bx;
+assign q = 'bz;
+assign r = 1'bz;
+assign s = 1'b0;
+assign t = 'b1;
+assign u = -'sb1;
 endmodule
 EOT
 
@@ -10,8 +16,14 @@ proc
 ## Equivalence checking
 
 read_verilog -formal <<EOT
-module gold(input clk, output [1:0] o);
-assign o = 2'bxx;
+module gold(input clk, output [32:0] o, p, q, r, s, t, u);
+assign o = {33{1'bx}};
+assign p = {{32{1'b0}}, 1'bx};
+assign q = {33{1'bz}};
+assign r = {{32{1'b0}}, 1'bz};
+assign s = {33{1'b0}};
+assign t = {{32{1'b0}}, 1'b1};
+assign u = {33{1'b1}};
 endmodule
 EOT
 
-- 
cgit v1.2.3


From c20adc52638b0f3ba3b1c39e5286ae92e901005d Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 20 Jun 2019 16:07:22 -0700
Subject: Add test

---
 tests/simple/generate.v | 11 +++++++++++
 1 file changed, 11 insertions(+)

(limited to 'tests')

diff --git a/tests/simple/generate.v b/tests/simple/generate.v
index 3c55682cb..0e353ad9b 100644
--- a/tests/simple/generate.v
+++ b/tests/simple/generate.v
@@ -148,3 +148,14 @@ generate
 endgenerate
 assign out = steps[WIDTH].outer[0].val;
 endmodule
+
+// ------------------------------------------
+
+module gen_test6(output [3:0] o);
+generate
+    genvar i;
+    for (i = 3; i >= 0; i = i-1) begin
+        assign o[i] = 1'b0;
+    end
+endgenerate
+endmodule
-- 
cgit v1.2.3


From 75375a3fbce622b5c4cb6f4464379bb0e66a1107 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 19 Jun 2019 10:07:34 -0700
Subject: Add test

---
 tests/various/muxcover.ys | 137 +++++++++++++++++++++++++++++++++++++++++++++-
 1 file changed, 136 insertions(+), 1 deletion(-)

(limited to 'tests')

diff --git a/tests/various/muxcover.ys b/tests/various/muxcover.ys
index 7ac460f13..d55a35b8c 100644
--- a/tests/various/muxcover.ys
+++ b/tests/various/muxcover.ys
@@ -13,7 +13,7 @@ read_verilog -formal <<EOT
 EOT
 
 
-## Examle usage for "pmuxtree" and "muxcover"
+## Example usage for "pmuxtree" and "muxcover"
 
 proc
 pmuxtree
@@ -49,3 +49,138 @@ hierarchy -top equiv
 equiv_simple -undef
 equiv_status -assert
 
+## Partial matching MUX4
+
+design -reset
+read_verilog -formal <<EOT
+module mux_if_bal_3_1 #(parameter N=3, parameter W=1) (input [N*W-1:0] i, input [$clog2(N)-1:0] s, output reg [W-1:0] o);
+always @* begin
+    o <= {{W{{1'bx}}}};
+    if (s[0] == 1'b0)
+     if (s[1] == 1'b0)
+      o <= i[0*W+:W];
+     else
+      o <= i[1*W+:W];
+    else
+     if (s[1] == 1'b0)
+      o <= i[2*W+:W];
+end
+endmodule
+EOT
+prep
+design -save gold
+
+techmap
+muxcover -mux4=150
+select -assert-count 0 t:$_MUX_
+select -assert-count 1 t:$_MUX4_
+select -assert-count 0 t:$_MUX8_
+select -assert-count 0 t:$_MUX16_
+techmap -map +/simcells.v t:$_MUX4_
+design -stash gate
+
+design -import gold -as gold
+design -import gate -as gate
+
+miter -equiv -flatten -make_assert -make_outputs gold gate miter
+sat -verify -prove-asserts -show-ports miter
+
+## Partial matching MUX8
+
+design -reset
+read_verilog -formal <<EOT
+module mux_if_bal_5_1 #(parameter N=5, parameter W=1) (input [N*W-1:0] i, input [$clog2(N)-1:0] s, output reg [W-1:0] o);
+always @* begin
+    o <= {{W{{1'bx}}}};
+    if (s[0] == 1'b0)
+     if (s[1] == 1'b0)
+      if (s[2] == 1'b0)
+       o <= i[0*W+:W];
+      else
+       o <= i[1*W+:W];
+     else
+      if (s[2] == 1'b0)
+       o <= i[2*W+:W];
+      else
+       o <= i[3*W+:W];
+    else
+     if (s[1] == 1'b0)
+      if (s[2] == 1'b0)
+       o <= i[4*W+:W];
+end
+endmodule
+EOT
+prep
+design -save gold
+
+techmap
+muxcover -mux4=150 -mux8=200
+select -assert-count 0 t:$_MUX_
+select -assert-count 0 t:$_MUX4_
+select -assert-count 1 t:$_MUX8_
+select -assert-count 0 t:$_MUX16_
+techmap -map +/simcells.v t:$_MUX8_
+design -stash gate
+
+design -import gold -as gold
+design -import gate -as gate
+
+miter -equiv -flatten -make_assert -make_outputs gold gate miter
+sat -verify -prove-asserts -show-ports miter
+
+## Partial matching MUX16
+
+design -reset
+read_verilog -formal <<EOT
+module mux_if_bal_9_1 #(parameter N=9, parameter W=1) (input [N*W-1:0] i, input [$clog2(N)-1:0] s, output reg [W-1:0] o);
+always @* begin
+    o <= {{W{{1'bx}}}};
+    if (s[0] == 1'b0)
+     if (s[1] == 1'b0)
+      if (s[2] == 1'b0)
+       if (s[3] == 1'b0)
+        o <= i[0*W+:W];
+       else
+        o <= i[1*W+:W];
+      else
+       if (s[3] == 1'b0)
+        o <= i[2*W+:W];
+       else
+        o <= i[3*W+:W];
+     else
+      if (s[2] == 1'b0)
+       if (s[3] == 1'b0)
+        o <= i[4*W+:W];
+       else
+        o <= i[5*W+:W];
+      else
+       if (s[3] == 1'b0)
+        o <= i[6*W+:W];
+       else
+        o <= i[7*W+:W];
+    else
+     if (s[1] == 1'b0)
+      if (s[2] == 1'b0)
+       if (s[3] == 1'b0)
+        o <= i[8*W+:W];
+end
+endmodule
+EOT
+prep
+design -save gold
+
+techmap
+muxcover -mux4=150 -mux8=200 -mux16=250
+select -assert-count 0 t:$_MUX_
+select -assert-count 0 t:$_MUX4_
+select -assert-count 0 t:$_MUX8_
+select -assert-count 1 t:$_MUX16_
+techmap -map +/simcells.v t:$_MUX16_
+design -stash gate
+
+design -import gold -as gold
+design -import gate -as gate
+
+miter -equiv -flatten -make_assert -make_outputs gold gate miter
+sat -verify -prove-asserts -show-ports miter
+
-- 
cgit v1.2.3


From 844c42cef8c7c04fa67653f998ccab0e90532d28 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 19 Jun 2019 10:15:41 -0700
Subject: Missing a `clean` and `opt_expr -mux_bool` in test

---
 tests/various/muxcover.ys | 4 ++++
 1 file changed, 4 insertions(+)

(limited to 'tests')

diff --git a/tests/various/muxcover.ys b/tests/various/muxcover.ys
index d55a35b8c..8ef619b46 100644
--- a/tests/various/muxcover.ys
+++ b/tests/various/muxcover.ys
@@ -115,6 +115,8 @@ design -save gold
 
 techmap
 muxcover -mux4=150 -mux8=200
+clean
+opt_expr -mux_bool
 select -assert-count 0 t:$_MUX_
 select -assert-count 0 t:$_MUX4_
 select -assert-count 1 t:$_MUX8_
@@ -171,6 +173,8 @@ design -save gold
 
 techmap
 muxcover -mux4=150 -mux8=200 -mux16=250
+clean
+opt_expr -mux_bool
 select -assert-count 0 t:$_MUX_
 select -assert-count 0 t:$_MUX4_
 select -assert-count 0 t:$_MUX8_
-- 
cgit v1.2.3


From 6ec816098153c733b97410ebc6aef166db8affd8 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 21 Jun 2019 11:45:53 -0700
Subject: Add more muxpack tests, with overlapping entries

---
 tests/various/muxpack.v  | 55 +++++++++++++++++++++++++++++++++++++++++++++++-
 tests/various/muxpack.ys | 30 ++++++++++++++++++++++++++
 2 files changed, 84 insertions(+), 1 deletion(-)

(limited to 'tests')

diff --git a/tests/various/muxpack.v b/tests/various/muxpack.v
index 3a1086dbf..7a658d754 100644
--- a/tests/various/muxpack.v
+++ b/tests/various/muxpack.v
@@ -187,7 +187,9 @@ module case_nonexclusive_select (
 );
         always @* begin
             case (x)
-                0, 2: o = b;
+                //0, 2: o = b;
+                0: o = b;
+                2: o = b;
                 1: o = c;
                 default: begin
                     o = a;
@@ -197,3 +199,54 @@ module case_nonexclusive_select (
         endcase
         end
 endmodule
+
+module case_nonoverlap (
+        input wire [2:0] x,
+        input wire a, b, c, d, e, f, g,
+        output reg o
+);
+        always @* begin
+            case (x)
+                //0, 2: o = b; // Creates $reduce_or
+                //0: o = b; 2: o = b; // Creates $reduce_or
+                0: o = b;
+                2: o = f;
+                1: o = c;
+                default:
+                    case (x)
+                        //3, 4: o = d; // Creates $reduce_or
+                        //3: o = d; 4: o = d; // Creates $reduce_or
+                        3: o = d;
+                        4: o = g;
+                        5: o = e;
+                        default: o = 1'b0;
+                    endcase
+        endcase
+        end
+endmodule
+
+module case_overlap (
+        input wire [2:0] x,
+        input wire a, b, c, d, e, f, g,
+        output reg o
+);
+        always @* begin
+            case (x)
+                //0, 2: o = b; // Creates $reduce_or
+                //0: o = b; 2: o = b; // Creates $reduce_or
+                0: o = b;
+                2: o = f;
+                1: o = c;
+                default:
+                    case (x)
+                        //3, 4: o = d; // Creates $reduce_or
+                        //3: o = d; 4: o = d; // Creates $reduce_or
+                        2: o = 1'b1; // Overlaps with previous $pmux
+                        3: o = d;
+                        4: o = g;
+                        5: o = e;
+                        default: o = 1'b0;
+                    endcase
+        endcase
+        end
+endmodule
diff --git a/tests/various/muxpack.ys b/tests/various/muxpack.ys
index 579dad8d3..ef8a6dab9 100644
--- a/tests/various/muxpack.ys
+++ b/tests/various/muxpack.ys
@@ -212,3 +212,33 @@ design -import gold -as gold
 design -import gate -as gate
 miter -equiv -flatten -make_assert -make_outputs gold gate miter
 sat -verify -prove-asserts -show-ports miter
+
+design -load read
+hierarchy -top case_nonoverlap
+prep
+design -save gold
+muxpack
+opt
+stat
+select -assert-count 0 t:$mux
+select -assert-count 1 t:$pmux
+design -stash gate
+design -import gold -as gold
+design -import gate -as gate
+miter -equiv -flatten -make_assert -make_outputs gold gate miter
+sat -verify -prove-asserts -show-ports miter
+
+design -load read
+hierarchy -top case_overlap
+prep
+design -save gold
+muxpack
+#opt # Do not opt otherwise $pmux's overlapping entry will get removed
+stat
+select -assert-count 0 t:$mux
+select -assert-count 1 t:$pmux
+design -stash gate
+design -import gold -as gold
+design -import gate -as gate
+miter -equiv -flatten -make_assert -make_outputs gold gate miter
+sat -verify -prove-asserts -show-ports miter
-- 
cgit v1.2.3


From ae8305ffcc0c812488163bcc35365d473ce1345d Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 21 Jun 2019 12:13:00 -0700
Subject: Fix testcase

---
 tests/various/muxpack.ys | 7 ++++---
 1 file changed, 4 insertions(+), 3 deletions(-)

(limited to 'tests')

diff --git a/tests/various/muxpack.ys b/tests/various/muxpack.ys
index ef8a6dab9..de5eec87f 100644
--- a/tests/various/muxpack.ys
+++ b/tests/various/muxpack.ys
@@ -230,13 +230,14 @@ sat -verify -prove-asserts -show-ports miter
 
 design -load read
 hierarchy -top case_overlap
-prep
+#prep # Do not prep otherwise $pmux's overlapping entry will get removed
+proc
 design -save gold
 muxpack
-#opt # Do not opt otherwise $pmux's overlapping entry will get removed
+opt
 stat
 select -assert-count 0 t:$mux
-select -assert-count 1 t:$pmux
+select -assert-count 2 t:$pmux
 design -stash gate
 design -import gold -as gold
 design -import gate -as gate
-- 
cgit v1.2.3


From 32f637ffdb0c0641b51227fad92bc80e284740d2 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 21 Jun 2019 12:31:04 -0700
Subject: Add more tests

---
 tests/various/muxpack.v  | 47 +++++++++++++++++++++++++++--------------------
 tests/various/muxpack.ys | 25 ++++++++++++++++++++++++-
 2 files changed, 51 insertions(+), 21 deletions(-)

(limited to 'tests')

diff --git a/tests/various/muxpack.v b/tests/various/muxpack.v
index 7a658d754..33ece1f16 100644
--- a/tests/various/muxpack.v
+++ b/tests/various/muxpack.v
@@ -187,7 +187,6 @@ module case_nonexclusive_select (
 );
         always @* begin
             case (x)
-                //0, 2: o = b;
                 0: o = b;
                 2: o = b;
                 1: o = c;
@@ -202,22 +201,16 @@ endmodule
 
 module case_nonoverlap (
         input wire [2:0] x,
-        input wire a, b, c, d, e, f, g,
+        input wire a, b, c, d, e,
         output reg o
 );
         always @* begin
             case (x)
-                //0, 2: o = b; // Creates $reduce_or
-                //0: o = b; 2: o = b; // Creates $reduce_or
-                0: o = b;
-                2: o = f;
+                0, 2: o = b; // Creates $reduce_or
                 1: o = c;
                 default:
                     case (x)
-                        //3, 4: o = d; // Creates $reduce_or
-                        //3: o = d; 4: o = d; // Creates $reduce_or
-                        3: o = d;
-                        4: o = g;
+                        3: o = d; 4: o = d; // Creates $reduce_or
                         5: o = e;
                         default: o = 1'b0;
                     endcase
@@ -227,23 +220,37 @@ endmodule
 
 module case_overlap (
         input wire [2:0] x,
-        input wire a, b, c, d, e, f, g,
+        input wire a, b, c, d, e,
         output reg o
 );
         always @* begin
             case (x)
-                //0, 2: o = b; // Creates $reduce_or
-                //0: o = b; 2: o = b; // Creates $reduce_or
-                0: o = b;
-                2: o = f;
+                0, 2: o = b; // Creates $reduce_or
+                1: o = c;
+                default:
+                    case (x)
+                        0: o = 1'b1; // OVERLAP!
+                        3, 4: o = d; // Creates $reduce_or
+                        5: o = e;
+                        default: o = 1'b0;
+                    endcase
+        endcase
+        end
+endmodule
+
+module case_overlap2 (
+        input wire [2:0] x,
+        input wire a, b, c, d, e,
+        output reg o
+);
+        always @* begin
+            case (x)
+                0: o = b; 2: o = b; // Creates $reduce_or
                 1: o = c;
                 default:
                     case (x)
-                        //3, 4: o = d; // Creates $reduce_or
-                        //3: o = d; 4: o = d; // Creates $reduce_or
-                        2: o = 1'b1; // Overlaps with previous $pmux
-                        3: o = d;
-                        4: o = g;
+                        0: o = d; 2: o = d; // Creates $reduce_or
+                        3: o = d; 4: o = d; // Creates $reduce_or
                         5: o = e;
                         default: o = 1'b0;
                     endcase
diff --git a/tests/various/muxpack.ys b/tests/various/muxpack.ys
index de5eec87f..af23fcec8 100644
--- a/tests/various/muxpack.ys
+++ b/tests/various/muxpack.ys
@@ -215,8 +215,11 @@ sat -verify -prove-asserts -show-ports miter
 
 design -load read
 hierarchy -top case_nonoverlap
-prep
+#prep # Do not prep otherwise $pmux's overlapping entry will get removed
+proc
 design -save gold
+opt -fast -mux_undef
+select -assert-count 2 t:$pmux
 muxpack
 opt
 stat
@@ -233,6 +236,26 @@ hierarchy -top case_overlap
 #prep # Do not prep otherwise $pmux's overlapping entry will get removed
 proc
 design -save gold
+opt -fast -mux_undef
+select -assert-count 2 t:$pmux
+muxpack
+opt
+stat
+select -assert-count 0 t:$mux
+select -assert-count 2 t:$pmux
+design -stash gate
+design -import gold -as gold
+design -import gate -as gate
+miter -equiv -flatten -make_assert -make_outputs gold gate miter
+sat -verify -prove-asserts -show-ports miter
+
+design -load read
+hierarchy -top case_overlap2
+#prep # Do not prep otherwise $pmux's overlapping entry will get removed
+proc
+design -save gold
+opt -fast -mux_undef
+select -assert-count 2 t:$pmux
 muxpack
 opt
 stat
-- 
cgit v1.2.3


From a701a2accf36abb6d0d1a90dc1811eb15708d5db Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Mon, 24 Jun 2019 18:32:58 -0700
Subject: Add test

---
 tests/memories/issue00710.v | 17 +++++++++++++++++
 tests/memories/run-test.sh  |  6 +++++-
 2 files changed, 22 insertions(+), 1 deletion(-)
 create mode 100644 tests/memories/issue00710.v

(limited to 'tests')

diff --git a/tests/memories/issue00710.v b/tests/memories/issue00710.v
new file mode 100644
index 000000000..7a5fad1c2
--- /dev/null
+++ b/tests/memories/issue00710.v
@@ -0,0 +1,17 @@
+// expect-wr-ports 1
+// expect-rd-ports 1
+// expect-rd-clk \clk
+
+module top(input clk, input we, re, reset, input [7:0] addr, wdata, output reg [7:0] rdata);
+
+reg [7:0] bram[0:255];
+(* keep *) reg dummy;
+
+always @(posedge clk)
+	if (reset)
+		dummy <= 1'b0;
+	else if (re)
+		rdata <= bram[addr];
+	else if (we)
+		bram[addr] <= wdata;
+endmodule
diff --git a/tests/memories/run-test.sh b/tests/memories/run-test.sh
index 734a96682..d0537bb98 100755
--- a/tests/memories/run-test.sh
+++ b/tests/memories/run-test.sh
@@ -14,7 +14,7 @@ shift "$((OPTIND-1))"
 
 bash ../tools/autotest.sh $seed -G *.v
 
-for f in `egrep -l 'expect-(wr|rd)-ports' *.v`; do
+for f in `egrep -l 'expect-(wr-ports|rd-ports|rd-clk)' *.v`; do
 	echo -n "Testing expectations for $f .."
 	../../yosys -qp "proc; opt; memory -nomap;; dump -outfile ${f%.v}.dmp t:\$mem" $f
 	if grep -q expect-wr-ports $f; then
@@ -25,6 +25,10 @@ for f in `egrep -l 'expect-(wr|rd)-ports' *.v`; do
 		grep -q "parameter \\\\RD_PORTS $(gawk '/expect-rd-ports/ { print $3; }' $f)\$" ${f%.v}.dmp ||
 				{ echo " ERROR: Unexpected number of read ports."; false; }
 	fi
+	if grep -q expect-rd-clk $f; then
+		grep -q "connect \\\\RD_CLK \\$(gawk '/expect-rd-clk/ { print $3; }' $f)\$" ${f%.v}.dmp ||
+				{ echo " ERROR: Unexpected read clock."; false; }
+	fi
 	echo " ok."
 done
 
-- 
cgit v1.2.3


From ab6e8ce0f00bc9fcf38dc62ae9de26405f7b59d7 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Tue, 25 Jun 2019 08:43:58 -0700
Subject: Add testcase from #335, fixed by #1130

---
 tests/memories/issue00335.v | 28 ++++++++++++++++++++++++++++
 1 file changed, 28 insertions(+)
 create mode 100644 tests/memories/issue00335.v

(limited to 'tests')

diff --git a/tests/memories/issue00335.v b/tests/memories/issue00335.v
new file mode 100644
index 000000000..f3b6e5dfe
--- /dev/null
+++ b/tests/memories/issue00335.v
@@ -0,0 +1,28 @@
+// expect-wr-ports 1
+// expect-rd-ports 1
+// expect-rd-clk \clk
+
+module ram2 (input clk,
+             input             sel,
+             input             we, 
+             input [SIZE-1:0]  adr, 
+             input [63:0]      dat_i, 
+             output reg [63:0] dat_o);
+   parameter  SIZE = 5; // Address size
+
+   reg [63:0] mem [0:(1 << SIZE)-1];
+   integer    i;
+
+   initial begin
+      for (i = 0; i < (1<<SIZE) - 1; i = i + 1)
+        mem[i] <= 0;
+   end
+   
+   always @(posedge clk)
+     if (sel) begin
+       if (~we)
+         dat_o <= mem[adr];
+       else
+         mem[adr] <= dat_i;
+     end
+endmodule
-- 
cgit v1.2.3