From 2b9c75f8e372f6886e073743d1df11bcd1c58281 Mon Sep 17 00:00:00 2001
From: Udi Finkelstein <github@udifink.com>
Date: Fri, 9 Mar 2018 10:35:33 +0200
Subject: This PR should be the base for discussion, do not merge it yet!

It correctly detects reg/wire mix and incorrect use on blocking,nonblocking assignments within blocks and assign statements.

What it DOES'T do:
Detect registers connected to output ports of instances.

Where it FAILS:
memorty nonblocking assignments causes spurious (I assume??) errors on yosys-generated "_ADDR", "_DATA", "EN" signals.

You can test it with tests/simple/reg_wire_error.v (look inside for the comments to enable/disable specific lines)
---
 tests/simple/reg_wire_error.v | 40 ++++++++++++++++++++++++++++++++++++++++
 1 file changed, 40 insertions(+)
 create mode 100644 tests/simple/reg_wire_error.v

(limited to 'tests')

diff --git a/tests/simple/reg_wire_error.v b/tests/simple/reg_wire_error.v
new file mode 100644
index 000000000..ab461b95a
--- /dev/null
+++ b/tests/simple/reg_wire_error.v
@@ -0,0 +1,40 @@
+module sub_mod(input i_in, output o_out);
+assign o_out = i_in;
+endmodule
+
+module test(i_clk, i_reg, o_reg, o_wire);
+input i_clk;
+input i_reg;
+output o_reg;
+output o_wire;
+
+// Enable this to see how it doesn't fail on yosys although it should
+//reg o_wire;
+// Enable this instead of the above to see how logic can be mapped to a wire
+logic o_wire;
+// Enable this to see how it doesn't fail on yosys although it should
+//reg i_reg;
+// Disable this to see how it doesn't fail on yosys although it should
+reg o_reg;
+
+logic l_reg;
+
+// Enable this to tst if logic-turne-reg will catch assignments even if done before it turned into a reg
+//assign l_reg = !o_reg;
+initial o_reg = 1'b0;
+always @(posedge i_clk)
+begin
+  o_reg <= !o_reg;
+  l_reg <= !o_reg;
+end
+
+assign o_wire = !o_reg;
+// Uncomment this to see how a logic already turned intoa reg can be freely assigned on yosys
+//assign l_reg = !o_reg;
+
+sub_mod sm_inst (
+  .i_in(1'b1),
+  .o_out(o_reg)
+);
+endmodule
+
-- 
cgit v1.2.3


From 80d9d15f1c4b73ee73172b06fd2c8c55703aea54 Mon Sep 17 00:00:00 2001
From: Udi Finkelstein <github@udifink.com>
Date: Tue, 5 Jun 2018 12:15:59 +0300
Subject: reg_wire_error test needs the -sv flag so it is run via a script so
 it had to be moved out of the tests/simple dir that only runs Verilog files

---
 tests/simple/reg_wire_error.v   | 40 ----------------------------------------
 tests/various/reg_wire_error.sv | 40 ++++++++++++++++++++++++++++++++++++++++
 tests/various/reg_wire_error.ys |  1 +
 3 files changed, 41 insertions(+), 40 deletions(-)
 delete mode 100644 tests/simple/reg_wire_error.v
 create mode 100644 tests/various/reg_wire_error.sv
 create mode 100644 tests/various/reg_wire_error.ys

(limited to 'tests')

diff --git a/tests/simple/reg_wire_error.v b/tests/simple/reg_wire_error.v
deleted file mode 100644
index ab461b95a..000000000
--- a/tests/simple/reg_wire_error.v
+++ /dev/null
@@ -1,40 +0,0 @@
-module sub_mod(input i_in, output o_out);
-assign o_out = i_in;
-endmodule
-
-module test(i_clk, i_reg, o_reg, o_wire);
-input i_clk;
-input i_reg;
-output o_reg;
-output o_wire;
-
-// Enable this to see how it doesn't fail on yosys although it should
-//reg o_wire;
-// Enable this instead of the above to see how logic can be mapped to a wire
-logic o_wire;
-// Enable this to see how it doesn't fail on yosys although it should
-//reg i_reg;
-// Disable this to see how it doesn't fail on yosys although it should
-reg o_reg;
-
-logic l_reg;
-
-// Enable this to tst if logic-turne-reg will catch assignments even if done before it turned into a reg
-//assign l_reg = !o_reg;
-initial o_reg = 1'b0;
-always @(posedge i_clk)
-begin
-  o_reg <= !o_reg;
-  l_reg <= !o_reg;
-end
-
-assign o_wire = !o_reg;
-// Uncomment this to see how a logic already turned intoa reg can be freely assigned on yosys
-//assign l_reg = !o_reg;
-
-sub_mod sm_inst (
-  .i_in(1'b1),
-  .o_out(o_reg)
-);
-endmodule
-
diff --git a/tests/various/reg_wire_error.sv b/tests/various/reg_wire_error.sv
new file mode 100644
index 000000000..ab461b95a
--- /dev/null
+++ b/tests/various/reg_wire_error.sv
@@ -0,0 +1,40 @@
+module sub_mod(input i_in, output o_out);
+assign o_out = i_in;
+endmodule
+
+module test(i_clk, i_reg, o_reg, o_wire);
+input i_clk;
+input i_reg;
+output o_reg;
+output o_wire;
+
+// Enable this to see how it doesn't fail on yosys although it should
+//reg o_wire;
+// Enable this instead of the above to see how logic can be mapped to a wire
+logic o_wire;
+// Enable this to see how it doesn't fail on yosys although it should
+//reg i_reg;
+// Disable this to see how it doesn't fail on yosys although it should
+reg o_reg;
+
+logic l_reg;
+
+// Enable this to tst if logic-turne-reg will catch assignments even if done before it turned into a reg
+//assign l_reg = !o_reg;
+initial o_reg = 1'b0;
+always @(posedge i_clk)
+begin
+  o_reg <= !o_reg;
+  l_reg <= !o_reg;
+end
+
+assign o_wire = !o_reg;
+// Uncomment this to see how a logic already turned intoa reg can be freely assigned on yosys
+//assign l_reg = !o_reg;
+
+sub_mod sm_inst (
+  .i_in(1'b1),
+  .o_out(o_reg)
+);
+endmodule
+
diff --git a/tests/various/reg_wire_error.ys b/tests/various/reg_wire_error.ys
new file mode 100644
index 000000000..b9d03155d
--- /dev/null
+++ b/tests/various/reg_wire_error.ys
@@ -0,0 +1 @@
+read_verilog -sv reg_wire_error.sv
-- 
cgit v1.2.3


From 73d426bc879087ca522ca595a8ba921b647fae27 Mon Sep 17 00:00:00 2001
From: Udi Finkelstein <github@udifink.com>
Date: Tue, 5 Jun 2018 17:44:24 +0300
Subject: Modified errors into warnings No longer false warnings for memories
 and assertions

---
 tests/various/reg_wire_error.sv | 42 +++++++++++++++++++++++++++++++++++++----
 1 file changed, 38 insertions(+), 4 deletions(-)

(limited to 'tests')

diff --git a/tests/various/reg_wire_error.sv b/tests/various/reg_wire_error.sv
index ab461b95a..fe5ff3abd 100644
--- a/tests/various/reg_wire_error.sv
+++ b/tests/various/reg_wire_error.sv
@@ -2,11 +2,13 @@ module sub_mod(input i_in, output o_out);
 assign o_out = i_in;
 endmodule
 
-module test(i_clk, i_reg, o_reg, o_wire);
+module test(i_clk, i, i_reg, o_reg, o_wire, o_mr, o_mw, o_ml);
 input i_clk;
+input i;
 input i_reg;
 output o_reg;
 output o_wire;
+output o_mr, o_mw, o_ml;
 
 // Enable this to see how it doesn't fail on yosys although it should
 //reg o_wire;
@@ -15,12 +17,12 @@ logic o_wire;
 // Enable this to see how it doesn't fail on yosys although it should
 //reg i_reg;
 // Disable this to see how it doesn't fail on yosys although it should
-reg o_reg;
+//reg o_reg;
 
 logic l_reg;
 
 // Enable this to tst if logic-turne-reg will catch assignments even if done before it turned into a reg
-//assign l_reg = !o_reg;
+assign l_reg = !o_reg;
 initial o_reg = 1'b0;
 always @(posedge i_clk)
 begin
@@ -30,11 +32,43 @@ end
 
 assign o_wire = !o_reg;
 // Uncomment this to see how a logic already turned intoa reg can be freely assigned on yosys
-//assign l_reg = !o_reg;
+assign l_reg = !o_reg;
 
 sub_mod sm_inst (
   .i_in(1'b1),
   .o_out(o_reg)
 );
+
+wire   mw1[0:1];
+wire   mw2[0:1];
+wire   mw3[0:1];
+reg    mr1[0:1];
+reg    mr2[0:1];
+reg    mr3[0:1];
+logic  ml1[0:1];
+logic  ml2[0:1];
+logic  ml3[0:1];
+
+assign o_mw = mw1[i];
+assign o_mr = mr1[i];
+assign o_ml = ml1[i];
+
+assign mw1[1] = 1'b1;
+//assign mr1[1] = 1'b1;
+assign ml1[1] = 1'b1;
+always @(posedge i_clk)
+begin
+  mr2[0] = 1'b0;
+  mw2[0] = 1'b0;
+  ml2[0] = 1'b0;
+end
+
+always @(posedge i_clk)
+begin
+  mr3[0] <= 1'b0;
+  mw3[0] <= 1'b0;
+  ml3[0] <= 1'b0;
+end
+
 endmodule
 
-- 
cgit v1.2.3


From 75009ada3c2a4bcd38c52c8fb871c9e8c1f2e6b1 Mon Sep 17 00:00:00 2001
From: Ruben Undheim <ruben.undheim@gmail.com>
Date: Thu, 11 Oct 2018 23:33:31 +0200
Subject: Synthesis support for SystemVerilog interfaces

This time doing the changes mostly in AST before RTLIL generation
---
 tests/simple/svinterface1.sv | 76 ++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 76 insertions(+)
 create mode 100644 tests/simple/svinterface1.sv

(limited to 'tests')

diff --git a/tests/simple/svinterface1.sv b/tests/simple/svinterface1.sv
new file mode 100644
index 000000000..779d50c14
--- /dev/null
+++ b/tests/simple/svinterface1.sv
@@ -0,0 +1,76 @@
+
+
+module TopModule(
+    input logic clk,
+    input logic rst,
+    input logic [1:0] sig,
+    output logic [1:0] sig_out);
+
+  MyInterface #(.WIDTH(4)) MyInterfaceInstance();
+
+  SubModule1 u_SubModule1 (
+    .clk(clk),
+    .rst(rst),
+    .u_MyInterface(MyInterfaceInstance),
+    .sig (sig)
+  );
+
+  assign sig_out = MyInterfaceInstance.mysig_out;
+
+
+  assign MyInterfaceInstance.setting = 1;
+  assign MyInterfaceInstance.other_setting[2:0] = 3'b101;
+
+endmodule
+
+interface MyInterface #(
+  parameter WIDTH = 3)(
+  );
+
+  logic setting;
+  logic [WIDTH-1:0] other_setting;
+
+  logic [1:0] mysig_out;
+
+endinterface
+
+
+module SubModule1(
+    input logic clk,
+    input logic rst,
+    MyInterface u_MyInterface,
+    input logic [1:0] sig
+
+  );
+
+  always_ff @(posedge clk or posedge rst)
+    if(rst)
+      u_MyInterface.mysig_out <= 0;
+    else begin
+      if(u_MyInterface.setting)
+        u_MyInterface.mysig_out <= sig;
+      else
+        u_MyInterface.mysig_out <= ~sig;
+    end
+
+  MyInterface #(.WIDTH(22)) MyInterfaceInstanceInSub();
+
+  SubModule2 u_SubModule2 (
+    .clk(clk),
+    .rst(rst),
+    .u_MyInterfaceInSub2(u_MyInterface),
+    .sig (sig)
+  );
+
+endmodule
+
+module SubModule2(
+
+    input logic clk,
+    input logic rst,
+    MyInterface u_MyInterfaceInSub2,
+    input logic [1:0] sig
+
+  );
+
+endmodule
-- 
cgit v1.2.3


From 458a94059e6738d93a87ddb9af282d0e1d28791d Mon Sep 17 00:00:00 2001
From: Ruben Undheim <ruben.undheim@gmail.com>
Date: Fri, 12 Oct 2018 20:58:37 +0200
Subject: Support for 'modports' for System Verilog interfaces

---
 tests/simple/svinterface1.sv | 20 +++++++++++++++++---
 1 file changed, 17 insertions(+), 3 deletions(-)

(limited to 'tests')

diff --git a/tests/simple/svinterface1.sv b/tests/simple/svinterface1.sv
index 779d50c14..64383a06c 100644
--- a/tests/simple/svinterface1.sv
+++ b/tests/simple/svinterface1.sv
@@ -19,7 +19,7 @@ module TopModule(
 
 
   assign MyInterfaceInstance.setting = 1;
-  assign MyInterfaceInstance.other_setting[2:0] = 3'b101;
+//  assign MyInterfaceInstance.other_setting[2:0] = 3'b101;
 
 endmodule
 
@@ -32,13 +32,25 @@ interface MyInterface #(
 
   logic [1:0] mysig_out;
 
+    modport submodule1 (
+        input  setting,
+        output other_setting,
+        output mysig_out
+    );
+
+    modport submodule2 (
+        input  setting,
+        output other_setting,
+        input  mysig_out
+    );
+
 endinterface
 
 
 module SubModule1(
     input logic clk,
     input logic rst,
-    MyInterface u_MyInterface,
+    MyInterface.submodule1 u_MyInterface,
     input logic [1:0] sig
 
   );
@@ -68,9 +80,11 @@ module SubModule2(
 
     input logic clk,
     input logic rst,
-    MyInterface u_MyInterfaceInSub2,
+    MyInterface.submodule2 u_MyInterfaceInSub2,
     input logic [1:0] sig
 
   );
 
+   assign u_MyInterfaceInSub2.other_setting[2:0] = 9;
+
 endmodule
-- 
cgit v1.2.3


From d5aac2650f9169b2b890854083c5502b84adf115 Mon Sep 17 00:00:00 2001
From: Ruben Undheim <ruben.undheim@gmail.com>
Date: Thu, 18 Oct 2018 21:27:04 +0200
Subject: Basic test for checking correct synthesis of SystemVerilog interfaces

---
 tests/simple/svinterface1.sv          |  90 --------------------------
 tests/svinterfaces/run-test.sh        |   5 ++
 tests/svinterfaces/runone.sh          |  41 ++++++++++++
 tests/svinterfaces/svinterface1.sv    | 117 ++++++++++++++++++++++++++++++++++
 tests/svinterfaces/svinterface1_ref.v | 107 +++++++++++++++++++++++++++++++
 tests/svinterfaces/svinterface1_tb.v  |  57 +++++++++++++++++
 6 files changed, 327 insertions(+), 90 deletions(-)
 delete mode 100644 tests/simple/svinterface1.sv
 create mode 100755 tests/svinterfaces/run-test.sh
 create mode 100755 tests/svinterfaces/runone.sh
 create mode 100644 tests/svinterfaces/svinterface1.sv
 create mode 100644 tests/svinterfaces/svinterface1_ref.v
 create mode 100644 tests/svinterfaces/svinterface1_tb.v

(limited to 'tests')

diff --git a/tests/simple/svinterface1.sv b/tests/simple/svinterface1.sv
deleted file mode 100644
index 64383a06c..000000000
--- a/tests/simple/svinterface1.sv
+++ /dev/null
@@ -1,90 +0,0 @@
-
-
-module TopModule(
-    input logic clk,
-    input logic rst,
-    input logic [1:0] sig,
-    output logic [1:0] sig_out);
-
-  MyInterface #(.WIDTH(4)) MyInterfaceInstance();
-
-  SubModule1 u_SubModule1 (
-    .clk(clk),
-    .rst(rst),
-    .u_MyInterface(MyInterfaceInstance),
-    .sig (sig)
-  );
-
-  assign sig_out = MyInterfaceInstance.mysig_out;
-
-
-  assign MyInterfaceInstance.setting = 1;
-//  assign MyInterfaceInstance.other_setting[2:0] = 3'b101;
-
-endmodule
-
-interface MyInterface #(
-  parameter WIDTH = 3)(
-  );
-
-  logic setting;
-  logic [WIDTH-1:0] other_setting;
-
-  logic [1:0] mysig_out;
-
-    modport submodule1 (
-        input  setting,
-        output other_setting,
-        output mysig_out
-    );
-
-    modport submodule2 (
-        input  setting,
-        output other_setting,
-        input  mysig_out
-    );
-
-endinterface
-
-
-module SubModule1(
-    input logic clk,
-    input logic rst,
-    MyInterface.submodule1 u_MyInterface,
-    input logic [1:0] sig
-
-  );
-
-  always_ff @(posedge clk or posedge rst)
-    if(rst)
-      u_MyInterface.mysig_out <= 0;
-    else begin
-      if(u_MyInterface.setting)
-        u_MyInterface.mysig_out <= sig;
-      else
-        u_MyInterface.mysig_out <= ~sig;
-    end
-
-  MyInterface #(.WIDTH(22)) MyInterfaceInstanceInSub();
-
-  SubModule2 u_SubModule2 (
-    .clk(clk),
-    .rst(rst),
-    .u_MyInterfaceInSub2(u_MyInterface),
-    .sig (sig)
-  );
-
-endmodule
-
-module SubModule2(
-
-    input logic clk,
-    input logic rst,
-    MyInterface.submodule2 u_MyInterfaceInSub2,
-    input logic [1:0] sig
-
-  );
-
-   assign u_MyInterfaceInSub2.other_setting[2:0] = 9;
-
-endmodule
diff --git a/tests/svinterfaces/run-test.sh b/tests/svinterfaces/run-test.sh
new file mode 100755
index 000000000..1630859bd
--- /dev/null
+++ b/tests/svinterfaces/run-test.sh
@@ -0,0 +1,5 @@
+#/bin/bash -e
+
+
+
+./runone.sh  svinterface1
diff --git a/tests/svinterfaces/runone.sh b/tests/svinterfaces/runone.sh
new file mode 100755
index 000000000..345801389
--- /dev/null
+++ b/tests/svinterfaces/runone.sh
@@ -0,0 +1,41 @@
+#!/bin/bash
+
+
+TESTNAME=$1
+
+STDOUTFILE=${TESTNAME}.log_stdout
+STDERRFILE=${TESTNAME}.log_stderr
+
+echo "" > $STDOUTFILE
+echo "" > $STDERRFILE
+
+echo -n "Test: ${TESTNAME} -> "
+
+$PWD/../../yosys -p "read_verilog -sv ${TESTNAME}.sv ; hierarchy -check -top TopModule ; synth ; write_verilog ${TESTNAME}_syn.v" >> $STDOUTFILE >> $STDERRFILE
+$PWD/../../yosys -p "read_verilog -sv ${TESTNAME}_ref.v ; hierarchy -check -top TopModule ; synth ; write_verilog ${TESTNAME}_ref_syn.v" >> $STDOUTFILE >> $STDERRFILE
+
+rm -f a.out reference_result.txt dut_result.txt
+
+set -e
+
+iverilog -g2012 ${TESTNAME}_syn.v
+iverilog -g2012 ${TESTNAME}_ref_syn.v
+
+set +e
+
+iverilog -g2012 ${TESTNAME}_tb.v ${TESTNAME}_ref_syn.v
+./a.out
+mv output.txt reference_result.txt
+iverilog -g2012 ${TESTNAME}_tb.v ${TESTNAME}_syn.v
+./a.out
+mv output.txt dut_result.txt
+
+diff reference_result.txt dut_result.txt > ${TESTNAME}.diff
+RET=$?
+if [ "$RET" != "0" ] ; then
+    echo "ERROR!"
+    exit -1
+fi
+
+echo "ok"
+exit 0
diff --git a/tests/svinterfaces/svinterface1.sv b/tests/svinterfaces/svinterface1.sv
new file mode 100644
index 000000000..6d60b4880
--- /dev/null
+++ b/tests/svinterfaces/svinterface1.sv
@@ -0,0 +1,117 @@
+
+
+module TopModule(
+    input logic clk,
+    input logic rst,
+    output logic [21:0] outOther,
+    input logic [1:0] sig,
+    input logic flip,
+    output logic [1:0] sig_out,
+    output logic [15:0] passThrough);
+
+  MyInterface #(.WIDTH(4)) MyInterfaceInstance();
+
+  SubModule1 u_SubModule1 (
+    .clk(clk),
+    .rst(rst),
+    .u_MyInterface(MyInterfaceInstance),
+    .outOther(outOther),
+    .sig (sig)
+  );
+
+  assign sig_out = MyInterfaceInstance.mysig_out;
+
+
+  assign MyInterfaceInstance.setting = flip;
+
+  assign passThrough = MyInterfaceInstance.passThrough;
+
+endmodule
+
+interface MyInterface #(
+  parameter WIDTH = 3)(
+  );
+
+  logic setting;
+  logic [WIDTH-1:0] other_setting;
+
+  logic [1:0] mysig_out;
+
+  logic [15:0] passThrough;
+
+    modport submodule1 (
+        input  setting,
+        output other_setting,
+        output mysig_out,
+        output passThrough
+    );
+
+    modport submodule2 (
+        input  setting,
+        output other_setting,
+        input  mysig_out,
+        output passThrough
+    );
+
+endinterface
+
+
+module SubModule1(
+    input logic clk,
+    input logic rst,
+    MyInterface.submodule1 u_MyInterface,
+    input logic [1:0] sig,
+    output logic [21:0] outOther
+
+  );
+
+  always_ff @(posedge clk or posedge rst)
+    if(rst)
+      u_MyInterface.mysig_out <= 0;
+    else begin
+      if(u_MyInterface.setting)
+        u_MyInterface.mysig_out <= sig;
+      else
+        u_MyInterface.mysig_out <= ~sig;
+    end
+
+  MyInterface #(.WIDTH(22)) MyInterfaceInstanceInSub();
+
+  SubModule2 u_SubModule2 (
+    .clk(clk),
+    .rst(rst),
+    .u_MyInterfaceInSub2(u_MyInterface),
+    .u_MyInterfaceInSub3(MyInterfaceInstanceInSub)
+  );
+
+    assign outOther = MyInterfaceInstanceInSub.other_setting;
+
+    assign MyInterfaceInstanceInSub.setting = 0;
+    assign MyInterfaceInstanceInSub.mysig_out = sig;
+
+endmodule
+
+module SubModule2(
+
+    input logic clk,
+    input logic rst,
+    MyInterface.submodule2 u_MyInterfaceInSub2,
+    MyInterface.submodule2 u_MyInterfaceInSub3
+
+  );
+
+   always_comb begin
+      if (u_MyInterfaceInSub3.mysig_out == 2'b00)
+        u_MyInterfaceInSub3.other_setting[21:0] = 1000;
+      else if (u_MyInterfaceInSub3.mysig_out == 2'b01)
+        u_MyInterfaceInSub3.other_setting[21:0] = 2000;
+      else if (u_MyInterfaceInSub3.mysig_out == 2'b10)
+        u_MyInterfaceInSub3.other_setting[21:0] = 3000;
+      else
+        u_MyInterfaceInSub3.other_setting[21:0] = 4000;
+   end
+
+    assign u_MyInterfaceInSub2.passThrough[7:0] = 124;
+    assign u_MyInterfaceInSub2.passThrough[15:8] = 200;
+
+endmodule
diff --git a/tests/svinterfaces/svinterface1_ref.v b/tests/svinterfaces/svinterface1_ref.v
new file mode 100644
index 000000000..b119f4037
--- /dev/null
+++ b/tests/svinterfaces/svinterface1_ref.v
@@ -0,0 +1,107 @@
+
+module TopModule(
+    input logic clk,
+    input logic rst,
+    input logic [1:0] sig,
+    input logic flip,
+    output logic [15:0] passThrough,
+    output logic [21:0] outOther,
+    output logic [1:0] sig_out);
+
+
+    logic MyInterfaceInstance_setting;
+    logic [3:0] MyInterfaceInstance_other_setting;
+    logic [1:0] MyInterfaceInstance_mysig_out;
+
+  SubModule1 u_SubModule1 (
+    .clk(clk),
+    .rst(rst),
+    .u_MyInterface_setting(MyInterfaceInstance_setting),
+    .u_MyInterface_mysig_out(MyInterfaceInstance_mysig_out),
+    .u_MyInterface_other_setting(MyInterfaceInstance_other_setting),
+    .outOther(outOther),
+    .passThrough (passThrough),
+    .sig (sig)
+  );
+
+  assign sig_out = MyInterfaceInstance_mysig_out;
+
+
+  assign MyInterfaceInstance_setting = flip;
+
+endmodule
+
+
+module SubModule1(
+    input logic clk,
+    input logic rst,
+    input logic u_MyInterface_setting,
+    output logic [3:0] u_MyInterface_other_setting,
+    output logic [1:0] u_MyInterface_mysig_out,
+    output logic [21:0] outOther,
+    input logic [1:0] sig,
+    output logic [15:0] passThrough
+  );
+
+  always @(posedge clk or posedge rst)
+    if(rst)
+      u_MyInterface_mysig_out <= 0;
+    else begin
+      if(u_MyInterface_setting)
+        u_MyInterface_mysig_out <= sig;
+      else
+        u_MyInterface_mysig_out <= ~sig;
+    end
+
+    logic MyInterfaceInstanceInSub_setting;
+    logic [21:0] MyInterfaceInstanceInSub_other_setting;
+    logic [1:0] MyInterfaceInstanceInSub_mysig_out;
+
+
+  SubModule2 u_SubModule2 (
+    .clk(clk),
+    .rst(rst),
+    .u_MyInterfaceInSub2_setting(u_MyInterface_setting),
+    .u_MyInterfaceInSub2_mysig_out(u_MyInterface_mysig_out),
+    .u_MyInterfaceInSub2_other_setting(u_MyInterface_other_setting),
+    .u_MyInterfaceInSub3_setting(MyInterfaceInstanceInSub_setting),
+    .u_MyInterfaceInSub3_mysig_out(MyInterfaceInstanceInSub_mysig_out),
+    .u_MyInterfaceInSub3_other_setting(MyInterfaceInstanceInSub_other_setting),
+    .passThrough (passThrough)
+  );
+    assign outOther = MyInterfaceInstanceInSub_other_setting;
+
+    assign MyInterfaceInstanceInSub_setting = 0;
+    assign MyInterfaceInstanceInSub_mysig_out = sig;
+
+endmodule
+
+module SubModule2(
+
+    input logic clk,
+    input logic rst,
+    input logic u_MyInterfaceInSub2_setting,
+    output logic [3:0] u_MyInterfaceInSub2_other_setting,
+    input  logic [1:0] u_MyInterfaceInSub2_mysig_out,
+    input logic u_MyInterfaceInSub3_setting,
+    output logic [21:0] u_MyInterfaceInSub3_other_setting,
+    input  logic [1:0] u_MyInterfaceInSub3_mysig_out,
+    output logic [15:0] passThrough
+
+  );
+
+    always @(u_MyInterfaceInSub3_mysig_out) begin
+      if (u_MyInterfaceInSub3_mysig_out == 2'b00)
+        u_MyInterfaceInSub3_other_setting[21:0] = 1000;
+      else if (u_MyInterfaceInSub3_mysig_out == 2'b01)
+        u_MyInterfaceInSub3_other_setting[21:0] = 2000;
+      else if (u_MyInterfaceInSub3_mysig_out == 2'b10)
+        u_MyInterfaceInSub3_other_setting[21:0] = 3000;
+      else
+        u_MyInterfaceInSub3_other_setting[21:0] = 4000;
+    end
+
+    assign passThrough[7:0] = 124;
+    assign passThrough[15:8] = 200;
+
+endmodule
diff --git a/tests/svinterfaces/svinterface1_tb.v b/tests/svinterfaces/svinterface1_tb.v
new file mode 100644
index 000000000..44c3b5f68
--- /dev/null
+++ b/tests/svinterfaces/svinterface1_tb.v
@@ -0,0 +1,57 @@
+`timescale 1ns/10ps
+
+module svinterface1_tb;
+
+
+  logic clk;
+  logic rst;
+  logic [21:0] outOther;
+  logic [1:0] sig;
+  logic [1:0] sig_out;
+  logic flip;
+  logic [15:0] passThrough;
+  integer outfile;
+
+  TopModule u_dut (
+    .clk(clk),
+    .rst(rst),
+    .outOther(outOther),
+    .sig(sig),
+    .flip(flip),
+    .passThrough(passThrough),
+    .sig_out(sig_out)
+  );
+
+  initial begin
+    clk = 0;
+    while(1) begin
+      clk = ~clk;
+      #50;
+    end
+  end
+
+  initial begin
+    outfile = $fopen("output.txt");
+    rst = 1;
+    sig = 0;
+    flip = 0;
+    @(posedge clk);
+    #(2);
+    rst = 0;
+    @(posedge clk);
+    for(int j=0;j<2;j++) begin
+      for(int i=0;i<20;i++) begin
+        #(2);
+        flip = j;
+        sig = i;
+        @(posedge clk);
+      end
+    end
+    $finish;
+  end
+
+  always @(negedge clk) begin
+    $fdisplay(outfile, "%d %d %d", outOther, sig_out, passThrough);
+  end
+
+endmodule
-- 
cgit v1.2.3


From 397dfccb304a12a40d34c4454a5cb4acee8be75f Mon Sep 17 00:00:00 2001
From: Ruben Undheim <ruben.undheim@gmail.com>
Date: Sat, 20 Oct 2018 11:58:25 +0200
Subject: Support for SystemVerilog interfaces as a port in the top level
 module + test case

---
 tests/svinterfaces/run-test.sh                     |   1 +
 tests/svinterfaces/runone.sh                       |   7 +-
 tests/svinterfaces/svinterface_at_top.sv           | 125 +++++++++++++++++++++
 tests/svinterfaces/svinterface_at_top_ref.v        | 120 ++++++++++++++++++++
 tests/svinterfaces/svinterface_at_top_tb.v         |  68 +++++++++++
 tests/svinterfaces/svinterface_at_top_tb_wrapper.v |  68 +++++++++++
 tests/svinterfaces/svinterface_at_top_wrapper.v    |  33 ++++++
 7 files changed, 420 insertions(+), 2 deletions(-)
 create mode 100644 tests/svinterfaces/svinterface_at_top.sv
 create mode 100644 tests/svinterfaces/svinterface_at_top_ref.v
 create mode 100644 tests/svinterfaces/svinterface_at_top_tb.v
 create mode 100644 tests/svinterfaces/svinterface_at_top_tb_wrapper.v
 create mode 100644 tests/svinterfaces/svinterface_at_top_wrapper.v

(limited to 'tests')

diff --git a/tests/svinterfaces/run-test.sh b/tests/svinterfaces/run-test.sh
index 1630859bd..86567d1c1 100755
--- a/tests/svinterfaces/run-test.sh
+++ b/tests/svinterfaces/run-test.sh
@@ -3,3 +3,4 @@
 
 
 ./runone.sh  svinterface1
+./runone.sh  svinterface_at_top
diff --git a/tests/svinterfaces/runone.sh b/tests/svinterfaces/runone.sh
index 345801389..0adecc797 100755
--- a/tests/svinterfaces/runone.sh
+++ b/tests/svinterfaces/runone.sh
@@ -22,11 +22,14 @@ iverilog -g2012 ${TESTNAME}_syn.v
 iverilog -g2012 ${TESTNAME}_ref_syn.v
 
 set +e
-
 iverilog -g2012 ${TESTNAME}_tb.v ${TESTNAME}_ref_syn.v
 ./a.out
 mv output.txt reference_result.txt
-iverilog -g2012 ${TESTNAME}_tb.v ${TESTNAME}_syn.v
+if [ -f ${TESTNAME}_wrapper.v ] ; then
+    iverilog -g2012 ${TESTNAME}_tb_wrapper.v ${TESTNAME}_syn.v
+else
+    iverilog -g2012 ${TESTNAME}_tb.v ${TESTNAME}_syn.v
+fi
 ./a.out
 mv output.txt dut_result.txt
 
diff --git a/tests/svinterfaces/svinterface_at_top.sv b/tests/svinterfaces/svinterface_at_top.sv
new file mode 100644
index 000000000..b5aa8c8f5
--- /dev/null
+++ b/tests/svinterfaces/svinterface_at_top.sv
@@ -0,0 +1,125 @@
+
+
+module TopModule(
+    input logic clk,
+    input logic rst,
+    output logic [21:0] outOther,
+    input logic [1:0] sig,
+    input logic flip,
+    output logic [1:0] sig_out,
+    MyInterface.submodule1 interfaceInstanceAtTop,
+    output logic [15:0] passThrough);
+
+  MyInterface #(.WIDTH(4)) MyInterfaceInstance();
+
+  SubModule1 u_SubModule1 (
+    .clk(clk),
+    .rst(rst),
+    .u_MyInterface(MyInterfaceInstance),
+    .u_MyInterfaceFromTop(interfaceInstanceAtTop),
+    .outOther(outOther),
+    .sig (sig)
+  );
+
+  assign sig_out = MyInterfaceInstance.mysig_out;
+
+
+  assign MyInterfaceInstance.setting = flip;
+
+  assign passThrough = MyInterfaceInstance.passThrough;
+
+endmodule
+
+interface MyInterface #(
+  parameter WIDTH = 3)(
+  );
+
+  logic setting;
+  logic [WIDTH-1:0] other_setting;
+
+  logic [1:0] mysig_out;
+
+  logic [15:0] passThrough;
+
+    modport submodule1 (
+        input  setting,
+        output other_setting,
+        output mysig_out,
+        output passThrough
+    );
+
+    modport submodule2 (
+        input  setting,
+        output other_setting,
+        input  mysig_out,
+        output passThrough
+    );
+
+endinterface
+
+
+module SubModule1(
+    input logic clk,
+    input logic rst,
+    MyInterface.submodule1 u_MyInterface,
+    MyInterface.submodule1 u_MyInterfaceFromTop,
+    input logic [1:0] sig,
+    output logic [21:0] outOther
+
+  );
+
+
+  always_ff @(posedge clk or posedge rst)
+    if(rst)
+      u_MyInterface.mysig_out <= 0;
+    else begin
+      if(u_MyInterface.setting)
+        u_MyInterface.mysig_out <= sig;
+      else
+        u_MyInterface.mysig_out <= ~sig;
+    end
+
+  MyInterface #(.WIDTH(22)) MyInterfaceInstanceInSub();
+
+  SubModule2 u_SubModule2 (
+    .clk(clk),
+    .rst(rst),
+    .u_MyInterfaceFromTopDown(u_MyInterfaceFromTop),
+    .u_MyInterfaceInSub2(u_MyInterface),
+    .u_MyInterfaceInSub3(MyInterfaceInstanceInSub)
+  );
+
+    assign outOther = MyInterfaceInstanceInSub.other_setting;
+
+    assign MyInterfaceInstanceInSub.setting = 0;
+    assign MyInterfaceInstanceInSub.mysig_out = sig;
+
+endmodule
+
+module SubModule2(
+
+    input logic clk,
+    input logic rst,
+    MyInterface.submodule2 u_MyInterfaceInSub2,
+    MyInterface.submodule1 u_MyInterfaceFromTopDown,
+    MyInterface.submodule2 u_MyInterfaceInSub3
+
+  );
+
+  assign u_MyInterfaceFromTopDown.mysig_out = u_MyInterfaceFromTop.setting ? 10 :  20;
+
+   always_comb begin
+      if (u_MyInterfaceInSub3.mysig_out == 2'b00)
+        u_MyInterfaceInSub3.other_setting[21:0] = 1000;
+      else if (u_MyInterfaceInSub3.mysig_out == 2'b01)
+        u_MyInterfaceInSub3.other_setting[21:0] = 2000;
+      else if (u_MyInterfaceInSub3.mysig_out == 2'b10)
+        u_MyInterfaceInSub3.other_setting[21:0] = 3000;
+      else
+        u_MyInterfaceInSub3.other_setting[21:0] = 4000;
+   end
+
+    assign u_MyInterfaceInSub2.passThrough[7:0] = 124;
+    assign u_MyInterfaceInSub2.passThrough[15:8] = 200;
+
+endmodule
diff --git a/tests/svinterfaces/svinterface_at_top_ref.v b/tests/svinterfaces/svinterface_at_top_ref.v
new file mode 100644
index 000000000..7b54a26d6
--- /dev/null
+++ b/tests/svinterfaces/svinterface_at_top_ref.v
@@ -0,0 +1,120 @@
+
+module TopModule(
+    input logic clk,
+    input logic rst,
+    input logic [1:0] sig,
+    input logic flip,
+    output logic [15:0] passThrough,
+    output logic [21:0] outOther,
+    input logic interfaceInstanceAtTop_setting,
+    output logic [2:0] interfaceInstanceAtTop_other_setting,
+    output logic [1:0] interfaceInstanceAtTop_mysig_out,
+    output logic [15:0] interfaceInstanceAtTop_passThrough,
+    output logic [1:0] sig_out);
+
+
+    logic MyInterfaceInstance_setting;
+    logic [3:0] MyInterfaceInstance_other_setting;
+    logic [1:0] MyInterfaceInstance_mysig_out;
+
+  SubModule1 u_SubModule1 (
+    .clk(clk),
+    .rst(rst),
+    .u_MyInterface_setting(MyInterfaceInstance_setting),
+    .u_MyInterface_mysig_out(MyInterfaceInstance_mysig_out),
+    .u_MyInterface_other_setting(MyInterfaceInstance_other_setting),
+    .u_MyInterfaceFromTop_setting(interfaceInstanceAtTop_setting),
+    .u_MyInterfaceFromTop_other_setting(interfaceInstanceAtTop_other_setting),
+    .u_MyInterfaceFromTop_mysig_out(interfaceInstanceAtTop_mysig_out),
+    .u_MyInterfaceFromTop_passThrough(interfaceInstanceAtTop_passThrough),
+    .outOther(outOther),
+    .passThrough (passThrough),
+    .sig (sig)
+  );
+
+  assign sig_out = MyInterfaceInstance_mysig_out;
+
+
+  assign MyInterfaceInstance_setting = flip;
+
+endmodule
+
+
+module SubModule1(
+    input logic clk,
+    input logic rst,
+    input logic u_MyInterface_setting,
+    output logic [3:0] u_MyInterface_other_setting,
+    output logic [1:0] u_MyInterface_mysig_out,
+    output logic [21:0] outOther,
+    input logic [1:0] sig,
+    input logic u_MyInterfaceFromTop_setting,
+    output logic [2:0]  u_MyInterfaceFromTop_other_setting,
+    output logic [1:0]  u_MyInterfaceFromTop_mysig_out,
+    output logic [14:0] u_MyInterfaceFromTop_passThrough,
+    output logic [15:0] passThrough
+  );
+
+  always @(posedge clk or posedge rst)
+    if(rst)
+      u_MyInterface_mysig_out <= 0;
+    else begin
+      if(u_MyInterface_setting)
+        u_MyInterface_mysig_out <= sig;
+      else
+        u_MyInterface_mysig_out <= ~sig;
+    end
+
+    logic MyInterfaceInstanceInSub_setting;
+    logic [21:0] MyInterfaceInstanceInSub_other_setting;
+    logic [1:0] MyInterfaceInstanceInSub_mysig_out;
+
+  assign u_MyInterfaceFromTop_mysig_out = u_MyInterfaceFromTop_setting ? 10 :  20;
+
+  SubModule2 u_SubModule2 (
+    .clk(clk),
+    .rst(rst),
+    .u_MyInterfaceInSub2_setting(u_MyInterface_setting),
+    .u_MyInterfaceInSub2_mysig_out(u_MyInterface_mysig_out),
+    .u_MyInterfaceInSub2_other_setting(u_MyInterface_other_setting),
+    .u_MyInterfaceInSub3_setting(MyInterfaceInstanceInSub_setting),
+    .u_MyInterfaceInSub3_mysig_out(MyInterfaceInstanceInSub_mysig_out),
+    .u_MyInterfaceInSub3_other_setting(MyInterfaceInstanceInSub_other_setting),
+    .passThrough (passThrough)
+  );
+    assign outOther = MyInterfaceInstanceInSub_other_setting;
+
+    assign MyInterfaceInstanceInSub_setting = 0;
+    assign MyInterfaceInstanceInSub_mysig_out = sig;
+
+endmodule
+
+module SubModule2(
+
+    input logic clk,
+    input logic rst,
+    input logic u_MyInterfaceInSub2_setting,
+    output logic [3:0] u_MyInterfaceInSub2_other_setting,
+    input  logic [1:0] u_MyInterfaceInSub2_mysig_out,
+    input logic u_MyInterfaceInSub3_setting,
+    output logic [21:0] u_MyInterfaceInSub3_other_setting,
+    input  logic [1:0] u_MyInterfaceInSub3_mysig_out,
+    output logic [15:0] passThrough
+
+  );
+
+    always @(u_MyInterfaceInSub3_mysig_out) begin
+      if (u_MyInterfaceInSub3_mysig_out == 2'b00)
+        u_MyInterfaceInSub3_other_setting[21:0] = 1000;
+      else if (u_MyInterfaceInSub3_mysig_out == 2'b01)
+        u_MyInterfaceInSub3_other_setting[21:0] = 2000;
+      else if (u_MyInterfaceInSub3_mysig_out == 2'b10)
+        u_MyInterfaceInSub3_other_setting[21:0] = 3000;
+      else
+        u_MyInterfaceInSub3_other_setting[21:0] = 4000;
+    end
+
+    assign passThrough[7:0] = 124;
+    assign passThrough[15:8] = 200;
+
+endmodule
diff --git a/tests/svinterfaces/svinterface_at_top_tb.v b/tests/svinterfaces/svinterface_at_top_tb.v
new file mode 100644
index 000000000..bf37a148d
--- /dev/null
+++ b/tests/svinterfaces/svinterface_at_top_tb.v
@@ -0,0 +1,68 @@
+`timescale 1ns/10ps
+
+module svinterface_at_top_tb;
+
+
+  logic clk;
+  logic rst;
+  logic [21:0] outOther;
+  logic [1:0] sig;
+  logic [1:0] sig_out;
+  logic flip;
+  logic [15:0] passThrough;
+  integer outfile;
+
+  logic interfaceInstanceAtTop_setting;
+  logic [2:0] interfaceInstanceAtTop_other_setting;
+  logic [1:0] interfaceInstanceAtTop_mysig_out;
+  logic [15:0] interfaceInstanceAtTop_passThrough;
+
+
+  TopModule u_dut (
+    .clk(clk),
+    .rst(rst),
+    .outOther(outOther),
+    .sig(sig),
+    .flip(flip),
+    .passThrough(passThrough),
+    .interfaceInstanceAtTop_setting(interfaceInstanceAtTop_setting),
+    .interfaceInstanceAtTop_other_setting(interfaceInstanceAtTop_other_setting),
+    .interfaceInstanceAtTop_mysig_out(interfaceInstanceAtTop_mysig_out),
+    .interfaceInstanceAtTop_passThrough(interfaceInstanceAtTop_passThrough),
+    .sig_out(sig_out)
+  );
+
+  initial begin
+    clk = 0;
+    while(1) begin
+      clk = ~clk;
+      #50;
+    end
+  end
+
+  initial begin
+    outfile = $fopen("output.txt");
+    rst = 1;
+    interfaceInstanceAtTop_setting = 0;
+    sig = 0;
+    flip = 0;
+    @(posedge clk);
+    #(2);
+    rst = 0;
+    @(posedge clk);
+    for(int j=0;j<2;j++) begin
+      for(int i=0;i<20;i++) begin
+        #(2);
+        flip = j;
+        sig = i;
+        @(posedge clk);
+      end
+    end
+    $finish;
+  end
+
+  always @(negedge clk) begin
+    $fdisplay(outfile, "%d %d %d %d", outOther, sig_out, passThrough, interfaceInstanceAtTop_mysig_out);
+  end
+
+endmodule
diff --git a/tests/svinterfaces/svinterface_at_top_tb_wrapper.v b/tests/svinterfaces/svinterface_at_top_tb_wrapper.v
new file mode 100644
index 000000000..b344a7b88
--- /dev/null
+++ b/tests/svinterfaces/svinterface_at_top_tb_wrapper.v
@@ -0,0 +1,68 @@
+`timescale 1ns/10ps
+
+module svinterface_at_top_tb_wrapper;
+
+
+  logic clk;
+  logic rst;
+  logic [21:0] outOther;
+  logic [1:0] sig;
+  logic [1:0] sig_out;
+  logic flip;
+  logic [15:0] passThrough;
+  integer outfile;
+
+  logic interfaceInstanceAtTop_setting;
+  logic [2:0] interfaceInstanceAtTop_other_setting;
+  logic [1:0] interfaceInstanceAtTop_mysig_out;
+  logic [15:0] interfaceInstanceAtTop_passThrough;
+
+
+  TopModule u_dut (
+    .clk(clk),
+    .rst(rst),
+    .outOther(outOther),
+    .sig(sig),
+    .flip(flip),
+    .passThrough(passThrough),
+    .\interfaceInstanceAtTop.setting (interfaceInstanceAtTop_setting),
+    .\interfaceInstanceAtTop.other_setting (interfaceInstanceAtTop_other_setting),
+    .\interfaceInstanceAtTop.mysig_out (interfaceInstanceAtTop_mysig_out),
+    .\interfaceInstanceAtTop.passThrough (interfaceInstanceAtTop_passThrough),
+    .sig_out(sig_out)
+  );
+
+  initial begin
+    clk = 0;
+    while(1) begin
+      clk = ~clk;
+      #50;
+    end
+  end
+
+  initial begin
+    outfile = $fopen("output.txt");
+    rst = 1;
+    sig = 0;
+    interfaceInstanceAtTop_setting = 0;
+    flip = 0;
+    @(posedge clk);
+    #(2);
+    rst = 0;
+    @(posedge clk);
+    for(int j=0;j<2;j++) begin
+      for(int i=0;i<20;i++) begin
+        #(2);
+        flip = j;
+        sig = i;
+        @(posedge clk);
+      end
+    end
+    $finish;
+  end
+
+  always @(negedge clk) begin
+    $fdisplay(outfile, "%d %d %d %d", outOther, sig_out, passThrough, interfaceInstanceAtTop_mysig_out);
+  end
+
+endmodule
diff --git a/tests/svinterfaces/svinterface_at_top_wrapper.v b/tests/svinterfaces/svinterface_at_top_wrapper.v
new file mode 100644
index 000000000..64f906c07
--- /dev/null
+++ b/tests/svinterfaces/svinterface_at_top_wrapper.v
@@ -0,0 +1,33 @@
+`timescale 1ns/10ps
+
+module svinterface_at_top_wrapper(
+  input logic clk,
+  input logic rst,
+  output logic [21:0] outOther,
+  input logic [1:0] sig,
+  output logic [1:0] sig_out,
+  input logic flip,
+  output logic [15:0] passThrough,
+
+    input logic interfaceInstanceAtTop_setting,
+    output logic [2:0] interfaceInstanceAtTop_other_setting,
+    output logic [1:0] interfaceInstanceAtTop_mysig_out,
+    output logic [15:0] interfaceInstanceAtTop_passThrough,
+  );
+
+
+  TopModule u_dut (
+    .clk(clk),
+    .rst(rst),
+    .outOther(outOther),
+    .sig(sig),
+    .flip(flip),
+    .passThrough(passThrough),
+    .\interfaceInstanceAtTop.setting(interfaceInstanceAtTop_setting),
+    .\interfaceInstanceAtTop.other_setting(interfaceInstanceAtTop_other_setting),
+    .\interfaceInstanceAtTop.mysig_out(interfaceInstanceAtTop_mysig_out),
+    .\interfaceInstanceAtTop.passThrough(interfaceInstanceAtTop_passThrough),
+    .sig_out(sig_out)
+  );
+
+endmodule
-- 
cgit v1.2.3


From 536ae16c3abcf3fef1dd14df8733bf51fa1bce1a Mon Sep 17 00:00:00 2001
From: Udi Finkelstein <github@udifink.com>
Date: Thu, 25 Oct 2018 02:37:56 +0300
Subject: Rename the generic "Syntax error" message from the
 Verilog/SystemVerilog parser into unique, meaningful info on the error. Also
 add 13 compilation examples that triggers each of these messages.

---
 tests/errors/syntax_err01.v | 4 ++++
 tests/errors/syntax_err02.v | 7 +++++++
 tests/errors/syntax_err03.v | 7 +++++++
 tests/errors/syntax_err04.v | 4 ++++
 tests/errors/syntax_err05.v | 4 ++++
 tests/errors/syntax_err06.v | 6 ++++++
 tests/errors/syntax_err07.v | 6 ++++++
 tests/errors/syntax_err08.v | 6 ++++++
 tests/errors/syntax_err09.v | 3 +++
 tests/errors/syntax_err10.v | 3 +++
 tests/errors/syntax_err11.v | 3 +++
 tests/errors/syntax_err12.v | 7 +++++++
 tests/errors/syntax_err13.v | 4 ++++
 13 files changed, 64 insertions(+)
 create mode 100644 tests/errors/syntax_err01.v
 create mode 100644 tests/errors/syntax_err02.v
 create mode 100644 tests/errors/syntax_err03.v
 create mode 100644 tests/errors/syntax_err04.v
 create mode 100644 tests/errors/syntax_err05.v
 create mode 100644 tests/errors/syntax_err06.v
 create mode 100644 tests/errors/syntax_err07.v
 create mode 100644 tests/errors/syntax_err08.v
 create mode 100644 tests/errors/syntax_err09.v
 create mode 100644 tests/errors/syntax_err10.v
 create mode 100644 tests/errors/syntax_err11.v
 create mode 100644 tests/errors/syntax_err12.v
 create mode 100644 tests/errors/syntax_err13.v

(limited to 'tests')

diff --git a/tests/errors/syntax_err01.v b/tests/errors/syntax_err01.v
new file mode 100644
index 000000000..68e9b1d50
--- /dev/null
+++ b/tests/errors/syntax_err01.v
@@ -0,0 +1,4 @@
+module a;
+integer [31:0]w;
+endmodule
+
diff --git a/tests/errors/syntax_err02.v b/tests/errors/syntax_err02.v
new file mode 100644
index 000000000..c72e976a8
--- /dev/null
+++ b/tests/errors/syntax_err02.v
@@ -0,0 +1,7 @@
+module a;
+task to (
+  input integer [3:0]x
+);
+endtask
+endmodule
+
diff --git a/tests/errors/syntax_err03.v b/tests/errors/syntax_err03.v
new file mode 100644
index 000000000..6eec44ade
--- /dev/null
+++ b/tests/errors/syntax_err03.v
@@ -0,0 +1,7 @@
+module a;
+task to (
+  input [3]x
+);
+endtask
+endmodule
+
diff --git a/tests/errors/syntax_err04.v b/tests/errors/syntax_err04.v
new file mode 100644
index 000000000..d488e5dbb
--- /dev/null
+++ b/tests/errors/syntax_err04.v
@@ -0,0 +1,4 @@
+module a;
+wire [3]x;
+endmodule
+
diff --git a/tests/errors/syntax_err05.v b/tests/errors/syntax_err05.v
new file mode 100644
index 000000000..8a1f11532
--- /dev/null
+++ b/tests/errors/syntax_err05.v
@@ -0,0 +1,4 @@
+module a;
+input x[2:0];
+endmodule
+
diff --git a/tests/errors/syntax_err06.v b/tests/errors/syntax_err06.v
new file mode 100644
index 000000000..b35a1dea2
--- /dev/null
+++ b/tests/errors/syntax_err06.v
@@ -0,0 +1,6 @@
+module a;
+initial
+begin : label1
+end: label2
+endmodule
+
diff --git a/tests/errors/syntax_err07.v b/tests/errors/syntax_err07.v
new file mode 100644
index 000000000..62bcc6b3e
--- /dev/null
+++ b/tests/errors/syntax_err07.v
@@ -0,0 +1,6 @@
+module a;
+wire [5:0]x;
+wire [3:0]y;
+assign y = (4)55;
+endmodule
+
diff --git a/tests/errors/syntax_err08.v b/tests/errors/syntax_err08.v
new file mode 100644
index 000000000..d41bfd6c9
--- /dev/null
+++ b/tests/errors/syntax_err08.v
@@ -0,0 +1,6 @@
+module a;
+wire [5:0]x;
+wire [3:0]y;
+assign y = x 55;
+endmodule
+
diff --git a/tests/errors/syntax_err09.v b/tests/errors/syntax_err09.v
new file mode 100644
index 000000000..1e472eb94
--- /dev/null
+++ b/tests/errors/syntax_err09.v
@@ -0,0 +1,3 @@
+module a(input wire x = 1'b0);
+endmodule
+
diff --git a/tests/errors/syntax_err10.v b/tests/errors/syntax_err10.v
new file mode 100644
index 000000000..d3280405c
--- /dev/null
+++ b/tests/errors/syntax_err10.v
@@ -0,0 +1,3 @@
+module a;
+parameter integer [2:0]x=0;
+endmodule
diff --git a/tests/errors/syntax_err11.v b/tests/errors/syntax_err11.v
new file mode 100644
index 000000000..f3cde9dfc
--- /dev/null
+++ b/tests/errors/syntax_err11.v
@@ -0,0 +1,3 @@
+module a;
+parameter integer real x=0;
+endmodule
diff --git a/tests/errors/syntax_err12.v b/tests/errors/syntax_err12.v
new file mode 100644
index 000000000..f9b5d5b0b
--- /dev/null
+++ b/tests/errors/syntax_err12.v
@@ -0,0 +1,7 @@
+interface iface;
+endinterface
+
+module a (
+  iface x = 1'b0
+);
+endmodule
diff --git a/tests/errors/syntax_err13.v b/tests/errors/syntax_err13.v
new file mode 100644
index 000000000..b5c942fca
--- /dev/null
+++ b/tests/errors/syntax_err13.v
@@ -0,0 +1,4 @@
+module a #(p = 0)
+();
+endmodule
+
-- 
cgit v1.2.3


From 9e072ec21f9985126e1cfeb04fa7f2bc963790b3 Mon Sep 17 00:00:00 2001
From: whitequark <whitequark@whitequark.org>
Date: Wed, 5 Dec 2018 00:23:22 +0000
Subject: opt_lut: new pass, to combine LUTs for tighter packing.

---
 tests/opt/.gitignore    |  1 +
 tests/opt/ice40_carry.v |  3 +++
 tests/opt/opt_lut.v     | 18 ++++++++++++++++++
 tests/opt/opt_lut.ys    | 15 +++++++++++++++
 tests/opt/run-test.sh   |  6 ++++++
 5 files changed, 43 insertions(+)
 create mode 100644 tests/opt/.gitignore
 create mode 100644 tests/opt/ice40_carry.v
 create mode 100644 tests/opt/opt_lut.v
 create mode 100644 tests/opt/opt_lut.ys
 create mode 100755 tests/opt/run-test.sh

(limited to 'tests')

diff --git a/tests/opt/.gitignore b/tests/opt/.gitignore
new file mode 100644
index 000000000..397b4a762
--- /dev/null
+++ b/tests/opt/.gitignore
@@ -0,0 +1 @@
+*.log
diff --git a/tests/opt/ice40_carry.v b/tests/opt/ice40_carry.v
new file mode 100644
index 000000000..ed938932a
--- /dev/null
+++ b/tests/opt/ice40_carry.v
@@ -0,0 +1,3 @@
+module SB_CARRY (output CO, input I0, I1, CI);
+    assign CO = (I0 && I1) || ((I0 || I1) && CI);
+endmodule
diff --git a/tests/opt/opt_lut.v b/tests/opt/opt_lut.v
new file mode 100644
index 000000000..b13db367d
--- /dev/null
+++ b/tests/opt/opt_lut.v
@@ -0,0 +1,18 @@
+module top(
+    input [8:0] a,
+    input [8:0] b,
+    output [8:0] o1,
+    output [2:0] o2,
+    input [2:0] c,
+    input [2:0] d,
+    output [2:0] o3,
+    output [2:0] o4,
+    input s
+);
+
+assign o1 = (s ? 0 : a + b);
+assign o2 = (s ? a : a - b);
+assign o3 = (s ? 4'b1111 : d + c);
+assign o4 = (s ? d : c - d);
+
+endmodule
diff --git a/tests/opt/opt_lut.ys b/tests/opt/opt_lut.ys
new file mode 100644
index 000000000..1c7dc1473
--- /dev/null
+++ b/tests/opt/opt_lut.ys
@@ -0,0 +1,15 @@
+read_verilog opt_lut.v
+synth_ice40
+ice40_unlut
+design -save preopt
+
+opt_lut
+design -stash postopt
+
+design -copy-from preopt -as preopt top
+design -copy-from postopt -as postopt top
+equiv_make preopt postopt equiv
+techmap -map ice40_carry.v
+prep -flatten -top equiv
+equiv_induct
+equiv_status -assert
diff --git a/tests/opt/run-test.sh b/tests/opt/run-test.sh
new file mode 100755
index 000000000..44ce7e674
--- /dev/null
+++ b/tests/opt/run-test.sh
@@ -0,0 +1,6 @@
+#!/bin/bash
+set -e
+for x in *.ys; do
+  echo "Running $x.."
+  ../../yosys -ql ${x%.ys}.log $x
+done
-- 
cgit v1.2.3


From 45cb6200af13469724de42656f2c1f0f61c8766a Mon Sep 17 00:00:00 2001
From: whitequark <whitequark@whitequark.org>
Date: Wed, 5 Dec 2018 15:26:40 +0000
Subject: opt_lut: add -dlogic, to avoid disturbing logic such as carry chains.

---
 tests/opt/opt_lut.ys | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'tests')

diff --git a/tests/opt/opt_lut.ys b/tests/opt/opt_lut.ys
index 1c7dc1473..86ad93bb3 100644
--- a/tests/opt/opt_lut.ys
+++ b/tests/opt/opt_lut.ys
@@ -3,7 +3,7 @@ synth_ice40
 ice40_unlut
 design -save preopt
 
-opt_lut
+opt_lut -dlogic SB_CARRY:I0=1:I1=2:CI=3
 design -stash postopt
 
 design -copy-from preopt -as preopt top
-- 
cgit v1.2.3


From 9ef078848a5b121336b83043c565ce47433eb2d8 Mon Sep 17 00:00:00 2001
From: whitequark <whitequark@whitequark.org>
Date: Wed, 5 Dec 2018 04:50:38 +0000
Subject: gate2lut: new techlib, for converting Yosys gates to FPGA LUTs.

---
 tests/lut/.gitignore   |  1 +
 tests/lut/check_map.ys | 13 +++++++++++++
 tests/lut/map_and.v    |  5 +++++
 tests/lut/map_mux.v    |  5 +++++
 tests/lut/map_not.v    |  5 +++++
 tests/lut/map_or.v     |  5 +++++
 tests/lut/map_xor.v    |  5 +++++
 tests/lut/run-test.sh  |  6 ++++++
 8 files changed, 45 insertions(+)
 create mode 100644 tests/lut/.gitignore
 create mode 100644 tests/lut/check_map.ys
 create mode 100644 tests/lut/map_and.v
 create mode 100644 tests/lut/map_mux.v
 create mode 100644 tests/lut/map_not.v
 create mode 100644 tests/lut/map_or.v
 create mode 100644 tests/lut/map_xor.v
 create mode 100644 tests/lut/run-test.sh

(limited to 'tests')

diff --git a/tests/lut/.gitignore b/tests/lut/.gitignore
new file mode 100644
index 000000000..397b4a762
--- /dev/null
+++ b/tests/lut/.gitignore
@@ -0,0 +1 @@
+*.log
diff --git a/tests/lut/check_map.ys b/tests/lut/check_map.ys
new file mode 100644
index 000000000..6d659891f
--- /dev/null
+++ b/tests/lut/check_map.ys
@@ -0,0 +1,13 @@
+design -save preopt
+
+simplemap
+techmap -map +/gate2lut.v -D LUT_WIDTH=4
+select -assert-count 1 t:$lut
+design -stash postopt
+
+design -copy-from preopt -as preopt top
+design -copy-from postopt -as postopt top
+equiv_make preopt postopt equiv
+prep -flatten -top equiv
+equiv_induct
+equiv_status -assert
diff --git a/tests/lut/map_and.v b/tests/lut/map_and.v
new file mode 100644
index 000000000..68ae33fd6
--- /dev/null
+++ b/tests/lut/map_and.v
@@ -0,0 +1,5 @@
+module top(...);
+    input a, b;
+    output y;
+    assign y = a&b;
+endmodule
diff --git a/tests/lut/map_mux.v b/tests/lut/map_mux.v
new file mode 100644
index 000000000..ccecf3023
--- /dev/null
+++ b/tests/lut/map_mux.v
@@ -0,0 +1,5 @@
+module top(...);
+    input a, b, s;
+    output y;
+    assign y = s?a:b;
+endmodule
diff --git a/tests/lut/map_not.v b/tests/lut/map_not.v
new file mode 100644
index 000000000..385997414
--- /dev/null
+++ b/tests/lut/map_not.v
@@ -0,0 +1,5 @@
+module top(...);
+    input a;
+    output y;
+    assign y = ~a;
+endmodule
diff --git a/tests/lut/map_or.v b/tests/lut/map_or.v
new file mode 100644
index 000000000..8b8c55188
--- /dev/null
+++ b/tests/lut/map_or.v
@@ -0,0 +1,5 @@
+module top(...);
+    input a, b;
+    output y;
+    assign y = a|b;
+endmodule
diff --git a/tests/lut/map_xor.v b/tests/lut/map_xor.v
new file mode 100644
index 000000000..708a05789
--- /dev/null
+++ b/tests/lut/map_xor.v
@@ -0,0 +1,5 @@
+module top(...);
+    input a, b;
+    output y;
+    assign y = a^b;
+endmodule
diff --git a/tests/lut/run-test.sh b/tests/lut/run-test.sh
new file mode 100644
index 000000000..207417fa6
--- /dev/null
+++ b/tests/lut/run-test.sh
@@ -0,0 +1,6 @@
+#!/bin/bash
+set -e
+for x in *.v; do
+  echo "Running $x.."
+  ../../yosys -q -s check_map.ys -l ${x%.v}.log $x
+done
-- 
cgit v1.2.3


From 7d1088afc453f57f0ecc0f55ac2c91fd72ad8f2e Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Thu, 6 Dec 2018 07:29:37 +0100
Subject: Add missing .gitignore

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 tests/svinterfaces/.gitignore | 8 ++++++++
 1 file changed, 8 insertions(+)
 create mode 100644 tests/svinterfaces/.gitignore

(limited to 'tests')

diff --git a/tests/svinterfaces/.gitignore b/tests/svinterfaces/.gitignore
new file mode 100644
index 000000000..a5b7927d1
--- /dev/null
+++ b/tests/svinterfaces/.gitignore
@@ -0,0 +1,8 @@
+/a.out
+/dut_result.txt
+/reference_result.txt
+/*.diff
+/*.log_stderr
+/*.log_stdout
+/*_ref_syn.v
+/*_syn.v
-- 
cgit v1.2.3


From 7ec740b7ad4ee4bc02e2564671e0153cdd08152f Mon Sep 17 00:00:00 2001
From: whitequark <whitequark@whitequark.org>
Date: Fri, 7 Dec 2018 17:13:52 +0000
Subject: opt_lut: leave intact LUTs with cascade feeding module outputs.

---
 tests/opt/opt_lut_port.il | 18 ++++++++++++++++++
 tests/opt/opt_lut_port.ys |  2 ++
 2 files changed, 20 insertions(+)
 create mode 100644 tests/opt/opt_lut_port.il
 create mode 100644 tests/opt/opt_lut_port.ys

(limited to 'tests')

diff --git a/tests/opt/opt_lut_port.il b/tests/opt/opt_lut_port.il
new file mode 100644
index 000000000..7eb71890f
--- /dev/null
+++ b/tests/opt/opt_lut_port.il
@@ -0,0 +1,18 @@
+module $1
+  wire width 4 input 2 \_0_
+  wire output 4 \_1_
+  wire input 3 \_2_
+  wire output 1 \o
+  cell $lut \_3_
+    parameter \LUT 16'0011000000000011
+    parameter \WIDTH 4
+    connect \A { \_0_ [3] \o 2'00 }
+    connect \Y \_1_
+  end
+  cell $lut \_4_
+    parameter \LUT 4'0001
+    parameter \WIDTH 4
+    connect \A { 3'000 \_2_ }
+    connect \Y \o
+  end
+end
diff --git a/tests/opt/opt_lut_port.ys b/tests/opt/opt_lut_port.ys
new file mode 100644
index 000000000..51dfd988b
--- /dev/null
+++ b/tests/opt/opt_lut_port.ys
@@ -0,0 +1,2 @@
+read_ilang opt_lut_port.il
+select -assert-count 2 t:$lut
-- 
cgit v1.2.3


From c38ea9ae65b2a987d6a7ea790abf339944069f9a Mon Sep 17 00:00:00 2001
From: whitequark <whitequark@whitequark.org>
Date: Thu, 6 Dec 2018 14:28:20 +0000
Subject: equiv_opt: new command, for verifying optimization passes.

---
 tests/lut/check_map.ys | 13 ++-----------
 tests/opt/opt_lut.ys   | 13 +------------
 2 files changed, 3 insertions(+), 23 deletions(-)

(limited to 'tests')

diff --git a/tests/lut/check_map.ys b/tests/lut/check_map.ys
index 6d659891f..dc0aaffc2 100644
--- a/tests/lut/check_map.ys
+++ b/tests/lut/check_map.ys
@@ -1,13 +1,4 @@
-design -save preopt
-
 simplemap
-techmap -map +/gate2lut.v -D LUT_WIDTH=4
+equiv_opt -assert techmap -map +/gate2lut.v -D LUT_WIDTH=4
+design -load postopt
 select -assert-count 1 t:$lut
-design -stash postopt
-
-design -copy-from preopt -as preopt top
-design -copy-from postopt -as postopt top
-equiv_make preopt postopt equiv
-prep -flatten -top equiv
-equiv_induct
-equiv_status -assert
diff --git a/tests/opt/opt_lut.ys b/tests/opt/opt_lut.ys
index 86ad93bb3..f3c1e2822 100644
--- a/tests/opt/opt_lut.ys
+++ b/tests/opt/opt_lut.ys
@@ -1,15 +1,4 @@
 read_verilog opt_lut.v
 synth_ice40
 ice40_unlut
-design -save preopt
-
-opt_lut -dlogic SB_CARRY:I0=1:I1=2:CI=3
-design -stash postopt
-
-design -copy-from preopt -as preopt top
-design -copy-from postopt -as postopt top
-equiv_make preopt postopt equiv
-techmap -map ice40_carry.v
-prep -flatten -top equiv
-equiv_induct
-equiv_status -assert
+equiv_opt -map ice40_carry.v -assert opt_lut -dlogic SB_CARRY:I0=1:I1=2:CI=3
-- 
cgit v1.2.3


From 7ff5a9db2d17c384260c2220c9205a7b4891f001 Mon Sep 17 00:00:00 2001
From: whitequark <whitequark@whitequark.org>
Date: Fri, 7 Dec 2018 16:58:33 +0000
Subject: equiv_opt: pass -D EQUIV when techmapping.

This allows avoiding techmap crashes e.g. because of large memories
in white-box cell models.
---
 tests/opt/ice40_carry.v | 3 ---
 tests/opt/opt_lut.ys    | 2 +-
 2 files changed, 1 insertion(+), 4 deletions(-)
 delete mode 100644 tests/opt/ice40_carry.v

(limited to 'tests')

diff --git a/tests/opt/ice40_carry.v b/tests/opt/ice40_carry.v
deleted file mode 100644
index ed938932a..000000000
--- a/tests/opt/ice40_carry.v
+++ /dev/null
@@ -1,3 +0,0 @@
-module SB_CARRY (output CO, input I0, I1, CI);
-    assign CO = (I0 && I1) || ((I0 || I1) && CI);
-endmodule
diff --git a/tests/opt/opt_lut.ys b/tests/opt/opt_lut.ys
index f3c1e2822..59b12c351 100644
--- a/tests/opt/opt_lut.ys
+++ b/tests/opt/opt_lut.ys
@@ -1,4 +1,4 @@
 read_verilog opt_lut.v
 synth_ice40
 ice40_unlut
-equiv_opt -map ice40_carry.v -assert opt_lut -dlogic SB_CARRY:I0=1:I1=2:CI=3
+equiv_opt -map +/ice40/cells_sim.v -assert opt_lut -dlogic SB_CARRY:I0=1:I1=2:CI=3
-- 
cgit v1.2.3


From 99706b3bf48de121e58b76d4341d601f0bcc26cd Mon Sep 17 00:00:00 2001
From: Larry Doolittle <ldoolitt@recycle.lbl.gov>
Date: Fri, 28 Dec 2018 08:24:31 -0800
Subject: Squelch a little more trailing whitespace

---
 tests/sva/basic01.sv | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'tests')

diff --git a/tests/sva/basic01.sv b/tests/sva/basic01.sv
index 74ab93430..d5ad497dd 100644
--- a/tests/sva/basic01.sv
+++ b/tests/sva/basic01.sv
@@ -6,7 +6,7 @@ module top (input logic clock, ctrl);
 		write <= ctrl;
 		ready <= write;
 	end
-	
+
 	a_rw: assert property ( @(posedge clock) !(read && write) );
 `ifdef FAIL
 	a_wr: assert property ( @(posedge clock) write |-> ready );
-- 
cgit v1.2.3


From 42c356c49c04a735fe27e672ff31452170f84b40 Mon Sep 17 00:00:00 2001
From: whitequark <whitequark@whitequark.org>
Date: Mon, 31 Dec 2018 23:53:23 +0000
Subject: opt_lut: eliminate LUTs evaluating to constants or inputs.

---
 tests/opt/opt_lut_elim.il | 19 +++++++++++++++++++
 tests/opt/opt_lut_elim.ys |  3 +++
 tests/opt/opt_lut_port.ys |  1 +
 3 files changed, 23 insertions(+)
 create mode 100644 tests/opt/opt_lut_elim.il
 create mode 100644 tests/opt/opt_lut_elim.ys

(limited to 'tests')

diff --git a/tests/opt/opt_lut_elim.il b/tests/opt/opt_lut_elim.il
new file mode 100644
index 000000000..75675d983
--- /dev/null
+++ b/tests/opt/opt_lut_elim.il
@@ -0,0 +1,19 @@
+module \test
+  wire input 1 \i
+
+  wire output 2 \o1
+  cell $lut $1
+    parameter \LUT 16'0110100110010110
+    parameter \WIDTH 4
+    connect \A { \i 3'000 }
+    connect \Y \o1
+  end
+
+  wire output 2 \o2
+  cell $lut $2
+    parameter \LUT 16'0110100010010110
+    parameter \WIDTH 4
+    connect \A { \i 3'000 }
+    connect \Y \o2
+  end
+end
diff --git a/tests/opt/opt_lut_elim.ys b/tests/opt/opt_lut_elim.ys
new file mode 100644
index 000000000..8e5e23aea
--- /dev/null
+++ b/tests/opt/opt_lut_elim.ys
@@ -0,0 +1,3 @@
+read_ilang opt_lut_elim.il
+opt_lut
+select -assert-count 0 t:$lut
diff --git a/tests/opt/opt_lut_port.ys b/tests/opt/opt_lut_port.ys
index 51dfd988b..3cb4ecb23 100644
--- a/tests/opt/opt_lut_port.ys
+++ b/tests/opt/opt_lut_port.ys
@@ -1,2 +1,3 @@
 read_ilang opt_lut_port.il
+opt_lut
 select -assert-count 2 t:$lut
-- 
cgit v1.2.3


From 8e53d2e0bf3584709cd320447ad5a89a80dcfd94 Mon Sep 17 00:00:00 2001
From: whitequark <whitequark@whitequark.org>
Date: Wed, 2 Jan 2019 02:45:49 +0000
Subject: opt_expr: simplify any unsigned comparisons with all-0 and all-1.

Before this commit, only unsigned comparisons with all-0 would be
simplified. This commit also makes the code handling such comparisons
to be more rigorous and not abort on unexpected input.
---
 tests/opt/opt_expr_cmp.v  | 11 +++++++++++
 tests/opt/opt_expr_cmp.ys |  4 ++++
 2 files changed, 15 insertions(+)
 create mode 100644 tests/opt/opt_expr_cmp.v
 create mode 100644 tests/opt/opt_expr_cmp.ys

(limited to 'tests')

diff --git a/tests/opt/opt_expr_cmp.v b/tests/opt/opt_expr_cmp.v
new file mode 100644
index 000000000..7eb65d531
--- /dev/null
+++ b/tests/opt/opt_expr_cmp.v
@@ -0,0 +1,11 @@
+module top(...);
+  input [3:0] a;
+  output o1 = 4'b0000 >  a;
+  output o2 = 4'b0000 <= a;
+  output o3 = 4'b1111 <  a;
+  output o4 = 4'b1111 >= a;
+  output o5 = a <  4'b0000;
+  output o6 = a >= 4'b0000;
+  output o7 = a >  4'b1111;
+  output o8 = a <= 4'b1111;
+endmodule
diff --git a/tests/opt/opt_expr_cmp.ys b/tests/opt/opt_expr_cmp.ys
new file mode 100644
index 000000000..214ce8b11
--- /dev/null
+++ b/tests/opt/opt_expr_cmp.ys
@@ -0,0 +1,4 @@
+read_verilog opt_expr_cmp.v
+equiv_opt -assert opt_expr -fine
+design -load postopt
+select -assert-count 0 t:$gt t:$ge t:$lt t:$le
-- 
cgit v1.2.3


From 9e9846a6ead700756fbd7a5e6c72ccb424006934 Mon Sep 17 00:00:00 2001
From: whitequark <whitequark@whitequark.org>
Date: Wed, 2 Jan 2019 03:01:25 +0000
Subject: opt_expr: refactor simplification of signed X>=0 and X<0. NFCI.

---
 tests/opt/opt_expr_cmp.v | 22 ++++++++++++++--------
 1 file changed, 14 insertions(+), 8 deletions(-)

(limited to 'tests')

diff --git a/tests/opt/opt_expr_cmp.v b/tests/opt/opt_expr_cmp.v
index 7eb65d531..72372bdf0 100644
--- a/tests/opt/opt_expr_cmp.v
+++ b/tests/opt/opt_expr_cmp.v
@@ -1,11 +1,17 @@
 module top(...);
   input [3:0] a;
-  output o1 = 4'b0000 >  a;
-  output o2 = 4'b0000 <= a;
-  output o3 = 4'b1111 <  a;
-  output o4 = 4'b1111 >= a;
-  output o5 = a <  4'b0000;
-  output o6 = a >= 4'b0000;
-  output o7 = a >  4'b1111;
-  output o8 = a <= 4'b1111;
+
+  output o1_1 = 4'b0000 >  a;
+  output o1_2 = 4'b0000 <= a;
+  output o1_3 = 4'b1111 <  a;
+  output o1_4 = 4'b1111 >= a;
+  output o1_5 = a <  4'b0000;
+  output o1_6 = a >= 4'b0000;
+  output o1_7 = a >  4'b1111;
+  output o1_8 = a <= 4'b1111;
+
+  output o2_1 = 4'sb0000 >  $signed(a);
+  output o2_2 = 4'sb0000 <= $signed(a);
+  output o2_3 = $signed(a) <  4'sb0000;
+  output o2_4 = $signed(a) >= 4'sb0000;
 endmodule
-- 
cgit v1.2.3


From 4fd458290c3da4c3f372f2e1fdd99829a9462a38 Mon Sep 17 00:00:00 2001
From: whitequark <whitequark@whitequark.org>
Date: Wed, 2 Jan 2019 04:31:20 +0000
Subject: opt_expr: refactor simplification of unsigned X<onehot and X>=onehot.
 NFCI.

---
 tests/opt/opt_expr_cmp.v | 5 +++++
 1 file changed, 5 insertions(+)

(limited to 'tests')

diff --git a/tests/opt/opt_expr_cmp.v b/tests/opt/opt_expr_cmp.v
index 72372bdf0..500b15f1b 100644
--- a/tests/opt/opt_expr_cmp.v
+++ b/tests/opt/opt_expr_cmp.v
@@ -14,4 +14,9 @@ module top(...);
   output o2_2 = 4'sb0000 <= $signed(a);
   output o2_3 = $signed(a) <  4'sb0000;
   output o2_4 = $signed(a) >= 4'sb0000;
+
+  output o3_1 = 4'b0100 >  a;
+  output o3_2 = 4'b0100 <= a;
+  output o3_3 = a <  4'b0100;
+  output o3_4 = a >= 4'b0100;
 endmodule
-- 
cgit v1.2.3


From a91892bba422bbe8de080a105a6fb4b44f96df1a Mon Sep 17 00:00:00 2001
From: whitequark <whitequark@whitequark.org>
Date: Wed, 2 Jan 2019 07:53:31 +0000
Subject: cmp2lut: new techmap pass.

---
 tests/lut/check_map.ys |  6 ++++--
 tests/lut/map_cmp.v    | 29 +++++++++++++++++++++++++++++
 tests/lut/run-test.sh  |  0
 3 files changed, 33 insertions(+), 2 deletions(-)
 create mode 100644 tests/lut/map_cmp.v
 mode change 100644 => 100755 tests/lut/run-test.sh

(limited to 'tests')

diff --git a/tests/lut/check_map.ys b/tests/lut/check_map.ys
index dc0aaffc2..46854e82e 100644
--- a/tests/lut/check_map.ys
+++ b/tests/lut/check_map.ys
@@ -1,4 +1,6 @@
 simplemap
-equiv_opt -assert techmap -map +/gate2lut.v -D LUT_WIDTH=4
+equiv_opt -assert techmap -D LUT_WIDTH=4 -map +/cmp2lut.v
 design -load postopt
-select -assert-count 1 t:$lut
+equiv_opt -assert techmap -D LUT_WIDTH=4 -map +/gate2lut.v
+design -load postopt
+select -assert-count 0 t:* t:$lut %d
diff --git a/tests/lut/map_cmp.v b/tests/lut/map_cmp.v
new file mode 100644
index 000000000..5e413f894
--- /dev/null
+++ b/tests/lut/map_cmp.v
@@ -0,0 +1,29 @@
+module top(...);
+	input [3:0] a;
+
+	output o1_1 = 4'b1010 <= a;
+	output o1_2 = 4'b1010 <  a;
+	output o1_3 = 4'b1010 >= a;
+	output o1_4 = 4'b1010 >  a;
+	output o1_5 = 4'b1010 == a;
+	output o1_6 = 4'b1010 != a;
+
+	output o2_1 = a <= 4'b1010;
+	output o2_2 = a <  4'b1010;
+	output o2_3 = a >= 4'b1010;
+	output o2_4 = a >  4'b1010;
+	output o2_5 = a == 4'b1010;
+	output o2_6 = a != 4'b1010;
+
+	output o3_1 = 4'sb0101 <= $signed(a);
+	output o3_2 = 4'sb0101 <  $signed(a);
+	output o3_3 = 4'sb0101 >= $signed(a);
+	output o3_4 = 4'sb0101 >  $signed(a);
+	output o3_5 = 4'sb0101 == $signed(a);
+	output o3_6 = 4'sb0101 != $signed(a);
+
+	output o4_1 = $signed(a) <= 4'sb0000;
+	output o4_2 = $signed(a) <  4'sb0000;
+	output o4_3 = $signed(a) >= 4'sb0000;
+	output o4_4 = $signed(a) >  4'sb0000;
+endmodule
diff --git a/tests/lut/run-test.sh b/tests/lut/run-test.sh
old mode 100644
new mode 100755
-- 
cgit v1.2.3


From bf8db55ef36f6839827cd8bc69f673fd3fd43cca Mon Sep 17 00:00:00 2001
From: whitequark <whitequark@whitequark.org>
Date: Wed, 2 Jan 2019 05:04:28 +0000
Subject: opt_expr: improve simplification of comparisons with large constants.

The idea behind this simplification is that a N-bit signal X being
compared with an M-bit constant where M>N and the constant has Nth
or higher bit set, it either always succeeds or always fails.

However, the existing implementation only worked with one-hot signals
for some reason. It also printed incorrect messages.

This commit adjusts the simplification to have as much power as
possible, and fixes other bugs.
---
 tests/opt/opt_expr_cmp.v | 18 ++++++++++++++++++
 1 file changed, 18 insertions(+)

(limited to 'tests')

diff --git a/tests/opt/opt_expr_cmp.v b/tests/opt/opt_expr_cmp.v
index 500b15f1b..5aff4b80f 100644
--- a/tests/opt/opt_expr_cmp.v
+++ b/tests/opt/opt_expr_cmp.v
@@ -19,4 +19,22 @@ module top(...);
   output o3_2 = 4'b0100 <= a;
   output o3_3 = a <  4'b0100;
   output o3_4 = a >= 4'b0100;
+
+  output o4_1 = 5'b10000 >  a;
+  output o4_2 = 5'b10000 >= a;
+  output o4_3 = 5'b10000 <  a;
+  output o4_4 = 5'b10000 <= a;
+  output o4_5 = a <  5'b10000;
+  output o4_6 = a <= 5'b10000;
+  output o4_7 = a >  5'b10000;
+  output o4_8 = a >= 5'b10000;
+
+  output o5_1 = 5'b10100 >  a;
+  output o5_2 = 5'b10100 >= a;
+  output o5_3 = 5'b10100 <  a;
+  output o5_4 = 5'b10100 <= a;
+  output o5_5 = a <  5'b10100;
+  output o5_6 = a <= 5'b10100;
+  output o5_7 = a >  5'b10100;
+  output o5_8 = a >= 5'b10100;
 endmodule
-- 
cgit v1.2.3


From 9666cca9ddba2e6d242006e80d66277b8b4df0fd Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Sun, 27 Jan 2019 09:17:02 +0100
Subject: Remove asicworld tests for (unsupported) switch-level modelling

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 tests/asicworld/code_hdl_models_misc1.v         | 22 ----------------------
 tests/asicworld/code_hdl_models_mux21_switch.v  | 22 ----------------------
 tests/asicworld/code_hdl_models_nand_switch.v   | 14 --------------
 tests/asicworld/code_hdl_models_t_gate_switch.v | 11 -----------
 4 files changed, 69 deletions(-)
 delete mode 100644 tests/asicworld/code_hdl_models_misc1.v
 delete mode 100644 tests/asicworld/code_hdl_models_mux21_switch.v
 delete mode 100644 tests/asicworld/code_hdl_models_nand_switch.v
 delete mode 100644 tests/asicworld/code_hdl_models_t_gate_switch.v

(limited to 'tests')

diff --git a/tests/asicworld/code_hdl_models_misc1.v b/tests/asicworld/code_hdl_models_misc1.v
deleted file mode 100644
index e3d9d5d64..000000000
--- a/tests/asicworld/code_hdl_models_misc1.v
+++ /dev/null
@@ -1,22 +0,0 @@
-module misc1 (a,b,c,d,y);
-input a, b,c,d;
-output y;
-
-wire net1,net2,net3;
-
-supply1 vdd;
-supply0 vss;
-
-// y = !((a+b+c).d)
-
-pmos p1 (vdd,net1,a);
-pmos p2 (net1,net2,b);
-pmos p3 (net2,y,c);
-pmos p4 (vdd,y,d);
-
-nmos n1 (vss,net3,a);
-nmos n2 (vss,net3,b);
-nmos n3 (vss,net3,c);
-nmos n4 (net3,y,d);
-
-endmodule
diff --git a/tests/asicworld/code_hdl_models_mux21_switch.v b/tests/asicworld/code_hdl_models_mux21_switch.v
deleted file mode 100644
index 519c07fc5..000000000
--- a/tests/asicworld/code_hdl_models_mux21_switch.v
+++ /dev/null
@@ -1,22 +0,0 @@
-//-----------------------------------------------------
-// Design Name : mux21_switch
-// File Name   : mux21_switch.v
-// Function    : 2:1 Mux using Switch Primitives
-// Coder       : Deepak Kumar Tala
-//-----------------------------------------------------
-module mux21_switch (out, ctrl, in1, in2);
-   
-   output out;                    
-   input  ctrl, in1, in2;         
-   wire          w;            
-
-   supply1 power;             
-   supply0 ground;      
-   
-   pmos N1 (w, power, ctrl);     
-   nmos N2 (w, ground, ctrl);   
-   
-   cmos C1 (out, in1, w, ctrl);   
-   cmos C2 (out, in2, ctrl, w);
-   
-endmodule
diff --git a/tests/asicworld/code_hdl_models_nand_switch.v b/tests/asicworld/code_hdl_models_nand_switch.v
deleted file mode 100644
index 1ccdd3a7c..000000000
--- a/tests/asicworld/code_hdl_models_nand_switch.v
+++ /dev/null
@@ -1,14 +0,0 @@
-module nand_switch(a,b,out);
-input a,b;
-output out;
-
-supply0 vss;
-supply1 vdd;
-wire net1;
-
-pmos p1 (vdd,out,a);
-pmos p2 (vdd,out,b);
-nmos n1 (vss,net1,a);
-nmos n2 (net1,out,b);
-
-endmodule
\ No newline at end of file
diff --git a/tests/asicworld/code_hdl_models_t_gate_switch.v b/tests/asicworld/code_hdl_models_t_gate_switch.v
deleted file mode 100644
index 5a7e0eaff..000000000
--- a/tests/asicworld/code_hdl_models_t_gate_switch.v
+++ /dev/null
@@ -1,11 +0,0 @@
-module t_gate_switch (L,R,nC,C);
- inout L;
- inout R;
- input nC;
- input C;
-
- //Syntax: keyword unique_name (drain. source, gate);
- pmos p1 (L,R,nC);
- nmos p2 (L,R,C);
-
-endmodule
-- 
cgit v1.2.3


From 3f0bb441f8a3014bf6b3a656b673fc07663bda76 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddieh@ece.ubc.ca>
Date: Mon, 4 Feb 2019 16:46:24 -0800
Subject: Add tests

---
 tests/aig/and.aag       |  5 +++++
 tests/aig/buffer.aag    |  3 +++
 tests/aig/cnt1.aag      |  3 +++
 tests/aig/cnt1e.aag     |  8 ++++++++
 tests/aig/empty.aag     |  1 +
 tests/aig/false.aag     |  2 ++
 tests/aig/halfadder.aag | 14 ++++++++++++++
 tests/aig/inverter.aag  |  3 +++
 tests/aig/notcnt1.aag   |  4 ++++
 tests/aig/notcnt1e.aag  |  8 ++++++++
 tests/aig/or.aag        |  5 +++++
 tests/aig/run-test.sh   | 20 ++++++++++++++++++++
 tests/aig/toggle-re.aag | 14 ++++++++++++++
 tests/aig/toggle.aag    |  4 ++++
 tests/aig/true.aag      |  2 ++
 tests/tools/autotest.sh | 21 +++++++++++++--------
 16 files changed, 109 insertions(+), 8 deletions(-)
 create mode 100644 tests/aig/and.aag
 create mode 100644 tests/aig/buffer.aag
 create mode 100644 tests/aig/cnt1.aag
 create mode 100644 tests/aig/cnt1e.aag
 create mode 100644 tests/aig/empty.aag
 create mode 100644 tests/aig/false.aag
 create mode 100644 tests/aig/halfadder.aag
 create mode 100644 tests/aig/inverter.aag
 create mode 100644 tests/aig/notcnt1.aag
 create mode 100644 tests/aig/notcnt1e.aag
 create mode 100644 tests/aig/or.aag
 create mode 100755 tests/aig/run-test.sh
 create mode 100644 tests/aig/toggle-re.aag
 create mode 100644 tests/aig/toggle.aag
 create mode 100644 tests/aig/true.aag

(limited to 'tests')

diff --git a/tests/aig/and.aag b/tests/aig/and.aag
new file mode 100644
index 000000000..d1ef2c5a5
--- /dev/null
+++ b/tests/aig/and.aag
@@ -0,0 +1,5 @@
+aag 3 2 0 1 1
+2
+4
+6
+6 2 4
diff --git a/tests/aig/buffer.aag b/tests/aig/buffer.aag
new file mode 100644
index 000000000..94a6fb1ed
--- /dev/null
+++ b/tests/aig/buffer.aag
@@ -0,0 +1,3 @@
+aag 1 1 0 1 0
+2
+2
diff --git a/tests/aig/cnt1.aag b/tests/aig/cnt1.aag
new file mode 100644
index 000000000..ce4f28fcb
--- /dev/null
+++ b/tests/aig/cnt1.aag
@@ -0,0 +1,3 @@
+aag 1 0 1 0 0 1
+2 3
+2
diff --git a/tests/aig/cnt1e.aag b/tests/aig/cnt1e.aag
new file mode 100644
index 000000000..6db3f0ffd
--- /dev/null
+++ b/tests/aig/cnt1e.aag
@@ -0,0 +1,8 @@
+aag 5 1 1 0 3 1
+2
+4 10
+4
+6 5 3
+8 4 2
+10 9 7
+b0 AIGER_NEVER
diff --git a/tests/aig/empty.aag b/tests/aig/empty.aag
new file mode 100644
index 000000000..40c0f00cb
--- /dev/null
+++ b/tests/aig/empty.aag
@@ -0,0 +1 @@
+aag 0 0 0 0 0
diff --git a/tests/aig/false.aag b/tests/aig/false.aag
new file mode 100644
index 000000000..421e64a91
--- /dev/null
+++ b/tests/aig/false.aag
@@ -0,0 +1,2 @@
+aag 0 0 0 1 0
+0
diff --git a/tests/aig/halfadder.aag b/tests/aig/halfadder.aag
new file mode 100644
index 000000000..5bf54d38d
--- /dev/null
+++ b/tests/aig/halfadder.aag
@@ -0,0 +1,14 @@
+aag 7 2 0 2 3
+2
+4
+6
+12
+6 13 15
+12 2 4
+14 3 5
+i0 x
+i1 y
+o0 s
+o1 c
+c
+half adder
diff --git a/tests/aig/inverter.aag b/tests/aig/inverter.aag
new file mode 100644
index 000000000..ff7c28542
--- /dev/null
+++ b/tests/aig/inverter.aag
@@ -0,0 +1,3 @@
+aag 1 1 0 1 0
+2
+3
diff --git a/tests/aig/notcnt1.aag b/tests/aig/notcnt1.aag
new file mode 100644
index 000000000..e92815f23
--- /dev/null
+++ b/tests/aig/notcnt1.aag
@@ -0,0 +1,4 @@
+aag 1 0 1 0 0 1
+2 3
+3
+b0 AIGER_NEVER
diff --git a/tests/aig/notcnt1e.aag b/tests/aig/notcnt1e.aag
new file mode 100644
index 000000000..141c864f7
--- /dev/null
+++ b/tests/aig/notcnt1e.aag
@@ -0,0 +1,8 @@
+aag 5 1 1 0 3 1
+2
+4 10
+5
+6 5 3
+8 4 2
+10 9 7
+b0 AIGER_NEVER
diff --git a/tests/aig/or.aag b/tests/aig/or.aag
new file mode 100644
index 000000000..f780e339f
--- /dev/null
+++ b/tests/aig/or.aag
@@ -0,0 +1,5 @@
+aag 3 2 0 1 1
+2
+4
+7
+6 3 5
diff --git a/tests/aig/run-test.sh b/tests/aig/run-test.sh
new file mode 100755
index 000000000..308578f01
--- /dev/null
+++ b/tests/aig/run-test.sh
@@ -0,0 +1,20 @@
+#!/bin/bash
+
+OPTIND=1
+seed=""    # default to no seed specified
+while getopts "S:" opt
+do
+    case "$opt" in
+	S) arg="${OPTARG#"${OPTARG%%[![:space:]]*}"}" # remove leading space
+	   seed="SEED=$arg" ;;
+    esac
+done
+shift "$((OPTIND-1))"
+
+# check for Icarus Verilog
+if ! which iverilog > /dev/null ; then
+  echo "$0: Error: Icarus Verilog 'iverilog' not found."
+  exit 1
+fi
+
+exec ${MAKE:-make} -f ../tools/autotest.mk $seed *.aag EXTRA_FLAGS="-f aiger"
diff --git a/tests/aig/toggle-re.aag b/tests/aig/toggle-re.aag
new file mode 100644
index 000000000..b662bb386
--- /dev/null
+++ b/tests/aig/toggle-re.aag
@@ -0,0 +1,14 @@
+aag 7 2 1 2 4
+2
+4
+6 8
+6
+7
+8 4 10
+10 13 15
+12 2 6
+14 3 7
+i0 enable
+i1 reset
+o0 Q
+o1 !Q
diff --git a/tests/aig/toggle.aag b/tests/aig/toggle.aag
new file mode 100644
index 000000000..09651012d
--- /dev/null
+++ b/tests/aig/toggle.aag
@@ -0,0 +1,4 @@
+aag 1 0 1 2 0
+2 3
+2
+3
diff --git a/tests/aig/true.aag b/tests/aig/true.aag
new file mode 100644
index 000000000..366893648
--- /dev/null
+++ b/tests/aig/true.aag
@@ -0,0 +1,2 @@
+aag 0 0 0 1 0
+1
diff --git a/tests/tools/autotest.sh b/tests/tools/autotest.sh
index d6216244f..c01ce5611 100755
--- a/tests/tools/autotest.sh
+++ b/tests/tools/autotest.sh
@@ -86,8 +86,9 @@ shift $((OPTIND - 1))
 
 for fn
 do
-	bn=${fn%.v}
-	if [ "$bn" == "$fn" ]; then
+	bn=${fn%.*}
+	ext=${fn##*.}
+	if [[ "$ext" != "v" ]] && [[ "$ext" != "aag" ]]; then
 		echo "Invalid argument: $fn" >&2
 		exit 1
 	fi
@@ -109,10 +110,14 @@ do
 		fn=$(basename $fn)
 		bn=$(basename $bn)
 
-		egrep -v '^\s*`timescale' ../$fn > ${bn}_ref.v
+		if [[ "$ext" == "v" ]]; then
+			egrep -v '^\s*`timescale' ../$fn > ${bn}_ref.${ext}
+		else
+			cp ../$fn ${bn}_ref.${ext}
+		fi
 
 		if [ ! -f ../${bn}_tb.v ]; then
-			"$toolsdir"/../../yosys -f "$frontend $include_opts" -b "test_autotb $autotb_opts" -o ${bn}_tb.v ${bn}_ref.v
+			"$toolsdir"/../../yosys -f "$frontend $include_opts" -b "test_autotb $autotb_opts" -o ${bn}_tb.v ${bn}_ref.${ext}
 		else
 			cp ../${bn}_tb.v ${bn}_tb.v
 		fi
@@ -138,16 +143,16 @@ do
 		fi
 
 		if [ -n "$scriptfiles" ]; then
-			test_passes -f "$frontend $include_opts" ${bn}_ref.v $scriptfiles
+			test_passes -f "$frontend $include_opts" ${bn}_ref.${ext} $scriptfiles
 		elif [ -n "$scriptopt" ]; then
-			test_passes -f "$frontend $include_opts" -p "$scriptopt" ${bn}_ref.v
+			test_passes -f "$frontend $include_opts" -p "$scriptopt" ${bn}_ref.${ext}
 		elif [ "$frontend" = "verific" ]; then
 			test_passes -p "verific -vlog2k ${bn}_ref.v; verific -import -all; opt; memory;;"
 		elif [ "$frontend" = "verific_gates" ]; then
 			test_passes -p "verific -vlog2k ${bn}_ref.v; verific -import -gates -all; opt; memory;;"
 		else
-			test_passes -f "$frontend $include_opts" -p "hierarchy; proc; opt; memory; opt; fsm; opt -full -fine" ${bn}_ref.v
-			test_passes -f "$frontend $include_opts" -p "hierarchy; synth -run coarse; techmap; opt; abc -dff" ${bn}_ref.v
+			test_passes -f "$frontend $include_opts" -p "hierarchy; proc; opt; memory; opt; fsm; opt -full -fine" ${bn}_ref.${ext}
+			test_passes -f "$frontend $include_opts" -p "hierarchy; synth -run coarse; techmap; opt; abc -dff" ${bn}_ref.${ext}
 		fi
 		touch ../${bn}.log
 	}
-- 
cgit v1.2.3


From fdd55d064b16f9334c86bb15b1c32cfb45294802 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddieh@ece.ubc.ca>
Date: Wed, 6 Feb 2019 12:20:36 -0800
Subject: Rename ASCII tests

---
 tests/aig/and.aag         |  5 -----
 tests/aig/buffer.aag      |  3 ---
 tests/aig/cnt1.aag        |  3 ---
 tests/aig/cnt1e.aag       |  8 --------
 tests/aig/empty.aag       |  1 -
 tests/aig/false.aag       |  2 --
 tests/aig/halfadder.aag   | 14 --------------
 tests/aig/inverter.aag    |  3 ---
 tests/aig/notcnt1.aag     |  4 ----
 tests/aig/notcnt1e.aag    |  8 --------
 tests/aig/or.aag          |  5 -----
 tests/aig/run-test.sh     | 20 --------------------
 tests/aig/toggle-re.aag   | 14 --------------
 tests/aig/toggle.aag      |  4 ----
 tests/aig/true.aag        |  2 --
 tests/aiger/and.aag       |  5 +++++
 tests/aiger/buffer.aag    |  3 +++
 tests/aiger/cnt1.aag      |  3 +++
 tests/aiger/cnt1e.aag     |  8 ++++++++
 tests/aiger/empty.aag     |  1 +
 tests/aiger/false.aag     |  2 ++
 tests/aiger/halfadder.aag | 14 ++++++++++++++
 tests/aiger/inverter.aag  |  3 +++
 tests/aiger/notcnt1.aag   |  4 ++++
 tests/aiger/notcnt1e.aag  |  8 ++++++++
 tests/aiger/or.aag        |  5 +++++
 tests/aiger/run-test.sh   | 20 ++++++++++++++++++++
 tests/aiger/toggle-re.aag | 14 ++++++++++++++
 tests/aiger/toggle.aag    |  4 ++++
 tests/aiger/true.aag      |  2 ++
 30 files changed, 96 insertions(+), 96 deletions(-)
 delete mode 100644 tests/aig/and.aag
 delete mode 100644 tests/aig/buffer.aag
 delete mode 100644 tests/aig/cnt1.aag
 delete mode 100644 tests/aig/cnt1e.aag
 delete mode 100644 tests/aig/empty.aag
 delete mode 100644 tests/aig/false.aag
 delete mode 100644 tests/aig/halfadder.aag
 delete mode 100644 tests/aig/inverter.aag
 delete mode 100644 tests/aig/notcnt1.aag
 delete mode 100644 tests/aig/notcnt1e.aag
 delete mode 100644 tests/aig/or.aag
 delete mode 100755 tests/aig/run-test.sh
 delete mode 100644 tests/aig/toggle-re.aag
 delete mode 100644 tests/aig/toggle.aag
 delete mode 100644 tests/aig/true.aag
 create mode 100644 tests/aiger/and.aag
 create mode 100644 tests/aiger/buffer.aag
 create mode 100644 tests/aiger/cnt1.aag
 create mode 100644 tests/aiger/cnt1e.aag
 create mode 100644 tests/aiger/empty.aag
 create mode 100644 tests/aiger/false.aag
 create mode 100644 tests/aiger/halfadder.aag
 create mode 100644 tests/aiger/inverter.aag
 create mode 100644 tests/aiger/notcnt1.aag
 create mode 100644 tests/aiger/notcnt1e.aag
 create mode 100644 tests/aiger/or.aag
 create mode 100755 tests/aiger/run-test.sh
 create mode 100644 tests/aiger/toggle-re.aag
 create mode 100644 tests/aiger/toggle.aag
 create mode 100644 tests/aiger/true.aag

(limited to 'tests')

diff --git a/tests/aig/and.aag b/tests/aig/and.aag
deleted file mode 100644
index d1ef2c5a5..000000000
--- a/tests/aig/and.aag
+++ /dev/null
@@ -1,5 +0,0 @@
-aag 3 2 0 1 1
-2
-4
-6
-6 2 4
diff --git a/tests/aig/buffer.aag b/tests/aig/buffer.aag
deleted file mode 100644
index 94a6fb1ed..000000000
--- a/tests/aig/buffer.aag
+++ /dev/null
@@ -1,3 +0,0 @@
-aag 1 1 0 1 0
-2
-2
diff --git a/tests/aig/cnt1.aag b/tests/aig/cnt1.aag
deleted file mode 100644
index ce4f28fcb..000000000
--- a/tests/aig/cnt1.aag
+++ /dev/null
@@ -1,3 +0,0 @@
-aag 1 0 1 0 0 1
-2 3
-2
diff --git a/tests/aig/cnt1e.aag b/tests/aig/cnt1e.aag
deleted file mode 100644
index 6db3f0ffd..000000000
--- a/tests/aig/cnt1e.aag
+++ /dev/null
@@ -1,8 +0,0 @@
-aag 5 1 1 0 3 1
-2
-4 10
-4
-6 5 3
-8 4 2
-10 9 7
-b0 AIGER_NEVER
diff --git a/tests/aig/empty.aag b/tests/aig/empty.aag
deleted file mode 100644
index 40c0f00cb..000000000
--- a/tests/aig/empty.aag
+++ /dev/null
@@ -1 +0,0 @@
-aag 0 0 0 0 0
diff --git a/tests/aig/false.aag b/tests/aig/false.aag
deleted file mode 100644
index 421e64a91..000000000
--- a/tests/aig/false.aag
+++ /dev/null
@@ -1,2 +0,0 @@
-aag 0 0 0 1 0
-0
diff --git a/tests/aig/halfadder.aag b/tests/aig/halfadder.aag
deleted file mode 100644
index 5bf54d38d..000000000
--- a/tests/aig/halfadder.aag
+++ /dev/null
@@ -1,14 +0,0 @@
-aag 7 2 0 2 3
-2
-4
-6
-12
-6 13 15
-12 2 4
-14 3 5
-i0 x
-i1 y
-o0 s
-o1 c
-c
-half adder
diff --git a/tests/aig/inverter.aag b/tests/aig/inverter.aag
deleted file mode 100644
index ff7c28542..000000000
--- a/tests/aig/inverter.aag
+++ /dev/null
@@ -1,3 +0,0 @@
-aag 1 1 0 1 0
-2
-3
diff --git a/tests/aig/notcnt1.aag b/tests/aig/notcnt1.aag
deleted file mode 100644
index e92815f23..000000000
--- a/tests/aig/notcnt1.aag
+++ /dev/null
@@ -1,4 +0,0 @@
-aag 1 0 1 0 0 1
-2 3
-3
-b0 AIGER_NEVER
diff --git a/tests/aig/notcnt1e.aag b/tests/aig/notcnt1e.aag
deleted file mode 100644
index 141c864f7..000000000
--- a/tests/aig/notcnt1e.aag
+++ /dev/null
@@ -1,8 +0,0 @@
-aag 5 1 1 0 3 1
-2
-4 10
-5
-6 5 3
-8 4 2
-10 9 7
-b0 AIGER_NEVER
diff --git a/tests/aig/or.aag b/tests/aig/or.aag
deleted file mode 100644
index f780e339f..000000000
--- a/tests/aig/or.aag
+++ /dev/null
@@ -1,5 +0,0 @@
-aag 3 2 0 1 1
-2
-4
-7
-6 3 5
diff --git a/tests/aig/run-test.sh b/tests/aig/run-test.sh
deleted file mode 100755
index 308578f01..000000000
--- a/tests/aig/run-test.sh
+++ /dev/null
@@ -1,20 +0,0 @@
-#!/bin/bash
-
-OPTIND=1
-seed=""    # default to no seed specified
-while getopts "S:" opt
-do
-    case "$opt" in
-	S) arg="${OPTARG#"${OPTARG%%[![:space:]]*}"}" # remove leading space
-	   seed="SEED=$arg" ;;
-    esac
-done
-shift "$((OPTIND-1))"
-
-# check for Icarus Verilog
-if ! which iverilog > /dev/null ; then
-  echo "$0: Error: Icarus Verilog 'iverilog' not found."
-  exit 1
-fi
-
-exec ${MAKE:-make} -f ../tools/autotest.mk $seed *.aag EXTRA_FLAGS="-f aiger"
diff --git a/tests/aig/toggle-re.aag b/tests/aig/toggle-re.aag
deleted file mode 100644
index b662bb386..000000000
--- a/tests/aig/toggle-re.aag
+++ /dev/null
@@ -1,14 +0,0 @@
-aag 7 2 1 2 4
-2
-4
-6 8
-6
-7
-8 4 10
-10 13 15
-12 2 6
-14 3 7
-i0 enable
-i1 reset
-o0 Q
-o1 !Q
diff --git a/tests/aig/toggle.aag b/tests/aig/toggle.aag
deleted file mode 100644
index 09651012d..000000000
--- a/tests/aig/toggle.aag
+++ /dev/null
@@ -1,4 +0,0 @@
-aag 1 0 1 2 0
-2 3
-2
-3
diff --git a/tests/aig/true.aag b/tests/aig/true.aag
deleted file mode 100644
index 366893648..000000000
--- a/tests/aig/true.aag
+++ /dev/null
@@ -1,2 +0,0 @@
-aag 0 0 0 1 0
-1
diff --git a/tests/aiger/and.aag b/tests/aiger/and.aag
new file mode 100644
index 000000000..d1ef2c5a5
--- /dev/null
+++ b/tests/aiger/and.aag
@@ -0,0 +1,5 @@
+aag 3 2 0 1 1
+2
+4
+6
+6 2 4
diff --git a/tests/aiger/buffer.aag b/tests/aiger/buffer.aag
new file mode 100644
index 000000000..94a6fb1ed
--- /dev/null
+++ b/tests/aiger/buffer.aag
@@ -0,0 +1,3 @@
+aag 1 1 0 1 0
+2
+2
diff --git a/tests/aiger/cnt1.aag b/tests/aiger/cnt1.aag
new file mode 100644
index 000000000..ce4f28fcb
--- /dev/null
+++ b/tests/aiger/cnt1.aag
@@ -0,0 +1,3 @@
+aag 1 0 1 0 0 1
+2 3
+2
diff --git a/tests/aiger/cnt1e.aag b/tests/aiger/cnt1e.aag
new file mode 100644
index 000000000..6db3f0ffd
--- /dev/null
+++ b/tests/aiger/cnt1e.aag
@@ -0,0 +1,8 @@
+aag 5 1 1 0 3 1
+2
+4 10
+4
+6 5 3
+8 4 2
+10 9 7
+b0 AIGER_NEVER
diff --git a/tests/aiger/empty.aag b/tests/aiger/empty.aag
new file mode 100644
index 000000000..40c0f00cb
--- /dev/null
+++ b/tests/aiger/empty.aag
@@ -0,0 +1 @@
+aag 0 0 0 0 0
diff --git a/tests/aiger/false.aag b/tests/aiger/false.aag
new file mode 100644
index 000000000..421e64a91
--- /dev/null
+++ b/tests/aiger/false.aag
@@ -0,0 +1,2 @@
+aag 0 0 0 1 0
+0
diff --git a/tests/aiger/halfadder.aag b/tests/aiger/halfadder.aag
new file mode 100644
index 000000000..5bf54d38d
--- /dev/null
+++ b/tests/aiger/halfadder.aag
@@ -0,0 +1,14 @@
+aag 7 2 0 2 3
+2
+4
+6
+12
+6 13 15
+12 2 4
+14 3 5
+i0 x
+i1 y
+o0 s
+o1 c
+c
+half adder
diff --git a/tests/aiger/inverter.aag b/tests/aiger/inverter.aag
new file mode 100644
index 000000000..ff7c28542
--- /dev/null
+++ b/tests/aiger/inverter.aag
@@ -0,0 +1,3 @@
+aag 1 1 0 1 0
+2
+3
diff --git a/tests/aiger/notcnt1.aag b/tests/aiger/notcnt1.aag
new file mode 100644
index 000000000..e92815f23
--- /dev/null
+++ b/tests/aiger/notcnt1.aag
@@ -0,0 +1,4 @@
+aag 1 0 1 0 0 1
+2 3
+3
+b0 AIGER_NEVER
diff --git a/tests/aiger/notcnt1e.aag b/tests/aiger/notcnt1e.aag
new file mode 100644
index 000000000..141c864f7
--- /dev/null
+++ b/tests/aiger/notcnt1e.aag
@@ -0,0 +1,8 @@
+aag 5 1 1 0 3 1
+2
+4 10
+5
+6 5 3
+8 4 2
+10 9 7
+b0 AIGER_NEVER
diff --git a/tests/aiger/or.aag b/tests/aiger/or.aag
new file mode 100644
index 000000000..f780e339f
--- /dev/null
+++ b/tests/aiger/or.aag
@@ -0,0 +1,5 @@
+aag 3 2 0 1 1
+2
+4
+7
+6 3 5
diff --git a/tests/aiger/run-test.sh b/tests/aiger/run-test.sh
new file mode 100755
index 000000000..308578f01
--- /dev/null
+++ b/tests/aiger/run-test.sh
@@ -0,0 +1,20 @@
+#!/bin/bash
+
+OPTIND=1
+seed=""    # default to no seed specified
+while getopts "S:" opt
+do
+    case "$opt" in
+	S) arg="${OPTARG#"${OPTARG%%[![:space:]]*}"}" # remove leading space
+	   seed="SEED=$arg" ;;
+    esac
+done
+shift "$((OPTIND-1))"
+
+# check for Icarus Verilog
+if ! which iverilog > /dev/null ; then
+  echo "$0: Error: Icarus Verilog 'iverilog' not found."
+  exit 1
+fi
+
+exec ${MAKE:-make} -f ../tools/autotest.mk $seed *.aag EXTRA_FLAGS="-f aiger"
diff --git a/tests/aiger/toggle-re.aag b/tests/aiger/toggle-re.aag
new file mode 100644
index 000000000..b662bb386
--- /dev/null
+++ b/tests/aiger/toggle-re.aag
@@ -0,0 +1,14 @@
+aag 7 2 1 2 4
+2
+4
+6 8
+6
+7
+8 4 10
+10 13 15
+12 2 6
+14 3 7
+i0 enable
+i1 reset
+o0 Q
+o1 !Q
diff --git a/tests/aiger/toggle.aag b/tests/aiger/toggle.aag
new file mode 100644
index 000000000..09651012d
--- /dev/null
+++ b/tests/aiger/toggle.aag
@@ -0,0 +1,4 @@
+aag 1 0 1 2 0
+2 3
+2
+3
diff --git a/tests/aiger/true.aag b/tests/aiger/true.aag
new file mode 100644
index 000000000..366893648
--- /dev/null
+++ b/tests/aiger/true.aag
@@ -0,0 +1,2 @@
+aag 0 0 0 1 0
+1
-- 
cgit v1.2.3


From a9674bd2eca5efac6e4f7b2871a01cbba80f64ec Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddieh@ece.ubc.ca>
Date: Wed, 6 Feb 2019 12:49:30 -0800
Subject: Add testcase

---
 tests/simple/dff_init.v | 10 ++++++++++
 1 file changed, 10 insertions(+)
 create mode 100644 tests/simple/dff_init.v

(limited to 'tests')

diff --git a/tests/simple/dff_init.v b/tests/simple/dff_init.v
new file mode 100644
index 000000000..aad378346
--- /dev/null
+++ b/tests/simple/dff_init.v
@@ -0,0 +1,10 @@
+module dff_test(n1, n1_inv, clk);
+  input clk;
+  (* init = 32'd0 *)
+  output n1;
+  reg n1 = 32'd0;
+  output n1_inv;
+  always @(posedge clk)
+      n1 <= n1_inv;
+  assign n1_inv = ~n1;
+endmodule
-- 
cgit v1.2.3


From 03cf1532a70d705ada69dcb8ae79ae405a86b7da Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddieh@ece.ubc.ca>
Date: Wed, 6 Feb 2019 14:02:11 -0800
Subject: Extend testcase

---
 tests/simple/dff_init.v | 36 ++++++++++++++++++++++++++++++++++--
 1 file changed, 34 insertions(+), 2 deletions(-)

(limited to 'tests')

diff --git a/tests/simple/dff_init.v b/tests/simple/dff_init.v
index aad378346..be947042e 100644
--- a/tests/simple/dff_init.v
+++ b/tests/simple/dff_init.v
@@ -1,6 +1,5 @@
-module dff_test(n1, n1_inv, clk);
+module dff0_test(n1, n1_inv, clk);
   input clk;
-  (* init = 32'd0 *)
   output n1;
   reg n1 = 32'd0;
   output n1_inv;
@@ -8,3 +7,36 @@ module dff_test(n1, n1_inv, clk);
       n1 <= n1_inv;
   assign n1_inv = ~n1;
 endmodule
+
+module dff1_test(n1, n1_inv, clk);
+  input clk;
+  (* init = 32'd1 *)
+  output n1;
+  reg n1 = 32'd1;
+  output n1_inv;
+  always @(posedge clk)
+      n1 <= n1_inv;
+  assign n1_inv = ~n1;
+endmodule
+
+module dff0a_test(n1, n1_inv, clk);
+  input clk;
+  (* init = 32'd0 *) // Must be consistent with reg initialiser below
+  output n1;
+  reg n1 = 32'd0;
+  output n1_inv;
+  always @(posedge clk)
+      n1 <= n1_inv;
+  assign n1_inv = ~n1;
+endmodule
+
+module dff1a_test(n1, n1_inv, clk);
+  input clk;
+  (* init = 32'd1 *) // Must be consistent with reg initialiser below
+  output n1;
+  reg n1 = 32'd1;
+  output n1_inv;
+  always @(posedge clk)
+      n1 <= n1_inv;
+  assign n1_inv = ~n1;
+endmodule
-- 
cgit v1.2.3


From 281f2aadcab01465f83a3f3a697eec42503e9f8b Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddieh@ece.ubc.ca>
Date: Wed, 6 Feb 2019 14:14:55 -0800
Subject: Add -B option to autotest.sh to append to backend_opts

---
 tests/tools/autotest.sh | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

(limited to 'tests')

diff --git a/tests/tools/autotest.sh b/tests/tools/autotest.sh
index d6216244f..800fa3ad5 100755
--- a/tests/tools/autotest.sh
+++ b/tests/tools/autotest.sh
@@ -22,7 +22,7 @@ if [ ! -f $toolsdir/cmp_tbdata -o $toolsdir/cmp_tbdata.c -nt $toolsdir/cmp_tbdat
 	( set -ex; ${CC:-gcc} -Wall -o $toolsdir/cmp_tbdata $toolsdir/cmp_tbdata.c; ) || exit 1
 fi
 
-while getopts xmGl:wkjvref:s:p:n:S:I: opt; do
+while getopts xmGl:wkjvref:s:p:n:S:I:B: opt; do
 	case "$opt" in
 		x)
 			use_xsim=true ;;
@@ -59,8 +59,10 @@ while getopts xmGl:wkjvref:s:p:n:S:I: opt; do
 			include_opts="$include_opts -I $OPTARG"
 			xinclude_opts="$xinclude_opts -i $OPTARG"
 			minclude_opts="$minclude_opts +incdir+$OPTARG" ;;
+        B)
+			backend_opts="$backend_opts $OPTARG" ;;
 		*)
-			echo "Usage: $0 [-x|-m] [-G] [-w] [-k] [-j] [-v] [-r] [-e] [-l libs] [-f frontend] [-s script] [-p cmdstring] [-n iters] [-S seed] [-I incdir] verilog-files\n" >&2
+			echo "Usage: $0 [-x|-m] [-G] [-w] [-k] [-j] [-v] [-r] [-e] [-l libs] [-f frontend] [-s script] [-p cmdstring] [-n iters] [-S seed] [-I incdir] [-B backend_opt] verilog-files\n" >&2
 			exit 1
 	esac
 done
-- 
cgit v1.2.3


From 115883f467cb79688ffb93c136a6ee61368765e8 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddieh@ece.ubc.ca>
Date: Wed, 6 Feb 2019 14:15:17 -0800
Subject: Add tests for simple cases using defparam

---
 tests/simple_defparam/run-test.sh | 21 +++++++++++++++++++++
 1 file changed, 21 insertions(+)
 create mode 100755 tests/simple_defparam/run-test.sh

(limited to 'tests')

diff --git a/tests/simple_defparam/run-test.sh b/tests/simple_defparam/run-test.sh
new file mode 100755
index 000000000..137e15076
--- /dev/null
+++ b/tests/simple_defparam/run-test.sh
@@ -0,0 +1,21 @@
+#!/bin/bash
+
+OPTIND=1
+seed=""    # default to no seed specified
+while getopts "S:" opt
+do
+    case "$opt" in
+	S) arg="${OPTARG#"${OPTARG%%[![:space:]]*}"}" # remove leading space
+	   seed="SEED=$arg" ;;
+    esac
+done
+shift "$((OPTIND-1))"
+
+# check for Icarus Verilog
+if ! which iverilog > /dev/null ; then
+  echo "$0: Error: Icarus Verilog 'iverilog' not found."
+  exit 1
+fi
+
+cp ../simple/*.v .
+exec ${MAKE:-make} -f ../tools/autotest.mk $seed *.v EXTRA_FLAGS="-B \"-defparam\""
-- 
cgit v1.2.3


From 3f87cf86ccefe6e66f768fbf19c34db97cf7246d Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddieh@ece.ubc.ca>
Date: Wed, 6 Feb 2019 14:30:19 -0800
Subject: Revert most of autotest.sh; for non *.v use Yosys to translate

---
 tests/tools/autotest.sh | 16 +++++++++-------
 1 file changed, 9 insertions(+), 7 deletions(-)

(limited to 'tests')

diff --git a/tests/tools/autotest.sh b/tests/tools/autotest.sh
index c01ce5611..3bce003e1 100755
--- a/tests/tools/autotest.sh
+++ b/tests/tools/autotest.sh
@@ -113,16 +113,18 @@ do
 		if [[ "$ext" == "v" ]]; then
 			egrep -v '^\s*`timescale' ../$fn > ${bn}_ref.${ext}
 		else
-			cp ../$fn ${bn}_ref.${ext}
+			"$toolsdir"/../../yosys -f "$frontend $include_opts" -b "verilog" -o ${bn}_ref.v ../${fn}
+			frontend="verilog"
 		fi
 
 		if [ ! -f ../${bn}_tb.v ]; then
-			"$toolsdir"/../../yosys -f "$frontend $include_opts" -b "test_autotb $autotb_opts" -o ${bn}_tb.v ${bn}_ref.${ext}
+			"$toolsdir"/../../yosys -f "$frontend $include_opts" -b "test_autotb $autotb_opts" -o ${bn}_tb.v ${bn}_ref.v
 		else
 			cp ../${bn}_tb.v ${bn}_tb.v
 		fi
 		if $genvcd; then sed -i 's,// \$dump,$dump,g' ${bn}_tb.v; fi
-		compile_and_run ${bn}_tb_ref ${bn}_out_ref ${bn}_tb.v ${bn}_ref.v $libs
+		compile_and_run ${bn}_tb_ref ${bn}_out_ref ${bn}_tb.v ${bn}_ref.v $libs \
+					"$toolsdir"/../../techlibs/common/simlib.v
 		if $genvcd; then mv testbench.vcd ${bn}_ref.vcd; fi
 
 		test_count=0
@@ -143,16 +145,16 @@ do
 		fi
 
 		if [ -n "$scriptfiles" ]; then
-			test_passes -f "$frontend $include_opts" ${bn}_ref.${ext} $scriptfiles
+			test_passes -f "$frontend $include_opts" ${bn}_ref.v $scriptfiles
 		elif [ -n "$scriptopt" ]; then
-			test_passes -f "$frontend $include_opts" -p "$scriptopt" ${bn}_ref.${ext}
+			test_passes -f "$frontend $include_opts" -p "$scriptopt" ${bn}_ref.v
 		elif [ "$frontend" = "verific" ]; then
 			test_passes -p "verific -vlog2k ${bn}_ref.v; verific -import -all; opt; memory;;"
 		elif [ "$frontend" = "verific_gates" ]; then
 			test_passes -p "verific -vlog2k ${bn}_ref.v; verific -import -gates -all; opt; memory;;"
 		else
-			test_passes -f "$frontend $include_opts" -p "hierarchy; proc; opt; memory; opt; fsm; opt -full -fine" ${bn}_ref.${ext}
-			test_passes -f "$frontend $include_opts" -p "hierarchy; synth -run coarse; techmap; opt; abc -dff" ${bn}_ref.${ext}
+			test_passes -f "$frontend $include_opts" -p "hierarchy; proc; opt; memory; opt; fsm; opt -full -fine" ${bn}_ref.v
+			test_passes -f "$frontend $include_opts" -p "hierarchy; synth -run coarse; techmap; opt; abc -dff" ${bn}_ref.v
 		fi
 		touch ../${bn}.log
 	}
-- 
cgit v1.2.3


From 4e6c5e46725bb99e0c919a5f82ce5290da2ce2f9 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddieh@ece.ubc.ca>
Date: Fri, 8 Feb 2019 11:41:25 -0800
Subject: Add binary AIGs converted from AAG

---
 tests/aiger/and.aig       | 3 +++
 tests/aiger/buffer.aig    | 2 ++
 tests/aiger/cnt1.aig      | 3 +++
 tests/aiger/cnt1e.aig     | 4 ++++
 tests/aiger/empty.aig     | 1 +
 tests/aiger/false.aig     | 2 ++
 tests/aiger/halfadder.aig | 9 +++++++++
 tests/aiger/inverter.aig  | 2 ++
 tests/aiger/notcnt1.aig   | 4 ++++
 tests/aiger/notcnt1e.aig  | 4 ++++
 tests/aiger/or.aig        | 3 +++
 tests/aiger/toggle-re.aig | 8 ++++++++
 tests/aiger/toggle.aig    | 4 ++++
 tests/aiger/true.aig      | 2 ++
 14 files changed, 51 insertions(+)
 create mode 100644 tests/aiger/and.aig
 create mode 100644 tests/aiger/buffer.aig
 create mode 100644 tests/aiger/cnt1.aig
 create mode 100644 tests/aiger/cnt1e.aig
 create mode 100644 tests/aiger/empty.aig
 create mode 100644 tests/aiger/false.aig
 create mode 100644 tests/aiger/halfadder.aig
 create mode 100644 tests/aiger/inverter.aig
 create mode 100644 tests/aiger/notcnt1.aig
 create mode 100644 tests/aiger/notcnt1e.aig
 create mode 100644 tests/aiger/or.aig
 create mode 100644 tests/aiger/toggle-re.aig
 create mode 100644 tests/aiger/toggle.aig
 create mode 100644 tests/aiger/true.aig

(limited to 'tests')

diff --git a/tests/aiger/and.aig b/tests/aiger/and.aig
new file mode 100644
index 000000000..da0fa0719
--- /dev/null
+++ b/tests/aiger/and.aig
@@ -0,0 +1,3 @@
+aig 3 2 0 1 1
+6
+
\ No newline at end of file
diff --git a/tests/aiger/buffer.aig b/tests/aiger/buffer.aig
new file mode 100644
index 000000000..0c715fdeb
--- /dev/null
+++ b/tests/aiger/buffer.aig
@@ -0,0 +1,2 @@
+aig 1 1 0 1 0
+2
diff --git a/tests/aiger/cnt1.aig b/tests/aiger/cnt1.aig
new file mode 100644
index 000000000..8d0ba13b1
--- /dev/null
+++ b/tests/aiger/cnt1.aig
@@ -0,0 +1,3 @@
+aig 1 0 1 0 0 1
+3
+2
diff --git a/tests/aiger/cnt1e.aig b/tests/aiger/cnt1e.aig
new file mode 100644
index 000000000..d8d159f11
--- /dev/null
+++ b/tests/aiger/cnt1e.aig
@@ -0,0 +1,4 @@
+aig 5 1 1 0 3 1
+10
+4
+

b0 AIGER_NEVER
diff --git a/tests/aiger/empty.aig b/tests/aiger/empty.aig
new file mode 100644
index 000000000..a28373cd3
--- /dev/null
+++ b/tests/aiger/empty.aig
@@ -0,0 +1 @@
+aig 0 0 0 0 0
diff --git a/tests/aiger/false.aig b/tests/aiger/false.aig
new file mode 100644
index 000000000..ad7d039fa
--- /dev/null
+++ b/tests/aiger/false.aig
@@ -0,0 +1,2 @@
+aig 0 0 0 1 0
+0
diff --git a/tests/aiger/halfadder.aig b/tests/aiger/halfadder.aig
new file mode 100644
index 000000000..83727ee63
--- /dev/null
+++ b/tests/aiger/halfadder.aig
@@ -0,0 +1,9 @@
+aig 5 2 0 2 3
+10
+6
+
i0 x
+i1 y
+o0 s
+o1 c
+c
+half adder
diff --git a/tests/aiger/inverter.aig b/tests/aiger/inverter.aig
new file mode 100644
index 000000000..525d82392
--- /dev/null
+++ b/tests/aiger/inverter.aig
@@ -0,0 +1,2 @@
+aig 1 1 0 1 0
+3
diff --git a/tests/aiger/notcnt1.aig b/tests/aiger/notcnt1.aig
new file mode 100644
index 000000000..f8a667f1f
--- /dev/null
+++ b/tests/aiger/notcnt1.aig
@@ -0,0 +1,4 @@
+aig 1 0 1 0 0 1
+3
+3
+b0 AIGER_NEVER
diff --git a/tests/aiger/notcnt1e.aig b/tests/aiger/notcnt1e.aig
new file mode 100644
index 000000000..7c85a7290
--- /dev/null
+++ b/tests/aiger/notcnt1e.aig
@@ -0,0 +1,4 @@
+aig 5 1 1 0 3 1
+10
+5
+

b0 AIGER_NEVER
diff --git a/tests/aiger/or.aig b/tests/aiger/or.aig
new file mode 100644
index 000000000..75c9e4480
--- /dev/null
+++ b/tests/aiger/or.aig
@@ -0,0 +1,3 @@
+aig 3 2 0 1 1
+7
+

\ No newline at end of file
diff --git a/tests/aiger/toggle-re.aig b/tests/aiger/toggle-re.aig
new file mode 100644
index 000000000..9d6730f21
--- /dev/null
+++ b/tests/aiger/toggle-re.aig
@@ -0,0 +1,8 @@
+aig 7 2 1 2 4
+14
+6
+7
+
i0 enable
+i1 reset
+o0 Q
+o1 !Q
diff --git a/tests/aiger/toggle.aig b/tests/aiger/toggle.aig
new file mode 100644
index 000000000..b69e21aaf
--- /dev/null
+++ b/tests/aiger/toggle.aig
@@ -0,0 +1,4 @@
+aig 1 0 1 2 0
+3
+2
+3
diff --git a/tests/aiger/true.aig b/tests/aiger/true.aig
new file mode 100644
index 000000000..10086f389
--- /dev/null
+++ b/tests/aiger/true.aig
@@ -0,0 +1,2 @@
+aig 0 0 0 1 0
+1
-- 
cgit v1.2.3


From 587872236ecd1ca2f2a466bccc8d41618feb0dfb Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddieh@ece.ubc.ca>
Date: Fri, 8 Feb 2019 12:41:59 -0800
Subject: Support and differentiate between ASCII and binary AIG testing

---
 tests/aiger/run-test.sh | 6 +++++-
 tests/tools/autotest.sh | 2 +-
 2 files changed, 6 insertions(+), 2 deletions(-)

(limited to 'tests')

diff --git a/tests/aiger/run-test.sh b/tests/aiger/run-test.sh
index 308578f01..e0a34f023 100755
--- a/tests/aiger/run-test.sh
+++ b/tests/aiger/run-test.sh
@@ -17,4 +17,8 @@ if ! which iverilog > /dev/null ; then
   exit 1
 fi
 
-exec ${MAKE:-make} -f ../tools/autotest.mk $seed *.aag EXTRA_FLAGS="-f aiger"
+echo "===== AAG ======"
+${MAKE:-make} -f ../tools/autotest.mk $seed *.aag EXTRA_FLAGS="-f aiger"
+
+echo "===== AIG ======"
+exec ${MAKE:-make} -f ../tools/autotest.mk $seed *.aig EXTRA_FLAGS="-f aiger"
diff --git a/tests/tools/autotest.sh b/tests/tools/autotest.sh
index 3e1325b33..0ffa062e3 100755
--- a/tests/tools/autotest.sh
+++ b/tests/tools/autotest.sh
@@ -90,7 +90,7 @@ for fn
 do
 	bn=${fn%.*}
 	ext=${fn##*.}
-	if [[ "$ext" != "v" ]] && [[ "$ext" != "aag" ]]; then
+	if [[ "$ext" != "v" ]] && [[ "$ext" != "aag" ]] && [[ "$ext" != "aig" ]]; then
 		echo "Invalid argument: $fn" >&2
 		exit 1
 	fi
-- 
cgit v1.2.3


From fc1c9aa11fbfbb1ea5b63e1830549d453ba01dfb Mon Sep 17 00:00:00 2001
From: Jim Lawson <ucbjrl@berkeley.edu>
Date: Fri, 15 Feb 2019 11:14:17 -0800
Subject: Update cells supported for verilog to FIRRTL conversion. Issue
 warning messages for missing parameterized modules and attempts to set
 initial values. Replace simple "if (cell-type)" with "else if" chain. Fix
 FIRRTL shift handling. Add support for parameterized modules, $shift,
 $shiftx. Handle default output file. Deal with no top module. Automatically
 run pmuxtree pass. Allow EXTRA_FLAGS and SEED parameters to be set in the
 environment for tests/tools/autotest.mk. Support FIRRTL regression testing in
 tests/tools/autotest.sh Add xfirrtl files to test directories to exclude
 files from FIRRTL regression tests that are known to fail.

---
 tests/asicworld/xfirrtl | 24 ++++++++++++++++++++++++
 tests/simple/xfirrtl    | 26 ++++++++++++++++++++++++++
 tests/tools/autotest.mk |  6 +++---
 tests/tools/autotest.sh | 43 +++++++++++++++++++++++++++++++++++++++----
 4 files changed, 92 insertions(+), 7 deletions(-)
 create mode 100644 tests/asicworld/xfirrtl
 create mode 100644 tests/simple/xfirrtl

(limited to 'tests')

diff --git a/tests/asicworld/xfirrtl b/tests/asicworld/xfirrtl
new file mode 100644
index 000000000..c782a2bd6
--- /dev/null
+++ b/tests/asicworld/xfirrtl
@@ -0,0 +1,24 @@
+# This file contains the names of verilog files to exclude from verilog to FIRRTL regression tests due to known failures.
+code_hdl_models_arbiter.v	error: reg rst; cannot be driven by primitives or continuous assignment.
+code_hdl_models_clk_div_45.v	yosys issue: 2nd PMUXTREE pass yields: ERROR: Negative edge clock on FF clk_div_45.$procdff$49.
+code_hdl_models_d_ff_gates.v	combinational loop
+code_hdl_models_d_latch_gates.v	combinational loop
+code_hdl_models_dff_async_reset.v	$adff
+code_hdl_models_tff_async_reset.v	$adff
+code_hdl_models_uart.v	$adff
+code_specman_switch_fabric.v	subfield assignment (bits() <= ...)
+code_tidbits_asyn_reset.v	$adff
+code_tidbits_reg_seq_example.v	$adff
+code_verilog_tutorial_always_example.v	empty module
+code_verilog_tutorial_escape_id.v	make_id issues (name begins with a digit)
+code_verilog_tutorial_explicit.v	firrtl backend bug (empty module)
+code_verilog_tutorial_first_counter.v	error: reg rst; cannot be driven by primitives or continuous assignment.
+code_verilog_tutorial_fsm_full.v	error: reg reset; cannot be driven by primitives or continuous assignment.
+code_verilog_tutorial_if_else.v	empty module (everything is under 'always @ (posedge clk)')
+[code_verilog_tutorial_n_out_primitive.v	empty module
+code_verilog_tutorial_parallel_if.v	empty module (everything is under 'always @ (posedge clk)')
+code_verilog_tutorial_simple_function.v	empty module (no hardware)
+code_verilog_tutorial_simple_if.v	empty module (everything is under 'always @ (posedge clk)')
+code_verilog_tutorial_task_global.v	empty module (everything is under 'always @ (posedge clk)')
+code_verilog_tutorial_v2k_reg.v		empty module
+code_verilog_tutorial_which_clock.v	 $adff
diff --git a/tests/simple/xfirrtl b/tests/simple/xfirrtl
new file mode 100644
index 000000000..00e89b389
--- /dev/null
+++ b/tests/simple/xfirrtl
@@ -0,0 +1,26 @@
+# This file contains the names of verilog files to exclude from verilog to FIRRTL regression tests due to known failures.
+arraycells.v	inst id[0] of
+dff_different_styles.v
+generate.v	combinational loop
+hierdefparam.v	inst id[0] of
+i2c_master_tests.v   $adff
+macros.v	drops modules
+mem2reg.v	drops modules
+mem_arst.v	$adff
+memory.v	$adff
+multiplier.v	inst id[0] of
+muxtree.v	drops modules
+omsp_dbg_uart.v	$adff
+operators.v	$pow
+paramods.v	subfield assignment (bits() <= ...)
+partsel.v	drops modules
+process.v	drops modules
+realexpr.v	drops modules
+scopes.v	original verilog issues ( -x where x isn't declared signed)
+sincos.v	$adff
+specify.v	no code (empty module generates error
+subbytes.v	$adff
+task_func.v	drops modules
+values.v	combinational loop
+vloghammer.v	combinational loop
+wreduce.v	original verilog issues ( -x where x isn't declared signed)
diff --git a/tests/tools/autotest.mk b/tests/tools/autotest.mk
index c68678929..e0f2bcdc1 100644
--- a/tests/tools/autotest.mk
+++ b/tests/tools/autotest.mk
@@ -1,7 +1,7 @@
 
-EXTRA_FLAGS=
-SEED=
-
+# Don't bother defining default values for SEED and EXTRA_FLAGS.
+# Their "natural" default values should be sufficient,
+#   and they may be overridden in the environment.
 ifneq ($(strip $(SEED)),)
 SEEDOPT=-S$(SEED)
 endif
diff --git a/tests/tools/autotest.sh b/tests/tools/autotest.sh
index d6216244f..218edf931 100755
--- a/tests/tools/autotest.sh
+++ b/tests/tools/autotest.sh
@@ -17,12 +17,18 @@ scriptfiles=""
 scriptopt=""
 toolsdir="$(cd $(dirname $0); pwd)"
 warn_iverilog_git=false
+# The following are used in verilog to firrtl regression tests.
+# Typically these will be passed as environment variables:
+#EXTRA_FLAGS="--firrtl2verilog 'java -cp /.../firrtl/utils/bin/firrtl.jar firrtl.Driver'"
+# The tests are skipped if firrtl2verilog is the empty string (the default).
+firrtl2verilog=""
+xfirrtl="../xfirrtl"
 
 if [ ! -f $toolsdir/cmp_tbdata -o $toolsdir/cmp_tbdata.c -nt $toolsdir/cmp_tbdata ]; then
 	( set -ex; ${CC:-gcc} -Wall -o $toolsdir/cmp_tbdata $toolsdir/cmp_tbdata.c; ) || exit 1
 fi
 
-while getopts xmGl:wkjvref:s:p:n:S:I: opt; do
+while getopts xmGl:wkjvref:s:p:n:S:I:-: opt; do
 	case "$opt" in
 		x)
 			use_xsim=true ;;
@@ -59,8 +65,24 @@ while getopts xmGl:wkjvref:s:p:n:S:I: opt; do
 			include_opts="$include_opts -I $OPTARG"
 			xinclude_opts="$xinclude_opts -i $OPTARG"
 			minclude_opts="$minclude_opts +incdir+$OPTARG" ;;
+		-)
+			case "${OPTARG}" in
+			    xfirrtl)
+			    	xfirrtl="${!OPTIND}"
+				OPTIND=$(( $OPTIND + 1 ))
+				;;
+			    firrtl2verilog)
+			    	firrtl2verilog="${!OPTIND}"
+				OPTIND=$(( $OPTIND + 1 ))
+				;;
+			    *)
+			    	if [ "$OPTERR" == 1 ] && [ "${optspec:0:1}" != ":" ]; then
+				    echo "Unknown option --${OPTARG}" >&2
+				fi
+				;;
+			esac;;
 		*)
-			echo "Usage: $0 [-x|-m] [-G] [-w] [-k] [-j] [-v] [-r] [-e] [-l libs] [-f frontend] [-s script] [-p cmdstring] [-n iters] [-S seed] [-I incdir] verilog-files\n" >&2
+			echo "Usage: $0 [-x|-m] [-G] [-w] [-k] [-j] [-v] [-r] [-e] [-l libs] [-f frontend] [-s script] [-p cmdstring] [-n iters] [-S seed] [-I incdir] [--xfirrtl FIRRTL test exclude file] [--firrtl2verilog command to generate verilog from firrtl] verilog-files\n" >&2
 			exit 1
 	esac
 done
@@ -109,6 +131,8 @@ do
 		fn=$(basename $fn)
 		bn=$(basename $bn)
 
+		rm -f ${bn}_ref.fir
+
 		egrep -v '^\s*`timescale' ../$fn > ${bn}_ref.v
 
 		if [ ! -f ../${bn}_tb.v ]; then
@@ -148,6 +172,13 @@ do
 		else
 			test_passes -f "$frontend $include_opts" -p "hierarchy; proc; opt; memory; opt; fsm; opt -full -fine" ${bn}_ref.v
 			test_passes -f "$frontend $include_opts" -p "hierarchy; synth -run coarse; techmap; opt; abc -dff" ${bn}_ref.v
+			if [ -n "$firrtl2verilog" ]; then
+			    if test -z "$xfirrtl" || ! grep "$fn" "$xfirrtl" ; then
+				"$toolsdir"/../../yosys -b "firrtl" -o ${bn}_ref.fir -f "$frontend $include_opts" -p "prep -nordff; proc; opt; memory; opt; fsm; opt -full -fine; pmuxtree" ${bn}_ref.v
+				$firrtl2verilog -i ${bn}_ref.fir -o ${bn}_ref.fir.v  -X verilog
+				test_passes -f "$frontend $include_opts" -p "hierarchy; proc; opt; memory; opt; fsm; opt -full -fine" ${bn}_ref.fir.v
+			    fi
+			fi
 		fi
 		touch ../${bn}.log
 	}
@@ -160,14 +191,18 @@ do
 		( set -ex; body; ) > ${bn}.err 2>&1
 	fi
 
+	did_firrtl=""
+	if [ -f ${bn}.out/${bn}_ref.fir ]; then
+	    did_firrtl="+FIRRTL "
+	fi
 	if [ -f ${bn}.log ]; then
 		mv ${bn}.err ${bn}.log
-		echo "${status_prefix}-> ok"
+		echo "${status_prefix}${did_firrtl}-> ok"
 	elif [ -f ${bn}.skip ]; then
 		mv ${bn}.err ${bn}.skip
 		echo "${status_prefix}-> skip"
 	else
-		echo "${status_prefix}-> ERROR!"
+		echo "${status_prefix}${did_firrtl}-> ERROR!"
 		if $warn_iverilog_git; then
 			echo "Note: Make sure that 'iverilog' is an up-to-date git checkout of Icarus Verilog."
 		fi
-- 
cgit v1.2.3


From 34153adef408bc226430f05d14cd4af9384359f9 Mon Sep 17 00:00:00 2001
From: Jim Lawson <ucbjrl@berkeley.edu>
Date: Fri, 15 Feb 2019 11:56:51 -0800
Subject: Append (instead of over-writing) EXTRA_FLAGS

---
 tests/asicworld/run-test.sh | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'tests')

diff --git a/tests/asicworld/run-test.sh b/tests/asicworld/run-test.sh
index d5708c456..c22ab6928 100755
--- a/tests/asicworld/run-test.sh
+++ b/tests/asicworld/run-test.sh
@@ -11,4 +11,4 @@ do
 done
 shift "$((OPTIND-1))"
 
-exec ${MAKE:-make} -f ../tools/autotest.mk $seed EXTRA_FLAGS="-e" *.v
+exec ${MAKE:-make} -f ../tools/autotest.mk $seed EXTRA_FLAGS+="-e" *.v
-- 
cgit v1.2.3


From 430a7548bca6046c812f713877253f8c3d81d805 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddieh@ece.ubc.ca>
Date: Sun, 17 Feb 2019 11:50:55 -0800
Subject: One more merge conflict

---
 tests/tools/autotest.sh | 7 +------
 1 file changed, 1 insertion(+), 6 deletions(-)

(limited to 'tests')

diff --git a/tests/tools/autotest.sh b/tests/tools/autotest.sh
index 2722cba19..b5abc3570 100755
--- a/tests/tools/autotest.sh
+++ b/tests/tools/autotest.sh
@@ -134,18 +134,13 @@ do
 		fn=$(basename $fn)
 		bn=$(basename $bn)
 
-<<<<<<< HEAD
+		rm -f ${bn}_ref.fir
 		if [[ "$ext" == "v" ]]; then
 			egrep -v '^\s*`timescale' ../$fn > ${bn}_ref.${ext}
 		else
 			"$toolsdir"/../../yosys -f "$frontend $include_opts" -b "verilog" -o ${bn}_ref.v ../${fn}
 			frontend="verilog"
 		fi
-=======
-		rm -f ${bn}_ref.fir
-
-		egrep -v '^\s*`timescale' ../$fn > ${bn}_ref.v
->>>>>>> e45f62b0c56717a23099425f078d1e56212aa632
 
 		if [ ! -f ../${bn}_tb.v ]; then
 			"$toolsdir"/../../yosys -f "$frontend $include_opts" -b "test_autotb $autotb_opts" -o ${bn}_tb.v ${bn}_ref.v
-- 
cgit v1.2.3


From 5c4a72c43ef61420b4b099d87949b0fdba0f4b55 Mon Sep 17 00:00:00 2001
From: Jim Lawson <ucbjrl@berkeley.edu>
Date: Tue, 19 Feb 2019 14:35:15 -0800
Subject: Fix normal (non-array) hierarchy -auto-top. Add simple test.

---
 tests/various/hierarchy.sh | 56 ++++++++++++++++++++++++++++++++++++++++++++++
 tests/various/run-test.sh  | 10 ++++++++-
 2 files changed, 65 insertions(+), 1 deletion(-)
 create mode 100644 tests/various/hierarchy.sh

(limited to 'tests')

diff --git a/tests/various/hierarchy.sh b/tests/various/hierarchy.sh
new file mode 100644
index 000000000..dcb4dc056
--- /dev/null
+++ b/tests/various/hierarchy.sh
@@ -0,0 +1,56 @@
+#!/usr/bin/env bash
+# Simple test of hierarchy -auto-top.
+
+set -e
+
+../../yosys -q -s - <<- EOY 2>&1 | grep "Automatically selected TOP as design top module"
+  read_verilog << EOV
+    module TOP(a, y);
+      input a;
+      output [31:0] y;
+
+      aoi12 p [31:0] (a, y);
+    endmodule
+
+    module aoi12(a, y);
+      input a;
+      output y;
+      assign y = ~a;
+    endmodule
+  EOV
+  hierarchy -auto-top
+EOY
+
+../../yosys -q -s - <<- EOY 2>&1 | grep "Automatically selected TOP as design top module"
+  read_verilog << EOV
+    module aoi12(a, y);
+      input a;
+      output y;
+      assign y = ~a;
+    endmodule
+
+    module TOP(a, y);
+      input a;
+      output [31:0] y;
+
+      aoi12 foo (a, y);
+    endmodule
+  EOV
+  hierarchy -auto-top
+EOY
+
+../../yosys -q -s - <<- EOY 2>&1 | grep "Automatically selected noTop as design top module."
+  read_verilog << EOV
+    module aoi12(a, y);
+      input a;
+      output y;
+      assign y = ~a;
+    endmodule
+
+    module noTop(a, y);
+      input a;
+      output [31:0] y;
+    endmodule
+  EOV
+  hierarchy -auto-top
+EOY
diff --git a/tests/various/run-test.sh b/tests/various/run-test.sh
index 67e1beb23..7cd1a8650 100755
--- a/tests/various/run-test.sh
+++ b/tests/various/run-test.sh
@@ -1,6 +1,14 @@
-#!/bin/bash
+#!/usr/bin/env bash
 set -e
 for x in *.ys; do
 	echo "Running $x.."
 	../../yosys -ql ${x%.ys}.log $x
 done
+# Run any .sh files in this directory (with the exception of the file - run-test.sh
+shell_tests=$(echo *.sh | sed -e 's/run-test.sh//')
+if [ "$shell_tests" ]; then
+    for s in $shell_tests; do
+        echo "Running $s.."
+        bash $s >& ${s%.sh}.log
+    done
+fi
-- 
cgit v1.2.3


From 4035ec8933cd187670788fb6eca5cefa80fe7170 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddieh@ece.ubc.ca>
Date: Wed, 20 Feb 2019 15:45:45 -0800
Subject: Remove simple_defparam tests

---
 tests/simple_defparam/run-test.sh | 21 ---------------------
 1 file changed, 21 deletions(-)
 delete mode 100755 tests/simple_defparam/run-test.sh

(limited to 'tests')

diff --git a/tests/simple_defparam/run-test.sh b/tests/simple_defparam/run-test.sh
deleted file mode 100755
index 137e15076..000000000
--- a/tests/simple_defparam/run-test.sh
+++ /dev/null
@@ -1,21 +0,0 @@
-#!/bin/bash
-
-OPTIND=1
-seed=""    # default to no seed specified
-while getopts "S:" opt
-do
-    case "$opt" in
-	S) arg="${OPTARG#"${OPTARG%%[![:space:]]*}"}" # remove leading space
-	   seed="SEED=$arg" ;;
-    esac
-done
-shift "$((OPTIND-1))"
-
-# check for Icarus Verilog
-if ! which iverilog > /dev/null ; then
-  echo "$0: Error: Icarus Verilog 'iverilog' not found."
-  exit 1
-fi
-
-cp ../simple/*.v .
-exec ${MAKE:-make} -f ../tools/autotest.mk $seed *.v EXTRA_FLAGS="-B \"-defparam\""
-- 
cgit v1.2.3


From 8e789da74c6702ededc668e3dbd899de8d0c2821 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddieh@ece.ubc.ca>
Date: Thu, 21 Feb 2019 09:22:29 -0800
Subject: Revert "Add -B option to autotest.sh to append to backend_opts"

This reverts commit 281f2aadcab01465f83a3f3a697eec42503e9f8b.
---
 tests/tools/autotest.sh | 6 ++----
 1 file changed, 2 insertions(+), 4 deletions(-)

(limited to 'tests')

diff --git a/tests/tools/autotest.sh b/tests/tools/autotest.sh
index 6fdd1e80a..218edf931 100755
--- a/tests/tools/autotest.sh
+++ b/tests/tools/autotest.sh
@@ -28,7 +28,7 @@ if [ ! -f $toolsdir/cmp_tbdata -o $toolsdir/cmp_tbdata.c -nt $toolsdir/cmp_tbdat
 	( set -ex; ${CC:-gcc} -Wall -o $toolsdir/cmp_tbdata $toolsdir/cmp_tbdata.c; ) || exit 1
 fi
 
-while getopts xmGl:wkjvref:s:p:n:S:I:B:-: opt; do
+while getopts xmGl:wkjvref:s:p:n:S:I:-: opt; do
 	case "$opt" in
 		x)
 			use_xsim=true ;;
@@ -65,8 +65,6 @@ while getopts xmGl:wkjvref:s:p:n:S:I:B:-: opt; do
 			include_opts="$include_opts -I $OPTARG"
 			xinclude_opts="$xinclude_opts -i $OPTARG"
 			minclude_opts="$minclude_opts +incdir+$OPTARG" ;;
-        B)
-			backend_opts="$backend_opts $OPTARG" ;;
 		-)
 			case "${OPTARG}" in
 			    xfirrtl)
@@ -84,7 +82,7 @@ while getopts xmGl:wkjvref:s:p:n:S:I:B:-: opt; do
 				;;
 			esac;;
 		*)
-			echo "Usage: $0 [-x|-m] [-G] [-w] [-k] [-j] [-v] [-r] [-e] [-l libs] [-f frontend] [-s script] [-p cmdstring] [-n iters] [-S seed] [-I incdir] [-B backend_opt] [--xfirrtl FIRRTL test exclude file] [--firrtl2verilog command to generate verilog from firrtl] verilog-files\n" >&2
+			echo "Usage: $0 [-x|-m] [-G] [-w] [-k] [-j] [-v] [-r] [-e] [-l libs] [-f frontend] [-s script] [-p cmdstring] [-n iters] [-S seed] [-I incdir] [--xfirrtl FIRRTL test exclude file] [--firrtl2verilog command to generate verilog from firrtl] verilog-files\n" >&2
 			exit 1
 	esac
 done
-- 
cgit v1.2.3


From 25680f6a078bb32f157bd580705656496717bafb Mon Sep 17 00:00:00 2001
From: Keith Rothman <537074+litghost@users.noreply.github.com>
Date: Fri, 22 Feb 2019 10:28:28 -0800
Subject: Fix WREDUCE on FF not fixing ARST_VALUE parameter.

Adds test case that fails without code change.

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
---
 tests/opt/opt_ff.v  | 21 +++++++++++++++++++++
 tests/opt/opt_ff.ys |  3 +++
 2 files changed, 24 insertions(+)
 create mode 100644 tests/opt/opt_ff.v
 create mode 100644 tests/opt/opt_ff.ys

(limited to 'tests')

diff --git a/tests/opt/opt_ff.v b/tests/opt/opt_ff.v
new file mode 100644
index 000000000..a01b64b61
--- /dev/null
+++ b/tests/opt/opt_ff.v
@@ -0,0 +1,21 @@
+module top(
+    input clk,
+    input rst,
+    input [2:0] a,
+    output [1:0] b
+);
+    reg [2:0] b_reg;
+    initial begin
+        b_reg <= 3'b0;
+    end
+
+    assign b = b_reg[1:0];
+    always @(posedge clk or posedge rst) begin
+        if(rst) begin
+            b_reg <= 3'b0;
+        end else begin
+            b_reg <= a;
+        end
+    end
+endmodule
+
diff --git a/tests/opt/opt_ff.ys b/tests/opt/opt_ff.ys
new file mode 100644
index 000000000..704c7acf3
--- /dev/null
+++ b/tests/opt/opt_ff.ys
@@ -0,0 +1,3 @@
+read_verilog opt_ff.v
+synth_ice40
+ice40_unlut
-- 
cgit v1.2.3


From 71bcc4c644b0dafa760ff8b6d7bd1109836be621 Mon Sep 17 00:00:00 2001
From: Jim Lawson <ucbjrl@berkeley.edu>
Date: Fri, 22 Feb 2019 16:06:10 -0800
Subject: Address requested changes - don't require non-$ name. Suppress
 warning if name does begin with a `$`. Fix hierachy tests so they have
 something to grep. Announce hierarchy test types.

---
 tests/various/hierarchy.sh | 9 ++++++---
 tests/various/run-test.sh  | 2 +-
 2 files changed, 7 insertions(+), 4 deletions(-)

(limited to 'tests')

diff --git a/tests/various/hierarchy.sh b/tests/various/hierarchy.sh
index dcb4dc056..d33a247be 100644
--- a/tests/various/hierarchy.sh
+++ b/tests/various/hierarchy.sh
@@ -3,7 +3,8 @@
 
 set -e
 
-../../yosys -q -s - <<- EOY 2>&1 | grep "Automatically selected TOP as design top module"
+echo -n "  TOP first - "
+../../yosys -s - <<- EOY | grep "Automatically selected TOP as design top module"
   read_verilog << EOV
     module TOP(a, y);
       input a;
@@ -21,7 +22,8 @@ set -e
   hierarchy -auto-top
 EOY
 
-../../yosys -q -s - <<- EOY 2>&1 | grep "Automatically selected TOP as design top module"
+echo -n "  TOP last - "
+../../yosys -s - <<- EOY | grep "Automatically selected TOP as design top module"
   read_verilog << EOV
     module aoi12(a, y);
       input a;
@@ -39,7 +41,8 @@ EOY
   hierarchy -auto-top
 EOY
 
-../../yosys -q -s - <<- EOY 2>&1 | grep "Automatically selected noTop as design top module."
+echo -n "  no explicit top - "
+../../yosys -s - <<- EOY | grep "Automatically selected noTop as design top module."
   read_verilog << EOV
     module aoi12(a, y);
       input a;
diff --git a/tests/various/run-test.sh b/tests/various/run-test.sh
index 7cd1a8650..d49553ede 100755
--- a/tests/various/run-test.sh
+++ b/tests/various/run-test.sh
@@ -9,6 +9,6 @@ shell_tests=$(echo *.sh | sed -e 's/run-test.sh//')
 if [ "$shell_tests" ]; then
     for s in $shell_tests; do
         echo "Running $s.."
-        bash $s >& ${s%.sh}.log
+        bash $s
     done
 fi
-- 
cgit v1.2.3


From 1816fe06af9ab2c50bd293dc10359238acc88f12 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Sun, 24 Feb 2019 20:09:41 +0100
Subject: Fix handling of defparam for when default_nettype is none

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 tests/simple/hierdefparam.v | 2 ++
 1 file changed, 2 insertions(+)

(limited to 'tests')

diff --git a/tests/simple/hierdefparam.v b/tests/simple/hierdefparam.v
index ff92c38bd..c9368ca7a 100644
--- a/tests/simple/hierdefparam.v
+++ b/tests/simple/hierdefparam.v
@@ -1,3 +1,5 @@
+`default_nettype none
+
 module hierdefparam_top(input [7:0] A, output [7:0] Y);
   generate begin:foo
     hierdefparam_a mod_a(.A(A), .Y(Y));
-- 
cgit v1.2.3


From 171c425cf9addb61ef3f03596fd26355ed8af76d Mon Sep 17 00:00:00 2001
From: Jim Lawson <ucbjrl@berkeley.edu>
Date: Mon, 25 Feb 2019 16:18:13 -0800
Subject: Fix FIRRTL to Verilog process instance subfield assignment. Don't
 emit subfield assignments: bits(x, y, z) <= ... - but instead, add them to
 the reverse-wire-map where they'll be treated at the end of the module.
 Enable tests which were disabled due to incorrect treatment of subfields.
 Assume the `$firrtl2verilog` variable contains any additional switches to
 control verilog generation (i.e. `--no-dedup -X mverilog`)

---
 tests/asicworld/xfirrtl | 1 -
 tests/simple/xfirrtl    | 1 -
 tests/tools/autotest.sh | 2 +-
 3 files changed, 1 insertion(+), 3 deletions(-)

(limited to 'tests')

diff --git a/tests/asicworld/xfirrtl b/tests/asicworld/xfirrtl
index c782a2bd6..08bf4ccd8 100644
--- a/tests/asicworld/xfirrtl
+++ b/tests/asicworld/xfirrtl
@@ -6,7 +6,6 @@ code_hdl_models_d_latch_gates.v	combinational loop
 code_hdl_models_dff_async_reset.v	$adff
 code_hdl_models_tff_async_reset.v	$adff
 code_hdl_models_uart.v	$adff
-code_specman_switch_fabric.v	subfield assignment (bits() <= ...)
 code_tidbits_asyn_reset.v	$adff
 code_tidbits_reg_seq_example.v	$adff
 code_verilog_tutorial_always_example.v	empty module
diff --git a/tests/simple/xfirrtl b/tests/simple/xfirrtl
index 00e89b389..5bc75347b 100644
--- a/tests/simple/xfirrtl
+++ b/tests/simple/xfirrtl
@@ -12,7 +12,6 @@ multiplier.v	inst id[0] of
 muxtree.v	drops modules
 omsp_dbg_uart.v	$adff
 operators.v	$pow
-paramods.v	subfield assignment (bits() <= ...)
 partsel.v	drops modules
 process.v	drops modules
 realexpr.v	drops modules
diff --git a/tests/tools/autotest.sh b/tests/tools/autotest.sh
index 218edf931..99ec3e7cd 100755
--- a/tests/tools/autotest.sh
+++ b/tests/tools/autotest.sh
@@ -175,7 +175,7 @@ do
 			if [ -n "$firrtl2verilog" ]; then
 			    if test -z "$xfirrtl" || ! grep "$fn" "$xfirrtl" ; then
 				"$toolsdir"/../../yosys -b "firrtl" -o ${bn}_ref.fir -f "$frontend $include_opts" -p "prep -nordff; proc; opt; memory; opt; fsm; opt -full -fine; pmuxtree" ${bn}_ref.v
-				$firrtl2verilog -i ${bn}_ref.fir -o ${bn}_ref.fir.v  -X verilog
+				$firrtl2verilog -i ${bn}_ref.fir -o ${bn}_ref.fir.v
 				test_passes -f "$frontend $include_opts" -p "hierarchy; proc; opt; memory; opt; fsm; opt -full -fine" ${bn}_ref.fir.v
 			    fi
 			fi
-- 
cgit v1.2.3


From 241901461ae02c6a41837e254088f277b8167476 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Thu, 28 Feb 2019 14:56:55 -0800
Subject: Add "write_verilog -siminit"

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 tests/tools/autotest.sh | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'tests')

diff --git a/tests/tools/autotest.sh b/tests/tools/autotest.sh
index 99ec3e7cd..0b9aceacc 100755
--- a/tests/tools/autotest.sh
+++ b/tests/tools/autotest.sh
@@ -8,7 +8,7 @@ verbose=false
 keeprunning=false
 makejmode=false
 frontend="verilog"
-backend_opts="-noattr -noexpr"
+backend_opts="-noattr -noexpr -siminit"
 autotb_opts=""
 include_opts=""
 xinclude_opts=""
-- 
cgit v1.2.3


From b84febafd75bc66d64cdc573265e086800b3e420 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Thu, 28 Feb 2019 20:26:54 -0800
Subject: Hotfix for "make test"

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 tests/tools/autotest.sh | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'tests')

diff --git a/tests/tools/autotest.sh b/tests/tools/autotest.sh
index 0b9aceacc..84e62e011 100755
--- a/tests/tools/autotest.sh
+++ b/tests/tools/autotest.sh
@@ -49,7 +49,7 @@ while getopts xmGl:wkjvref:s:p:n:S:I:-: opt; do
 		r)
 			backend_opts="$backend_opts -norename" ;;
 		e)
-			backend_opts="$( echo " $backend_opts " | sed 's, -noexpr ,,; s,^ ,,; s, $,,;'; )" ;;
+			backend_opts="$( echo " $backend_opts " | sed 's, -noexpr , ,; s,^ ,,; s, $,,;'; )" ;;
 		f)
 			frontend="$OPTARG" ;;
 		s)
-- 
cgit v1.2.3


From d6c4dfb9020ee19eebe3adadca89b65627184d81 Mon Sep 17 00:00:00 2001
From: Jim Lawson <ucbjrl@berkeley.edu>
Date: Mon, 4 Mar 2019 13:23:58 -0800
Subject: Ensure fid() calls make_id() for consistency; tests/simple/dff_init.v
 fails Mark dff_init.v as expected to fail since it uses "initial value".

---
 tests/simple/xfirrtl | 1 +
 1 file changed, 1 insertion(+)

(limited to 'tests')

diff --git a/tests/simple/xfirrtl b/tests/simple/xfirrtl
index 5bc75347b..50d693513 100644
--- a/tests/simple/xfirrtl
+++ b/tests/simple/xfirrtl
@@ -1,6 +1,7 @@
 # This file contains the names of verilog files to exclude from verilog to FIRRTL regression tests due to known failures.
 arraycells.v	inst id[0] of
 dff_different_styles.v
+dff_init.v	Initial value not supported
 generate.v	combinational loop
 hierdefparam.v	inst id[0] of
 i2c_master_tests.v   $adff
-- 
cgit v1.2.3


From a330c6836318d43d52cda68959f2b86c2b2ede9c Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Thu, 7 Mar 2019 22:44:37 -0800
Subject: Fix handling of task output ports in clocked always blocks, fixes
 #857

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 tests/simple/task_func.v | 19 +++++++++++++++++++
 1 file changed, 19 insertions(+)

(limited to 'tests')

diff --git a/tests/simple/task_func.v b/tests/simple/task_func.v
index fa50c1d5c..f6e902f63 100644
--- a/tests/simple/task_func.v
+++ b/tests/simple/task_func.v
@@ -120,3 +120,22 @@ module task_func_test04(input [7:0] in, output [7:0] out1, out2, out3, out4);
 	assign out3 = test3(in);
 	assign out4 = test4(in);
 endmodule
+
+// -------------------------------------------------------------------
+
+// https://github.com/YosysHQ/yosys/issues/857
+module task_func_test05(data_in,data_out,clk);
+	output reg data_out;
+	input data_in;
+	input clk;
+
+	task myTask;
+		output out;
+		input in;
+		out = in;
+	endtask
+
+	always @(posedge clk) begin
+		myTask(data_out,data_in);
+	end
+endmodule
-- 
cgit v1.2.3


From a5f4b836376e1457847da4946c1e12d2d41dc4f4 Mon Sep 17 00:00:00 2001
From: Zachary Snow <zach@zachjs.com>
Date: Mon, 18 Mar 2019 20:34:21 -0400
Subject: fix local name resolution in prefix constructs

---
 tests/simple/generate.v | 56 +++++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 56 insertions(+)

(limited to 'tests')

diff --git a/tests/simple/generate.v b/tests/simple/generate.v
index 24eb4462c..3c55682cb 100644
--- a/tests/simple/generate.v
+++ b/tests/simple/generate.v
@@ -90,5 +90,61 @@ generate
 		endcase
 	end
 endgenerate
+endmodule
+
+// ------------------------------------------
+
+module gen_test4(a, b);
+
+input [3:0] a;
+output [3:0] b;
+
+genvar i;
+generate
+	for (i=0; i < 3; i=i+1) begin : foo
+		localparam PREV = i - 1;
+		wire temp;
+		if (i == 0)
+			assign temp = a[0];
+		else
+			assign temp = foo[PREV].temp & a[i];
+		assign b[i] = temp;
+	end
+endgenerate
+endmodule
+
+// ------------------------------------------
+
+module gen_test5(input_bits, out);
+
+parameter WIDTH = 256;
+parameter CHUNK = 4;
 
+input [WIDTH-1:0] input_bits;
+output out;
+
+genvar step, i, j;
+generate
+	for (step = 1; step <= WIDTH; step = step * CHUNK) begin : steps
+		localparam PREV = step / CHUNK;
+		localparam DIM = WIDTH / step;
+		for (i = 0; i < DIM; i = i + 1) begin : outer
+			localparam LAST_START = i * CHUNK;
+			for (j = 0; j < CHUNK; j = j + 1) begin : inner
+				wire temp;
+				if (step == 1)
+					assign temp = input_bits[i];
+				else if (j == 0)
+					assign temp = steps[PREV].outer[LAST_START].val;
+				else
+					assign temp
+						= steps[step].outer[i].inner[j-1].temp
+						& steps[PREV].outer[LAST_START + j].val;
+			end
+			wire val;
+			assign val = steps[step].outer[i].inner[CHUNK - 1].temp;
+		end
+	end
+endgenerate
+assign out = steps[WIDTH].outer[0].val;
 endmodule
-- 
cgit v1.2.3


From 3b3b77291a21ed23a2763c79335501beebb10746 Mon Sep 17 00:00:00 2001
From: Niels Moseley <n.a.moseley@moseleyinstruments.com>
Date: Sun, 24 Mar 2019 22:54:18 +0100
Subject: Updated the liberty parser to accept [A:B] ranges (AST has not been
 updated). Liberty parser now also accepts key : value pair lines that do not
 end in ';'.

---
 tests/liberty/.gitignore         |   2 +
 tests/liberty/busdef.lib         |  81 +++++++++
 tests/liberty/normal.lib         | 360 +++++++++++++++++++++++++++++++++++++++
 tests/liberty/run-test.sh        |  10 ++
 tests/liberty/semicolmissing.lib |  72 ++++++++
 tests/liberty/small.v            |  16 ++
 6 files changed, 541 insertions(+)
 create mode 100644 tests/liberty/.gitignore
 create mode 100644 tests/liberty/busdef.lib
 create mode 100644 tests/liberty/normal.lib
 create mode 100755 tests/liberty/run-test.sh
 create mode 100644 tests/liberty/semicolmissing.lib
 create mode 100644 tests/liberty/small.v

(limited to 'tests')

diff --git a/tests/liberty/.gitignore b/tests/liberty/.gitignore
new file mode 100644
index 000000000..e6ec49c4a
--- /dev/null
+++ b/tests/liberty/.gitignore
@@ -0,0 +1,2 @@
+*.log
+test.ys
diff --git a/tests/liberty/busdef.lib b/tests/liberty/busdef.lib
new file mode 100644
index 000000000..b5e3d50b9
--- /dev/null
+++ b/tests/liberty/busdef.lib
@@ -0,0 +1,81 @@
+/********************************************/
+/*                                          */
+/* Supergate cell library for Bench marking */
+/*                                          */
+/* Symbiotic EDA GmbH / Moseley Instruments */
+/* Niels A. Moseley                         */
+/*                                          */
+/* Process: none                            */
+/*                                          */
+/* Date   : 02-11-2018                      */
+/* Version: 1.0                             */
+/*                                          */
+/********************************************/
+
+library(supergate) {
+  technology (cmos);
+  revision : 1.0;
+  
+  time_unit                     : "1ps";
+  pulling_resistance_unit       : "1kohm";  
+  voltage_unit                  : "1V";
+  current_unit                  : "1uA";  
+  
+  capacitive_load_unit(1,ff);
+  
+  default_inout_pin_cap         :  7.0;
+  default_input_pin_cap         :  7.0;
+  default_output_pin_cap        :  0.0;
+  default_fanout_load           :  1.0;
+
+  default_wire_load_capacitance : 0.1;
+  default_wire_load_resistance  : 1.0e-3;
+  default_wire_load_area        : 0.0;
+
+  nom_process                   :  1.0;
+  nom_temperature               : 25.0;
+  nom_voltage                   :  1.2;
+  
+  delay_model                   : generic_cmos;
+  
+    type( IO_bus_3_to_0 ) {
+        base_type : array ;
+        data_type : bit ;
+        bit_width : 4;
+        bit_from : 3 ;
+        bit_to : 0 ;
+        downto : true ;
+    }
+
+    cell (SRAM) {
+        area : 1 ;
+        memory() {
+            type : ram;
+            address_width : 4;
+            word_width : 4;
+        }
+        pin(CE1) {
+            direction : input;
+            capacitance : 0.021;
+            max_transition : 1.024;
+            switch_pin : true;
+        }
+        bus(I1)  {
+            bus_type : IO_bus_3_to_0 ;
+            direction : input;
+            pin (I1[3:0]) {
+                timing() {
+                    related_pin :   "CE1" ;
+                    timing_type : setup_rising ;
+                    rise_constraint (scalar) {
+                        values("0.0507786");
+                    }
+                    fall_constraint (scalar) {
+                        values("0.0507786");
+                    }
+                }
+            }
+        }
+    }
+
+} /* end */
diff --git a/tests/liberty/normal.lib b/tests/liberty/normal.lib
new file mode 100644
index 000000000..1474e2b59
--- /dev/null
+++ b/tests/liberty/normal.lib
@@ -0,0 +1,360 @@
+/********************************************/
+/*                                          */
+/* Supergate cell library for Bench marking */
+/*                                          */
+/* Symbiotic EDA GmbH / Moseley Instruments */
+/* Niels A. Moseley                         */
+/*                                          */
+/* Process: none                            */
+/*                                          */
+/* Date   : 02-11-2018                      */
+/* Version: 1.0                             */
+/*                                          */
+/********************************************/
+
+library(supergate) {
+  technology (cmos);
+  revision : 1.0;
+  
+  time_unit                     : "1ps";
+  pulling_resistance_unit       : "1kohm";  
+  voltage_unit                  : "1V";
+  current_unit                  : "1uA";  
+  
+  capacitive_load_unit(1,ff);
+  
+  default_inout_pin_cap         :  7.0;
+  default_input_pin_cap         :  7.0;
+  default_output_pin_cap        :  0.0;
+  default_fanout_load           :  1.0;
+
+  default_wire_load_capacitance : 0.1;
+  default_wire_load_resistance  : 1.0e-3;
+  default_wire_load_area        : 0.0;
+
+  nom_process                   :  1.0;
+  nom_temperature               : 25.0;
+  nom_voltage                   :  1.2;
+  
+  delay_model                   : generic_cmos;
+  
+  /* Inverter */
+  cell (inv) {
+    area : 1;
+    pin(A) {
+      direction : input;
+    }
+    
+    pin(Y) {
+      direction : output;
+      function : "A'";
+    }
+  }
+  
+  /* tri-state inverter */
+  cell (tri_inv) {
+    area : 4;
+    pin(A) {
+      direction : input;    
+    }
+    pin(S) {
+      direction : input;
+    }
+    pin(Z) {
+      direction : output;
+      function  : "A'";
+      three_State : "S'";
+    }
+  }
+  
+  cell (buffer) {
+    area : 5;
+    pin(A) {
+      direction : input;
+    }
+    pin(Y) {
+      direction : output;
+      function : "A";
+    }
+  }  
+  
+  /* 2-input NAND gate */
+  cell (nand2) {
+    area : 3;
+    pin(A) {
+      direction : input;
+    }
+    pin(B) {
+      direction : input;
+    }
+    pin(Y) {
+      direction: output;
+      function : "(A * B)'";
+    }
+  }
+  
+  /* 2-input NOR gate */
+  cell (nor2) {
+    area : 3;
+    pin(A) {
+      direction : input;
+    }
+    pin(B) {
+      direction : input;
+    }
+    pin(Y) {
+      direction: output;
+      function : "(A + B)'";
+    }
+  }
+  
+  /* 2-input XOR */
+  cell (xor2) {
+    area : 6;
+    pin(A) {
+      direction : input;
+    }
+    pin(B) {
+      direction : input;
+    }
+    pin(Y) {
+      direction: output;
+      function : "(A *B') + (A' * B)";
+    }
+  }
+  
+  /* 2-input inverting MUX */
+  cell (imux2) {
+    area : 5;
+    pin(A) {
+      direction : input;
+    }
+    pin(B) {
+      direction : input;
+    }
+    pin(S) {
+      direction : input;
+    } 
+    pin(Y) {
+      direction: output;
+      function : "( (A * S) + (B * S') )'";
+    }
+  }
+  
+  /* D-type flip-flop with asynchronous reset and preset */
+  cell (dff) 
+  {
+    area : 6;
+    ff("IQ", "IQN") {
+      next_state : "D";
+      clocked_on : "CLK";
+      clear      : "RESET";
+      preset     : "PRESET";
+      clear_preset_var1 : L;
+      clear_preset_var2 : L;
+    } 
+    pin(D) {
+      direction : input;
+    }
+    pin(CLK) {
+      direction : input;
+    }
+    pin(RESET) {
+      direction : input;
+    }
+    pin(PRESET) {
+      direction : input;
+    }
+    pin(Q) {
+      direction: output;
+      function : "IQ";
+      timing() {
+        timing_type : rising_edge;
+        intrinsic_rise : 65;
+        intrinsic_fall : 65;
+        rise_resistance : 0;
+        fall_resistance : 0; 
+        related_pin : "CLK";
+      }
+      timing () {
+        timing_type : clear;
+        timing_sense : positive_unate;
+        intrinsic_fall : 75;
+        related_pin : "RESET";
+      }
+      timing () {
+        timing_type : preset;
+        timing_sense : negative_unate;
+        intrinsic_rise : 75;
+        related_pin : "PRESET";
+      }      
+    }
+    pin(QN) {
+      direction: output;
+      function : "IQN";
+      timing() {
+        timing_type : rising_edge;
+        intrinsic_rise : 65;
+        intrinsic_fall : 65;
+        rise_resistance : 0;
+        fall_resistance : 0; 
+        related_pin : "CLK";
+      }
+      timing () {
+        timing_type : preset;
+        timing_sense : negative_unate;
+        intrinsic_rise : 75;
+        related_pin : "RESET";
+      }
+      timing () {
+        timing_type : clear;
+        timing_sense : positive_unate;
+        intrinsic_fall : 75;
+        related_pin : "PRESET";
+      }      
+    } 
+  }
+
+  /* Latch */
+  cell(latch) {
+    area : 5;
+    latch ("IQ","IQN") {
+      enable : "G";
+      data_in : "D";
+    }
+
+    pin(D) {
+      direction : input;
+    }
+    pin(G) {
+      direction : input;
+    }
+ 
+    pin(Q) {
+      direction : output;
+      function : "IQ";
+      internal_node : "Q";
+      
+      timing() {
+        timing_type : rising_edge;
+        intrinsic_rise : 65;
+        intrinsic_fall : 65;
+        rise_resistance : 0;
+        fall_resistance : 0;
+        related_pin : "G";
+      }
+      
+      timing() {
+        timing_sense : positive_unate;
+        intrinsic_rise : 65;
+        intrinsic_fall : 65;
+        rise_resistance : 0;
+        fall_resistance : 0;
+        related_pin : "D";
+      }
+    }
+    
+    pin(QN) {
+      direction : output;
+      function : "IQN";
+      internal_node : "QN";
+      
+      timing() {
+        timing_type : rising_edge;
+        intrinsic_rise : 65;
+        intrinsic_fall : 65;
+        rise_resistance : 0;
+        fall_resistance : 0;
+        related_pin : "G";
+      }
+      
+      timing() {
+        timing_sense : negative_unate;
+        intrinsic_rise : 65;
+        intrinsic_fall : 65;
+        rise_resistance : 0;
+        fall_resistance : 0;
+        related_pin : "D";
+      }
+    }
+  }
+
+  /* 3 input AND-OR-INVERT gate */
+  cell (aoi211) {
+    area : 3;
+    pin(A) {
+      direction : input;
+    }
+    pin(B) {
+      direction : input;
+    }
+    pin(C) {
+      direction : input;
+    }    
+    pin(Y) {
+      direction: output;
+      function : "((A * B) + C)'";
+    }
+  }
+
+
+  /* 3 input OR-AND-INVERT gate */
+  cell (oai211) {
+    area : 3;
+    pin(A) {
+      direction : input;
+    }
+    pin(B) {
+      direction : input;
+    }
+    pin(C) {
+      direction : input;
+    }    
+    pin(Y) {
+      direction: output;
+      function : "((A + B) * C)'";
+    }
+  }
+
+  /* half adder */
+  cell (halfadder) {
+    area : 5;
+    pin(A) {
+      direction : input;
+    }
+    pin(B) {
+      direction : input;
+    }
+    pin(C) {
+      direction : output;
+      function  : "(A * B)";
+    }    
+    pin(Y) {
+      direction: output;
+      function : "(A *B') + (A' * B)";
+    }    
+  }
+
+  /* full adder */
+  cell (fulladder) {
+    area : 8;
+    pin(A) {
+      direction : input;
+    }
+    pin(B) {
+      direction : input;
+    }
+    pin(CI) {
+      direction : input;
+    }    
+    pin(CO) {
+      direction : output;
+      function : "(((A * B)+(B * CI))+(CI * A))";
+    }
+    pin(Y) {
+      direction: output;
+      function : "((A^B)^CI)";
+    }    
+  }
+
+} /* end */
diff --git a/tests/liberty/run-test.sh b/tests/liberty/run-test.sh
new file mode 100755
index 000000000..7e2ed2370
--- /dev/null
+++ b/tests/liberty/run-test.sh
@@ -0,0 +1,10 @@
+#!/bin/bash
+set -e
+
+for x in *.lib; do
+	echo "Running $x.."
+    echo "read_verilog small.v" > test.ys
+    echo "synth -top small" >> test.ys
+    echo "dfflibmap -liberty ${x}" >> test.ys
+	../../yosys -ql ${x%.lib}.log -s test.ys
+done
diff --git a/tests/liberty/semicolmissing.lib b/tests/liberty/semicolmissing.lib
new file mode 100644
index 000000000..f7c20750a
--- /dev/null
+++ b/tests/liberty/semicolmissing.lib
@@ -0,0 +1,72 @@
+/********************************************/
+/*                                          */
+/* Supergate cell library for Bench marking */
+/*                                          */
+/* Symbiotic EDA GmbH / Moseley Instruments */
+/* Niels A. Moseley                         */
+/*                                          */
+/* Process: none                            */
+/*                                          */
+/* Date   : 24-03-2019                      */
+/* Version: 1.0                             */
+/* Version: 1.1 - Removed semicolons in     */
+/*                full adder                */
+/*                                          */
+/********************************************/
+
+/* 
+    semi colon is missing in full-adder specification
+    some TSMC liberty files are formatted this way..
+*/
+
+library(supergate) {
+  technology (cmos);
+  revision : 1.0;
+  
+  time_unit                     : "1ps";
+  pulling_resistance_unit       : "1kohm";  
+  voltage_unit                  : "1V";
+  current_unit                  : "1uA";  
+  
+  capacitive_load_unit(1,ff);
+  
+  default_inout_pin_cap         :  7.0;
+  default_input_pin_cap         :  7.0;
+  default_output_pin_cap        :  0.0;
+  default_fanout_load           :  1.0;
+
+  default_wire_load_capacitance : 0.1;
+  default_wire_load_resistance  : 1.0e-3;
+  default_wire_load_area        : 0.0;
+
+  nom_process                   :  1.0;
+  nom_temperature               : 25.0;
+  nom_voltage                   :  1.2;
+  
+  delay_model                   : generic_cmos;
+  
+  /* full adder */
+  cell (fulladder) {
+    area : 8
+    pin(A) {
+      direction : input
+    }
+    pin(B) {
+      direction : input
+    }
+    pin(CI) {
+      direction : input
+    }    
+    pin(CO) {
+      direction : output
+      function : "(((A * B)+(B * CI))+(CI * A))"
+    }
+    pin(Y) {
+      direction: output
+      function : "((A^B)^CI)"
+    }    
+  }
+
+} /* end */
+
+
diff --git a/tests/liberty/small.v b/tests/liberty/small.v
new file mode 100644
index 000000000..bd94be4fc
--- /dev/null
+++ b/tests/liberty/small.v
@@ -0,0 +1,16 @@
+/** small, meaningless design to test loading of liberty files */
+
+module small
+(
+    input clk,
+    output reg[7:0] count
+);
+
+initial count = 0;
+
+always @ (posedge clk) 
+begin
+    count <= count + 1'b1;
+end
+
+endmodule
-- 
cgit v1.2.3


From c863796e9ff91c76f0f8679b6871b8ffcb75edb6 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Tue, 26 Mar 2019 14:17:46 +0100
Subject: Fix "verific -extnets" for more complex situations

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 tests/sva/extnets.sv | 22 ++++++++++++++++++++++
 1 file changed, 22 insertions(+)
 create mode 100644 tests/sva/extnets.sv

(limited to 'tests')

diff --git a/tests/sva/extnets.sv b/tests/sva/extnets.sv
new file mode 100644
index 000000000..47312de7a
--- /dev/null
+++ b/tests/sva/extnets.sv
@@ -0,0 +1,22 @@
+module top(input i, output o);
+	A A();
+	B B();
+	assign A.i = i;
+	assign o = B.o;
+	always @* assert(o == i);
+endmodule
+
+module A;
+	wire i, y;
+`ifdef FAIL
+	assign B.x = i;
+`else
+	assign B.x = !i;
+`endif
+	assign y = !B.y;
+endmodule
+
+module B;
+	wire x, y, o;
+	assign y = x, o = A.y;
+endmodule
-- 
cgit v1.2.3


From 487cb45b87ce1cbcc8c2b8127e37d85dd192dceb Mon Sep 17 00:00:00 2001
From: Niels Moseley <n.a.moseley@moseleyinstruments.com>
Date: Wed, 27 Mar 2019 15:15:53 +0100
Subject: Liberty file parser now accepts superfluous ;

---
 tests/liberty/normal.lib       |  3 +--
 tests/liberty/processdefs.lib  | 48 ++++++++++++++++++++++++++++++++++++++++++
 tests/liberty/semicolextra.lib | 48 ++++++++++++++++++++++++++++++++++++++++++
 3 files changed, 97 insertions(+), 2 deletions(-)
 create mode 100644 tests/liberty/processdefs.lib
 create mode 100644 tests/liberty/semicolextra.lib

(limited to 'tests')

diff --git a/tests/liberty/normal.lib b/tests/liberty/normal.lib
index 1474e2b59..4621194dd 100644
--- a/tests/liberty/normal.lib
+++ b/tests/liberty/normal.lib
@@ -142,8 +142,7 @@ library(supergate) {
   }
   
   /* D-type flip-flop with asynchronous reset and preset */
-  cell (dff) 
-  {
+  cell (dff) {
     area : 6;
     ff("IQ", "IQN") {
       next_state : "D";
diff --git a/tests/liberty/processdefs.lib b/tests/liberty/processdefs.lib
new file mode 100644
index 000000000..37a6bbaf8
--- /dev/null
+++ b/tests/liberty/processdefs.lib
@@ -0,0 +1,48 @@
+/********************************************/
+/*                                          */
+/* Supergate cell library for Bench marking */
+/*                                          */
+/* Symbiotic EDA GmbH / Moseley Instruments */
+/* Niels A. Moseley                         */
+/*                                          */
+/* Process: none                            */
+/*                                          */
+/* Date   : 25-03-2019                      */
+/* Version: 1.0                             */
+/*                                          */
+/********************************************/
+
+library(processdefs) {
+    technology (cmos);
+    revision : 1.0;
+
+    time_unit                     : "1ps";
+    pulling_resistance_unit       : "1kohm";  
+    voltage_unit                  : "1V";
+    current_unit                  : "1uA";  
+
+    capacitive_load_unit(1,ff);
+
+    default_inout_pin_cap         :  7.0;
+    default_input_pin_cap         :  7.0;
+    default_output_pin_cap        :  0.0;
+    default_fanout_load           :  1.0;
+
+    default_wire_load_capacitance : 0.1;
+    default_wire_load_resistance  : 1.0e-3;
+    default_wire_load_area        : 0.0;
+
+    nom_process                   :  1.0;
+    nom_temperature               : 25.0;
+    nom_voltage                   :  1.2;
+
+    delay_model                   : generic_cmos;
+    
+    define_cell_area(bond_pads,pad_slots)
+    input_voltage(cmos) {
+        vil : 0.3 * VDD ;
+        vih : 0.7 * VDD ;
+        vimin : -0.5 ;
+        vimax : VDD + 0.5 ;
+    }
+}
diff --git a/tests/liberty/semicolextra.lib b/tests/liberty/semicolextra.lib
new file mode 100644
index 000000000..0144fa3ac
--- /dev/null
+++ b/tests/liberty/semicolextra.lib
@@ -0,0 +1,48 @@
+/*
+
+	Test case for https://www.reddit.com/r/yosys/comments/b5texg/yosys_fails_to_parse_apparentlycorrect_liberty/
+
+	fall_constraint (SETUP_HOLD) formatting.
+
+*/
+
+library(supergate) {
+  technology (cmos);
+  revision : 1.0;
+
+    cell (DFF) {
+        cell_footprint : dff;
+        area : 50;
+        pin(D) {
+            direction : input;
+            capacitance : 0.002;
+            timing() {
+                related_pin : "CK";
+                timing_type : setup_rising;
+
+                fall_constraint (SETUP_HOLD) { values ("0.4000, 0.3000, 0.2000, 0.1000, 0.0000", \
+                    "0.4000, 0.3000, 0.2000, 0.1000, 0.000", \
+                    "0.5000, 0.4000, 0.3000, 0.2000, 0.0000", \
+                    "0.7000, 0.6000, 0.5000, 0.4000, 0.2000", \
+                    "1.0000, 1.0000, 0.9000, 0.8000, 0.6000"); } ;
+            }
+        }	
+
+        pin(CK) {
+            direction : input;
+            clock : true;
+            capacitance : 0.00290;
+        }
+
+        ff(IQ,IQN) {
+            clocked_on : "CK";
+            next_state : "D";
+        }
+        pin(Q) {
+            direction : output;
+            capacitance : 0.003;
+            max_capacitance : 0.3;
+        }
+        cell_leakage_power : 0.3;
+    }
+}
-- 
cgit v1.2.3


From ee130f67cdd2ea40defa873e9a6511329850bf8e Mon Sep 17 00:00:00 2001
From: Niels Moseley <n.a.moseley@moseleyinstruments.com>
Date: Wed, 27 Mar 2019 15:16:19 +0100
Subject: Liberty file parser now accepts superfluous ;

---
 tests/liberty/semicolextra.lib | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'tests')

diff --git a/tests/liberty/semicolextra.lib b/tests/liberty/semicolextra.lib
index 0144fa3ac..6a7fa77cc 100644
--- a/tests/liberty/semicolextra.lib
+++ b/tests/liberty/semicolextra.lib
@@ -24,7 +24,7 @@ library(supergate) {
                     "0.4000, 0.3000, 0.2000, 0.1000, 0.000", \
                     "0.5000, 0.4000, 0.3000, 0.2000, 0.0000", \
                     "0.7000, 0.6000, 0.5000, 0.4000, 0.2000", \
-                    "1.0000, 1.0000, 0.9000, 0.8000, 0.6000"); } ;
+                    "1.0000, 1.0000, 0.9000, 0.8000, 0.6000"); };
             }
         }	
 
-- 
cgit v1.2.3